LAT Communication Board Driver: Software Architecture and Interfaces
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1.3. Initialization and Configuration

Before using the LCB it must first be configured for a particular task. Before configuring, however, the board must first be initialized.

1.3.1. Initialization

Initialization refers to the set of required operations necessary to put the LCB into a functioning, well known state. These operations include:

1.3.1.1. Interface Allocation

The LCBD hardware interface is managed using an opaque handle, whose type is pointer to struct _LCB. All of the hardware interface functions use the members of struct _LCB to access the underlying hardware.

Before initializing the LCB, memory must first be allocated for the opaque handle. The LCB_sizeOf() function returns the size of struct _LCB, allowing the higher level interface to manage memory allocation.

unsigned int LCB_sizeOf(void);

A simple-minded example using malloc() is shown below: 


typedef struct _LCB LCB;

LCB *lcb;

lcb = (LCB *)malloc(LCB_sizeOf());

1.3.1.2. Board Discovery

Board discovery refers to the process of detecting the LCB within the cPCI crate. Once detected various parameters about the LCB are stored in the opaque handle previously allocated. Examples of parameters include the memory mapped locations of the PCI I/O Space and PCI Memory Space. These parameters are used by subsequent calls to the hardware interface in order to access registers.

The LCB_boardDetect() function attempts to detect a LCB. If successful this routine stores the associated parameters in the opaque handle lcb.

int LCB_boardDetect(LCB *lcb);

An example of detecting the LCB is shown below: 


if ( LCB_boardDetect(lcb) != LCB_OK) {
   // bad things
}
else {
   // access hardware with lcb handle
}

1.3.2. Default Configuration

The hardware interface is also responsible for leaving the LCB in a default, well known state after initialization. The default state requires programming of PCI Configuration Space registers and PCI I/O Space registers.

1.3.2.1. PCI Configuration Space Registers

The Command and Interrupt Control/Status registers require special handling for the default configuration.

For the Command register the settings are:

  • PCI I/O Space Enabled

  • PCI Memory Space Enabled

  • Bus Master Enabled

For the Interrupt Control/Status register the settings are:

  • PCI Interrupts Disabled

1.3.2.2. PCI I/O Space Registers

Setting the default configuration requires setting the CSR (Section 1.2.2.1).

For the CSR the settings are:

  • Unsolicited Data Disabled

  • Event Path A Selected

  • Command Path A Selected

  • Odd Header Parity

  • Odd Payload Parity

  • Pending Events FIFO Enabled

For the PMR the settings are TBD.

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