| LAT Communication Board Driver: Software Architecture and Interfaces | ||
|---|---|---|
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The LCB has registers in the three PCI memory spaces: Configuration, Memory and I/O. See [huffer1] for a complete list of these registers. The LCBD hardware interface will provide read/write access to these registers and in certain cases access to fields within registers.
The PCI configuration space registers are used to identify and locate the LCB on the PCI bus. Once the LCB is located the configuration space registers are used to configure the PCI memory locations for the I/O Space and the Memory Space.
The PCI configuration space registers are manipulated on long word(32 bit), word(16 bit) or byte(8 bit) boundaries at byte offsets from the beginning on the configuration space. Word in/out routines are shown below:
The PCI I/O space registers are all 32-bit registers. These registers control various aspects of the LCB, including LATp parameters, resets, test features and event data taking.
All registers have 32-bit read/write interface functions. Some registers also have read/write functions for accessing register sub-fields.
The 32-bit Read/Write functions for the CSR are shown below.
The 32-bit CSR has multiple sub-fields controlling various operations of the LCB. The hardware interfaces for the CSR sub-fields are shown next.
// Read/Write of RESET bit |
int LCB_IO_CSR_Reset(LCB *lcb);
int LCB_IO_CSR_Reset_Read(LCB *lcb, unsigned short *rst);
// Read/Write of Event Enable bit |
int LCB_IO_CSR_EventEnable_Write(LCB *lcb, unsigned short val);
int LCB_IO_CSR_EventEnable_Read(LCB *lcb, unsigned short *val);
// Read/Write of Event Path Select bit |
int LCB_IO_CSR_EventPath_Write(LCB *lcb, unsigned short val);
int LCB_IO_CSR_EventPath_Read(LCB *lcb, unsigned short *val);
// Read/Write of Command Path Select bit |
int LCB_IO_CSR_CmdPath_Write(LCB *lcb, unsigned short val);
int LCB_IO_CSR_CmdPath_Read(LCB *lcb, unsigned short *val);
// Read/Write of Header Parity Definition Select bit |
int LCB_IO_CSR_HdrParity_Write(LCB *lcb, unsigned short val);
int LCB_IO_CSR_HdrParity_Read(LCB *lcb, unsigned short *val);
// Read/Write of Payload Parity Definition Select bit |
int LCB_IO_CSR_PayloadParity_Write(LCB *lcb, unsigned short val);
int LCB_IO_CSR_PayloadParity_Read(LCB *lcb, unsigned short *val);
// Read/Write of Inhibit Pending Event bit |
int LCB_IO_CSR_InhibitPendEvt_Write(LCB *lcb, unsigned short val);
int LCB_IO_CSR_InhibitPendEvt_Read(LCB *lcb, unsigned short *val);
The FIFO Faults register latches any read or write faults for the internal FIFOs of the LCB. Writing this register clears any and all latched status.
The EVENTS_BASE and EVENTS_FREE registers help manage the circular buffer used for event data. The EVENTS_BASE register defines the origin of the circular buffer, while the EVENTS_FREE register maintains the "read pointer" for the circular buffer. The "write pointer" is maintained internally by the LCB.
The LCB's PCI Memory Space provides access to the export and result FIFOs, which are used to send and receive data. These FIFOs are 32-bits wide and 1024 entries deep, holding a total of 4KB.
When sending data a 32-bit export descriptor is written to the export FIFO. This descriptor defines where the data to be sent resides.
When receiving data a 32-bit result descriptor is read from the result FIFO. This descriptor defines where the received data resides.
The use of these FIFOs is fully described in Chapter 2. The interface functions are shown below.