ACD Registers

Table 1: Details for ACD registers. ``Group'' is the hardware component on which the register is located. ``Multiplicity'' means the number of associated registers with similar names and functionality. ``Subsections'' are the number of independent data on the register. If ``Type'' is ``int'' then the register should just be read as a number, if ``type'' is ``fields'' then the register should be broken into component fields, and if ``type'' is ``mask'' the register is a bit mask where each bit enables or disables a channel or group of channel.

Group	Register Name	Multiplicity	Subsections	Type	Width (bits)	Precinct
AEM: ACD Electronics Module. 1 Instance.
AEM	aem_configuration	1	1	mask	12	GNL_Mode
AEM	trgseq	1	2	fields	12	GNL_Mode
ARC: ACD Readout Controller. 12 Instances.
ARC	veto_en	2	1	mask	6	ACD_Mode
ARC	pha_en	2	1	mask	6	ACD_Mode
ARC	max_pha	1	1	int	6	ACD_Mode
ARC	pha_threshold	18	1	int	6	ACD_PHA
ARC	hitmap_deadtime	1	1	int	6	ACD_Timing
ARC	hold_delay	1	1	int	6	ACD_Timing
ARC	hitmap_width	1	1	int	6	ACD_Timing
ARC	hitmap_delay	1	1	int	6	ACD_Timing
ARC	veto_delay	1	1	int	6	ACD_Timing
ARC	adc_tacq	1	1	int	6	ACD_Timing
ARC	veto_width	1	1	int	6	ACD_Timing
AFe: ACD Front End chips. 12 x 18 Instances.
AFE	config_reg	1	1	fields	6	ACD_Mode
AFE	tci_dac	1	1	int	6	ACD_Mode
AFE	bias_dac	1	1	int	6	ACD_Bias
AFE	veto_dac	1	1	int	6	ACD_Veto
AFE	veto_vernier	1	1	int	6	ACD_Veto
AFE	hld_dac	1	1	int	6	ACD_Hld