TRG_GEM: GEM configuration

The TRG_GEM precinct controls almost all the aspect of the Trigger configuration. This includes enabling the various inputs to the trigger, specifying which conditions are allowed to cause a trigger, how those conditions map into the trigger accept messages (TAM) that are sent back to the readout electronics, and the details of the periodic trigger. It is almost certain that the TRG_GEM precinct will have the largest number of different configurations for any precinct.

• Registers:
  

  Group	Register Name	Instances	Multiplicity	Subsections	Type	Width (bits)
  GEM	conditions	1	32	8	int	32
  GEM	configuration	1	1	1	fields	1
  GEM	engine	1	16	1	fields	32
  GEM	periodic_rate	1	1	1	fields	32
  GEM	periodic_mode	1	1	1	fields	2
  GEM	periodic_limit	1	1	1	int	32
  GEM	window_open_mask	1	1	1	fields	8
  GEM	window_width	1	1	1	int	5
  GEM	towers	1	4	4	mask	12
  GEM	tiles	1	24	2	mask	18
  GEM	acd_cno	1	1	1	mask	12
  GEM	tower_busy	1	1	1	mask	16
  GEM	external	1	1	1	mask	1

  
  

  The conditions and engine registers are by far the most complex of GEM registers to configure; they are described in detail below. Also, the mapping of bits to channels in the tiles and towers registers are fairly complicated. Both of these have specialized input XML syntax described below.

  For the other GEM registers that can be split into fields, the breakout of the fields is:
  

  Field	Mask	Comments
  configuration
  use_acd_as_trigger	0x00000001	Bit set allows ACD self triggering
  periodic_rate
  prescale	0x00ffffff
  use_1_pps	0x80000000	Bit set means use 1-pps as counter. Otherwise use 20 MHz.
  periodic_mode
  free_run	0x01
  window_open_mask
  roi	0x01
  tkr	0x02
  calle	0x04
  calhe	0x08
  cno	0x10
  periodic	0x20
  solicited	0x40
  external	0x80

  
  

  On the other hand the acd_cno, tower_busy and external registers are just straight bit-masks with LSB corresponding to channel 0.

• Methods: BCAST
• Ancillary files: None.
• Constants: None.
• Conditions register rules.
  Since the GEM conditions words has 8 bits, it takes 256 possible values. The conditions registers map each of those 256 values to one of the trigger engines defined by the engine registers. Each of the conditions register breaks into eight 4 bit sections which specify the engine used for that set of conditions. The conditions registers take names from conditions_00_07 to conditions_F8_FF which specify the range of 8 conditions word values mapped in that register. Since many of the GEM conditions are ``un-physical'', rather than specify all 256 values, we specify a set of rules used to create the conditions mapping.

  Each rule for mapping the conditions register is defined in a <rule> XML node under the <GEM_conditions> register node. To define a rule for a mapping the conditions register, at least two things must be specified, the rule number and the engine number the rule maps to. These are given as attributes to the <rule> node called ``number'' and ``engine''. Beyond that, the status of each of the GEM conditions bits may be constrained by assigning ``1'' (must be true), ``0'' (must be false) or ``x'' (don't care) to the attribute corresponding to that bit. The attribute names are: ``roi'', ``tkr'', ``clo'', ``chi'', ``cno'', ``per'', ``sol'', ``ext''.

  An example of rule definitions is:

    <GEM_conditions>
      <rule number='0' engine='0' ext='1' sol='x' per='x'
          cno='x' chi='x' clo='x' tkr='x' roi='x'/>
      <rule number='1' engine='1' ext='0' sol='x' per='x' 
          cno='x' chi='x' clo='x' tkr='0' roi='1'/>
    <GEM_conditions>
  

  It would map any external triggers to engine 0 regardless of the other bits (128 values would be mapped) and any events with the ``roi'' condition set but not the ``tkr'' into engine 1, regardless of the other values (a further 32 values would be mapped). The mapping algorithm assigns a GEM conditions word value to the first rule that matches. Also, any unclaimed values of the GEM conditions word will be mapped to the next available engine number (engine 2 in the case of the example above).

• Engine registers.
  The 16 engine nodes are named engine_0 to engine_f and can be defined in <engine> nodes under the <GEM_engine> XML register node. This is done by specifying the engine number and the values for the various register fields.

      <GEM_engine>
        <engine number='0' calstrobe='0' fourrange='0' inhibit='0' 
              marker='0' prescale='0' tack='1' zerosuppress='1'/>
        <engine number='1' calstrobe='0' fourrange='0' inhibit='0' 
              marker='0' prescale='0' tack='1' zerosuppress='1'/>
      </GEM_engine>
  

  The breakout for the fields in the engine registers is:
  

  Field	Mask	Comments
  prescale	0x000000ff	Prescale counter. Accept event when counter reaches 0
  inhibit	0x00008000	Bit set means trigger inhibited.
  calstrobe	0x00010000	Bit set means issue charge injection strobe.
  tack	0x00080000
  four_range	0x00100000	Bit set mean read out all four ranges in CAL
  zero_suppress	0x00200000	Bit set means apply zero suppression
  marker	0x01c00000	Marker value (0-8) is written to event
  destination	0x1e000000

  
  

• GEM Trigger Input Enable <tower> registers:
  The GEM Trigger Input Enable (TIE) section has four registers to mask the tower triggers. These registers are named <tower_0_3>, <tower_4_7>, <tower_8_b> and <tower_c_f>. Each register has 12 bits which mask the ``tkr'', ``clo'' and ``chi'' lines from each of 4 towers. Since this mapping is somewhat complicated we choose to specify the mask by trigger type.

      <GEM_towers>
        <tkr_tower_mask>0xffff</tkr_tower_mask> 
        <clo_tower_mask>0xffff</clo_tower_mask> 
        <chi_tower_mask>0xffff</chi_tower_mask> 
      </GEM_towers>
  

• GEM Trigger Input Enable <tiles> registers:
  The GEM Trigger Input Enable (TIE) section has 24 registers to mask the ACD inputs. These names and mappings of these registers are listed in appendix B.2. Rather than do anything complicated we specify if the tiles should be masked on not, and which channels should be reversed.

      <GEM_tiles>
        <enableAll>True</enableAll>
        <exceptTileList>000</exceptTileList>
      </GEM_tiles>