Channel mapping in Trigger Input Enable tiles registers

Table 6: Trigger enable tile register names. Each register mask 9 channels. Since each physical channel has 2 PMT this masking requires 18 bits. Bits 0-8 mask the A side PMT, Bits 9-17 mask the B side PMT.

Register Name	LSB	Channels							MSB
tiles_000_013	000	001	002	003	004	010	011	012	013
tiles_014_032	014	020	021	022	023	024	030	031	032
tiles_033_NA3	033	034	040	041	042	043	044	NA2	NA3
tiles_100_113	100	101	102	103	104	110	111	112	113
tiles_114_NA5	114	120	121	122	123	124	130	NA4	NA5
tiles_200_213	200	201	202	203	204	210	211	212	213
tiles_214_NA7	214	220	221	222	223	224	230	NA6	NA7
tiles_300_313	300	301	302	303	304	310	311	312	313
tiles_314_NA9	314	320	321	322	323	324	330	NA8	NA9
tiles_400_413	400	401	402	403	404	410	411	412	413
tiles_414_NA1	414	420	421	422	423	424	430	NA0	NA1
tiles_500_NA10	400	401	402	403	500	501	502	503	NA10