"PIG configuration information" (APP/LHK)

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Focus:	Maintenance / Operation
Structures:	Abstract / Concrete

Description:

PIG configuration information, derived from the SIB power control register, three CRU registers (including PPS and GBM selectors), and 8 EBM registers (including SSR selector)

Layout:  (show detail; help)

Offset	S	L		Type	ITOS name	ITOS description
0x00E	0	16		U12	LHKRSVPIGSTAT	LHK reserved field
0x010	0	16		U1234	LHKSPARE16U1234	Explicit 16 bit pad in unsigned short
	16	8		U1234	LHKSPARE8U1234	Explicit 8 bit pad in unsigned char
	24	3		U1234	LHKSPARE3U1234	Explicit 3 bit pad in unsigned char
	27	1		U12	LHKSIBMAINFEED	Mainfeed primary/redundant selector
	28	1		U12	LHKSIBPDUPRIM	SIB PDU primary power switch
	29	1		U12	LHKSIBPDURED	SIB PDU redundant power switch
	30	1		U12	LHKSIBGASUPRIM	SIB GASU primary power switch
	31	1		U12	LHKSIBGASURED	SIB GASU redundant power switch
0x014	0	1		U12	LHKCRUCONFIGST	CRU configuration register read status
	1	7		U1234	LHKSPARE7U1234	Explicit 7 bit pad in unsigned char
	8	8		U1	LHKCRUVERSIONID	CRU hardware version ID
	16	8		U1234	LHKSPARE8U1234	Explicit 8 bit pad in unsigned char
	24	3		U1234	LHKSPARE3U1234	Explicit 3 bit pad in unsigned char
	27	1		U1	LHKCRUEVENCELL	CRU configuration enable even parity (cell)
	28	1		U1	LHKCRUEVENHDR	CRU configuration enable even parity (header)
	29	1		U12	LHKCRUGBMSELECT	CRU configuration GBM signal path selector
	30	1		U12	LHKCRUPPSSELECT	CRU configuration PPS signal path selector
	31	1		U1	LHKCRUPPSGEN	CRU configuration enable internal PPS generator
0x018	0	1		U12	LHKCRUCOMMANDST	CRU command enable register read status
	1	1		U1234	LHKSPARE1U1234	PID status
	2	1		U1	LHKCRUCMDEPU2	CRU command enable EPU2
	3	1		U1	LHKCRUCMDEPU1	CRU command enable EPU1
	4	1		U1	LHKCRUCMDEPU0	CRU command enable EPU0
	5	1		U1	LHKCRUCMDSIU1	CRU command enable SIU1
	6	1		U1	LHKCRUCMDSIU0	CRU command enable SIU0
	7	1		U1	LHKCRUCMDSIUE	CRU command enable SIUE
	8	3		U1234	LHKSPARE3U1234	Explicit 3 bit pad in unsigned char
	11	1		U1	LHKCRUCMDPDU1	CRU command enable PDU1
	12	1		U1	LHKCRUCMDPDU0	CRU command enable PDU0
	13	1		U1	LHKCRUCMDEBM	CRU command enable EBM
	14	1		U1	LHKCRUCMDAEM	CRU command enable AEM
	15	1		U1	LHKCRUCMDGEM	CRU command enable GEM
	16	1		U1	LHKCRUCMDTEMF	CRU command enable TEM F
	17	1		U1	LHKCRUCMDTEME	CRU command enable TEM E
	18	1		U1	LHKCRUCMDTEMD	CRU command enable TEM D
	19	1		U1	LHKCRUCMDTEMC	CRU command enable TEM C
	20	1		U1	LHKCRUCMDTEMB	CRU command enable TEM B
	21	1		U1	LHKCRUCMDTEMA	CRU command enable TEM A
	22	1		U1	LHKCRUCMDTEM9	CRU command enable TEM 9
	23	1		U1	LHKCRUCMDTEM8	CRU command enable TEM 8
	24	1		U1	LHKCRUCMDTEM7	CRU command enable TEM 7
	25	1		U1	LHKCRUCMDTEM6	CRU command enable TEM 6
	26	1		U1	LHKCRUCMDTEM5	CRU command enable TEM 5
	27	1		U1	LHKCRUCMDTEM4	CRU command enable TEM 4
	28	1		U1	LHKCRUCMDTEM3	CRU command enable TEM 3
	29	1		U1	LHKCRUCMDTEM2	CRU command enable TEM 2
	30	1		U1	LHKCRUCMDTEM1	CRU command enable TEM 1
	31	1		U1	LHKCRUCMDTEM0	CRU command enable TEM 0
0x01C	0	1		U12	LHKCRURSPST	CRU response enable register read status
	1	1		U1234	LHKSPARE1U1234	Explicit 1 bit pad in unsigned char
	2	1		U1	LHKCRURSPEPU2	CRU response enable EPU2
	3	1		U1	LHKCRURSPEPU1	CRU response enable EPU1
	4	1		U1	LHKCRURSPEPU0	CRU response enable EPU0
	5	1		U1	LHKCRURSPSIU1	CRU response enable SIU1
	6	1		U1	LHKCRURSPSIU0	CRU response enable SIU0
	7	1		U1	LHKCRURSPSIUE	CRU response enable SIUE
	8	3		U1234	LHKSPARE3U1234	Explicit 3 bit pad in unsigned char
	11	1		U1	LHKCRURSPPDU1	CRU response enable PDU1
	12	1		U1	LHKCRURSPPDU0	CRU response enable PDU0
	13	1		U1	LHKCRURSPEBM	CRU response enable EBM
	14	1		U1	LHKCRURSPAEM	CRU response enable AEM
	15	1		U1	LHKCRURSPGEM	CRU response enable GEM
	16	1		U1	LHKCRURSPTEMF	CRU response enable TEM F
	17	1		U1	LHKCRURSPTEME	CRU response enable TEM E
	18	1		U1	LHKCRURSPTEMD	CRU response enable TEM D
	19	1		U1	LHKCRURSPTEMC	CRU response enable TEM C
	20	1		U1	LHKCRURSPTEMB	CRU response enable TEM B
	21	1		U1	LHKCRURSPTEMA	CRU response enable TEM A
	22	1		U1	LHKCRURSPTEM9	CRU response enable TEM 9
	23	1		U1	LHKCRURSPTEM8	CRU response enable TEM 8
	24	1		U1	LHKCRURSPTEM7	CRU response enable TEM 7
	25	1		U1	LHKCRURSPTEM6	CRU response enable TEM 6
	26	1		U1	LHKCRURSPTEM5	CRU response enable TEM 5
	27	1		U1	LHKCRURSPTEM4	CRU response enable TEM 4
	28	1		U1	LHKCRURSPTEM3	CRU response enable TEM 3
	29	1		U1	LHKCRURSPTEM2	CRU response enable TEM 2
	30	1		U1	LHKCRURSPTEM1	CRU response enable TEM 1
	31	1		U1	LHKCRURSPTEM0	CRU response enable TEM 0
0x020	0	1		U12	LHKEBMBECFGST	EBM back-end configuration register read status
	1	7		U1234	LHKSPARE7U1234	Explicit 7 bit pad in unsigned char
	8	8		U1	LHKEBMBEVID	EBM back-end hardware version ID
	16	8		U1234	LHKSPARE8U1234	Explicit 8 bit pad in unsigned char
	24	1		U1	LHKEBMBESSRSEND	EBM back-end configuration output SSR header word
	25	1		U1	LHKEBMBEEVENDC	EBM back-end configuration send even parity (data, cell)
	26	1		U1	LHKEBMBEEVENDH	EBM back-end configuration send even parity (data, header)
	27	1		U1	LHKEBMBEEVENEC	EBM back-end configuration send even parity (event, cell)
	28	1		U1	LHKEBMBEEVENEH	EBM back-end configuration send even parity (event, header)
	29	1		U1	LHKEBMBEEVENRC	EBM back-end configuration send even parity (response, cell)
	30	1		U1	LHKEBMBEEVENRH	EBM back-end configuration send even parity (response, header)
	31	1		U1	LHKEBMBESSRPATH	EBM back-end configuration SSR path selector
0x024	0	1		U12	LHKEBMFEACFGST	EBM front-end A configuration register read status
	1	7		U1234	LHKSPARE7U1234	Explicit 7 bit pad in unsigned char
	8	8		U1	LHKEBMFEAVID	EBM front-end A-end hardware version ID
	16	8		U1	LHKSPARE8U1234	Explicit 8 bit pad in unsigned char
	24	8		U1	LHKEBMFEARELOC	EBM front-end A relocation control
0x028	0	1		U12	LHKEBMFEBCFGST	EBM front-end B configuration register read status
	1	7		U1234	LHKSPARE7U1234	Explicit 7 bit pad in unsigned char
	8	8		U1	LHKEBMFEBVID	EBM front-end B hardware version ID
	16	8		U1234	LHKSPARE8U1234	Explicit 8 bit pad in unsigned char
	24	8		U1	LHKEBMFEBRELOC	EBM front-end B relocation control
0x02C	0	1		U12	LHKEBMADDRESSST	EBM address register read status
	1	7		U1234	LHKSPARE7U1234	Explicit 7 bit pad in unsigned char
	8	8		U1234	LHKSPARE8U1234	Explicit 8 bit pad in unsigned char
	16	8		U1234	LHKSPARE8U1234	Explicit 8 bit pad in unsigned char
	24	8		U1	LHKEBMADDRESS	EBM node address on command/response fabric
0x030	0	1		U12	LHKEBMINPUTST	EBM input enables register read status
	1	7		U1	LHKSPARE7U1234	Explicit 7 bit pad in unsigned char
	8	1		U1	LHKEBMINPUTEPU2	EBM input enable EPU2
	9	1		U1	LHKEBMINPUTEPU1	EBM input enable EPU1
	10	1		U1	LHKEBMINPUTEPU0	EBM input enable EPU0
	11	1		U1	LHKEBMINPUTSIU1	EBM input enable SIU1
	12	1		U1	LHKEBMINPUTSIU0	EBM input enable SIU0
	13	1		U1	LHKEBMINPUTSIUE	EBM input enable SIUE
	14	1		U1	LHKEBMINPUTAEM	EBM input enable AEM
	15	1		U1	LHKEBMINPUTTEMF	EBM input enable TEM F
	16	1		U1	LHKEBMINPUTTEME	EBM input enable TEM E
	17	1		U1	LHKEBMINPUTTEMD	EBM input enable TEM D
	18	1		U1	LHKEBMINPUTTEMC	EBM input enable TEM C
	19	1		U1	LHKEBMINPUTTEMB	EBM input enable TEM B
	20	1		U1	LHKEBMINPUTTEMA	EBM input enable TEM A
	21	1		U1	LHKEBMINPUTTEM9	EBM input enable TEM 9
	22	1		U1	LHKEBMINPUTTEM8	EBM input enable TEM 8
	23	1		U1	LHKEBMINPUTTEM7	EBM input enable TEM 7
	24	1		U1	LHKEBMINPUTTEM6	EBM input enable TEM 6
	25	1		U1	LHKEBMINPUTTEM5	EBM input enable TEM 5
	26	1		U1	LHKEBMINPUTTEM4	EBM input enable TEM 4
	27	1		U1	LHKEBMINPUTTEM3	EBM input enable TEM 3
	28	1		U1	LHKEBMINPUTTEM2	EBM input enable TEM 2
	29	1		U1	LHKEBMINPUTTEM1	EBM input enable TEM 1
	30	1		U1	LHKEBMINPUTTEM0	EBM input enable TEM 0
	31	1		U1	LHKEBMINPUTGEM	EBM input enable GEM
0x034	0	1		U12	LHKEBMCTRBST	EBM contributor enables register read status
	1	7		U1	LHKSPARE7U1234	Explicit 7 bit pad in unsigned char
	8	1		U1	LHKEBMCTRBEPU2	EBM contributor enable EPU2
	9	1		U1	LHKEBMCTRBEPU1	EBM contributor enable EPU1
	10	1		U1	LHKEBMCTRBEPU0	EBM contributor enable EPU0
	11	1		U1	LHKEBMCTRBSIU1	EBM contributor enable SIU1
	12	1		U1	LHKEBMCTRBSIU0	EBM contributor enable SIU0
	13	1		U1	LHKEBMCTRBSIUE	EBM contributor enable SIUE
	14	1		U1	LHKEBMCTRBAEM	EBM contributor enable AEM
	15	1		U1	LHKEBMCTRBTEMF	EBM contributor enable TEM F
	16	1		U1	LHKEBMCTRBTEME	EBM contributor enable TEM E
	17	1		U1	LHKEBMCTRBTEMD	EBM contributor enable TEM D
	18	1		U1	LHKEBMCTRBTEMC	EBM contributor enable TEM C
	19	1		U1	LHKEBMCTRBTEMB	EBM contributor enable TEM B
	20	1		U1	LHKEBMCTRBTEMA	EBM contributor enable TEM A
	21	1		U1	LHKEBMCTRBTEM9	EBM contributor enable TEM 9
	22	1		U1	LHKEBMCTRBTEM8	EBM contributor enable TEM 8
	23	1		U1	LHKEBMCTRBTEM7	EBM contributor enable TEM 7
	24	1		U1	LHKEBMCTRBTEM6	EBM contributor enable TEM 6
	25	1		U1	LHKEBMCTRBTEM5	EBM contributor enable TEM 5
	26	1		U1	LHKEBMCTRBTEM4	EBM contributor enable TEM 4
	27	1		U1	LHKEBMCTRBTEM3	EBM contributor enable TEM 3
	28	1		U1	LHKEBMCTRBTEM2	EBM contributor enable TEM 2
	29	1		U1	LHKEBMCTRBTEM1	EBM contributor enable TEM 1
	30	1		U1	LHKEBMCTRBTEM0	EBM contributor enable TEM 0
	31	1		U1	LHKEBMCTRBGEM	EBM contributor enable GEM
0x038	0	1		U12	LHKEBMDESTST	EBM destination enables register read status
	1	1		U1234	LHKSPARE1U1234	Explicit 1 bit pad in unsigned char
	2	1		U1	LHKEBMDSTDBEPU2	EBM destination enable EPU2 (data,broadcast)
	3	1		U1	LHKEBMDSTDBEPU1	EBM destination enable EPU1 (data,broadcast)
	4	1		U1	LHKEBMDSTDBEPU0	EBM destination enable EPU0 (data,broadcast)
	5	1		U1	LHKEBMDSTDBSIU1	EBM destination enable SIU1 (data,broadcast)
	6	1		U1	LHKEBMDSTDBSIU0	EBM destination enable SIU0 (data,broadcast)
	7	1		U1	LHKEBMDSTDBSIUE	EBM destination enable SIUE (data,broadcast)
	8	8		U1234	LHKSPARE8U1234	Explicit 8 bit pad in unsigned char
	16	2		U1234	LHKSPARE2U1234	Explicit 2 bit pad in unsigned char
	18	1		U1	LHKEBMDSTEBEPU2	EBM destination enable EPU2 (events,broadcast)
	19	1		U1	LHKEBMDSTEBEPU1	EBM destination enable EPU1 (events,broadcast)
	20	1		U1	LHKEBMDSTEBEPU0	EBM destination enable EPU0 (events,broadcast)
	21	1		U1	LHKEBMDSTEBSIU1	EBM destination enable SIU1 (events,broadcast)
	22	1		U1	LHKEBMDSTEBSIU0	EBM destination enable SIU0 (events,broadcast)
	23	1		U1	LHKEBMDSTEBSIUE	EBM destination enable SIUE (events,broadcast)
	24	2		U1234	?	?
	26	1		U1	?	?
	27	1		U1	?	?
	28	1		U1	?	?
	29	1		U1	?	?
	30	1		U1	?	?
	31	1		U1	?	?
0x03C	0	1		U12	LHKEBMTIMEOUTST	EBM timeout register read status
	1	14		U1234	LHKSPARE14U1234	Explicit 14 bit pad in unsigned int
	15	17		U1234	LHKEBMTIMEOUT	EBM timeout (17 bits)
0x040	0	32		U1234	LHKSPARE32U1234	Explicit 32 bit pad in unsigned int
0x044	0	32		U1234	LHKSPARE32U1234	Explicit 32 bit pad in unsigned int
0x048	0	32		U1234	LHKSPARE32U1234	Explicit 32 bit pad in unsigned int
0x04C	0	32		U1234	LHKSPARE32U1234	Explicit 32 bit pad in unsigned int
0x050	0	32		U1234	LHKSPARE32U1234	Explicit 32 bit pad in unsigned int
0x054	0	32		U1234	LHKSPARE32U1234	Explicit 32 bit pad in unsigned int
0x058	0	32		U1234	LHKSPARE32U1234	Explicit 32 bit pad in unsigned int
0x05C	0	32		U1234	LHKSPARE32U1234	Explicit 32 bit pad in unsigned int
0x060	0	32		U1234	LHKSPARE32U1234	Explicit 32 bit pad in unsigned int
0x064	0	32		U1234	LHKSPARE32U1234	Explicit 32 bit pad in unsigned int
0x068	0	32		U1234	LHKSPARE32U1234	Explicit 32 bit pad in unsigned int
0x06C	0	32		U1234	LHKSPARE32U1234	Explicit 32 bit pad in unsigned int
0x070	0	32		U1234	LHKSPARE32U1234	Explicit 32 bit pad in unsigned int