"Processor Register Write" (SVC/MEM)

ITOS Mnemonic:  LMEMLOADREG

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Focus:	Maintenance / Operation
Structures:	Abstract / Concrete

Context:

Description:

Load data to CPU registers.

Layout:  (show detail; help)

Processor Register Write (LMEMLOADREG) Telecommand Packet Format
0x	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15
000	Version=0			T=1	SH	APID=0x644:6
002	SF=3		Sequence Count
004	Packet Length=55
006	0	Function Code=6
008	CIDBF idents
00A	CSIZE16 wordCount
00C	CADDR32 offset
010	CDATA16 data[0-21]
03C	Packet Checksum

Fields:

CADDR32 (index)

Attribute(s):  

Brief:  "32-Bit Address/Offset Bitfield"

Instance(s):  offset

Bitfield containing the full 32 bits of the starting address or offset.

CDATA16 (index)

Attribute(s):  

Brief:  "16-Bit Data Value"

Instance(s):  data

16-bit data value.

CIDBF (index)

Attribute(s):  

Brief:  "LAT Unit and Transaction ID Bitfield"

Instance(s):  idents

Bitfield to contain the LAT unit that is the target of a MEM telecommand and the transaction ID for the MEM telecommand.

CSIZE16 (index)

Attribute(s):  

Brief:  "16-Bit Word count"

Instance(s):  wordCount

Number of 32-bit words to load/dump.