| LAT Internal Communications System: Software Interface Conceptual Design | ||
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The LCB provides access to the LAT Internal Communications System (LICS); for up to three SBCs. The access is provided via a memory-mapped interface, where each SBC accesses a certain portion of the LCB's memory space. For the system to function correctly a SBC must access that LCB memory which pertains to it, without accessing memory allocated for another SBC.
The LCB exposes memory-mapped registers for low-level initialization and and confifuration, which only a single SBC, the Director SBC, should ever access. As described in [8] the Director SBC is the SBC that resides in the system slot of the cPCI crate.
In the LICS the SBCs must be enumerated unambiguously. This is acccomplished by each SBC inspecting the cPCI bus to determine which physical slot it resides in.
The SBCs can also determine the PCI slot positions of every other SBC in the crate by leveraging the fact that all the SBCs are homogeneous in hardware . Since every SBC has the same PCI host-bridge chip with the same PCI DeviceId and VendorId a SBC can locate every other SBC.
Once all the SBCs are located they can enumerate themselvs from 0 to 2 starting with the Director SBC at 0 and increasing with increasing PCI slot number.
This enumerates the SBCs from 0 to 2 regardless of which PCI slot the SBC occupies ( except for the Director SBC which must reside in the cPCI system slot ).
The LICS defines three different classes of PCI memory. Two of the memory classes map to physical memory on the LCB, while the third class of memory maps to physical memory on each SBC.
A SBC will use its enumeration to setup it memory maps and avoid conflicting with the other SBCs.
The LCB exposes three sets of registers for event data and command/response data, one set for each of the three SBCs. For event data the registers are EVENTS_BASEn and EVENTS_FREEn, while for command/response the registers are EXPORTn and RESULTSn with n ranging from 0 through 2 for all sets.
A SBC will use its enumeration (see Section 1.1.1) as an index into these register sets, thus avoiding any conflicts.