_BFregControl Struct Reference

map of the comm i/o board 32-bit control register More...

#include <reg_p.h>

Data Fields

unsigned int startAcq:1

unsigned int startAcqSrc:1

unsigned int chn0clk:1

unsigned int dataChn:4

unsigned int mode:1

unsigned int rbfwDelay:8

unsigned int rfpr:1

unsigned int rfmr:1

unsigned int pfpr:1

unsigned int pfmr:1

unsigned int rbcDelay:6

unsigned int c0delay:6

Detailed Description

map of the comm i/o board 32-bit control register

unsigned int _BFregControl::c0delay

channel 0 delay in 2ns steps. max 60ns

unsigned int _BFregControl::chn0clk

Channel 0 clock mode: 0 programmable pulse train, 1 continuous clock

unsigned int _BFregControl::dataChn

Select input channel when running LATp

unsigned int _BFregControl::mode

Record FIFO mode. 0 - "dumb FIFO", 1 - "LATp FIFO"

unsigned int _BFregControl::pfmr

play FIFO master reset: 0 reset, reset data and config

unsigned int _BFregControl::pfpr

play FIFO partial reset: 0 reset, reset data, no config

unsigned int _BFregControl::rbcDelay

read back clock dealy in 2ns steps. max 60ns

unsigned int _BFregControl::rbfwDelay

Delay of write to record FIFO for up to 6.4 usec

unsigned int _BFregControl::rfmr

record FIFO master reset: 0 reset, reset data and config

unsigned int _BFregControl::rfpr

record FIFO partial reset: 0 reset, reset data, no config

unsigned int _BFregControl::startAcq

Start acquisition on 0 to 1 transition

unsigned int _BFregControl::startAcqSrc

Select source of start acquisition: 0 startAcq, 1 external

The documentation for this struct was generated from the following file:

Generated on Tue Apr 6 11:13:00 2004 by

1.3.3