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GGLT / V1-4-12
Constituent: gglt Tag: sun-gcc
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_BFregTrgMaskCfg Struct Reference
map of the comm i/o board 32-bit "Trigger Mask/Config" register
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#include <gglt_reg_p.h>
Detailed Description
map of the comm i/o board 32-bit "Trigger Mask/Config" register
Hybrid register where half of the bits are for one purpose and half the bits are for an other, unrelated purpose. Ugly, yes, but sometimes you just got to get on with it.
The bit ignoreBusy allows the sending of triggers even when the destination module is asserting busy.
The bits tem3_in_a_row, temCAL_high, temCAL_low, extTrigger and intTrigger are all used for the trigger calculation.
The bits latchConfig, eventNum, tag and parityDef are used for the initial starting values of the trigger message. The latchConfig bit is a bit special -- transitioning this bit from 0 to 1 cause the board to internally latch the values of the eventNum, tag and parityDef bits. This allows us to twiddle the upper bits for the trigger mask without reseting the event number.
Field Documentation
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source of flow control signal -- FIFO channel 4(clear), record FIFO almost full flag(set) |
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enable mask of trigger sources |
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latch configuration toggle on 0 -> 1 transition |
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enable mask of trigger sources |
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parity definition -- even(0) odd(1) |
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0 = virtual AEM mode, 1 = normal |
The documentation for this struct was generated from the following file:
Generated on Thu Apr 29 06:31:00 2004 by
1.3.3