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UNIV.h File Reference

Universe II Utilities, Interface. More...


Data Structures

struct  _UNIV_dcp
 Universe II DMA Control Packet. More...


Defines

#define UNIV_K_DCTL_LD64EN   ( 1 << UNIV_V_DCTL_LD64EN)
 Enable PCI 64 Bit Bus Transactions.

#define UNIV_K_DCTL_VCT_NO_BLT   ( 0 << UNIV_V_DCTL_VCT)
 Disallow BLT's.

#define UNIV_K_DCTL_VCT_BLT   ( 1 << UNIV_V_DCTL_VCT)
 Allow BLT's.

#define UNIV_K_DCTL_SUPER_USER   (0x00 << UNIV_V_DCTL_SUPER)
 User AM Code.

#define UNIV_K_DCTL_SUPER_SUPER   (0x01 << UNIV_V_DCTL_SUPER)
 Supervisor AM Code.

#define UNIV_K_DCTL_PGM_DATA   (0x00 << UNIV_V_DCTL_PGM)
 Data AM Code.

#define UNIV_K_DCTL_PGM_PROGRAM   (0x01 << UNIV_V_DCTL_PGM)
 Program AM Code.

#define UNIV_K_DCTL_VAS_A16   (0x00 << UNIV_V_DCTL_VAS)
 VME Address Space = A16.

#define UNIV_K_DCTL_VAS_A24   (0x01 << UNIV_V_DCTL_VAS)
 VME Address Space = A24.

#define UNIV_K_DCTL_VAS_A32   (0x02 << UNIV_V_DCTL_VAS)
 VME Address Space = A32.

#define UNIV_K_DCTL_VAS_RSVD_3   (0x03 << UNIV_V_DCTL_VAS)
 VME Address Space = Reserved.

#define UNIV_K_DCTL_VAS_RSVD_4   (0x04 << UNIV_V_DCTL_VAS)
 VME Address Space = Reserved.

#define UNIV_K_DCTL_VAS_RSVD_5   (0x05 << UNIV_V_DCTL_VAS)
 VME Address Space = Reserved.

#define UNIV_K_DCTL_VAS_USER1   (0x06 << UNIV_V_DCTL_VAS)
 VME Address Space = User 1.

#define UNIV_K_DCTL_VAS_USER2   (0x07 << UNIV_V_DCTL_VAS)
 VME Address Space = User 2.

#define UNIV_K_DCTL_VDW_08   (0x00 << UNIV_V_DCTL_VDW)
 VME Maximum Datawidth = 8 bits.

#define UNIV_K_DCTL_VDW_16   (0x01 << UNIV_V_DCTL_VDW)
 VME Maximum Datawidth = 16 bits.

#define UNIV_K_DCTL_VDW_32   (0x02 << UNIV_V_DCTL_VDW)
 VME Maximum Datawidth = 32 bits.

#define UNIV_K_DCTL_VDW_64   (0x03 << UNIV_V_DCTL_VDW)
 VME Maximum Datawidth = 64 bits.

#define UNIV_K_DCTL_L2V_V2L   (0x00 << UNIV_V_DCTL_L2V)
 Transfer direction is PCI => VME.

#define UNIV_K_DCTL_L2V_L2V   (0x01 << UNIV_V_DCTL_V2L)
 Transfer direction is VME => PCI.


Typedefs

typedef _UNIV_dcp * UNIV_dcpp
 Typedef for a pointer to struct _UNIV_dcp. More...

typedef _UNIV_dcp UNIV_dcp
 Typedef for struct _UNIV_dcp.

typedef void(* UNIV_isr )(void *parameter)
 Signature for a UNIV interrupt service routine. More...

typedef enum _UNIV_V_dctl UNIV_V_dctl
 Typedef for enum _UNIV_V_dctl. More...

typedef enum _UNIV_S_dctl UNIV_S_dctl
 Typedef for enum _UNIV_S_dctl.

typedef enum _UNIV_M_dctl UNIV_M_dctl
 Typedef for enum _UNIV_M_dctl.

typedef enum _UNIV_V_dgcs UNIV_V_dgcs
 Typedef for enum _UNIV_V_dgcs. More...

typedef enum _UNIV_S_dgcs UNIV_S_dgcs
 Typedef for enum _UNIV_S_dgcs.

typedef enum _UNIV_M_dgcs UNIV_M_dgcs
 Typedef for enum _UNIV_S_dgcs.


Enumerations

enum  _UNIV_V_dctl {
  UNIV_V_DCTL_RSVD_0 = 6,
  UNIV_V_DCTL_LD64EN = 7,
  UNIV_V_DCTL_VCT = 8,
  UNIV_V_DCTL_RSVD_1 = 9,
  UNIV_V_DCTL_SUPER = 12,
  UNIV_V_DCTL_PGM = 14,
  UNIV_V_DCTL_VAS = 16,
  UNIV_V_DCTL_RSVD_2 = 19,
  UNIV_V_DCTL_VDW = 22,
  UNIV_V_DCTL_RSVD_3 = 24,
  UNIV_V_DCTL_L2V = 31
}
 Gives the number of bits to shift needed to right justify the bits field in the DCTL control word. More...

enum  _UNIV_S_dctl {
  UNIV_S_DCTL_RSVD_0 = 7,
  UNIV_S_DCTL_LD64EN = 1,
  UNIV_S_DCTL_VCT = 1,
  UNIV_S_DCTL_RSVD_1 = 3,
  UNIV_S_DCTL_SUPER = 3,
  UNIV_S_DCTL_PGM = 2,
  UNIV_S_DCTL_VAS = 3,
  UNIV_S_DCTL_RSVD_2 = 3,
  UNIV_S_DCTL_VDW = 2,
  UNIV_S_DCTL_RSVD_3 = 7,
  UNIV_S_DCTL_L2V = 1
}
 Gives the size of each of the bit fields in the DCTL control word. More...

enum  _UNIV_M_dctl {
  UNIV_M_DCTL_RSVD_0 = 0x0000007E,
  UNIV_M_DCTL_LD64EN = 0x00000080,
  UNIV_M_DCTL_VCT = 0x00000100,
  UNIV_M_DCTL_RSVD_1 = 0x00000E00,
  UNIV_M_DCTL_SUPER = 0x00003000,
  UNIV_M_DCTL_PGM = 0x0000C000,
  UNIV_M_DCTL_VAS = 0x00070000,
  UNIV_M_DCTL_RSVD_2 = 0x00380000,
  UNIV_M_DCTL_VDW = 0x00C00000,
  UNIV_M_DCTL_RSVD_3 = 0x7F000000,
  UNIV_M_DCTL_L2V = 0x80000000
}
 Gives in place extraction masks for each of the bit fields in the DCTL control word. More...

enum  _UNIV_V_dgcs {
  UNIV_V_DGCS_INT_P_ERR = 0,
  UNIV_V_DGCS_INT_VERR = 1,
  UNIV_V_DGCS_INT_LERR = 2,
  UNIV_V_DGCS_INT_DONE = 3,
  UNIV_V_DGCS_INT_RSVD4 = 4,
  UNIV_V_DGCS_INT_HALT = 5,
  UNIV_V_DGCS_INT_STOP = 6,
  UNIV_V_DGCS_INT_RSVD7 = 7,
  UNIV_V_DGCS_P_ERR = 8,
  UNIV_V_DGCS_VERR = 9,
  UNIV_V_DGCS_LERR = 10,
  UNIV_V_DGCS_DONE = 11,
  UNIV_V_DGCS_RSVD12 = 12,
  UNIV_V_DGCS_HALT = 13,
  UNIV_V_DGCS_STOP = 14,
  UNIV_V_DGCS_ACT = 15,
  UNIV_V_DGCS_VOFF = 16,
  UNIV_V_DGCS_VON = 20,
  UNIV_V_DGCS_RSVD23 = 23,
  UNIV_V_DGCS_RSVD24 = 24,
  UNIV_V_DGCS_CHAIN = 27,
  UNIV_V_DGCS_RSVD28 = 28,
  UNIV_V_DGCS_HALT_REQ = 29,
  UNIV_V_DGCS_STOP_REQ = 30,
  UNIV_V_DGCS_GO = 31,
  UNIV_V_DGCS_INT_ENB_ERR = 0,
  UNIV_V_DGCS_INT_ENB_SUC = 3,
  UNIV_V_DGCS_INT_ENB_ALL = 0,
  UNIV_V_DGCS_INT_STS_ERR = 8,
  UNIV_V_DGCS_INT_STS_SUC = 11,
  UNIV_V_DGCS_INT_STS_ALL = 8,
  UNIV_V_DGCS_STS_ALL = 8
}
 Maps out the DMA General Control/Status Register. More...

enum  _UNIV_S_dgcs {
  UNIV_S_DGCS_INT_P_ERR = 1,
  UNIV_S_DGCS_INT_VERR = 1,
  UNIV_S_DGCS_INT_LERR = 1,
  UNIV_S_DGCS_INT_RSVD4 = 1,
  UNIV_S_DGCS_INT_DONE = 1,
  UNIV_S_DGCS_INT_HALT = 1,
  UNIV_S_DGCS_INT_STOP = 1,
  UNIV_S_DGCS_INT_RSVD7 = 1,
  UNIV_S_DGCS_P_ERR = 1,
  UNIV_S_DGCS_VERR = 1,
  UNIV_S_DGCS_LERR = 1,
  UNIV_S_DGCS_DONE = 1,
  UNIV_S_DGCS_RSVD12 = 1,
  UNIV_S_DGCS_HALT = 1,
  UNIV_S_DGCS_STOP = 1,
  UNIV_S_DGCS_ACT = 1,
  UNIV_S_DGCS_VOFF = 4,
  UNIV_S_DGCS_VON = 3,
  UNIV_S_DGCS_RSVD23 = 1,
  UNIV_S_DGCS_RSVD24 = 3,
  UNIV_S_DGCS_CHAIN = 1,
  UNIV_S_DGCS_RSVD28 = 1,
  UNIV_S_DGCS_HALT_REQ = 1,
  UNIV_S_DGCS_STOP_REQ = 1,
  UNIV_S_DGCS_GO = 1,
  UNIV_S_DGCS_INT_ENB_ERR = 3,
  UNIV_S_DGCS_INT_ENB_SUC = 4,
  UNIV_S_DGCS_INT_ENB_ALL = 7,
  UNIV_S_DGCS_INT_STS_ERR = 3,
  UNIV_S_DGCS_INT_STS_SUC = 4,
  UNIV_S_DGCS_INT_STS_ALL = 3,
  UNIV_S_DGCS_STS_ALL = 8
}
 Maps out the sizes of bit fields in the DMA General Control/Status Register. More...

enum  _UNIV_M_dgcs {
  UNIV_M_DGCS_INT_P_ERR = (1<<UNIV_V_DGCS_INT_P_ERR),
  UNIV_M_DGCS_INT_VERR = (1<<UNIV_V_DGCS_INT_VERR ),
  UNIV_M_DGCS_INT_LERR = (1<<UNIV_V_DGCS_INT_LERR ),
  UNIV_M_DGCS_INT_DONE = (1<<UNIV_V_DGCS_INT_DONE ),
  UNIV_M_DGCS_INT_RSVD4 = (1<<UNIV_V_DGCS_INT_RSVD4),
  UNIV_M_DGCS_INT_HALT = (1<<UNIV_V_DGCS_INT_HALT ),
  UNIV_M_DGCS_INT_STOP = (1<<UNIV_V_DGCS_INT_STOP ),
  UNIV_M_DGCS_INT_RSVD7 = (1<<UNIV_V_DGCS_INT_RSVD7),
  UNIV_M_DGCS_P_ERR = (1 << UNIV_V_DGCS_P_ERR),
  UNIV_M_DGCS_VERR = (1 << UNIV_V_DGCS_VERR ),
  UNIV_M_DGCS_LERR = (1 << UNIV_V_DGCS_LERR ),
  UNIV_M_DGCS_DONE = (1 << UNIV_V_DGCS_DONE ),
  UNIV_M_DGCS_HALT = (1 << UNIV_V_DGCS_HALT ),
  UNIV_M_DGCS_STOP = (1 << UNIV_V_DGCS_STOP ),
  UNIV_M_DGCS_ACT = (1 << UNIV_V_DGCS_ACT ),
  UNIV_M_DGCS_VOFF = (0xf<<UNIV_V_DGCS_VOFF ),
  UNIV_M_DGCS_VON = (0x7<<UNIV_V_DGCS_VOFF ),
  UNIV_M_DGCS_RSVD23 = (1 <<UNIV_V_DGCS_RSVD23),
  UNIV_M_DGCS_RSVD24 = (0x7<<UNIV_V_DGCS_RSVD24),
  UNIV_M_DGCS_CHAIN = (1 <<UNIV_V_DGCS_CHAIN),
  UNIV_M_DGCS_RSVD28 = (1 <<UNIV_V_DGCS_RSVD28),
  UNIV_M_DGCS_HALT_REQ = (1<<UNIV_V_DGCS_HALT_REQ),
  UNIV_M_DGCS_STOP_REQ = (1<<UNIV_V_DGCS_STOP_REQ),
  UNIV_M_DGCS_GO = (1 <<UNIV_V_DGCS_GO),
  UNIV_M_DGCS_INT_ENB_ERR,
  UNIV_M_DGCS_INT_ENB_SUC,
  UNIV_M_DGCS_INT_ENB_ALL,
  UNIV_M_DGCS_INT_STS_ERR,
  UNIV_M_DGCS_INT_STS_SUC,
  UNIV_M_DGCS_INT_STS_ALL,
  UNIV_M_DGCS_STS_ALL = (UNIV_M_DGCS_INT_STS_ALL | UNIV_M_DGCS_ACT)
}
 Maps out in place masks of the bit fields in the DMA General Control/Status Register. More...


Functions

_UNIV_dcp * UNIV_DCPP_read (void)
 Reads the DCPP register, (Command Packet Pointer). More...

void UNIV_DCPP_write (const struct _UNIV_dcp *cmd)
 Write the DCPP register with the head of a DMA linked list. More...

unsigned int UNIV_DTBC_read (void)
 Reads the DTBC register, (Transfer Byte Count). More...

void UNIV_DTBC_write (unsigned int byte_count)
 Writes the DTBC register, (Transfer Byte Count). More...

unsigned int UNIV_DGCS_read (void)
 Reads the DGCS register, (General Control/Status Register. More...

unsigned int UNIV_go (void)
 Initiates a start on on a DMA operation by hitting to GO bit in the DGCS register. More...

unsigned int UNIV_request_halt (void)
 Request a halt on an ongoing DMA operation. More...

unsigned int UNIV_request_stop (void)
 Request a stop on an ongoing DMA operation. More...

unsigned int UNIV_DGCS_bclr (unsigned int bits_to_clr)
 Clears the specified bits in the DGCS register, (General Control/Status Register). More...

unsigned int UNIV_DGCS_bmod (unsigned int bits_to_mod, unsigned int value)
 Modifies a selected set of bits in the DGCS register. More...

unsigned int UNIV_DGCS_bset (unsigned int bits_to_set)
 Sets the specified bits in the DGCS register. More...

void UNIV_DGCS_write (unsigned int value)
 Writes the DGCS register, (General Control/Status Register). More...

int UNIV_int_connect (unsigned int which, UNIV_isr service, void *parameter)
 Connects a ISR routine to service the UNIVERSET II interrupts. More...

int UNIV_int_enable (void)
 Enables delivery of interrupts from the UNIVERSE II. More...

int UNIV_int_disable (void)
 Disables delivery of interrupts from the UNIVERSE II. More...

unsigned int UNIV_bus_master_set (void)
 Ensures the UNIVERSE II is a PCI bus master. More...

void UNIV_dcp_array_init (struct _UNIV_dcp *dcpp, int cnt)
 Initializes an array of Universe DMA Command packets to form a circular list. Only the link field is filled in. More...

void UNIV_dcp_complete (struct _UNIV_dcp *dcpp, unsigned int dctl, unsigned int vmeAdr, unsigned char *dstAdr, int nbytes)
 Complete the DMA Command Packet, ie finishes the job UNIV_dcp_array_init started. More...

void UNIV_go_at (struct _UNIV_dcp *dcpp)
 This initiates a chain UNIV transfer by the Universe at the specified command head. More...

Detailed Description

Universe II Utilities, Interface.

Author:
JJRussell - russell@slac.stanford.edu

Typedef Documentation

UNIV_dcpp
 

Typedef for a pointer to struct _UNIV_dcp.

Defines the DMA Control Packet. These packets can be linked together to form a chained DMA operation, which is seeded in the Universe's DCPP control register.

UNIV_isr
 

Signature for a UNIV interrupt service routine.

A Universe interrupt is serviced by a callback routine with this signature. 

       void (*isr)(void *parameter)

UNIV_V_dctl
 

Typedef for enum _UNIV_V_dctl.

The UNIVERSE control word contains bit fields which control the transfer of data between the PCI and VME busses.

In addition to definitions of the bare bit fields, several useful collections are defined. These are confined to the interrupt and status bits. There are basically two sets of the same bits, one set for enabling interrupt sources and one set of reporting/clearing interrupt status. Each set is confined to a byte, the enabling set in the least significant byte and the reporting/clearing set in the next byte out. These sets are referenced by UNIV_x_DGCS_INT_ENB_xxx and UNIV_x_DGCS_INT_STS_xxx.

Each of these sets are broken into two sets, a set which deal with error conditions and a set that deal with normal (expected, like DMA complete) conditions. These are referenced by the symbols with _ERR_ and _SUC_ in their names.

Warning:
The narrative descriptions of the bit fields where lifted straight out of the UNIVERSE II User Manual. That manual serves as the ultimate source of the information. An descrepancies between this documentation and the documentation in the UNIVERSE II User Manual is always resolved in favor of UNIVERSE II User Manual.

UNIV_V_dgcs
 

Typedef for enum _UNIV_V_dgcs.

The UNIVERSE DMA General Control/Status Register contains enables, status and action bits.

Enable bits are set by the user and are sticky, ie the stay in whatever state the user places them in.

Status bits are set by the hardware in response to some condition it detects and cleared by the user after acknowledging them.

Action bits are used to initiate some action. They are generally self-clearing. That is one sets them, and after the action is completed or acknowledged, the bit clears.

Warning:
The narrative descriptions of the bit fields where lifted straight out of the UNIVERSE II User Manual. That manual serves as the ultimate source of the information. An descrepancies between this documentation and the documentation in the UNIVERSE II User Manual is always resolved in favor of UNIVERSE II User Manual.

Enumeration Type Documentation

enum _UNIV_M_dctl
 

Gives in place extraction masks for each of the bit fields in the DCTL control word.

Enumeration values:
UNIV_M_DCTL_RSVD_0  Mask for this unused field
UNIV_M_DCTL_LD64EN  Mask for Enable PCI 64-bit transaction field
UNIV_M_DCTL_VCT  Mask for VME Bus Cycle type field
UNIV_M_DCTL_RSVD_1  Mask for this unused field
UNIV_M_DCTL_SUPER  Mask for Supervisor/User AM code field
UNIV_M_DCTL_PGM  Mask for Program/Data AM code field
UNIV_M_DCTL_VAS  Mask for VME Bus Address Space field
UNIV_M_DCTL_RSVD_2  Mask for this unused field
UNIV_M_DCTL_VDW  Mask for VME Maximum Datawidth field
UNIV_M_DCTL_RSVD_3  Mask for this unused field
UNIV_M_DCTL_L2V  Mask for Transaction Direction field

enum _UNIV_M_dgcs
 

Maps out in place masks of the bit fields in the DMA General Control/Status Register.

Enumeration values:
UNIV_M_DGCS_INT_P_ERR  P_ERR Enb mask
UNIV_M_DGCS_INT_VERR  VERR Enable mask
UNIV_M_DGCS_INT_LERR  LERR Enable mask
UNIV_M_DGCS_INT_DONE  DONE Enable mask
UNIV_M_DGCS_INT_RSVD4  Unused
UNIV_M_DGCS_INT_HALT  HALT Enable mask
UNIV_M_DGCS_INT_STOP  STOP Enable mask
UNIV_M_DGCS_P_ERR  Status, Protocol error
UNIV_M_DGCS_VERR  Status, VME bus error
UNIV_M_DGCS_LERR  Status, PCI bus error
UNIV_M_DGCS_DONE  Status, DMA done
UNIV_M_DGCS_HALT  Status, DMA halted
UNIV_M_DGCS_STOP  Status, DMA stopped
UNIV_M_DGCS_ACT  Status, DMA active
UNIV_M_DGCS_VOFF  VOFF counter mask
UNIV_M_DGCS_VON  VOFF counter mask
UNIV_M_DGCS_RSVD23  Unused
UNIV_M_DGCS_RSVD24  Unused
UNIV_M_DGCS_CHAIN  DMA Chaining mask
UNIV_M_DGCS_RSVD28  Unused
UNIV_M_DGCS_HALT_REQ  Halt Request mask
UNIV_M_DGCS_STOP_REQ  Stop Request mask
UNIV_M_DGCS_GO  Go Request mask
UNIV_M_DGCS_INT_ENB_ERR  Mask of all error interrupt enable bits
UNIV_M_DGCS_INT_ENB_SUC  Mask of all successful interrupt enable bits
UNIV_M_DGCS_INT_ENB_ALL  Mask of all interrupt enable bits
UNIV_M_DGCS_INT_STS_ERR  Mask of all error interrupt status bits
UNIV_M_DGCS_INT_STS_SUC  Mask of all successful interrupt status bits
UNIV_M_DGCS_INT_STS_ALL  Mask of all interrupt status bits
UNIV_M_DGCS_STS_ALL  Mask of all status bits

enum _UNIV_S_dctl
 

Gives the size of each of the bit fields in the DCTL control word.

Enumeration values:
UNIV_S_DCTL_RSVD_0  Size of this unused field
UNIV_S_DCTL_LD64EN  Size of Enable 64-Bit PCI Transaction
UNIV_S_DCTL_VCT  Size of VME Bus Cycle Type field
UNIV_S_DCTL_RSVD_1  Size of this unused field
UNIV_S_DCTL_SUPER  Size of Supervisor/User AM code field
UNIV_S_DCTL_PGM  Size of Program/Data AM code field
UNIV_S_DCTL_VAS  Size of VME Bus Address field
UNIV_S_DCTL_RSVD_2  Size of this unused field
UNIV_S_DCTL_VDW  Size of VME Bus Maximum Datawidth field
UNIV_S_DCTL_RSVD_3  Size of this unused field
UNIV_S_DCTL_L2V  Size of Transfer Direction field

enum _UNIV_S_dgcs
 

Maps out the sizes of bit fields in the DMA General Control/Status Register.

Enumeration values:
UNIV_S_DGCS_INT_P_ERR  Size of the P_ERR enable bit field
UNIV_S_DGCS_INT_VERR  Size of the VERR enable bit field
UNIV_S_DGCS_INT_LERR  Size of the LERR enable bit field
UNIV_S_DGCS_INT_RSVD4  Unused
UNIV_S_DGCS_INT_DONE  Size of the DONE enable bit field
UNIV_S_DGCS_INT_HALT  Size of the HALT enable bit field
UNIV_S_DGCS_INT_STOP  Size of the STOP enable bit field
UNIV_S_DGCS_INT_RSVD7  Unused
UNIV_S_DGCS_P_ERR  Size of the P_ERR status bit field
UNIV_S_DGCS_VERR  Size of the VERR status bit field
UNIV_S_DGCS_LERR  Size of the LERR status bit field
UNIV_S_DGCS_DONE  Size of the DONE status bit field
UNIV_S_DGCS_RSVD12  Unused
UNIV_S_DGCS_HALT  Size of the HALT status bit field
UNIV_S_DGCS_STOP  Size of the STOP status bit field
UNIV_S_DGCS_ACT  Size of the ACT status bit field
UNIV_S_DGCS_VOFF  Size of the VOFF bit field
UNIV_S_DGCS_VON  Size of the VON bit field
UNIV_S_DGCS_RSVD23  Unused
UNIV_S_DGCS_RSVD24  Unused
UNIV_S_DGCS_CHAIN  Size of the CHAIN enable bit field
UNIV_S_DGCS_RSVD28  Unused
UNIV_S_DGCS_HALT_REQ  Size of the HALT Requeset bit field
UNIV_S_DGCS_STOP_REQ  Size of the STOP Requeset bit field
UNIV_S_DGCS_GO  Size of the DMA Go bit field
UNIV_S_DGCS_INT_ENB_ERR  Size of ERR interrupt enable bits
UNIV_S_DGCS_INT_ENB_SUC  Size of SUC interrupt enable bits Note that this field has 1 unused bit in it
UNIV_S_DGCS_INT_ENB_ALL  Beginning of all interrupt enable bits
UNIV_S_DGCS_INT_STS_ERR  Size of ERR interrupt status bits
UNIV_S_DGCS_INT_STS_SUC  Size of SUC interrupt status bits
UNIV_S_DGCS_INT_STS_ALL  Size of ALL interrupt status bits
UNIV_S_DGCS_STS_ALL  Size of ALL status bits

enum _UNIV_V_dctl
 

Gives the number of bits to shift needed to right justify the bits field in the DCTL control word.

Enumeration values:
UNIV_V_DCTL_RSVD_0  Unused
UNIV_V_DCTL_LD64EN  Enable 64-bit PCI Bus Transactions 0 = Disable 1 = Enable
UNIV_V_DCTL_VCT  VME Bus Cycle Type 0 = No BLT's on VMEbus, 1 = BLT's on VME
UNIV_V_DCTL_RSVD_1  Unused
UNIV_V_DCTL_SUPER  Supervisor/User AM code 00 = Non-Privledged, 01 = Supervisor, Others = reserved
UNIV_V_DCTL_PGM  Program/Data AM code 00 = Data, 01 = Program, Others = Reserved
UNIV_V_DCTL_VAS  VME Bus Address space 000 = A16, 001 = A24, 010 = A32 011 = Reserved, 101 = Reserved 110 = User 1, 111 = User 2
UNIV_V_DCTL_RSVD_2  Unused
UNIV_V_DCTL_VDW  VME Maximum Bus Width 00 = 8-bit data width, 01 = 16-bit data width, 10 = 32-bit data width, 11 = 64-bit data width
UNIV_V_DCTL_RSVD_3  Unused
UNIV_V_DCTL_L2V  Transfer Direction 0 = Transfer from VME Bus to PCI Bus 1 = Transfer from PCI Bus to VME Bus

enum _UNIV_V_dgcs
 

Maps out the DMA General Control/Status Register.

Enumeration values:
UNIV_V_DGCS_INT_P_ERR  Enable Interrupt On Master Error
UNIV_V_DGCS_INT_VERR  Enable Interrupt on VERR (VME error)
UNIV_V_DGCS_INT_LERR  Enable Interrupt on LERR
UNIV_V_DGCS_INT_DONE  Enable Interrupt when Done
UNIV_V_DGCS_INT_RSVD4  Unused
UNIV_V_DGCS_INT_HALT  Enable Interrupt when Halted
UNIV_V_DGCS_INT_STOP  Enable Interrupt when Stopped
UNIV_V_DGCS_INT_RSVD7  Unused
UNIV_V_DGCS_P_ERR  Protocol error Asserted if PCI master interface disabled or lower 3 bits of the PCI and VME address fields differ. Also (determined experimentally) if the DMA packet is not 8 byte aligned
UNIV_V_DGCS_VERR  VME bus error
UNIV_V_DGCS_LERR  PCI bus error
UNIV_V_DGCS_DONE  DMA done
UNIV_V_DGCS_RSVD12  Unused
UNIV_V_DGCS_HALT  DMA halted
UNIV_V_DGCS_STOP  DMA stopped
UNIV_V_DGCS_ACT  DMA active
UNIV_V_DGCS_VOFF  VME Bus Off Counter (timer) 0000 = 0usec, 0001 = 16usec, 0010 = 32usec, 0011 = 64usec, 0100 = 128usec, 0101 = 256usec, 0110 = 512usec, 0111 = 1024usec, 1000 = 2usec, 1001 = 4usec, 1010 = 8usec, Others = reserved The DMA will not re-request the VME Master until this timer expires.
UNIV_V_DGCS_VON  VME Bus On Counter (bytes) 000 = until done, 001 = 256 bytes, 010 = 512 bytes, 011 = 1024 bytes, 100 = 2048 bytes, 101 = 4096 bytes, 110 = 8192 bytes, 111 = 16384 bytes others = reserved (what others?)
UNIV_V_DGCS_RSVD23  Unused
UNIV_V_DGCS_RSVD24  Unused
UNIV_V_DGCS_CHAIN  Enable DMA chaining
UNIV_V_DGCS_RSVD28  Unused
UNIV_V_DGCS_HALT_REQ  DMA Halt Request 0 = No Effect, 1 = Halt the DMA transfer at the completion of the current command packet.
UNIV_V_DGCS_STOP_REQ  DMA Stop Request 0 = No Effect, 1 = Stop the DMA transfer when all buffered data has been written
UNIV_V_DGCS_GO  DMA Go Bit
UNIV_V_DGCS_INT_ENB_ERR  Beginning of ERR interrupt enable bits
UNIV_V_DGCS_INT_ENB_SUC  Beginning of SUC interrupt nable bits Note that this field has 1 unused bit in it
UNIV_V_DGCS_INT_ENB_ALL  Beginning of all interrupt enable bits
UNIV_V_DGCS_INT_STS_ERR  Beginning of ERR interrupt status bits
UNIV_V_DGCS_INT_STS_SUC  Beginning of SUC interrupt status bits
UNIV_V_DGCS_INT_STS_ALL  Beginning of ALL interrupt status bits
UNIV_V_DGCS_STS_ALL  Beginning of all status bits

Function Documentation

int UNIV_bus_master_set (  void    ) 
 

Ensures the UNIVERSE II is a PCI bus master.

Returns:
The original value of the PCI CSR register.
There is very little reason to use this routine. VxWorks initializes the UNIVERSE II to be a PCI bus master, so unless it has been 'unset' there is no reason to set it. It is provided only in the interest of completeness.

void UNIV_dcp_array_init (  struct _UNIV_dcp *    dcpp,
int    cnt
) 
 

Initializes an array of Universe DMA Command packets to form a circular list. Only the link field is filled in.

Parameters:
dcpp  An array of command packets.
cnt  The number of elements in the command packets.
This routine is provided only as a convenience. It will probably be used as an example for the user to write his own initialization.

void UNIV_dcp_complete (  struct _UNIV_dcp *    dcpp,
unsigned int    dctl,
unsigned int    vmeAdr,
unsigned char *    lclAdr,
int    nbytes
) 
 

Complete the DMA Command Packet, ie finishes the job UNIV_dcp_array_init started.

Parameters:
dcpp  Pointer the the DMA Command Packet to complete.
dctl  The DCTL control word.
vmeAdr  The VME address
lclAdr  The local address
nbytes  The number of bytes to transfer.
This completes the DMA command packet. The attributes of the transfer, ie, the direction, the datawidth, the VME address space, etc. are all controlled by the DCTL control word.

unsigned int UNIV_DCPP_read (  void    ) 
 

Reads the DCPP register, (Command Packet Pointer).

Returns:
The read value.

void UNIV_DCPP_write (  const struct _UNIV_dcp *    dcpp ) 
 

Write the DCPP register with the head of a DMA linked list.

Parameters:
dcpp  The DMA linked list head.

unsigned int UNIV_DGCS_bclr (  unsigned int    bitsToClr ) 
 

Clears the specified bits in the DGCS register, (General Control/Status Register).

Parameters:
bitsToClr  The value to write.
Returns:
The original value before modification.
Clears the specified bits. This implements the following pseudocode 

       *adr &= ~bitsToClr;

Warning:
This is not done in an indivisible manner.

unsigned int UNIV_DGCS_bmod (  unsigned int    modMsk,
unsigned int    value
) 
 

Modifies a selected set of bits in the DGCS register.

Parameters:
modMsk  Which bits to modify.
value  The new values.
Returns:
The original value before modification.
Warning:
This is not done in an indivisible manner.

unsigned int UNIV_DGCS_bset (  unsigned int    bitsToSet ) 
 

Sets the specified bits in the DGCS register.

Parameters:
bitsToSet  The set mask. Bits set to 1 are set.
Returns:
The original value before the bits are set.
Sets the specified bits. This implements the following pseudocode 

       *adr |= bitsToSet;

Warning:
This is not done in an indivisible manner.

unsigned int UNIV_DGCS_read (  void    ) 
 

Reads the DGCS register, (General Control/Status Register.

Returns:
The read value.

unsigned int UNIV_DGCS_write (  unsigned int    value ) 
 

Writes the DGCS register, (General Control/Status Register).

Parameters:
value  The value to write.

unsigned int UNIV_DTBC_read (  void    ) 
 

Reads the DTBC register, (Transfer Byte Count).

Returns:
The read value.

void UNIV_DTBC_write (  unsigned int    byteCount ) 
 

Writes the DTBC register, (Transfer Byte Count).

Parameters:
byteCount  The value of the transfer byte counter.

unsigned int UNIV_go (  void    ) 
 

Initiates a start on on a DMA operation by hitting to GO bit in the DGCS register.

Returns:
The original value of the DGCS register before the GO bit was set.

void UNIV_go_at (  struct _UNIV_dcp *    head ) 
 

This initiates a chain UNIV transfer by the Universe at the specified command head.

Parameters:
head  Pointer to the head of the linked list of command packets.
This initiates a chain UNIV transfer by the Universe at the specified command head. It is assumed that the linked list has been programmed and is properly terminated. After the transfer count is cleared and the head of the command packet is placed in the Command Packet Pointer register, the GO bit is set. An EIEIO instruction should be performed right before the GO bit is set to ensure that the previous two writes have been flushed to the UNIV registers.

It is recommended that this function, rather the combination be used, since this function avoids unnecessary EIEIO's.

int UNIV_int_connect (  unsigned int    which,
UNIV_isr    routine,
void *    parameter
) 
 

Connects a ISR routine to service the UNIVERSET II interrupts.

Parameters:
which  A bit mask of which interrupts to service.
routine  The interrupt service routine. The callback signature is defined by the typedef UNIV_isr and is
                       void (*isr_routine) (void *parameter)
Parameters:
parameter  A user supplied parameter passed transparently through to the ISR routine.
Returns:
Status.
Except in very simple cases, any realistic implementation will connect to all possible sources. A layer of software will then have to be written to handle the dispatching of the interrupts to correct user.

A possible model is a QIO model, where the user submits IO requests to a central 'driver'. The IOs are placed on a que and the driver services them one by one. Part of the IO information would be a user supplied callback routine to handle the asynchronous completion.

The which parameter enable the sources on the Universe to generate interrupts. These are from the set 

          UNIV_M_DGCS_INT_P_ERR
          UNIV_M_DGCS_INT_VERR
          UNIV_M_DGCS_INT_LERR
          UNIV_M_DGCS_INT_DONE
          UNIV_M_DGCS_INT_HALT
          UNIV_M_DGCS_INT_STOP

These indicate which sources this particular ISR is willing to service.

int UNIV_int_disable (  void    ) 
 

Disables delivery of interrupts from the UNIVERSE II.

Returns:
Status

int UNIV_int_enable (  void    ) 
 

Enables delivery of interrupts from the UNIVERSE II.

Returns:
Status

unsigned int UNIV_request_halt (  void    ) 
 

Request a halt on an ongoing DMA operation.

Returns:
The original value of the DGCS register before the HALT_REQ bit was set.
A HALT request is honored at the end of processing a DMA packet. The UNIVERSE II User's manual (p 2-90) states:

"Linked-list operation can be halted by setting the HALT_REQ bit in the DGCS register. When the HALT_REG bit is set, the DMA terminates when all transfers defined by the current command packet is complete. It then load the next command packtet into its registers. The HALT bit in the DGCS register is asserted, and the ACT bit in the DGCS register is cleared. The PROCESSED bit in the linked-list is set to "1" approximately 1us after the HALT bit is set: therefore after a DMA halt the user should wait at least 1us before checking the PROCESSED bit."

"The DMA can be restarted by clearing the HALT status bit and setting the GO bit if desired during the same register write. If the DMA is restarted, the ACT is set by the Universe II and execution continues as if no HALT had occurred: i.e. the Universe II processes the current command packet."

Note that the HALT is done as an asynchronous operation, it is merely a request to HALT. The user must wait till the halt is actually done by either fielding the HALT interrupt or polling the HALTED status bit.

unsigned int UNIV_request_stop (  void    ) 
 

Request a stop on an ongoing DMA operation.

Returns:
The original value of the DGCS register before the STOP_REQ bit was set.
A STOP request waits until all buffered data is written. The Universe II User's manual (page 2-90) states:

"In contrast to a HALT, the DMA can also be immediately terminated through the STOP_REQ bit. This will stop all DMA operations on the source bus immediately, and set the STOP bit in the same register when the last piece of queued data in the DMA FIFO has been written to the destination bus."

"Once stopped the DVA, DLA and DTBC registers contain values indicating the addresses to read/write and the number of bytes remaining in the transfer. Clearing the STOP bit and setting the GO bit will cause the DMA to start up agian from where it left off, including continuing with subsequent command packets in the list."

Note that the STOP is done as an asynchronous operation, it is merely a request to STOP. The user must wait till the halt is actually done by either fielding the STOP interrupt or polling the HALTED status bit.

Generated on Fri Mar 1 18:14:52 2002 by doxygen1.2.13.1 written by Dimitri van Heesch, © 1997-2001