#include "BTU/TEM_ids.h"
#include "BTU/TEM_temInt.h"
Defines | |
| #define | BFI_V_INTSRC(_tem, _src) (BFI_V_INT_SRC_ ## _tem + TEM_V_TEM_INT_SRC_ ##_src - 1) |
| Internal macro to generate the names of each interrupt in the global interrupt mask. | |
| #define | BFI_M_INTSRC(_tem, _src) (1 << BFI_V_INT_SRC_##_tem##_##_src) |
| Internal macro to generate the names of each interrupt, as a mask, in the global interrupt mask. | |
| #define | BFI_M_INTERRSRCTEM(_tem, _src) (1 << BFI_V_INT_ERR_SRC_##_tem##_##_src) |
| Internal macro to generate the names of each interrupt in the global error source interrupt mask. | |
Typedefs | |
| typedef enum _BFI_V_intSrc | BFI_V_intSrc |
| Typedef for enum _BFI_V_int. More... | |
| typedef enum _BFI_M_intSrc | BFI_M_intSrc |
| Typedef for enum _BFI_intSrcMsk. More... | |
| typedef enum _BFI_V_intSrcTem | BFI_V_intSrcTem |
| Typedef for enum _BFI_V_intSrcTem. More... | |
| typedef enum _BFI_M_intSrcTem | BFI_M_intSrcTem |
| Typedef for enum _BFI_M_intSrcTem. More... | |
| typedef enum _BFI_V_intSrcGbl | BFI_V_intSrcGbl |
| Typedef for enum _BFI_intSrcGbl. | |
| typedef enum _BFI_M_intSrcGbl | BFI_M_intSrcGbl |
| Typedef for enum _BFI_MintSrcGbl. | |
| typedef enum _BFI_V_intErrSrcTem | BFI_V_intErrSrcTem |
| Typedef for enum _BFI_V_intErrSrcGbl. | |
| typedef enum _BFI_M_intErrSrcTem | BFI_M_intErrSrcTem |
| Typedef for enum _BFI_M_intErrSrcTem. More... | |
| typedef int | BFI_group |
| Typedef to hide the implementation type of a BFI_group. | |
Enumerations | |
| enum | _BFI_V_intSrc { BFI_V_INT_SRC_ERROR = (TEM_V_TEM_INT_SRC_ERROR - 1), BFI_V_INT_SRC_HFIFO = (TEM_V_TEM_INT_SRC_HFIFO - 1), BFI_V_INT_SRC_L1T = (TEM_V_TEM_INT_SRC_L1T - 1), BFI_V_INT_SRC_HSK = (TEM_V_TEM_INT_SRC_HSK - 1), BFI_K_INT_SRC_CNT = (TEM_K_TEM_INT_SRC_CNT) } |
| Defines the bit positions of each TEM interrupt. More... | |
| enum | _BFI_M_intSrc { BFI_M_INT_SRC_ERROR = (1 << BFI_V_INT_SRC_ERROR), BFI_M_INT_SRC_HFIFO = (1 << BFI_V_INT_SRC_HFIFO), BFI_M_INT_SRC_L1T = (1 << BFI_V_INT_SRC_L1T), BFI_M_INT_SRC_HSK = (1 << BFI_V_INT_SRC_HSK), BFI_M_INT_SRC_ALL = (1 << BFI_K_INT_SRC_CNT) - 1 } |
| Defines the masks of each TEM interrupt. More... | |
| enum | _BFI_V_intSrcTem { BFI_V_INT_SRC_ACD = (BFI_K_INT_SRC_CNT * TEM_C_ACD), BFI_V_INT_SRC_TKR = (BFI_K_INT_SRC_CNT * TEM_C_TKR), BFI_V_INT_SRC_CAL = (BFI_K_INT_SRC_CNT * TEM_C_CAL), BFI_V_INT_SRC_LTC = (BFI_K_INT_SRC_CNT * TEM_C_LTC), BFI_K_INT_SRC_TEMS = (BFI_K_INT_SRC_CNT * TEM_C_CNT) } |
| Defines the bit positions for the start of each set of TEM interrupts within the global interrupt mask. More... | |
| enum | _BFI_M_intSrcTem { BFI_M_INT_SRC_ACD = (BFI_M_INT_SRC_ALL << BFI_V_INT_SRC_ACD), BFI_M_INT_SRC_TKR = (BFI_M_INT_SRC_ALL << BFI_V_INT_SRC_TKR), BFI_M_INT_SRC_CAL = (BFI_M_INT_SRC_ALL << BFI_V_INT_SRC_CAL), BFI_M_INT_SRC_LTC = (BFI_M_INT_SRC_ALL << BFI_V_INT_SRC_LTC), BFI_M_INT_SRC_TEMS } |
| Defines the masks for each set of TEM interrupts within the global interrupt mask. | |
| enum | _BFI_V_intSrcGbl { BFI_V_INT_SRC_ACD_ERROR = BFI_V_INTSRC(ACD, ERROR), BFI_V_INT_SRC_ACD_HFIFO = BFI_V_INTSRC(ACD, HFIFO), BFI_V_INT_SRC_ACD_L1T = BFI_V_INTSRC(ACD, L1T), BFI_V_INT_SRC_ACD_HSK = BFI_V_INTSRC(ACD, HSK), BFI_V_INT_SRC_TKR_ERROR = BFI_V_INTSRC(TKR, ERROR), BFI_V_INT_SRC_TKR_HFIFO = BFI_V_INTSRC(TKR, HFIFO), BFI_V_INT_SRC_TKR_L1T = BFI_V_INTSRC(TKR, L1T), BFI_V_INT_SRC_TKR_HSK = BFI_V_INTSRC(TKR, HSK), BFI_V_INT_SRC_CAL_ERROR = BFI_V_INTSRC(CAL, ERROR), BFI_V_INT_SRC_CAL_HFIFO = BFI_V_INTSRC(CAL, HFIFO), BFI_V_INT_SRC_CAL_L1T = BFI_V_INTSRC(CAL, L1T), BFI_V_INT_SRC_CAL_HSK = BFI_V_INTSRC(CAL, HSK), BFI_V_INT_SRC_LTC_ERROR = BFI_V_INTSRC(LTC, ERROR), BFI_V_INT_SRC_LTC_HFIFO = BFI_V_INTSRC(LTC, HFIFO), BFI_V_INT_SRC_LTC_L1T = BFI_V_INTSRC(LTC, L1T), BFI_V_INT_SRC_LTC_HSK = BFI_V_INTSRC(LTC, HSK), BFI_K_INT_SRC_TEM_CNT = BFI_V_INT_SRC_LTC_HSK+1, BFI_V_INT_SRC_SOFT_BASE = BFI_K_INT_SRC_TEM_CNT, BFI_K_INT_SRC_SOFT_CNT = 31 - BFI_V_INT_SRC_SOFT_BASE, BFI_V_INT_SRC_TO = 31 } |
| Defines the bit position for each interrupt source within the global interrupt mask. More... | |
| enum | _BFI_M_intSrcGbl { BFI_M_INT_SRC_ACD_ERROR = BFI_M_INTSRC(ACD, ERROR), BFI_M_INT_SRC_ACD_HFIFO = BFI_M_INTSRC(ACD, HFIFO), BFI_M_INT_SRC_ACD_L1T = BFI_M_INTSRC(ACD, L1T), BFI_M_INT_SRC_ACD_HSK = BFI_M_INTSRC(ACD, HSK), BFI_M_INT_SRC_TKR_ERROR = BFI_M_INTSRC(TKR, ERROR), BFI_M_INT_SRC_TKR_HFIFO = BFI_M_INTSRC(TKR, HFIFO), BFI_M_INT_SRC_TKR_L1T = BFI_M_INTSRC(TKR, L1T), BFI_M_INT_SRC_TKR_HSK = BFI_M_INTSRC(TKR, HSK), BFI_M_INT_SRC_CAL_ERROR = BFI_M_INTSRC(CAL, ERROR), BFI_M_INT_SRC_CAL_HFIFO = BFI_M_INTSRC(CAL, HFIFO), BFI_M_INT_SRC_CAL_L1T = BFI_M_INTSRC(CAL, L1T), BFI_M_INT_SRC_CAL_HSK = BFI_M_INTSRC(CAL, HSK), BFI_M_INT_SRC_LTC_ERROR = BFI_M_INTSRC(LTC, ERROR), BFI_M_INT_SRC_LTC_HFIFO = BFI_M_INTSRC(LTC, HFIFO), BFI_M_INT_SRC_LTC_L1T = BFI_M_INTSRC(LTC, L1T), BFI_M_INT_SRC_LTC_HSK = BFI_M_INTSRC(LTC, HSK), BFI_M_INT_SRC_TEM_ALL = (1<<BFI_K_INT_SRC_TEM_CNT)-1, BFI_M_INT_SRC_SOFT_BASE = (1<<BFI_V_INT_SRC_SOFT_BASE), BFI_M_INT_SRC_SOFT_ALL, BFI_M_INT_SRC_TO = (1 << BFI_V_INT_SRC_TO) } |
| Defines the masks for each interrupt source within the global interrupt mask. More... | |
| enum | _BFI_V_intErrSrcTem { BFI_V_INT_ERR_SRC_ACD_DFIFO = 0, BFI_V_INT_ERR_SRC_ACD_RDOBSY = 1, BFI_V_INT_ERR_SRC_ACD_RDOLNGBSY = 2, BFI_V_INT_ERR_SRC_ACD_RDOTMOUT = 3, BFI_V_INT_ERR_SRC_TKR_DFIFO = 4, BFI_V_INT_ERR_SRC_TKR_RDOTMOUT = 5, BFI_V_INT_ERR_SRC_TKR_8DEEP = 6, BFI_V_INT_ERR_SRC_TKR_CABLE = 7, BFI_V_INT_ERR_SRC_CAL_DFIFO = 8, BFI_V_INT_ERR_SRC_CAL_RDOBSY = 9, BFI_V_INT_ERR_SRC_CAL_RDOLNGBSY = 10, BFI_V_INT_ERR_SRC_CAL_RDOTMOUT = 11, BFI_V_INT_ERR_SRC_LTC_DFIFO = 12, BFI_V_INT_ERR_SRC_L1T_DFIFO = 13 } |
| Defines the bit positions of each TEM error interrupt source. More... | |
| enum | _BFI_M_intErrSrcTem { BFI_M_INT_ERR_SRC_ACD_DFIFO = BFI_M_INTERRSRCTEM(ACD, DFIFO), BFI_M_INT_ERR_SRC_ACD_RDOBSY = BFI_M_INTERRSRCTEM(ACD, RDOBSY), BFI_M_INT_ERR_SRC_ACD_RDOLNGBSY = BFI_M_INTERRSRCTEM(ACD, RDOLNGBSY), BFI_M_INT_ERR_SRC_ACD_RDOTMOUT = BFI_M_INTERRSRCTEM(ACD, RDOTMOUT), BFI_M_INT_ERR_SRC_TKR_DFIFO = BFI_M_INTERRSRCTEM(TKR, DFIFO), BFI_M_INT_ERR_SRC_TKR_8DEEP = BFI_M_INTERRSRCTEM(TKR, 8DEEP), BFI_M_INT_ERR_SRC_TKR_CABLE = BFI_M_INTERRSRCTEM(TKR, CABLE), BFI_M_INT_ERR_SRC_TKR_RDOTMOUT = BFI_M_INTERRSRCTEM(TKR, RDOTMOUT), BFI_M_INT_ERR_SRC_CAL_DFIFO = BFI_M_INTERRSRCTEM(CAL, DFIFO), BFI_M_INT_ERR_SRC_CAL_RDOBSY = BFI_M_INTERRSRCTEM(CAL, RDOBSY), BFI_M_INT_ERR_SRC_CAL_RDOLNGBSY = BFI_M_INTERRSRCTEM(CAL, RDOLNGBSY), BFI_M_INT_ERR_SRC_CAL_RDOTMOUT = BFI_M_INTERRSRCTEM(CAL, RDOTMOUT), BFI_M_INT_ERR_SRC_LTC_DFIFO = BFI_M_INTERRSRCTEM(LTC, DFIFO), BFI_M_INT_ERR_SRC_L1T_DFIFO = BFI_M_INTERRSRCTEM(L1T, DFIFO) } |
| Defines the TEM error interrupt sources in terms of a bit mask. More... | |
Functions | |
| int | BFI_connect (void) |
| Connects all interrupts to their specified handlers. More... | |
| unsigned int | BFI_evtThresholdsSet (unsigned int temList, const unsigned int *thresholds) |
| Sets the event threshold for the specified set of TEMS. More... | |
| unsigned int | BFI_errorsGather (unsigned int irpts) |
| Returns a 32 bit mask with the reason for the error interrupts decoded. More... | |
| BFI_group | BFI_groupAdd (unsigned int irpts) |
| Defines a group to consist of the specified list of interrupts to service. More... | |
| unsigned int | BFI_groupDisable (BFI_group group, unsigned int disableInts) |
| Disables the specified list of interrupts for the specified group. More... | |
| unsigned int | BFI_groupEnable (BFI_group group, unsigned int enableInts) |
| Disables the specified list of interrupts for the specified group. More... | |
| unsigned int | BFI_groupPend (BFI_group group, int timeout) |
| Waits for the firing of any interrupt associated with the specified synchronization group. More... | |
| int | BFI_groupSignal (BFI_group group, unsigned int irpts) |
| Allows one to set a soft interrupt on the specified synchronization group. More... | |
| unsigned int | BFI_init (const struct _BFM_dsc *bfm, unsigned int temList, const unsigned int *levels, const unsigned int *base) |
| Initializes the system service context. Each active TEM has an interrupt level and a base vector assigned to it. More... | |
| unsigned int | BFI_masterDisable (unsigned int temList) |
| Disables the master interrupt enable for the specified list of TEMs. More... | |
| unsigned int | BFI_masterEnable (unsigned int temList) |
| Enables the master interrupt enable for the specified list of TEMs. More... | |
| unsigned int | BFI_masterReset (unsigned int temList) |
| Reset the master interrupt enable for the specified list of TEMs. This effectively clears all pending interrupts. More... | |
| int | BFI_minEventsGet (unsigned int temList, unsigned int *nevts) |
| Returns the minimum number of events pending from the specified list of tems, ie temList. More... | |
| unsigned int | BFI_trim (unsigned int temList, unsigned int intList) |
| Convenience routine to trim the interrupt sources associated with unused TEMs from the list. More... | |
| unsigned int | BFI_vmeDisable (unsigned int temList) |
| Disables the VME interrupt for the specified list of TEMs. More... | |
| unsigned int | BFI_vmeEnable (unsigned int temList) |
| Enables the VME interrupt for the specified list of TEMs. More... | |
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Typedef for enum _BFI_M_intErrSrcTem.
The error interrrupt from each TEM can be due to a variety of reasons. Some, such as the data FIFO overflow are common to all TEMs. Others are specific to an individual TEM. While the interrupt is delivered on a TEM-by-TEM basis, the source of the interrupts maps more closely with a data source, ie a TEM. Except for the LTC, 4 bits are used for each source. (Needed to save space.) |
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Typedef for enum _BFI_intSrcMsk.
These are the masks for each TEM interrupt. See BFI_V_intSrc for the corresponding bit positions The global interrupt mask consists of a set of these 4 interrupts for each TEM. The sets are laid out in order, by TEM id, ie ACD first, then TKR, then CAL, and finally LTC. See _BFI_intSrcTem for these definitions. |
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Typedef for enum _BFI_M_intSrcTem.
These are the mask for each TEM interrupt. See BFI_V_intSrcTem for the corresponding masks. The global interrupt mask consists of two collections of interrupt sources. The first of these sets of consists of the 4 interrupts (ERR, L1T, HFULL, PPS) for each TEM. The sets are laid out in order, by TEM id, ie ACD, first, then TKR, then CAL, and finally LTC. These occupy the lower 16 bits of the interrupt source mask. (Of course, no programmer will every refer to these sources by number, they will use the symbolics.) The upper 16 bits consist of a set of soft interrupts. These used to allow software signals to be set and handled in much the same manner as the hardware signals. For example, one could define a group to pend on all the hardware interrupts related to event taking (L1T, HFULL, ERR) and also to define a soft interrrupt which would deliver a run control message. The user could then pend on this group and, by examining the interrupt mask, make a decision on what to do, take more events or stop the run. |
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Typedef for enum _BFI_V_int.
These are the bit positions for each TEM interrupt. See BFI_M_intSrc for the corresponding mask definitions. The global interrupt mask consists of a set of these 4 interrupts for each TEM. The sets are laid out in order, by TEM id, ie ACD first, then TKR, then CAL, and finally LTC. See _BFI_intSrcTem for these definitions. |
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Typedef for enum _BFI_V_intSrcTem.
These are the starting bit positions for each TEM interrupts. See BFI_M_intSrcTemMsk for the corresponding masks. The global interrupt mask consists of a set of these 4 interrupts for each TEM. The sets are laid out in order, by TEM id, ie ACD first, then TKR, then CAL, and finally LTC. |
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Defines the masks of each TEM interrupt.
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Defines the masks for each interrupt source within the global interrupt mask.
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Defines the bit positions of each TEM error interrupt source.
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Defines the bit positions of each TEM interrupt.
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Defines the bit position for each interrupt source within the global interrupt mask.
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Defines the bit positions for the start of each set of TEM interrupts within the global interrupt mask.
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Connects all interrupts to their specified handlers.
1. The ID of the TEM to service.
2. The bit mask of interrupts that need servicing
3. The bit mask of group ids that perform the servicing.
All active interrupts must have one and only one group associated with them.
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Returns a 32 bit mask with the reason for the error interrupts decoded.
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Sets the event threshold for the specified set of TEMS.
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Defines a group to consist of the specified list of interrupts to service.
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Disables the specified list of interrupts for the specified group.
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Disables the specified list of interrupts for the specified group.
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Waits for the firing of any interrupt associated with the specified synchronization group.
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Allows one to set a soft interrupt on the specified synchronization group.
One could have implemented a different scheme where a software interrupt was associated with one and only one group, but there seemed to be no real advantage and it was more complicated. The only advantage I could think of was if the same soft interrupt was associated with multiple groups, allowing a kind of broadcast wake-up capability. This was an interesting idea, but did not mirror the usage of hard interrupts being constrained to be connected with only one group. Currently the only failure mode is if the semGive fails. If one specifies interrupts other than soft interrupts, they are quietly pitched on the ground, that is only the soft interrupts in the irpts will be signalled, any other bits are ignored. |
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Initializes the system service context. Each active TEM has an interrupt level and a base vector assigned to it.
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Disables the master interrupt enable for the specified list of TEMs.
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Enables the master interrupt enable for the specified list of TEMs.
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Reset the master interrupt enable for the specified list of TEMs. This effectively clears all pending interrupts.
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Returns the minimum number of events pending from the specified list of tems, ie temList.
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Convenience routine to trim the interrupt sources associated with unused TEMs from the list.
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Disables the VME interrupt for the specified list of TEMs.
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Enables the VME interrupt for the specified list of TEMs.
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1.2.14 written by Dimitri van Heesch,
© 1997-2002