QICK running on ZCU216, software version 0.2.376 Firmware configuration (built Wed Nov 26 17:13:27 2025): Global clocks (MHz): tProc dispatcher timing 430.080, RF reference 245.760 Groups of related clocks: [tProc core clock, tProc timing clock, DAC tile 0, DAC tile 1, DAC tile 2, DAC tile 3], [ADC tile 1, ADC tile 2] 16 signal generator channels: 0: axis_signal_gen_v6 - fs=6881.280 Msps, fabric=430.080 MHz envelope memory: 16384 real samples (2.381 us) 32-bit DDS, range=6881.280 MHz DAC tile 0, blk 0 is 0_228 on JHC1, or QICK box DAC port 0 1: axis_signal_gen_v6 - fs=6881.280 Msps, fabric=430.080 MHz envelope memory: 16384 real samples (2.381 us) 32-bit DDS, range=6881.280 MHz DAC tile 0, blk 1 is 1_228 on JHC2, or QICK box DAC port 1 2: axis_signal_gen_v6 - fs=6881.280 Msps, fabric=430.080 MHz envelope memory: 16384 real samples (2.381 us) 32-bit DDS, range=6881.280 MHz DAC tile 0, blk 2 is 2_228 on JHC1, or QICK box DAC port 2 3: axis_signal_gen_v6 - fs=6881.280 Msps, fabric=430.080 MHz envelope memory: 16384 real samples (2.381 us) 32-bit DDS, range=6881.280 MHz DAC tile 0, blk 3 is 3_228 on JHC2, or QICK box DAC port 3 4: axis_signal_gen_v6 - fs=6881.280 Msps, fabric=430.080 MHz envelope memory: 16384 real samples (2.381 us) 32-bit DDS, range=6881.280 MHz DAC tile 1, blk 0 is 0_229 on JHC1, or QICK box DAC port 4 5: axis_signal_gen_v6 - fs=6881.280 Msps, fabric=430.080 MHz envelope memory: 16384 real samples (2.381 us) 32-bit DDS, range=6881.280 MHz DAC tile 1, blk 1 is 1_229 on JHC2, or QICK box DAC port 5 6: axis_signal_gen_v6 - fs=6881.280 Msps, fabric=430.080 MHz envelope memory: 16384 real samples (2.381 us) 32-bit DDS, range=6881.280 MHz DAC tile 1, blk 2 is 2_229 on JHC1, or QICK box DAC port 6 7: axis_signal_gen_v6 - fs=6881.280 Msps, fabric=430.080 MHz envelope memory: 16384 real samples (2.381 us) 32-bit DDS, range=6881.280 MHz DAC tile 1, blk 3 is 3_229 on JHC2, or QICK box DAC port 7 8: axis_signal_gen_v6 - fs=6881.280 Msps, fabric=430.080 MHz envelope memory: 16384 real samples (2.381 us) 32-bit DDS, range=6881.280 MHz DAC tile 2, blk 0 is 0_230 on JHC3, or QICK box DAC port 8 9: axis_signal_gen_v6 - fs=6881.280 Msps, fabric=430.080 MHz envelope memory: 16384 real samples (2.381 us) 32-bit DDS, range=6881.280 MHz DAC tile 2, blk 1 is 1_230 on JHC4, or QICK box DAC port 9 10: axis_signal_gen_v6 - fs=6881.280 Msps, fabric=430.080 MHz envelope memory: 16384 real samples (2.381 us) 32-bit DDS, range=6881.280 MHz DAC tile 2, blk 2 is 2_230 on JHC3, or QICK box DAC port 10 11: axis_signal_gen_v6 - fs=6881.280 Msps, fabric=430.080 MHz envelope memory: 16384 real samples (2.381 us) 32-bit DDS, range=6881.280 MHz DAC tile 2, blk 3 is 3_230 on JHC4, or QICK box DAC port 11 12: axis_signal_gen_v6 - fs=6881.280 Msps, fabric=430.080 MHz envelope memory: 16384 real samples (2.381 us) 32-bit DDS, range=6881.280 MHz DAC tile 3, blk 0 is 0_231 on JHC3, or QICK box DAC port 12 13: axis_signal_gen_v6 - fs=6881.280 Msps, fabric=430.080 MHz envelope memory: 16384 real samples (2.381 us) 32-bit DDS, range=6881.280 MHz DAC tile 3, blk 1 is 1_231 on JHC4, or QICK box DAC port 13 14: axis_signal_gen_v6 - fs=6881.280 Msps, fabric=430.080 MHz envelope memory: 16384 real samples (2.381 us) 32-bit DDS, range=6881.280 MHz DAC tile 3, blk 2 is 2_231 on JHC3, or QICK box DAC port 14 15: axis_signal_gen_v6 - fs=6881.280 Msps, fabric=430.080 MHz envelope memory: 16384 real samples (2.381 us) 32-bit DDS, range=6881.280 MHz DAC tile 3, blk 3 is 3_231 on JHC4, or QICK box DAC port 15 8 readout channels: 0: axis_dyn_readout_v1 - configured by tProc output 15 fs=2457.600 Msps, decimated=307.200 MHz, 32-bit DDS, range=2457.600 MHz axis_avg_buffer v1.2 (has edge counter, no weights) memory 4096 accumulated, 4096 decimated (13.333 us) triggered by tport 10, pin 0, feedback to tProc input 0 ADC tile 1, blk 0 is 0_225 on JHC5, or QICK box ADC port 0 1: axis_dyn_readout_v1 - configured by tProc output 15 fs=2457.600 Msps, decimated=307.200 MHz, 32-bit DDS, range=2457.600 MHz axis_avg_buffer v1.2 (has edge counter, no weights) memory 4096 accumulated, 4096 decimated (13.333 us) triggered by tport 11, pin 0, feedback to tProc input 1 ADC tile 1, blk 1 is 1_225 on JHC6, or QICK box ADC port 1 2: axis_dyn_readout_v1 - configured by tProc output 15 fs=2457.600 Msps, decimated=307.200 MHz, 32-bit DDS, range=2457.600 MHz axis_avg_buffer v1.2 (has edge counter, no weights) memory 4096 accumulated, 4096 decimated (13.333 us) triggered by tport 12, pin 0, feedback to tProc input 2 ADC tile 1, blk 2 is 2_225 on JHC5, or QICK box ADC port 2 3: axis_dyn_readout_v1 - configured by tProc output 15 fs=2457.600 Msps, decimated=307.200 MHz, 32-bit DDS, range=2457.600 MHz axis_avg_buffer v1.2 (has edge counter, no weights) memory 4096 accumulated, 4096 decimated (13.333 us) triggered by tport 13, pin 0, feedback to tProc input 3 ADC tile 1, blk 3 is 3_225 on JHC6, or QICK box ADC port 3 4: axis_dyn_readout_v1 - configured by tProc output 15 fs=2457.600 Msps, decimated=307.200 MHz, 32-bit DDS, range=2457.600 MHz axis_avg_buffer v1.2 (has edge counter, no weights) memory 4096 accumulated, 4096 decimated (13.333 us) triggered by tport 14, pin 0, feedback to tProc input 4 ADC tile 2, blk 0 is 0_226 on JHC7, or QICK box ADC port 4 5: axis_dyn_readout_v1 - configured by tProc output 15 fs=2457.600 Msps, decimated=307.200 MHz, 32-bit DDS, range=2457.600 MHz axis_avg_buffer v1.2 (has edge counter, no weights) memory 4096 accumulated, 4096 decimated (13.333 us) triggered by tport 5, pin 0, feedback to tProc input 5 ADC tile 2, blk 1 is 1_226 on JHC8, or QICK box ADC port 5 6: axis_dyn_readout_v1 - configured by tProc output 15 fs=2457.600 Msps, decimated=307.200 MHz, 32-bit DDS, range=2457.600 MHz axis_avg_buffer v1.2 (has edge counter, no weights) memory 4096 accumulated, 4096 decimated (13.333 us) triggered by tport 6, pin 0, feedback to tProc input 6 ADC tile 2, blk 2 is 2_226 on JHC7, or QICK box ADC port 6 7: axis_dyn_readout_v1 - configured by tProc output 15 fs=2457.600 Msps, decimated=307.200 MHz, 32-bit DDS, range=2457.600 MHz axis_avg_buffer v1.2 (has edge counter, no weights) memory 4096 accumulated, 4096 decimated (13.333 us) triggered by tport 7, pin 0, feedback to tProc input 7 ADC tile 2, blk 3 is 3_226 on JHC8, or QICK box ADC port 7 5 digital output pins: 0: SPARE0_1V8 1: SPARE1_1V8 2: SPARE2_1V8 3: SPARE3_1V8 4: SPARE4_1V8 tProc: qick_processor ("v2") rev 27, core execution clock 215.040 MHz memories (words): program 4096, data 16384, waveform 1024 external start pin: SPARE5_1V8 external stop pin: None DDR4 memory buffer: 1073741824 samples (3.495 sec), 128 samples/transfer wired to readouts [0, 1, 2, 3, 4, 5, 6, 7] MR buffer: 8192 samples (3.333 us), wired to readouts [0, 1, 2, 3, 4, 5, 6, 7]