Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version      : Vivado v.2023.1 (lin64) Build 3865809 Sun May  7 15:04:56 MDT 2023
| Date              : Mon Aug 11 15:42:56 2025
| Host              : linux-139028 running 64-bit Debian GNU/Linux 12 (bookworm)
| Command           : report_timing_summary -max_paths 10 -report_unconstrained -file d_1_wrapper_timing_summary_routed.rpt -pb d_1_wrapper_timing_summary_routed.pb -rpx d_1_wrapper_timing_summary_routed.rpx -warn_on_violation
| Design            : d_1_wrapper
| Device            : xczu28dr-ffvg1517
| Speed File        : -2  PRODUCTION 1.30 05-03-2022
| Design State      : Routed
| Temperature Grade : E
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

Timing Summary Report

------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------

  Enable Multi Corner Analysis               :  Yes
  Enable Pessimism Removal                   :  Yes
  Pessimism Removal Resolution               :  Nearest Common Node
  Enable Input Delay Default Clock           :  No
  Enable Preset / Clear Arcs                 :  No
  Disable Flight Delays                      :  No
  Ignore I/O Paths                           :  No
  Timing Early Launch at Borrowing Latches   :  No
  Borrow Time for Max Delay Exceptions       :  Yes
  Merge Timing Exceptions                    :  Yes

  Corner  Analyze    Analyze    
  Name    Max Paths  Min Paths  
  ------  ---------  ---------  
  Slow    Yes        Yes        
  Fast    Yes        Yes        


------------------------------------------------------------------------------------------------
| Report Methodology
| ------------------
------------------------------------------------------------------------------------------------

Rule       Severity  Description                                 Violations  
---------  --------  ------------------------------------------  ----------  
DPIR-2     Warning   Asynchronous driver check                   384         
LUTAR-1    Warning   LUT drives async reset alert                3           
TIMING-9   Warning   Unknown CDC Logic                           1           
TIMING-10  Warning   Missing property on synchronizer            1           
TIMING-18  Warning   Missing input or output delay               8           
TIMING-24  Warning   Overridden Max delay datapath only          18          
CLKC-56    Advisory  MMCME4 with global clock driver has no LOC  1           

Note: This report is based on the most recent report_methodology run and may not be up-to-date. Run report_methodology on the current design for the latest report.



check_timing report

Table of Contents
-----------------
1. checking no_clock (0)
2. checking constant_clock (0)
3. checking pulse_width_clock (0)
4. checking unconstrained_internal_endpoints (0)
5. checking no_input_delay (0)
6. checking no_output_delay (8)
7. checking multiple_clock (0)
8. checking generated_clocks (0)
9. checking loops (0)
10. checking partial_input_delay (0)
11. checking partial_output_delay (0)
12. checking latch_loops (0)

1. checking no_clock (0)
------------------------
 There are 0 register/latch pins with no clock.


2. checking constant_clock (0)
------------------------------
 There are 0 register/latch pins with constant_clock.


3. checking pulse_width_clock (0)
---------------------------------
 There are 0 register/latch pins which need pulse_width check


4. checking unconstrained_internal_endpoints (0)
------------------------------------------------
 There are 0 pins that are not constrained for maximum delay.

 There are 0 pins that are not constrained for maximum delay due to constant clock.


5. checking no_input_delay (0)
------------------------------
 There are 0 input ports with no input delay specified.

 There are 0 input ports with no input delay but user has a false path constraint.


6. checking no_output_delay (8)
-------------------------------
 There are 8 ports with no output delay specified. (HIGH)

 There are 0 ports with no output delay but user has a false path constraint

 There are 0 ports with no output delay but with a timing clock defined on it or propagating through it


7. checking multiple_clock (0)
------------------------------
 There are 0 register/latch pins with multiple clocks.


8. checking generated_clocks (0)
--------------------------------
 There are 0 generated clocks that are not connected to a clock source.


9. checking loops (0)
---------------------
 There are 0 combinational loops in the design.


10. checking partial_input_delay (0)
------------------------------------
 There are 0 input ports with partial input delay specified.


11. checking partial_output_delay (0)
-------------------------------------
 There are 0 ports with partial output delay specified.


12. checking latch_loops (0)
----------------------------
 There are 0 combinational latch loops in the design through latch input



------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------

    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
      0.459        0.000                      0               169533        0.007        0.000                      0               169533        0.420        0.000                       0                 44734  


All user specified timing constraints are met.


------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------

Clock                         Waveform(ns)         Period(ns)      Frequency(MHz)
-----                         ------------         ----------      --------------
RFADC0_CLK                    {0.000 5.000}        10.000          100.000         
RFADC0_CLK_dummy              {0.000 5.000}        10.000          100.000         
RFADC0_FABCLK0                {0.000 5.000}        10.000          100.000         
RFADC0_FABCLK1                {0.000 5.000}        10.000          100.000         
RFADC0_FABCLK2                {0.000 5.000}        10.000          100.000         
RFADC0_FABCLK3                {0.000 5.000}        10.000          100.000         
RFADC1_CLK                    {0.000 3.906}        7.812           128.008         
  clk_out1_d_1_clk_adc0_x2_0  {0.000 1.953}        3.906           256.016         
RFADC1_CLK_dummy              {0.000 3.906}        7.812           128.008         
RFADC2_CLK                    {0.000 5.000}        10.000          100.000         
RFADC2_CLK_dummy              {0.000 5.000}        10.000          100.000         
RFADC2_FABCLK0                {0.000 5.000}        10.000          100.000         
RFADC2_FABCLK1                {0.000 5.000}        10.000          100.000         
RFADC2_FABCLK2                {0.000 5.000}        10.000          100.000         
RFADC2_FABCLK3                {0.000 5.000}        10.000          100.000         
RFADC3_CLK                    {0.000 5.000}        10.000          100.000         
RFADC3_CLK_dummy              {0.000 5.000}        10.000          100.000         
RFADC3_FABCLK0                {0.000 5.000}        10.000          100.000         
RFADC3_FABCLK1                {0.000 5.000}        10.000          100.000         
RFADC3_FABCLK2                {0.000 5.000}        10.000          100.000         
RFADC3_FABCLK3                {0.000 5.000}        10.000          100.000         
RFDAC0_CLK                    {0.000 1.221}        2.441           409.668         
RFDAC1_CLK                    {0.000 5.000}        10.000          100.000         
RFDAC1_FABCLK0                {0.000 5.000}        10.000          100.000         
RFDAC1_FABCLK1                {0.000 5.000}        10.000          100.000         
RFDAC1_FABCLK2                {0.000 5.000}        10.000          100.000         
RFDAC1_FABCLK3                {0.000 5.000}        10.000          100.000         
clk_pl_0                      {0.000 5.000}        10.000          100.000         


------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------

Clock                             WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
-----                             -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
RFADC1_CLK                                                                                                                                                                      1.562        0.000                       0                     3  
  clk_out1_d_1_clk_adc0_x2_0        0.766        0.000                      0                 6110        0.011        0.000                      0                 6110        1.153        0.000                       0                  2986  
RFDAC0_CLK                          0.459        0.000                      0                24370        0.012        0.000                      0                24370        0.420        0.000                       0                  5678  
clk_pl_0                            0.630        0.000                      0               129598        0.007        0.000                      0               129598        3.400        0.000                       0                 36067  


------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------

From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  


------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------

Path Group                  From Clock                  To Clock                        WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------                  ----------                  --------                        -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  
**async_default**           RFDAC0_CLK                  RFDAC0_CLK                        0.552        0.000                      0                  196        0.142        0.000                      0                  196  
**async_default**           clk_out1_d_1_clk_adc0_x2_0  clk_out1_d_1_clk_adc0_x2_0        1.854        0.000                      0                  372        0.147        0.000                      0                  372  
**async_default**           clk_pl_0                    clk_pl_0                          0.614        0.000                      0                 8887        0.230        0.000                      0                 8887  


------------------------------------------------------------------------------------------------
| User Ignored Path Table
| -----------------------
------------------------------------------------------------------------------------------------

Path Group                  From Clock                  To Clock                  
----------                  ----------                  --------                  
(none)                                                  RFDAC0_CLK                  
(none)                      clk_pl_0                    RFDAC0_CLK                  
(none)                                                  clk_out1_d_1_clk_adc0_x2_0  
(none)                      RFDAC0_CLK                  clk_out1_d_1_clk_adc0_x2_0  
(none)                      clk_pl_0                    clk_out1_d_1_clk_adc0_x2_0  
(none)                                                  clk_pl_0                    
(none)                      RFADC0_CLK                  clk_pl_0                    
(none)                      RFADC1_CLK                  clk_pl_0                    
(none)                      RFADC2_CLK                  clk_pl_0                    
(none)                      RFADC3_CLK                  clk_pl_0                    
(none)                      RFDAC0_CLK                  clk_pl_0                    
(none)                      RFDAC1_CLK                  clk_pl_0                    
(none)                      clk_out1_d_1_clk_adc0_x2_0  clk_pl_0                    
(none)                      clk_pl_0                    clk_pl_0                    


------------------------------------------------------------------------------------------------
| Unconstrained Path Table
| ------------------------
------------------------------------------------------------------------------------------------

Path Group                  From Clock                  To Clock                  
----------                  ----------                  --------                  
(none)                      RFDAC0_CLK                                              
(none)                      clk_pl_0                                                
(none)                                                  clk_out1_d_1_clk_adc0_x2_0  
(none)                                                  clk_pl_0                    


------------------------------------------------------------------------------------------------
| Timing Details
| --------------
------------------------------------------------------------------------------------------------


---------------------------------------------------------------------------------------------------
From Clock:  RFADC1_CLK
  To Clock:  RFADC1_CLK

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        1.562ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         RFADC1_CLK
Waveform(ns):       { 0.000 3.906 }
Period(ns):         7.812
Sources:            { d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX }

Check Type        Corner  Lib Pin            Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location       Pin
Min Period        n/a     HSADC/CLK_ADC      n/a            1.923         7.812       5.889      HSADC_X0Y1     d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
Min Period        n/a     BUFG_GT/I          n/a            1.290         7.812       6.522      BUFG_GT_X1Y27  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
Min Period        n/a     MMCME4_ADV/CLKIN1  n/a            1.071         7.812       6.741      MMCM_X0Y7      d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
Max Period        n/a     MMCME4_ADV/CLKIN1  n/a            100.000       7.812       92.188     MMCM_X0Y7      d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
Low Pulse Width   Slow    MMCME4_ADV/CLKIN1  n/a            2.344         3.906       1.562      MMCM_X0Y7      d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
Low Pulse Width   Fast    MMCME4_ADV/CLKIN1  n/a            2.344         3.906       1.562      MMCM_X0Y7      d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
Low Pulse Width   Slow    HSADC/CLK_ADC      n/a            0.800         3.906       3.106      HSADC_X0Y1     d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
Low Pulse Width   Fast    HSADC/CLK_ADC      n/a            0.800         3.906       3.106      HSADC_X0Y1     d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
High Pulse Width  Slow    MMCME4_ADV/CLKIN1  n/a            2.344         3.906       1.562      MMCM_X0Y7      d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
High Pulse Width  Fast    MMCME4_ADV/CLKIN1  n/a            2.344         3.906       1.562      MMCM_X0Y7      d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
High Pulse Width  Slow    HSADC/CLK_ADC      n/a            0.800         3.906       3.106      HSADC_X0Y1     d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
High Pulse Width  Fast    HSADC/CLK_ADC      n/a            0.800         3.906       3.106      HSADC_X0Y1     d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC



---------------------------------------------------------------------------------------------------
From Clock:  clk_out1_d_1_clk_adc0_x2_0
  To Clock:  clk_out1_d_1_clk_adc0_x2_0

Setup :            0  Failing Endpoints,  Worst Slack        0.766ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.011ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        1.153ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.766ns  (required time - arrival time)
  Source:                 d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/ENCODER/output_register.bin_dt_r_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/trig_time_ck_r_reg[22]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.906ns  (clk_out1_d_1_clk_adc0_x2_0 rise@3.906ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        2.860ns  (logic 0.223ns (7.798%)  route 2.637ns (92.202%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        -0.246ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.919ns = ( 9.825 - 3.906 ) 
    Source Clock Delay      (SCD):    6.001ns
    Clock Pessimism Removal (CPR):    -0.164ns
  Clock Uncertainty:      0.059ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.095ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.912ns (routing 1.754ns, distribution 1.158ns)
  Clock Net Delay (Destination): 2.501ns (routing 1.589ns, distribution 0.912ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.416     2.943    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                   -0.127     2.816 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.245     3.061    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.028     3.089 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.912     6.001    d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/ENCODER/adc_clk
                  SLICE_X96Y131        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/ENCODER/output_register.bin_dt_r_reg[0]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X96Y131        FDRE (Prop_DFF_SLICEM_C_Q)
                                                                    0.078     6.079 r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/ENCODER/output_register.bin_dt_r_reg[0]/Q
                                       net (fo=64, routed)          2.565     8.644    d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/ENCODER/Q[0]
    Routing       SLICE_X63Y269                                                     r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/ENCODER/trig_time_ck_r[22]_i_1/I5
    Routing       SLICE_X63Y269        LUT6 (Prop_D6LUT_SLICEM_I5_O)
                                                                    0.145     8.789 r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/ENCODER/trig_time_ck_r[22]_i_1/O
                                       net (fo=1, routed)           0.072     8.861    d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/time_ck_s[22]
    Routing       SLICE_X63Y269        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/trig_time_ck_r_reg[22]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    3.906     3.906 r  
                  HSADC_X0Y1           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.162     6.454    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                    0.630     7.084 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.216     7.300    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.024     7.324 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.501     9.825    d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/adc_clk
                  SLICE_X63Y269        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/trig_time_ck_r_reg[22]/C
                                       clock pessimism             -0.164     9.661    
                                       clock uncertainty           -0.059     9.602    
                  SLICE_X63Y269        FDRE (Setup_DFF_SLICEM_C_D)
                                                                    0.025     9.627    d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/trig_time_ck_r_reg[22]
  ---------------------------------------------------------------------------------
                                       required time                          9.627    
                                       arrival time                          -8.861    
  ---------------------------------------------------------------------------------
                                       slack                                  0.766    

Slack (MET) :             0.771ns  (required time - arrival time)
  Source:                 d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/ENCODER/output_register.bin_dt_r_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/trig_time_ck_r_reg[17]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.906ns  (clk_out1_d_1_clk_adc0_x2_0 rise@3.906ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        2.849ns  (logic 0.224ns (7.864%)  route 2.625ns (92.136%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        -0.252ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.913ns = ( 9.819 - 3.906 ) 
    Source Clock Delay      (SCD):    6.001ns
    Clock Pessimism Removal (CPR):    -0.164ns
  Clock Uncertainty:      0.059ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.095ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.912ns (routing 1.754ns, distribution 1.158ns)
  Clock Net Delay (Destination): 2.495ns (routing 1.589ns, distribution 0.906ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.416     2.943    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                   -0.127     2.816 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.245     3.061    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.028     3.089 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.912     6.001    d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/ENCODER/adc_clk
                  SLICE_X96Y131        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/ENCODER/output_register.bin_dt_r_reg[0]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X96Y131        FDRE (Prop_DFF_SLICEM_C_Q)
                                                                    0.078     6.079 r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/ENCODER/output_register.bin_dt_r_reg[0]/Q
                                       net (fo=64, routed)          2.576     8.655    d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/ENCODER/Q[0]
    Routing       SLICE_X62Y268                                                     r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/ENCODER/trig_time_ck_r[17]_i_1/I5
    Routing       SLICE_X62Y268        LUT6 (Prop_D6LUT_SLICEL_I5_O)
                                                                    0.146     8.801 r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/ENCODER/trig_time_ck_r[17]_i_1/O
                                       net (fo=1, routed)           0.049     8.850    d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/time_ck_s[17]
    Routing       SLICE_X62Y268        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/trig_time_ck_r_reg[17]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    3.906     3.906 r  
                  HSADC_X0Y1           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.162     6.454    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                    0.630     7.084 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.216     7.300    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.024     7.324 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.495     9.819    d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/adc_clk
                  SLICE_X62Y268        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/trig_time_ck_r_reg[17]/C
                                       clock pessimism             -0.164     9.655    
                                       clock uncertainty           -0.059     9.595    
                  SLICE_X62Y268        FDRE (Setup_DFF_SLICEL_C_D)
                                                                    0.025     9.620    d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/trig_time_ck_r_reg[17]
  ---------------------------------------------------------------------------------
                                       required time                          9.620    
                                       arrival time                          -8.850    
  ---------------------------------------------------------------------------------
                                       slack                                  0.771    

Slack (MET) :             0.771ns  (required time - arrival time)
  Source:                 d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/ENCODER/output_register.bin_dt_r_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/trig_time_ck_r_reg[18]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.906ns  (clk_out1_d_1_clk_adc0_x2_0 rise@3.906ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        2.849ns  (logic 0.224ns (7.864%)  route 2.625ns (92.136%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        -0.252ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.913ns = ( 9.819 - 3.906 ) 
    Source Clock Delay      (SCD):    6.001ns
    Clock Pessimism Removal (CPR):    -0.164ns
  Clock Uncertainty:      0.059ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.095ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.912ns (routing 1.754ns, distribution 1.158ns)
  Clock Net Delay (Destination): 2.495ns (routing 1.589ns, distribution 0.906ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.416     2.943    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                   -0.127     2.816 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.245     3.061    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.028     3.089 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.912     6.001    d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/ENCODER/adc_clk
                  SLICE_X96Y131        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/ENCODER/output_register.bin_dt_r_reg[0]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X96Y131        FDRE (Prop_DFF_SLICEM_C_Q)
                                                                    0.078     6.079 r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/ENCODER/output_register.bin_dt_r_reg[0]/Q
                                       net (fo=64, routed)          2.575     8.654    d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/ENCODER/Q[0]
    Routing       SLICE_X62Y268                                                     r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/ENCODER/trig_time_ck_r[18]_i_1/I5
    Routing       SLICE_X62Y268        LUT6 (Prop_C6LUT_SLICEL_I5_O)
                                                                    0.146     8.800 r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/ENCODER/trig_time_ck_r[18]_i_1/O
                                       net (fo=1, routed)           0.050     8.850    d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/time_ck_s[18]
    Routing       SLICE_X62Y268        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/trig_time_ck_r_reg[18]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    3.906     3.906 r  
                  HSADC_X0Y1           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.162     6.454    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                    0.630     7.084 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.216     7.300    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.024     7.324 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.495     9.819    d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/adc_clk
                  SLICE_X62Y268        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/trig_time_ck_r_reg[18]/C
                                       clock pessimism             -0.164     9.655    
                                       clock uncertainty           -0.059     9.595    
                  SLICE_X62Y268        FDRE (Setup_CFF_SLICEL_C_D)
                                                                    0.025     9.620    d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/trig_time_ck_r_reg[18]
  ---------------------------------------------------------------------------------
                                       required time                          9.620    
                                       arrival time                          -8.850    
  ---------------------------------------------------------------------------------
                                       slack                                  0.771    

Slack (MET) :             0.778ns  (required time - arrival time)
  Source:                 d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/ENCODER/output_register.bin_dt_r_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/trig_time_ck_r_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.906ns  (clk_out1_d_1_clk_adc0_x2_0 rise@3.906ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        3.031ns  (logic 0.223ns (7.358%)  route 2.808ns (92.642%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        -0.063ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.912ns = ( 9.818 - 3.906 ) 
    Source Clock Delay      (SCD):    5.811ns
    Clock Pessimism Removal (CPR):    -0.164ns
  Clock Uncertainty:      0.059ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.095ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.722ns (routing 1.754ns, distribution 0.968ns)
  Clock Net Delay (Destination): 2.494ns (routing 1.589ns, distribution 0.905ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.416     2.943    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                   -0.127     2.816 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.245     3.061    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.028     3.089 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.722     5.811    d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/ENCODER/adc_clk
                  SLICE_X67Y148        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/ENCODER/output_register.bin_dt_r_reg[2]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X67Y148        FDRE (Prop_DFF_SLICEM_C_Q)
                                                                    0.078     5.889 r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/ENCODER/output_register.bin_dt_r_reg[2]/Q
                                       net (fo=46, routed)          2.736     8.625    d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/ENCODER/enc_s[2]
    Routing       SLICE_X67Y268                                                     r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/ENCODER/trig_time_ck_r[15]_i_1/I4
    Routing       SLICE_X67Y268        LUT6 (Prop_D6LUT_SLICEM_I4_O)
                                                                    0.145     8.770 r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/ENCODER/trig_time_ck_r[15]_i_1/O
                                       net (fo=1, routed)           0.072     8.842    d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/time_ck_s[15]
    Routing       SLICE_X67Y268        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/trig_time_ck_r_reg[15]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    3.906     3.906 r  
                  HSADC_X0Y1           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.162     6.454    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                    0.630     7.084 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.216     7.300    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.024     7.324 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.494     9.818    d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/adc_clk
                  SLICE_X67Y268        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/trig_time_ck_r_reg[15]/C
                                       clock pessimism             -0.164     9.654    
                                       clock uncertainty           -0.059     9.594    
                  SLICE_X67Y268        FDRE (Setup_DFF_SLICEM_C_D)
                                                                    0.025     9.619    d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/trig_time_ck_r_reg[15]
  ---------------------------------------------------------------------------------
                                       required time                          9.619    
                                       arrival time                          -8.842    
  ---------------------------------------------------------------------------------
                                       slack                                  0.778    

Slack (MET) :             0.801ns  (required time - arrival time)
  Source:                 d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/ENCODER/output_register.bin_dt_r_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/trig_time_ck_r_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.906ns  (clk_out1_d_1_clk_adc0_x2_0 rise@3.906ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        2.820ns  (logic 0.166ns (5.887%)  route 2.654ns (94.113%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        -0.251ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.914ns = ( 9.820 - 3.906 ) 
    Source Clock Delay      (SCD):    6.001ns
    Clock Pessimism Removal (CPR):    -0.164ns
  Clock Uncertainty:      0.059ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.095ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.912ns (routing 1.754ns, distribution 1.158ns)
  Clock Net Delay (Destination): 2.496ns (routing 1.589ns, distribution 0.907ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.416     2.943    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                   -0.127     2.816 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.245     3.061    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.028     3.089 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.912     6.001    d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/ENCODER/adc_clk
                  SLICE_X96Y131        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/ENCODER/output_register.bin_dt_r_reg[0]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X96Y131        FDRE (Prop_DFF_SLICEM_C_Q)
                                                                    0.078     6.079 r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/ENCODER/output_register.bin_dt_r_reg[0]/Q
                                       net (fo=64, routed)          2.604     8.683    d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/ENCODER/Q[0]
    Routing       SLICE_X62Y267                                                     r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/ENCODER/trig_time_ck_r[5]_i_1/I5
    Routing       SLICE_X62Y267        LUT6 (Prop_C6LUT_SLICEL_I5_O)
                                                                    0.088     8.771 r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/ENCODER/trig_time_ck_r[5]_i_1/O
                                       net (fo=1, routed)           0.050     8.821    d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/time_ck_s[5]
    Routing       SLICE_X62Y267        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/trig_time_ck_r_reg[5]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    3.906     3.906 r  
                  HSADC_X0Y1           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.162     6.454    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                    0.630     7.084 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.216     7.300    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.024     7.324 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.496     9.820    d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/adc_clk
                  SLICE_X62Y267        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/trig_time_ck_r_reg[5]/C
                                       clock pessimism             -0.164     9.656    
                                       clock uncertainty           -0.059     9.596    
                  SLICE_X62Y267        FDRE (Setup_CFF_SLICEL_C_D)
                                                                    0.025     9.621    d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/trig_time_ck_r_reg[5]
  ---------------------------------------------------------------------------------
                                       required time                          9.621    
                                       arrival time                          -8.821    
  ---------------------------------------------------------------------------------
                                       slack                                  0.801    

Slack (MET) :             0.801ns  (required time - arrival time)
  Source:                 d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/ENCODER/output_register.bin_dt_r_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/trig_time_ck_r_reg[19]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.906ns  (clk_out1_d_1_clk_adc0_x2_0 rise@3.906ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        2.827ns  (logic 0.224ns (7.923%)  route 2.603ns (92.077%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        -0.243ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.922ns = ( 9.828 - 3.906 ) 
    Source Clock Delay      (SCD):    6.001ns
    Clock Pessimism Removal (CPR):    -0.164ns
  Clock Uncertainty:      0.059ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.095ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.912ns (routing 1.754ns, distribution 1.158ns)
  Clock Net Delay (Destination): 2.504ns (routing 1.589ns, distribution 0.915ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.416     2.943    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                   -0.127     2.816 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.245     3.061    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.028     3.089 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.912     6.001    d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/ENCODER/adc_clk
                  SLICE_X96Y131        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/ENCODER/output_register.bin_dt_r_reg[0]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X96Y131        FDRE (Prop_DFF_SLICEM_C_Q)
                                                                    0.078     6.079 r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/ENCODER/output_register.bin_dt_r_reg[0]/Q
                                       net (fo=64, routed)          2.554     8.633    d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/ENCODER/Q[0]
    Routing       SLICE_X64Y268                                                     r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/ENCODER/trig_time_ck_r[19]_i_1/I5
    Routing       SLICE_X64Y268        LUT6 (Prop_D6LUT_SLICEL_I5_O)
                                                                    0.146     8.779 r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/ENCODER/trig_time_ck_r[19]_i_1/O
                                       net (fo=1, routed)           0.049     8.828    d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/time_ck_s[19]
    Routing       SLICE_X64Y268        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/trig_time_ck_r_reg[19]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    3.906     3.906 r  
                  HSADC_X0Y1           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.162     6.454    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                    0.630     7.084 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.216     7.300    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.024     7.324 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.504     9.828    d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/adc_clk
                  SLICE_X64Y268        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/trig_time_ck_r_reg[19]/C
                                       clock pessimism             -0.164     9.664    
                                       clock uncertainty           -0.059     9.605    
                  SLICE_X64Y268        FDRE (Setup_DFF_SLICEL_C_D)
                                                                    0.025     9.630    d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/trig_time_ck_r_reg[19]
  ---------------------------------------------------------------------------------
                                       required time                          9.630    
                                       arrival time                          -8.828    
  ---------------------------------------------------------------------------------
                                       slack                                  0.801    

Slack (MET) :             0.818ns  (required time - arrival time)
  Source:                 d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/ENCODER/output_register.bin_dt_r_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/trig_time_ck_r_reg[20]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.906ns  (clk_out1_d_1_clk_adc0_x2_0 rise@3.906ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        2.814ns  (logic 0.223ns (7.924%)  route 2.591ns (92.076%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        -0.239ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.926ns = ( 9.832 - 3.906 ) 
    Source Clock Delay      (SCD):    6.001ns
    Clock Pessimism Removal (CPR):    -0.164ns
  Clock Uncertainty:      0.059ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.095ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.912ns (routing 1.754ns, distribution 1.158ns)
  Clock Net Delay (Destination): 2.508ns (routing 1.589ns, distribution 0.919ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.416     2.943    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                   -0.127     2.816 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.245     3.061    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.028     3.089 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.912     6.001    d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/ENCODER/adc_clk
                  SLICE_X96Y131        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/ENCODER/output_register.bin_dt_r_reg[0]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X96Y131        FDRE (Prop_DFF_SLICEM_C_Q)
                                                                    0.078     6.079 r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/ENCODER/output_register.bin_dt_r_reg[0]/Q
                                       net (fo=64, routed)          2.525     8.604    d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/ENCODER/Q[0]
    Routing       SLICE_X63Y268                                                     r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/ENCODER/trig_time_ck_r[20]_i_1/I5
    Routing       SLICE_X63Y268        LUT6 (Prop_C6LUT_SLICEM_I5_O)
                                                                    0.145     8.749 r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/ENCODER/trig_time_ck_r[20]_i_1/O
                                       net (fo=1, routed)           0.066     8.815    d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/time_ck_s[20]
    Routing       SLICE_X63Y268        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/trig_time_ck_r_reg[20]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    3.906     3.906 r  
                  HSADC_X0Y1           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.162     6.454    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                    0.630     7.084 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.216     7.300    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.024     7.324 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.508     9.832    d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/adc_clk
                  SLICE_X63Y268        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/trig_time_ck_r_reg[20]/C
                                       clock pessimism             -0.164     9.668    
                                       clock uncertainty           -0.059     9.609    
                  SLICE_X63Y268        FDRE (Setup_CFF_SLICEM_C_D)
                                                                    0.025     9.634    d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/trig_time_ck_r_reg[20]
  ---------------------------------------------------------------------------------
                                       required time                          9.634    
                                       arrival time                          -8.815    
  ---------------------------------------------------------------------------------
                                       slack                                  0.818    

Slack (MET) :             0.824ns  (required time - arrival time)
  Source:                 d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/ENCODER/output_register.bin_dt_r_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/trig_time_ck_r_reg[16]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.906ns  (clk_out1_d_1_clk_adc0_x2_0 rise@3.906ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        2.808ns  (logic 0.223ns (7.941%)  route 2.585ns (92.059%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        -0.239ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.926ns = ( 9.832 - 3.906 ) 
    Source Clock Delay      (SCD):    6.001ns
    Clock Pessimism Removal (CPR):    -0.164ns
  Clock Uncertainty:      0.059ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.095ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.912ns (routing 1.754ns, distribution 1.158ns)
  Clock Net Delay (Destination): 2.508ns (routing 1.589ns, distribution 0.919ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.416     2.943    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                   -0.127     2.816 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.245     3.061    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.028     3.089 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.912     6.001    d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/ENCODER/adc_clk
                  SLICE_X96Y131        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/ENCODER/output_register.bin_dt_r_reg[0]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X96Y131        FDRE (Prop_DFF_SLICEM_C_Q)
                                                                    0.078     6.079 r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/ENCODER/output_register.bin_dt_r_reg[0]/Q
                                       net (fo=64, routed)          2.513     8.592    d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/ENCODER/Q[0]
    Routing       SLICE_X63Y268                                                     r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/ENCODER/trig_time_ck_r[16]_i_1/I5
    Routing       SLICE_X63Y268        LUT6 (Prop_D6LUT_SLICEM_I5_O)
                                                                    0.145     8.737 r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/ENCODER/trig_time_ck_r[16]_i_1/O
                                       net (fo=1, routed)           0.072     8.809    d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/time_ck_s[16]
    Routing       SLICE_X63Y268        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/trig_time_ck_r_reg[16]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    3.906     3.906 r  
                  HSADC_X0Y1           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.162     6.454    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                    0.630     7.084 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.216     7.300    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.024     7.324 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.508     9.832    d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/adc_clk
                  SLICE_X63Y268        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/trig_time_ck_r_reg[16]/C
                                       clock pessimism             -0.164     9.668    
                                       clock uncertainty           -0.059     9.609    
                  SLICE_X63Y268        FDRE (Setup_DFF_SLICEM_C_D)
                                                                    0.025     9.634    d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/trig_time_ck_r_reg[16]
  ---------------------------------------------------------------------------------
                                       required time                          9.634    
                                       arrival time                          -8.809    
  ---------------------------------------------------------------------------------
                                       slack                                  0.824    

Slack (MET) :             0.837ns  (required time - arrival time)
  Source:                 d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/ENCODER/output_register.bin_dt_r_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/trig_time_ck_r_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.906ns  (clk_out1_d_1_clk_adc0_x2_0 rise@3.906ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        2.784ns  (logic 0.128ns (4.598%)  route 2.656ns (95.402%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        -0.251ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.914ns = ( 9.820 - 3.906 ) 
    Source Clock Delay      (SCD):    6.001ns
    Clock Pessimism Removal (CPR):    -0.164ns
  Clock Uncertainty:      0.059ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.095ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.912ns (routing 1.754ns, distribution 1.158ns)
  Clock Net Delay (Destination): 2.496ns (routing 1.589ns, distribution 0.907ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.416     2.943    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                   -0.127     2.816 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.245     3.061    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.028     3.089 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.912     6.001    d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/ENCODER/adc_clk
                  SLICE_X96Y131        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/ENCODER/output_register.bin_dt_r_reg[0]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X96Y131        FDRE (Prop_DFF_SLICEM_C_Q)
                                                                    0.078     6.079 r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/ENCODER/output_register.bin_dt_r_reg[0]/Q
                                       net (fo=64, routed)          2.607     8.686    d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/ENCODER/Q[0]
    Routing       SLICE_X62Y267                                                     r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/ENCODER/trig_time_ck_r[11]_i_1/I5
    Routing       SLICE_X62Y267        LUT6 (Prop_D6LUT_SLICEL_I5_O)
                                                                    0.050     8.736 r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/ENCODER/trig_time_ck_r[11]_i_1/O
                                       net (fo=1, routed)           0.049     8.785    d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/time_ck_s[11]
    Routing       SLICE_X62Y267        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/trig_time_ck_r_reg[11]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    3.906     3.906 r  
                  HSADC_X0Y1           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.162     6.454    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                    0.630     7.084 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.216     7.300    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.024     7.324 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.496     9.820    d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/adc_clk
                  SLICE_X62Y267        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/trig_time_ck_r_reg[11]/C
                                       clock pessimism             -0.164     9.656    
                                       clock uncertainty           -0.059     9.596    
                  SLICE_X62Y267        FDRE (Setup_DFF_SLICEL_C_D)
                                                                    0.025     9.621    d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/trig_time_ck_r_reg[11]
  ---------------------------------------------------------------------------------
                                       required time                          9.621    
                                       arrival time                          -8.785    
  ---------------------------------------------------------------------------------
                                       slack                                  0.837    

Slack (MET) :             0.847ns  (required time - arrival time)
  Source:                 d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/ENCODER/output_register.bin_dt_r_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/trig_time_ck_r_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.906ns  (clk_out1_d_1_clk_adc0_x2_0 rise@3.906ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        2.958ns  (logic 0.224ns (7.572%)  route 2.734ns (92.428%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        -0.066ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.909ns = ( 9.815 - 3.906 ) 
    Source Clock Delay      (SCD):    5.811ns
    Clock Pessimism Removal (CPR):    -0.164ns
  Clock Uncertainty:      0.059ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.095ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.722ns (routing 1.754ns, distribution 0.968ns)
  Clock Net Delay (Destination): 2.491ns (routing 1.589ns, distribution 0.902ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.416     2.943    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                   -0.127     2.816 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.245     3.061    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.028     3.089 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.722     5.811    d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/ENCODER/adc_clk
                  SLICE_X67Y148        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/ENCODER/output_register.bin_dt_r_reg[2]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X67Y148        FDRE (Prop_DFF_SLICEM_C_Q)
                                                                    0.078     5.889 r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/ENCODER/output_register.bin_dt_r_reg[2]/Q
                                       net (fo=46, routed)          2.685     8.574    d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/ENCODER/enc_s[2]
    Routing       SLICE_X68Y267                                                     r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/ENCODER/trig_time_ck_r[0]_i_1/I4
    Routing       SLICE_X68Y267        LUT6 (Prop_D6LUT_SLICEL_I4_O)
                                                                    0.146     8.720 r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/ENCODER/trig_time_ck_r[0]_i_1/O
                                       net (fo=1, routed)           0.049     8.769    d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/time_ck_s[0]
    Routing       SLICE_X68Y267        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/trig_time_ck_r_reg[0]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    3.906     3.906 r  
                  HSADC_X0Y1           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.162     6.454    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                    0.630     7.084 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.216     7.300    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.024     7.324 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.491     9.815    d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/adc_clk
                  SLICE_X68Y267        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/trig_time_ck_r_reg[0]/C
                                       clock pessimism             -0.164     9.651    
                                       clock uncertainty           -0.059     9.591    
                  SLICE_X68Y267        FDRE (Setup_DFF_SLICEL_C_D)
                                                                    0.025     9.616    d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/trig_time_ck_r_reg[0]
  ---------------------------------------------------------------------------------
                                       required time                          9.616    
                                       arrival time                          -8.769    
  ---------------------------------------------------------------------------------
                                       slack                                  0.847    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.011ns  (arrival time - required time)
  Source:                 d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/smp_wr_dt_2r_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/smp_wr_dt_3r_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.206ns  (logic 0.058ns (28.155%)  route 0.148ns (71.845%))
  Logic Levels:           0  
  Clock Path Skew:        0.133ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.003ns
    Source Clock Delay      (SCD):    6.030ns
    Clock Pessimism Removal (CPR):    -0.160ns
  Clock Net Delay (Source):      2.612ns (routing 1.589ns, distribution 1.023ns)
  Clock Net Delay (Destination): 2.914ns (routing 1.754ns, distribution 1.160ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.162     2.548    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                    0.630     3.178 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.216     3.394    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.024     3.418 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.612     6.030    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/adc_clk
                  SLICE_X93Y118        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/smp_wr_dt_2r_reg[4]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X93Y118        FDRE (Prop_HFF_SLICEM_C_Q)
                                                                    0.058     6.088 r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/smp_wr_dt_2r_reg[4]/Q
                                       net (fo=1, routed)           0.148     6.236    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/smp_wr_dt_2r[4]
    Routing       SLICE_X93Y122        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/smp_wr_dt_3r_reg[4]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.416     2.943    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                   -0.127     2.816 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.245     3.061    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.028     3.089 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.914     6.003    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/adc_clk
                  SLICE_X93Y122        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/smp_wr_dt_3r_reg[4]/C
                                       clock pessimism              0.160     6.163    
                  SLICE_X93Y122        FDRE (Hold_CFF2_SLICEM_C_D)
                                                                    0.062     6.225    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/smp_wr_dt_3r_reg[4]
  ---------------------------------------------------------------------------------
                                       required time                         -6.225    
                                       arrival time                           6.236    
  ---------------------------------------------------------------------------------
                                       slack                                  0.011    

Slack (MET) :             0.016ns  (arrival time - required time)
  Source:                 d_1_i/axis_register_slice_6/inst/axisc_register_slice_0/storage_data1_reg[71]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/smp_wr_dt_reg[71]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.167ns  (logic 0.059ns (35.251%)  route 0.108ns (64.749%))
  Logic Levels:           0  
  Clock Path Skew:        0.090ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.075ns
    Source Clock Delay      (SCD):    6.082ns
    Clock Pessimism Removal (CPR):    -0.097ns
  Clock Net Delay (Source):      2.664ns (routing 1.589ns, distribution 1.075ns)
  Clock Net Delay (Destination): 2.986ns (routing 1.754ns, distribution 1.232ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.162     2.548    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                    0.630     3.178 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.216     3.394    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.024     3.418 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.664     6.082    d_1_i/axis_register_slice_6/inst/axisc_register_slice_0/aclk
                  SLICE_X100Y124       FDRE                                         r  d_1_i/axis_register_slice_6/inst/axisc_register_slice_0/storage_data1_reg[71]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X100Y124       FDRE (Prop_GFF_SLICEL_C_Q)
                                                                    0.059     6.141 r  d_1_i/axis_register_slice_6/inst/axisc_register_slice_0/storage_data1_reg[71]/Q
                                       net (fo=12, routed)          0.108     6.249    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/adc0_s_axis_tdata_i[71]
    Routing       SLICE_X98Y126        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/smp_wr_dt_reg[71]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.416     2.943    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                   -0.127     2.816 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.245     3.061    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.028     3.089 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.986     6.075    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/adc_clk
                  SLICE_X98Y126        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/smp_wr_dt_reg[71]/C
                                       clock pessimism              0.097     6.172    
                  SLICE_X98Y126        FDRE (Hold_DFF2_SLICEL_C_D)
                                                                    0.062     6.234    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/smp_wr_dt_reg[71]
  ---------------------------------------------------------------------------------
                                       required time                         -6.234    
                                       arrival time                           6.249    
  ---------------------------------------------------------------------------------
                                       slack                                  0.016    

Slack (MET) :             0.020ns  (arrival time - required time)
  Source:                 d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/smp_wr_dt_2r_reg[42]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/smp_wr_dt_3r_reg[42]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.214ns  (logic 0.057ns (26.635%)  route 0.157ns (73.364%))
  Logic Levels:           0  
  Clock Path Skew:        0.132ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.012ns
    Source Clock Delay      (SCD):    6.040ns
    Clock Pessimism Removal (CPR):    -0.160ns
  Clock Net Delay (Source):      2.622ns (routing 1.589ns, distribution 1.033ns)
  Clock Net Delay (Destination): 2.923ns (routing 1.754ns, distribution 1.169ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.162     2.548    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                    0.630     3.178 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.216     3.394    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.024     3.418 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.622     6.040    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/adc_clk
                  SLICE_X94Y119        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/smp_wr_dt_2r_reg[42]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X94Y119        FDRE (Prop_FFF_SLICEM_C_Q)
                                                                    0.057     6.097 r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/smp_wr_dt_2r_reg[42]/Q
                                       net (fo=1, routed)           0.157     6.254    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/smp_wr_dt_2r[42]
    Routing       SLICE_X94Y126        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/smp_wr_dt_3r_reg[42]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.416     2.943    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                   -0.127     2.816 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.245     3.061    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.028     3.089 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.923     6.012    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/adc_clk
                  SLICE_X94Y126        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/smp_wr_dt_3r_reg[42]/C
                                       clock pessimism              0.160     6.172    
                  SLICE_X94Y126        FDRE (Hold_HFF2_SLICEM_C_D)
                                                                    0.062     6.234    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/smp_wr_dt_3r_reg[42]
  ---------------------------------------------------------------------------------
                                       required time                         -6.234    
                                       arrival time                           6.254    
  ---------------------------------------------------------------------------------
                                       slack                                  0.020    

Slack (MET) :             0.020ns  (arrival time - required time)
  Source:                 d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/smp_wr_dt_2r_reg[71]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/smp_wr_dt_3r_reg[71]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.192ns  (logic 0.058ns (30.208%)  route 0.134ns (69.792%))
  Logic Levels:           0  
  Clock Path Skew:        0.110ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.022ns
    Source Clock Delay      (SCD):    6.019ns
    Clock Pessimism Removal (CPR):    -0.106ns
  Clock Net Delay (Source):      2.601ns (routing 1.589ns, distribution 1.012ns)
  Clock Net Delay (Destination): 2.933ns (routing 1.754ns, distribution 1.179ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.162     2.548    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                    0.630     3.178 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.216     3.394    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.024     3.418 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.601     6.019    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/adc_clk
                  SLICE_X96Y125        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/smp_wr_dt_2r_reg[71]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X96Y125        FDRE (Prop_GFF_SLICEM_C_Q)
                                                                    0.058     6.077 r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/smp_wr_dt_2r_reg[71]/Q
                                       net (fo=1, routed)           0.134     6.211    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/smp_wr_dt_2r[71]
    Routing       SLICE_X94Y129        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/smp_wr_dt_3r_reg[71]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.416     2.943    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                   -0.127     2.816 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.245     3.061    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.028     3.089 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.933     6.022    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/adc_clk
                  SLICE_X94Y129        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/smp_wr_dt_3r_reg[71]/C
                                       clock pessimism              0.106     6.128    
                  SLICE_X94Y129        FDRE (Hold_GFF2_SLICEM_C_D)
                                                                    0.062     6.190    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/smp_wr_dt_3r_reg[71]
  ---------------------------------------------------------------------------------
                                       required time                         -6.190    
                                       arrival time                           6.211    
  ---------------------------------------------------------------------------------
                                       slack                                  0.020    

Slack (MET) :             0.021ns  (arrival time - required time)
  Source:                 d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/smp_wr_dt_2r_reg[31]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/smp_wr_dt_3r_reg[31]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.162ns  (logic 0.058ns (35.803%)  route 0.104ns (64.198%))
  Logic Levels:           0  
  Clock Path Skew:        0.079ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.988ns
    Source Clock Delay      (SCD):    6.010ns
    Clock Pessimism Removal (CPR):    -0.101ns
  Clock Net Delay (Source):      2.592ns (routing 1.589ns, distribution 1.003ns)
  Clock Net Delay (Destination): 2.899ns (routing 1.754ns, distribution 1.145ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.162     2.548    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                    0.630     3.178 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.216     3.394    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.024     3.418 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.592     6.010    d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/adc_clk
                  SLICE_X86Y99         FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/smp_wr_dt_2r_reg[31]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X86Y99         FDRE (Prop_HFF_SLICEM_C_Q)
                                                                    0.058     6.068 r  d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/smp_wr_dt_2r_reg[31]/Q
                                       net (fo=1, routed)           0.104     6.172    d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/smp_wr_dt_2r[31]
    Routing       SLICE_X85Y100        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/smp_wr_dt_3r_reg[31]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.416     2.943    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                   -0.127     2.816 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.245     3.061    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.028     3.089 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.899     5.988    d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/adc_clk
                  SLICE_X85Y100        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/smp_wr_dt_3r_reg[31]/C
                                       clock pessimism              0.101     6.089    
                  SLICE_X85Y100        FDRE (Hold_BFF2_SLICEL_C_D)
                                                                    0.062     6.151    d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/smp_wr_dt_3r_reg[31]
  ---------------------------------------------------------------------------------
                                       required time                         -6.151    
                                       arrival time                           6.172    
  ---------------------------------------------------------------------------------
                                       slack                                  0.021    

Slack (MET) :             0.022ns  (arrival time - required time)
  Source:                 d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/smp_wr_dt_r_reg[44]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/smp_wr_dt_2r_reg[44]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.189ns  (logic 0.058ns (30.688%)  route 0.131ns (69.312%))
  Logic Levels:           0  
  Clock Path Skew:        0.105ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.018ns
    Source Clock Delay      (SCD):    6.014ns
    Clock Pessimism Removal (CPR):    -0.101ns
  Clock Net Delay (Source):      2.596ns (routing 1.589ns, distribution 1.007ns)
  Clock Net Delay (Destination): 2.929ns (routing 1.754ns, distribution 1.175ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.162     2.548    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                    0.630     3.178 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.216     3.394    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.024     3.418 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.596     6.014    d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/adc_clk
                  SLICE_X92Y96         FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/smp_wr_dt_r_reg[44]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X92Y96         FDRE (Prop_FFF_SLICEL_C_Q)
                                                                    0.058     6.072 r  d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/smp_wr_dt_r_reg[44]/Q
                                       net (fo=1, routed)           0.131     6.203    d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/smp_wr_dt_r[44]
    Routing       SLICE_X91Y95         FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/smp_wr_dt_2r_reg[44]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.416     2.943    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                   -0.127     2.816 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.245     3.061    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.028     3.089 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.929     6.018    d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/adc_clk
                  SLICE_X91Y95         FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/smp_wr_dt_2r_reg[44]/C
                                       clock pessimism              0.101     6.119    
                  SLICE_X91Y95         FDRE (Hold_HFF2_SLICEL_C_D)
                                                                    0.062     6.181    d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/smp_wr_dt_2r_reg[44]
  ---------------------------------------------------------------------------------
                                       required time                         -6.181    
                                       arrival time                           6.203    
  ---------------------------------------------------------------------------------
                                       slack                                  0.022    

Slack (MET) :             0.024ns  (arrival time - required time)
  Source:                 d_1_i/axis_register_slice_6/inst/axisc_register_slice_0/storage_data1_reg[93]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/smp_wr_dt_reg[93]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.186ns  (logic 0.059ns (31.722%)  route 0.127ns (68.278%))
  Logic Levels:           0  
  Clock Path Skew:        0.102ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.080ns
    Source Clock Delay      (SCD):    6.075ns
    Clock Pessimism Removal (CPR):    -0.097ns
  Clock Net Delay (Source):      2.657ns (routing 1.589ns, distribution 1.068ns)
  Clock Net Delay (Destination): 2.991ns (routing 1.754ns, distribution 1.237ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.162     2.548    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                    0.630     3.178 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.216     3.394    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.024     3.418 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.657     6.075    d_1_i/axis_register_slice_6/inst/axisc_register_slice_0/aclk
                  SLICE_X102Y126       FDRE                                         r  d_1_i/axis_register_slice_6/inst/axisc_register_slice_0/storage_data1_reg[93]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X102Y126       FDRE (Prop_GFF_SLICEL_C_Q)
                                                                    0.059     6.134 r  d_1_i/axis_register_slice_6/inst/axisc_register_slice_0/storage_data1_reg[93]/Q
                                       net (fo=6, routed)           0.127     6.261    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/adc0_s_axis_tdata_i[93]
    Routing       SLICE_X97Y126        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/smp_wr_dt_reg[93]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.416     2.943    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                   -0.127     2.816 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.245     3.061    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.028     3.089 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.991     6.080    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/adc_clk
                  SLICE_X97Y126        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/smp_wr_dt_reg[93]/C
                                       clock pessimism              0.097     6.177    
                  SLICE_X97Y126        FDRE (Hold_HFF_SLICEM_C_D)
                                                                    0.060     6.237    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/smp_wr_dt_reg[93]
  ---------------------------------------------------------------------------------
                                       required time                         -6.237    
                                       arrival time                           6.261    
  ---------------------------------------------------------------------------------
                                       slack                                  0.024    

Slack (MET) :             0.025ns  (arrival time - required time)
  Source:                 d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/smp_wr_dt_reg[63]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/smp_wr_dt_r_reg[63]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.129ns  (logic 0.060ns (46.512%)  route 0.069ns (53.488%))
  Logic Levels:           0  
  Clock Path Skew:        0.042ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.075ns
    Source Clock Delay      (SCD):    6.080ns
    Clock Pessimism Removal (CPR):    -0.047ns
  Clock Net Delay (Source):      2.662ns (routing 1.589ns, distribution 1.073ns)
  Clock Net Delay (Destination): 2.986ns (routing 1.754ns, distribution 1.232ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.162     2.548    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                    0.630     3.178 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.216     3.394    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.024     3.418 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.662     6.080    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/adc_clk
                  SLICE_X98Y124        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/smp_wr_dt_reg[63]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X98Y124        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                                    0.060     6.140 r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/smp_wr_dt_reg[63]/Q
                                       net (fo=1, routed)           0.069     6.209    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/smp_wr_dt[63]
    Routing       SLICE_X98Y126        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/smp_wr_dt_r_reg[63]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.416     2.943    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                   -0.127     2.816 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.245     3.061    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.028     3.089 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.986     6.075    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/adc_clk
                  SLICE_X98Y126        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/smp_wr_dt_r_reg[63]/C
                                       clock pessimism              0.047     6.122    
                  SLICE_X98Y126        FDRE (Hold_BFF2_SLICEL_C_D)
                                                                    0.062     6.184    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/smp_wr_dt_r_reg[63]
  ---------------------------------------------------------------------------------
                                       required time                         -6.184    
                                       arrival time                           6.209    
  ---------------------------------------------------------------------------------
                                       slack                                  0.025    

Slack (MET) :             0.025ns  (arrival time - required time)
  Source:                 d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/smp_wr_dt_r_reg[16]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/smp_wr_dt_2r_reg[16]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.168ns  (logic 0.060ns (35.714%)  route 0.108ns (64.286%))
  Logic Levels:           0  
  Clock Path Skew:        0.081ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.984ns
    Source Clock Delay      (SCD):    6.004ns
    Clock Pessimism Removal (CPR):    -0.101ns
  Clock Net Delay (Source):      2.586ns (routing 1.589ns, distribution 0.997ns)
  Clock Net Delay (Destination): 2.895ns (routing 1.754ns, distribution 1.141ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.162     2.548    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                    0.630     3.178 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.216     3.394    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.024     3.418 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.586     6.004    d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/adc_clk
                  SLICE_X86Y94         FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/smp_wr_dt_r_reg[16]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X86Y94         FDRE (Prop_EFF2_SLICEM_C_Q)
                                                                    0.060     6.064 r  d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/smp_wr_dt_r_reg[16]/Q
                                       net (fo=1, routed)           0.108     6.172    d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/smp_wr_dt_r[16]
    Routing       SLICE_X85Y93         FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/smp_wr_dt_2r_reg[16]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.416     2.943    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                   -0.127     2.816 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.245     3.061    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.028     3.089 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.895     5.984    d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/adc_clk
                  SLICE_X85Y93         FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/smp_wr_dt_2r_reg[16]/C
                                       clock pessimism              0.101     6.085    
                  SLICE_X85Y93         FDRE (Hold_EFF2_SLICEL_C_D)
                                                                    0.062     6.147    d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/smp_wr_dt_2r_reg[16]
  ---------------------------------------------------------------------------------
                                       required time                         -6.147    
                                       arrival time                           6.172    
  ---------------------------------------------------------------------------------
                                       slack                                  0.025    

Slack (MET) :             0.025ns  (arrival time - required time)
  Source:                 d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/smp_wr_dt_2r_reg[36]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/smp_wr_dt_3r_reg[36]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.144ns  (logic 0.058ns (40.278%)  route 0.086ns (59.722%))
  Logic Levels:           0  
  Clock Path Skew:        0.057ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.010ns
    Source Clock Delay      (SCD):    6.003ns
    Clock Pessimism Removal (CPR):    -0.049ns
  Clock Net Delay (Source):      2.585ns (routing 1.589ns, distribution 0.996ns)
  Clock Net Delay (Destination): 2.921ns (routing 1.754ns, distribution 1.167ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.162     2.548    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                    0.630     3.178 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.216     3.394    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.024     3.418 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.585     6.003    d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/adc_clk
                  SLICE_X87Y91         FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/smp_wr_dt_2r_reg[36]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X87Y91         FDRE (Prop_EFF_SLICEM_C_Q)
                                                                    0.058     6.061 r  d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/smp_wr_dt_2r_reg[36]/Q
                                       net (fo=1, routed)           0.086     6.147    d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/smp_wr_dt_2r[36]
    Routing       SLICE_X87Y92         FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/smp_wr_dt_3r_reg[36]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.416     2.943    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                   -0.127     2.816 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.245     3.061    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.028     3.089 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.921     6.010    d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/adc_clk
                  SLICE_X87Y92         FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/smp_wr_dt_3r_reg[36]/C
                                       clock pessimism              0.049     6.059    
                  SLICE_X87Y92         FDRE (Hold_FFF2_SLICEM_C_D)
                                                                    0.062     6.121    d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/smp_wr_dt_3r_reg[36]
  ---------------------------------------------------------------------------------
                                       required time                         -6.121    
                                       arrival time                           6.147    
  ---------------------------------------------------------------------------------
                                       slack                                  0.025    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         clk_out1_d_1_clk_adc0_x2_0
Waveform(ns):       { 0.000 1.953 }
Period(ns):         3.906
Sources:            { d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0 }

Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location       Pin
Min Period        n/a     HSADC/FABRIC_CLK    n/a            1.923         3.906       1.983      HSADC_X0Y1     d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/FABRIC_CLK
Min Period        n/a     RAMB18E2/CLKBWRCLK  n/a            1.355         3.906       2.551      RAMB18_X5Y68   d_1_i/qick_time_tagger_0/inst/QTT/ARM.ARM_MEM/FIFO_PUSH/fifo_mem/mem_reg/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.355         3.906       2.551      RAMB36_X8Y20   d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/fifo_mem/mem_reg_0/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.355         3.906       2.551      RAMB36_X8Y21   d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/fifo_mem/mem_reg_1/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKARDCLK  n/a            1.355         3.906       2.551      RAMB36_X7Y27   d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/mem_reg_bram_0/CLKARDCLK
Min Period        n/a     RAMB18E2/CLKBWRCLK  n/a            1.355         3.906       2.551      RAMB18_X5Y110  d_1_i/qick_time_tagger_1/inst/QTT/ARM.ARM_MEM/FIFO_PUSH/fifo_mem/mem_reg/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.355         3.906       2.551      RAMB36_X9Y26   d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/fifo_mem/mem_reg_0/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.355         3.906       2.551      RAMB36_X9Y27   d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/fifo_mem/mem_reg_1/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKARDCLK  n/a            1.355         3.906       2.551      RAMB36_X6Y54   d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/mem_reg_bram_0/CLKARDCLK
Min Period        n/a     BUFGCE/I            n/a            1.290         3.906       2.616      BUFGCE_X0Y179  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
Low Pulse Width   Slow    HSADC/FABRIC_CLK    n/a            0.800         1.953       1.153      HSADC_X0Y1     d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/FABRIC_CLK
Low Pulse Width   Fast    HSADC/FABRIC_CLK    n/a            0.800         1.953       1.153      HSADC_X0Y1     d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/FABRIC_CLK
Low Pulse Width   Slow    RAMB18E2/CLKBWRCLK  n/a            0.542         1.953       1.411      RAMB18_X5Y68   d_1_i/qick_time_tagger_0/inst/QTT/ARM.ARM_MEM/FIFO_PUSH/fifo_mem/mem_reg/CLKBWRCLK
Low Pulse Width   Fast    RAMB18E2/CLKBWRCLK  n/a            0.542         1.953       1.411      RAMB18_X5Y68   d_1_i/qick_time_tagger_0/inst/QTT/ARM.ARM_MEM/FIFO_PUSH/fifo_mem/mem_reg/CLKBWRCLK
Low Pulse Width   Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         1.953       1.411      RAMB36_X8Y20   d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/fifo_mem/mem_reg_0/CLKBWRCLK
Low Pulse Width   Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         1.953       1.411      RAMB36_X8Y20   d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/fifo_mem/mem_reg_0/CLKBWRCLK
Low Pulse Width   Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         1.953       1.411      RAMB36_X8Y21   d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/fifo_mem/mem_reg_1/CLKBWRCLK
Low Pulse Width   Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         1.953       1.411      RAMB36_X8Y21   d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/fifo_mem/mem_reg_1/CLKBWRCLK
Low Pulse Width   Slow    RAMB36E2/CLKARDCLK  n/a            0.542         1.953       1.411      RAMB36_X7Y27   d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/mem_reg_bram_0/CLKARDCLK
Low Pulse Width   Fast    RAMB36E2/CLKARDCLK  n/a            0.542         1.953       1.411      RAMB36_X7Y27   d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/mem_reg_bram_0/CLKARDCLK
High Pulse Width  Slow    HSADC/FABRIC_CLK    n/a            0.800         1.953       1.153      HSADC_X0Y1     d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/FABRIC_CLK
High Pulse Width  Fast    HSADC/FABRIC_CLK    n/a            0.800         1.953       1.153      HSADC_X0Y1     d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/FABRIC_CLK
High Pulse Width  Slow    RAMB18E2/CLKBWRCLK  n/a            0.542         1.953       1.411      RAMB18_X5Y68   d_1_i/qick_time_tagger_0/inst/QTT/ARM.ARM_MEM/FIFO_PUSH/fifo_mem/mem_reg/CLKBWRCLK
High Pulse Width  Fast    RAMB18E2/CLKBWRCLK  n/a            0.542         1.953       1.411      RAMB18_X5Y68   d_1_i/qick_time_tagger_0/inst/QTT/ARM.ARM_MEM/FIFO_PUSH/fifo_mem/mem_reg/CLKBWRCLK
High Pulse Width  Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         1.953       1.411      RAMB36_X8Y20   d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/fifo_mem/mem_reg_0/CLKBWRCLK
High Pulse Width  Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         1.953       1.411      RAMB36_X8Y20   d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/fifo_mem/mem_reg_0/CLKBWRCLK
High Pulse Width  Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         1.953       1.411      RAMB36_X8Y21   d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/fifo_mem/mem_reg_1/CLKBWRCLK
High Pulse Width  Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         1.953       1.411      RAMB36_X8Y21   d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/fifo_mem/mem_reg_1/CLKBWRCLK
High Pulse Width  Slow    RAMB36E2/CLKARDCLK  n/a            0.542         1.953       1.411      RAMB36_X7Y27   d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/mem_reg_bram_0/CLKARDCLK
High Pulse Width  Fast    RAMB36E2/CLKARDCLK  n/a            0.542         1.953       1.411      RAMB36_X7Y27   d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/mem_reg_bram_0/CLKARDCLK



---------------------------------------------------------------------------------------------------
From Clock:  RFDAC0_CLK
  To Clock:  RFDAC0_CLK

Setup :            0  Failing Endpoints,  Worst Slack        0.459ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.012ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        0.420ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.459ns  (required time - arrival time)
  Source:                 d_1_i/rst_dac0/U0/SEQ/pr_reg/C
                            (rising edge-triggered cell FDSE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_PORT[0].wave_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2/REGCEAREGCE
                            (rising edge-triggered cell RAMB36E2 clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.441ns  (RFDAC0_CLK rise@2.441ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        1.643ns  (logic 0.247ns (15.037%)  route 1.396ns (84.963%))
  Logic Levels:           2  (LUT1=1 LUT4=1)
  Clock Path Skew:        -0.071ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.765ns = ( 5.206 - 2.441 ) 
    Source Clock Delay      (SCD):    3.097ns
    Clock Pessimism Removal (CPR):    0.261ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.424ns (routing 1.120ns, distribution 1.304ns)
  Clock Net Delay (Destination): 2.244ns (routing 1.015ns, distribution 1.229ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.424     3.097    d_1_i/rst_dac0/U0/SEQ/slowest_sync_clk
                  SLICE_X80Y125        FDSE                                         r  d_1_i/rst_dac0/U0/SEQ/pr_reg/C
  ---------------------------------------------------------------------------------    -------------------
    Placement     SLICE_X80Y125        FDSE (Prop_AFF_SLICEL_C_Q)
                                                                    0.079     3.176 f  d_1_i/rst_dac0/U0/SEQ/pr_reg/Q
                                       net (fo=2, routed)           0.042     3.218    d_1_i/rst_dac0/U0/SEQ/Pr_out
    Placement     SLICE_X80Y125                                                     f  d_1_i/rst_dac0/U0/SEQ/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_i_1/I0
    Placement     SLICE_X80Y125        LUT1 (Prop_A5LUT_SLICEL_I0_O)
                                                                    0.069     3.287 r  d_1_i/rst_dac0/U0/SEQ/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_i_1/O
                                       net (fo=22, routed)          0.972     4.260    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_PORT[0].wave_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/pwropt_2
    Placement     SLICE_X65Y63                                                      r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_PORT[0].wave_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2_REGCEAREGCE_cooolgate_en_gate_13/I0
    Placement     SLICE_X65Y63         LUT4 (Prop_E6LUT_SLICEL_I0_O)
                                                                    0.099     4.359 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_PORT[0].wave_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2_REGCEAREGCE_cooolgate_en_gate_13/O
                                       net (fo=1, routed)           0.381     4.740    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_PORT[0].wave_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2_REGCEAREGCE_cooolgate_en_sig_5
    Placement     RAMB36_X6Y13         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_PORT[0].wave_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2/REGCEAREGCE
  ---------------------------------------------------------------------------------    -------------------

                                       (clock RFDAC0_CLK rise edge)
                                                                    2.441     2.441 r  
                  HSDAC_X0Y0           HSDAC                        0.000     2.441 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.281     2.722 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.126     2.848    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     2.962 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.244     5.206    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_PORT[0].wave_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
                  RAMB36_X6Y13         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_PORT[0].wave_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2/CLKARDCLK
                                       clock pessimism              0.261     5.467    
                                       clock uncertainty           -0.035     5.432    
                  RAMB36_X6Y13         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_REGCEAREGCE)
                                                                   -0.233     5.199    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_PORT[0].wave_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2
  ---------------------------------------------------------------------------------
                                       required time                          5.199    
                                       arrival time                          -4.740    
  ---------------------------------------------------------------------------------
                                       slack                                  0.459    

Slack (MET) :             0.467ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/time_abs_r_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[1].ADDSUB_MACRO_T_inst/trig_pop_r[1]_i_1_psdsp/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.441ns  (RFDAC0_CLK rise@2.441ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        1.992ns  (logic 0.843ns (42.327%)  route 1.149ns (57.673%))
  Logic Levels:           3  (DSP_A_B_DATA=1 DSP_ALU=1 DSP_OUTPUT=1)
  Clock Path Skew:        0.028ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.707ns = ( 5.148 - 2.441 ) 
    Source Clock Delay      (SCD):    3.005ns
    Clock Pessimism Removal (CPR):    0.327ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.332ns (routing 1.120ns, distribution 1.212ns)
  Clock Net Delay (Destination): 2.186ns (routing 1.015ns, distribution 1.171ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.332     3.005    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
                  SLICE_X81Y69         FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/time_abs_r_reg[1]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X81Y69         FDCE (Prop_EFF_SLICEL_C_Q)
                                                                    0.079     3.084 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/time_abs_r_reg[1]/Q
                                       net (fo=8, routed)           0.785     3.869    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[1].ADDSUB_MACRO_T_inst/dsp_bl.DSP48E_BL/B[1]
    Routing       DSP48E2_X13Y30                                                    f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[1].ADDSUB_MACRO_T_inst/dsp_bl.DSP48E_BL/DSP_A_B_DATA_INST/B[1]
    Routing       DSP48E2_X13Y30       DSP_A_B_DATA (Prop_DSP_A_B_DATA_DSP48E2_B[1]_B_ALU[1])
                                                                    0.165     4.034 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[1].ADDSUB_MACRO_T_inst/dsp_bl.DSP48E_BL/DSP_A_B_DATA_INST/B_ALU[1]
                                       net (fo=1, routed)           0.000     4.034    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[1].ADDSUB_MACRO_T_inst/dsp_bl.DSP48E_BL/DSP_A_B_DATA.B_ALU<1>
    Routing       DSP48E2_X13Y30                                                    r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[1].ADDSUB_MACRO_T_inst/dsp_bl.DSP48E_BL/DSP_ALU_INST/B_ALU[1]
    Routing       DSP48E2_X13Y30       DSP_ALU (Prop_DSP_ALU_DSP48E2_B_ALU[1]_COUT[3])
                                                                    0.516     4.550 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[1].ADDSUB_MACRO_T_inst/dsp_bl.DSP48E_BL/DSP_ALU_INST/COUT[3]
                                       net (fo=1, routed)           0.000     4.550    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[1].ADDSUB_MACRO_T_inst/dsp_bl.DSP48E_BL/DSP_ALU.COUT<3>
    Routing       DSP48E2_X13Y30                                                    f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[1].ADDSUB_MACRO_T_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/COUT[3]
    Placement     DSP48E2_X13Y30       DSP_OUTPUT (Prop_DSP_OUTPUT_DSP48E2_COUT[3]_CARRYOUT[3])
                                                                    0.083     4.633 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[1].ADDSUB_MACRO_T_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/CARRYOUT[3]
                                       net (fo=1, routed)           0.364     4.997    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[1].ADDSUB_MACRO_T_inst/trig_pop_r[1]_i_1_psdsp_n
    Placement     SLICE_X76Y80         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[1].ADDSUB_MACRO_T_inst/trig_pop_r[1]_i_1_psdsp/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock RFDAC0_CLK rise edge)
                                                                    2.441     2.441 r  
                  HSDAC_X0Y0           HSDAC                        0.000     2.441 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.281     2.722 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.126     2.848    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     2.962 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.186     5.148    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[1].ADDSUB_MACRO_T_inst/t_clk_i
                  SLICE_X76Y80         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[1].ADDSUB_MACRO_T_inst/trig_pop_r[1]_i_1_psdsp/C
                                       clock pessimism              0.327     5.474    
                                       clock uncertainty           -0.035     5.439    
                  SLICE_X76Y80         FDRE (Setup_EFF_SLICEM_C_D)
                                                                    0.025     5.464    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[1].ADDSUB_MACRO_T_inst/trig_pop_r[1]_i_1_psdsp
  ---------------------------------------------------------------------------------
                                       required time                          5.464    
                                       arrival time                          -4.997    
  ---------------------------------------------------------------------------------
                                       slack                                  0.467    

Slack (MET) :             0.495ns  (required time - arrival time)
  Source:                 d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].prodg_y_full_imag_r_reg[0]/DSP_OUTPUT_INST/CLK
                            (rising edge-triggered cell DSP_OUTPUT clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/DATA_DAC0[27]
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.441ns  (RFDAC0_CLK rise@2.441ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        1.601ns  (logic 0.315ns (19.675%)  route 1.286ns (80.325%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        -0.026ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.846ns = ( 5.287 - 2.441 ) 
    Source Clock Delay      (SCD):    3.137ns
    Clock Pessimism Removal (CPR):    0.265ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.464ns (routing 1.120ns, distribution 1.344ns)
  Clock Net Delay (Destination): 2.228ns (routing 1.015ns, distribution 1.213ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.464     3.137    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].prodg_y_full_imag_r_reg[0]/CLK
                  DSP48E2_X20Y81       DSP_OUTPUT                                   r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].prodg_y_full_imag_r_reg[0]/DSP_OUTPUT_INST/CLK
  ---------------------------------------------------------------------------------    -------------------
    Routing       DSP48E2_X20Y81       DSP_OUTPUT (Prop_DSP_OUTPUT_DSP48E2_CLK_P[26])
                                                                    0.264     3.401 r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].prodg_y_full_imag_r_reg[0]/DSP_OUTPUT_INST/P[26]
                                       net (fo=1, routed)           0.679     4.080    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].round_r_reg[0][27]
    Routing       SLICE_X110Y213                                                    r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/m_axis_tdata[27]_INST_0/I0
    Routing       SLICE_X110Y213       LUT4 (Prop_C6LUT_SLICEM_I0_O)
                                                                    0.051     4.131 r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/m_axis_tdata[27]_INST_0/O
                                       net (fo=1, routed)           0.607     4.738    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s00_axis_tdata[27]
    Routing       HSDAC_X0Y0           HSDAC                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/DATA_DAC0[27]
  ---------------------------------------------------------------------------------    -------------------

                                       (clock RFDAC0_CLK rise edge)
                                                                    2.441     2.441 r  
                  HSDAC_X0Y0           HSDAC                        0.000     2.441 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.281     2.722 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.126     2.848    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     2.962 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.228     5.190    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s0_axis_aclk
                  HSDAC_X0Y0                                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/FABRIC_CLK
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_FABRIC_CLK_INTERNAL_FABRIC_CLK0)
                                                                    0.097     5.287 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FABRIC_CLK0
                                       clock pessimism              0.265     5.552    
                                       clock uncertainty           -0.035     5.517    
                  HSDAC_X0Y0           HSDAC (Setup_HSDAC_INTERNAL_FABRIC_CLK0_DATA_DAC0[27])
                                                                   -0.284     5.233    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac
  ---------------------------------------------------------------------------------
                                       required time                          5.233    
                                       arrival time                          -4.738    
  ---------------------------------------------------------------------------------
                                       slack                                  0.495    

Slack (MET) :             0.498ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/FSM_sequential_time_st_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_PORT[0].data_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/REGCEAREGCE
                            (rising edge-triggered cell RAMB36E2 clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.441ns  (RFDAC0_CLK rise@2.441ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        1.644ns  (logic 0.379ns (23.061%)  route 1.265ns (76.939%))
  Logic Levels:           4  (LUT3=2 LUT5=1 LUT6=1)
  Clock Path Skew:        -0.031ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.759ns = ( 5.200 - 2.441 ) 
    Source Clock Delay      (SCD):    3.123ns
    Clock Pessimism Removal (CPR):    0.333ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.450ns (routing 1.120ns, distribution 1.330ns)
  Clock Net Delay (Destination): 2.238ns (routing 1.015ns, distribution 1.223ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.450     3.123    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/t_clk_i
                  SLICE_X78Y77         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/FSM_sequential_time_st_reg[2]/C
  ---------------------------------------------------------------------------------    -------------------
    Placement     SLICE_X78Y77         FDRE (Prop_FFF_SLICEM_C_Q)
                                                                    0.076     3.199 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/FSM_sequential_time_st_reg[2]/Q
                                       net (fo=17, routed)          0.114     3.313    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/time_st[2]
    Placement     SLICE_X78Y76                                                      r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/AXI_DB.xreg_TPROC_STATUS[7]_i_1/I0
    Placement     SLICE_X78Y76         LUT3 (Prop_C6LUT_SLICEM_I0_O)
                                                                    0.088     3.401 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/AXI_DB.xreg_TPROC_STATUS[7]_i_1/O
                                       net (fo=11, routed)          0.372     3.773    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_PORT[0].ADDSUB_MACRO_D_inst/time_en
    Placement     SLICE_X72Y77                                                      r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_PORT[0].ADDSUB_MACRO_D_inst/data_pop_r[0]_i_1/I3
    Placement     SLICE_X72Y77         LUT5 (Prop_G6LUT_SLICEM_I3_O)
                                                                    0.090     3.863 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_PORT[0].ADDSUB_MACRO_D_inst/data_pop_r[0]_i_1/O
                                       net (fo=2, routed)           0.092     3.955    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/data_pop
    Placement     SLICE_X72Y75                                                      r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/xpm_fifo_async_inst_i_2__5/I4
    Placement     SLICE_X72Y75         LUT6 (Prop_F6LUT_SLICEM_I4_O)
                                                                    0.037     3.992 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/xpm_fifo_async_inst_i_2__5/O
                                       net (fo=11, routed)          0.152     4.145    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_PORT[0].data_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/rd_en
    Placement     SLICE_X70Y74                                                      r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_PORT[0].data_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst_i_3/I2
    Routing       SLICE_X70Y74         LUT3 (Prop_F6LUT_SLICEM_I2_O)
                                                                    0.088     4.233 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_PORT[0].data_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst_i_3/O
                                       net (fo=1, routed)           0.534     4.767    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_PORT[0].data_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/regceb
    Routing       RAMB36_X6Y15         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_PORT[0].data_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/REGCEAREGCE
  ---------------------------------------------------------------------------------    -------------------

                                       (clock RFDAC0_CLK rise edge)
                                                                    2.441     2.441 r  
                  HSDAC_X0Y0           HSDAC                        0.000     2.441 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.281     2.722 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.126     2.848    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     2.962 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.238     5.200    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_PORT[0].data_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
                  RAMB36_X6Y15         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_PORT[0].data_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKARDCLK
                                       clock pessimism              0.333     5.533    
                                       clock uncertainty           -0.035     5.498    
                  RAMB36_X6Y15         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_REGCEAREGCE)
                                                                   -0.233     5.265    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_PORT[0].data_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg
  ---------------------------------------------------------------------------------
                                       required time                          5.265    
                                       arrival time                          -4.767    
  ---------------------------------------------------------------------------------
                                       slack                                  0.498    

Slack (MET) :             0.503ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/time_abs_r_reg[32]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_PORT[0].ADDSUB_MACRO_W_inst/m_axis_tvalid_r[0]_i_1_psdsp/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.441ns  (RFDAC0_CLK rise@2.441ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        1.859ns  (logic 0.871ns (46.850%)  route 0.988ns (53.150%))
  Logic Levels:           3  (DSP_A_B_DATA=1 DSP_ALU=1 DSP_OUTPUT=1)
  Clock Path Skew:        -0.068ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.721ns = ( 5.162 - 2.441 ) 
    Source Clock Delay      (SCD):    3.120ns
    Clock Pessimism Removal (CPR):    0.331ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.447ns (routing 1.120ns, distribution 1.327ns)
  Clock Net Delay (Destination): 2.200ns (routing 1.015ns, distribution 1.185ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.447     3.120    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
                  SLICE_X76Y74         FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/time_abs_r_reg[32]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X76Y74         FDCE (Prop_EFF2_SLICEM_C_Q)
                                                                    0.079     3.199 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/time_abs_r_reg[32]/Q
                                       net (fo=8, routed)           0.603     3.802    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_PORT[0].ADDSUB_MACRO_W_inst/dsp_bl.DSP48E_BL/A[14]
    Routing       DSP48E2_X13Y26                                                    f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_PORT[0].ADDSUB_MACRO_W_inst/dsp_bl.DSP48E_BL/DSP_A_B_DATA_INST/A[14]
    Routing       DSP48E2_X13Y26       DSP_A_B_DATA (Prop_DSP_A_B_DATA_DSP48E2_A[14]_A_ALU[14])
                                                                    0.194     3.996 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_PORT[0].ADDSUB_MACRO_W_inst/dsp_bl.DSP48E_BL/DSP_A_B_DATA_INST/A_ALU[14]
                                       net (fo=1, routed)           0.000     3.996    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_PORT[0].ADDSUB_MACRO_W_inst/dsp_bl.DSP48E_BL/DSP_A_B_DATA.A_ALU<14>
    Routing       DSP48E2_X13Y26                                                    r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_PORT[0].ADDSUB_MACRO_W_inst/dsp_bl.DSP48E_BL/DSP_ALU_INST/A_ALU[14]
    Routing       DSP48E2_X13Y26       DSP_ALU (Prop_DSP_ALU_DSP48E2_A_ALU[14]_COUT[3])
                                                                    0.515     4.511 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_PORT[0].ADDSUB_MACRO_W_inst/dsp_bl.DSP48E_BL/DSP_ALU_INST/COUT[3]
                                       net (fo=1, routed)           0.000     4.511    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_PORT[0].ADDSUB_MACRO_W_inst/dsp_bl.DSP48E_BL/DSP_ALU.COUT<3>
    Routing       DSP48E2_X13Y26                                                    f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_PORT[0].ADDSUB_MACRO_W_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/COUT[3]
    Routing       DSP48E2_X13Y26       DSP_OUTPUT (Prop_DSP_OUTPUT_DSP48E2_COUT[3]_CARRYOUT[3])
                                                                    0.083     4.594 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_PORT[0].ADDSUB_MACRO_W_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/CARRYOUT[3]
                                       net (fo=1, routed)           0.385     4.979    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_PORT[0].ADDSUB_MACRO_W_inst/m_axis_tvalid_r[0]_i_1_psdsp_n
    Routing       SLICE_X75Y69         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_PORT[0].ADDSUB_MACRO_W_inst/m_axis_tvalid_r[0]_i_1_psdsp/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock RFDAC0_CLK rise edge)
                                                                    2.441     2.441 r  
                  HSDAC_X0Y0           HSDAC                        0.000     2.441 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.281     2.722 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.126     2.848    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     2.962 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.200     5.162    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_PORT[0].ADDSUB_MACRO_W_inst/t_clk_i
                  SLICE_X75Y69         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_PORT[0].ADDSUB_MACRO_W_inst/m_axis_tvalid_r[0]_i_1_psdsp/C
                                       clock pessimism              0.331     5.493    
                                       clock uncertainty           -0.035     5.457    
                  SLICE_X75Y69         FDRE (Setup_AFF_SLICEM_C_D)
                                                                    0.025     5.482    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_PORT[0].ADDSUB_MACRO_W_inst/m_axis_tvalid_r[0]_i_1_psdsp
  ---------------------------------------------------------------------------------
                                       required time                          5.482    
                                       arrival time                          -4.979    
  ---------------------------------------------------------------------------------
                                       slack                                  0.503    

Slack (MET) :             0.515ns  (required time - arrival time)
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_8/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/prod_y_full_imag_b[0]/DSP_A_B_DATA_INST/RSTB
                            (rising edge-triggered cell DSP_A_B_DATA clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.441ns  (RFDAC0_CLK rise@2.441ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        1.608ns  (logic 0.079ns (4.912%)  route 1.529ns (95.088%))
  Logic Levels:           0  
  Clock Path Skew:        -0.082ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.594ns = ( 5.035 - 2.441 ) 
    Source Clock Delay      (SCD):    2.994ns
    Clock Pessimism Removal (CPR):    0.318ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.321ns (routing 1.120ns, distribution 1.201ns)
  Clock Net Delay (Destination): 2.073ns (routing 1.015ns, distribution 1.058ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.321     2.994    d_1_i/rst_dac0/U0/slowest_sync_clk
                  SLICE_X88Y143        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_8/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X88Y143        FDRE (Prop_EFF_SLICEL_C_Q)
                                                                    0.079     3.073 f  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_8/Q
                                       net (fo=154, routed)         1.529     4.603    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/prod_y_full_imag_b[0]/RSTB
    Routing       DSP48E2_X18Y67       DSP_A_B_DATA                                 r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/prod_y_full_imag_b[0]/DSP_A_B_DATA_INST/RSTB  (IS_INVERTED)
  ---------------------------------------------------------------------------------    -------------------

                                       (clock RFDAC0_CLK rise edge)
                                                                    2.441     2.441 r  
                  HSDAC_X0Y0           HSDAC                        0.000     2.441 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.281     2.722 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.126     2.848    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     2.962 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.073     5.035    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/prod_y_full_imag_b[0]/CLK
                  DSP48E2_X18Y67       DSP_A_B_DATA                                 r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/prod_y_full_imag_b[0]/DSP_A_B_DATA_INST/CLK
                                       clock pessimism              0.318     5.354    
                                       clock uncertainty           -0.035     5.318    
                  DSP48E2_X18Y67       DSP_A_B_DATA (Setup_DSP_A_B_DATA_DSP48E2_CLK_RSTB)
                                                                   -0.201     5.117    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/prod_y_full_imag_b[0]/DSP_A_B_DATA_INST
  ---------------------------------------------------------------------------------
                                       required time                          5.117    
                                       arrival time                          -4.603    
  ---------------------------------------------------------------------------------
                                       slack                                  0.515    

Slack (MET) :             0.517ns  (required time - arrival time)
  Source:                 d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].prodg_y_full_imag_r_reg[0]/DSP_OUTPUT_INST/CLK
                            (rising edge-triggered cell DSP_OUTPUT clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/DATA_DAC0[17]
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.441ns  (RFDAC0_CLK rise@2.441ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        1.597ns  (logic 0.299ns (18.723%)  route 1.298ns (81.277%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        -0.026ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.846ns = ( 5.287 - 2.441 ) 
    Source Clock Delay      (SCD):    3.137ns
    Clock Pessimism Removal (CPR):    0.265ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.464ns (routing 1.120ns, distribution 1.344ns)
  Clock Net Delay (Destination): 2.228ns (routing 1.015ns, distribution 1.213ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.464     3.137    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].prodg_y_full_imag_r_reg[0]/CLK
                  DSP48E2_X20Y81       DSP_OUTPUT                                   r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].prodg_y_full_imag_r_reg[0]/DSP_OUTPUT_INST/CLK
  ---------------------------------------------------------------------------------    -------------------
    Routing       DSP48E2_X20Y81       DSP_OUTPUT (Prop_DSP_OUTPUT_DSP48E2_CLK_P[16])
                                                                    0.209     3.346 r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].prodg_y_full_imag_r_reg[0]/DSP_OUTPUT_INST/P[16]
                                       net (fo=1, routed)           0.688     4.034    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].round_r_reg[0][17]
    Routing       SLICE_X110Y213                                                    r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/m_axis_tdata[17]_INST_0/I0
    Routing       SLICE_X110Y213       LUT4 (Prop_G6LUT_SLICEM_I0_O)
                                                                    0.090     4.124 r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/m_axis_tdata[17]_INST_0/O
                                       net (fo=1, routed)           0.610     4.734    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s00_axis_tdata[17]
    Routing       HSDAC_X0Y0           HSDAC                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/DATA_DAC0[17]
  ---------------------------------------------------------------------------------    -------------------

                                       (clock RFDAC0_CLK rise edge)
                                                                    2.441     2.441 r  
                  HSDAC_X0Y0           HSDAC                        0.000     2.441 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.281     2.722 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.126     2.848    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     2.962 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.228     5.190    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s0_axis_aclk
                  HSDAC_X0Y0                                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/FABRIC_CLK
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_FABRIC_CLK_INTERNAL_FABRIC_CLK0)
                                                                    0.097     5.287 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FABRIC_CLK0
                                       clock pessimism              0.265     5.552    
                                       clock uncertainty           -0.035     5.517    
                  HSDAC_X0Y0           HSDAC (Setup_HSDAC_INTERNAL_FABRIC_CLK0_DATA_DAC0[17])
                                                                   -0.266     5.251    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac
  ---------------------------------------------------------------------------------
                                       required time                          5.251    
                                       arrival time                          -4.734    
  ---------------------------------------------------------------------------------
                                       slack                                  0.517    

Slack (MET) :             0.519ns  (required time - arrival time)
  Source:                 d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].prodg_y_full_imag_r_reg[0]/DSP_OUTPUT_INST/CLK
                            (rising edge-triggered cell DSP_OUTPUT clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/DATA_DAC0[28]
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.441ns  (RFDAC0_CLK rise@2.441ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        1.604ns  (logic 0.311ns (19.389%)  route 1.293ns (80.611%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        -0.026ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.846ns = ( 5.287 - 2.441 ) 
    Source Clock Delay      (SCD):    3.137ns
    Clock Pessimism Removal (CPR):    0.265ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.464ns (routing 1.120ns, distribution 1.344ns)
  Clock Net Delay (Destination): 2.228ns (routing 1.015ns, distribution 1.213ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.464     3.137    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].prodg_y_full_imag_r_reg[0]/CLK
                  DSP48E2_X20Y81       DSP_OUTPUT                                   r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].prodg_y_full_imag_r_reg[0]/DSP_OUTPUT_INST/CLK
  ---------------------------------------------------------------------------------    -------------------
    Routing       DSP48E2_X20Y81       DSP_OUTPUT (Prop_DSP_OUTPUT_DSP48E2_CLK_P[27])
                                                                    0.223     3.360 r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].prodg_y_full_imag_r_reg[0]/DSP_OUTPUT_INST/P[27]
                                       net (fo=1, routed)           0.688     4.048    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].round_r_reg[0][28]
    Routing       SLICE_X110Y213                                                    r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/m_axis_tdata[28]_INST_0/I0
    Routing       SLICE_X110Y213       LUT4 (Prop_F6LUT_SLICEM_I0_O)
                                                                    0.088     4.136 r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/m_axis_tdata[28]_INST_0/O
                                       net (fo=1, routed)           0.605     4.741    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s00_axis_tdata[28]
    Routing       HSDAC_X0Y0           HSDAC                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/DATA_DAC0[28]
  ---------------------------------------------------------------------------------    -------------------

                                       (clock RFDAC0_CLK rise edge)
                                                                    2.441     2.441 r  
                  HSDAC_X0Y0           HSDAC                        0.000     2.441 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.281     2.722 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.126     2.848    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     2.962 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.228     5.190    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s0_axis_aclk
                  HSDAC_X0Y0                                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/FABRIC_CLK
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_FABRIC_CLK_INTERNAL_FABRIC_CLK0)
                                                                    0.097     5.287 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FABRIC_CLK0
                                       clock pessimism              0.265     5.552    
                                       clock uncertainty           -0.035     5.517    
                  HSDAC_X0Y0           HSDAC (Setup_HSDAC_INTERNAL_FABRIC_CLK0_DATA_DAC0[28])
                                                                   -0.257     5.260    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac
  ---------------------------------------------------------------------------------
                                       required time                          5.260    
                                       arrival time                          -4.741    
  ---------------------------------------------------------------------------------
                                       slack                                  0.519    

Slack (MET) :             0.528ns  (required time - arrival time)
  Source:                 d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_non_symmetric.g_data_array.g_data[1].g_data_casc_buff.i_data_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][15]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[3].g_non_symmetric.g_madds.g_madd[2].i_madd/i_addsub_mult_add/g_dsp48.g_dsp48e2.i_dsp48e2/DSP_A_B_DATA_INST/A[25]
                            (rising edge-triggered cell DSP_A_B_DATA clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.441ns  (RFDAC0_CLK rise@2.441ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        1.470ns  (logic 0.078ns (5.308%)  route 1.392ns (94.692%))
  Logic Levels:           0  
  Clock Path Skew:        -0.109ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.572ns = ( 5.013 - 2.441 ) 
    Source Clock Delay      (SCD):    2.999ns
    Clock Pessimism Removal (CPR):    0.318ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.326ns (routing 1.120ns, distribution 1.206ns)
  Clock Net Delay (Destination): 2.051ns (routing 1.015ns, distribution 1.036ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.326     2.999    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_non_symmetric.g_data_array.g_data[1].g_data_casc_buff.i_data_casc_buff/g_buff.i_buff/aclk
                  SLICE_X87Y143        FDRE                                         r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_non_symmetric.g_data_array.g_data[1].g_data_casc_buff.i_data_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][15]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X87Y143        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                                    0.078     3.077 r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_non_symmetric.g_data_array.g_data[1].g_data_casc_buff.i_data_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][15]/Q
                                       net (fo=61, routed)          1.392     4.469    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[3].g_non_symmetric.g_madds.g_madd[2].i_madd/i_addsub_mult_add/g_dsp48.g_dsp48e2.i_dsp48e2/A[25]
    Routing       DSP48E2_X16Y65       DSP_A_B_DATA                                 r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[3].g_non_symmetric.g_madds.g_madd[2].i_madd/i_addsub_mult_add/g_dsp48.g_dsp48e2.i_dsp48e2/DSP_A_B_DATA_INST/A[25]
  ---------------------------------------------------------------------------------    -------------------

                                       (clock RFDAC0_CLK rise edge)
                                                                    2.441     2.441 r  
                  HSDAC_X0Y0           HSDAC                        0.000     2.441 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.281     2.722 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.126     2.848    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     2.962 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.051     5.013    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[3].g_non_symmetric.g_madds.g_madd[2].i_madd/i_addsub_mult_add/g_dsp48.g_dsp48e2.i_dsp48e2/CLK
                  DSP48E2_X16Y65       DSP_A_B_DATA                                 r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[3].g_non_symmetric.g_madds.g_madd[2].i_madd/i_addsub_mult_add/g_dsp48.g_dsp48e2.i_dsp48e2/DSP_A_B_DATA_INST/CLK
                                       clock pessimism              0.318     5.331    
                                       clock uncertainty           -0.035     5.296    
                  DSP48E2_X16Y65       DSP_A_B_DATA (Setup_DSP_A_B_DATA_DSP48E2_CLK_A[25])
                                                                   -0.299     4.997    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[3].g_non_symmetric.g_madds.g_madd[2].i_madd/i_addsub_mult_add/g_dsp48.g_dsp48e2.i_dsp48e2/DSP_A_B_DATA_INST
  ---------------------------------------------------------------------------------
                                       required time                          4.997    
                                       arrival time                          -4.469    
  ---------------------------------------------------------------------------------
                                       slack                                  0.528    

Slack (MET) :             0.529ns  (required time - arrival time)
  Source:                 d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].prodg_y_full_imag_r_reg[0]/DSP_OUTPUT_INST/CLK
                            (rising edge-triggered cell DSP_OUTPUT clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/DATA_DAC0[26]
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.441ns  (RFDAC0_CLK rise@2.441ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        1.548ns  (logic 0.360ns (23.256%)  route 1.188ns (76.744%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        -0.026ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.846ns = ( 5.287 - 2.441 ) 
    Source Clock Delay      (SCD):    3.137ns
    Clock Pessimism Removal (CPR):    0.265ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.464ns (routing 1.120ns, distribution 1.344ns)
  Clock Net Delay (Destination): 2.228ns (routing 1.015ns, distribution 1.213ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.464     3.137    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].prodg_y_full_imag_r_reg[0]/CLK
                  DSP48E2_X20Y81       DSP_OUTPUT                                   r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].prodg_y_full_imag_r_reg[0]/DSP_OUTPUT_INST/CLK
  ---------------------------------------------------------------------------------    -------------------
    Routing       DSP48E2_X20Y81       DSP_OUTPUT (Prop_DSP_OUTPUT_DSP48E2_CLK_P[25])
                                                                    0.214     3.351 r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].prodg_y_full_imag_r_reg[0]/DSP_OUTPUT_INST/P[25]
                                       net (fo=1, routed)           0.527     3.878    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].round_r_reg[0][26]
    Routing       SLICE_X111Y211                                                    r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/m_axis_tdata[26]_INST_0/I0
    Routing       SLICE_X111Y211       LUT4 (Prop_C6LUT_SLICEL_I0_O)
                                                                    0.146     4.024 r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/m_axis_tdata[26]_INST_0/O
                                       net (fo=1, routed)           0.661     4.685    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s00_axis_tdata[26]
    Routing       HSDAC_X0Y0           HSDAC                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/DATA_DAC0[26]
  ---------------------------------------------------------------------------------    -------------------

                                       (clock RFDAC0_CLK rise edge)
                                                                    2.441     2.441 r  
                  HSDAC_X0Y0           HSDAC                        0.000     2.441 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.281     2.722 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.126     2.848    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     2.962 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.228     5.190    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s0_axis_aclk
                  HSDAC_X0Y0                                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/FABRIC_CLK
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_FABRIC_CLK_INTERNAL_FABRIC_CLK0)
                                                                    0.097     5.287 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FABRIC_CLK0
                                       clock pessimism              0.265     5.552    
                                       clock uncertainty           -0.035     5.517    
                  HSDAC_X0Y0           HSDAC (Setup_HSDAC_INTERNAL_FABRIC_CLK0_DATA_DAC0[26])
                                                                   -0.303     5.214    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac
  ---------------------------------------------------------------------------------
                                       required time                          5.214    
                                       arrival time                          -4.685    
  ---------------------------------------------------------------------------------
                                       slack                                  0.529    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.012ns  (arrival time - required time)
  Source:                 d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[226]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[3].dds_i/U0/i_synth/has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC0_CLK rise@0.000ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        0.316ns  (logic 0.058ns (18.341%)  route 0.258ns (81.659%))
  Logic Levels:           0  
  Clock Path Skew:        0.243ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.089ns
    Source Clock Delay      (SCD):    2.585ns
    Clock Pessimism Removal (CPR):    0.261ns
  Clock Net Delay (Source):      2.064ns (routing 1.015ns, distribution 1.049ns)
  Clock Net Delay (Destination): 2.416ns (routing 1.120ns, distribution 1.296ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.064     2.585    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/aclk
                  SLICE_X93Y120        FDRE                                         r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[226]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X93Y120        FDRE (Prop_BFF_SLICEM_C_Q)
                                                                    0.058     2.643 r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[226]/Q
                                       net (fo=8, routed)           0.258     2.901    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[3].dds_i/U0/i_synth/s_axis_phase_tdata[10]
    Routing       SLICE_X103Y111       FDRE                                         r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[3].dds_i/U0/i_synth/has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[10]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.416     3.089    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[3].dds_i/U0/i_synth/aclk
                  SLICE_X103Y111       FDRE                                         r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[3].dds_i/U0/i_synth/has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[10]/C
                                       clock pessimism             -0.261     2.828    
                  SLICE_X103Y111       FDRE (Hold_DFF2_SLICEM_C_D)
                                                                    0.061     2.889    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[3].dds_i/U0/i_synth/has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[10]
  ---------------------------------------------------------------------------------
                                       required time                         -2.889    
                                       arrival time                           2.901    
  ---------------------------------------------------------------------------------
                                       slack                                  0.012    

Slack (MET) :             0.012ns  (arrival time - required time)
  Source:                 d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/fifo_dout_r_reg[49]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_r3_reg[17]_srl3___inst_signal_gen_top_i_signal_gen_i_ctrl_i_en_reg_r3_reg_r/D
                            (rising edge-triggered cell SRL16E clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC0_CLK rise@0.000ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        0.165ns  (logic 0.058ns (35.152%)  route 0.107ns (64.848%))
  Logic Levels:           0  
  Clock Path Skew:        0.124ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.037ns
    Source Clock Delay      (SCD):    2.588ns
    Clock Pessimism Removal (CPR):    0.324ns
  Clock Net Delay (Source):      2.067ns (routing 1.015ns, distribution 1.052ns)
  Clock Net Delay (Destination): 2.364ns (routing 1.120ns, distribution 1.244ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.067     2.588    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
                  SLICE_X85Y111        FDRE                                         r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/fifo_dout_r_reg[49]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X85Y111        FDRE (Prop_AFF_SLICEL_C_Q)
                                                                    0.058     2.646 r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/fifo_dout_r_reg[49]/Q
                                       net (fo=1, routed)           0.107     2.753    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_int[17]
    Routing       SLICE_X86Y112        SRL16E                                       r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_r3_reg[17]_srl3___inst_signal_gen_top_i_signal_gen_i_ctrl_i_en_reg_r3_reg_r/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.364     3.037    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
                  SLICE_X86Y112        SRL16E                                       r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_r3_reg[17]_srl3___inst_signal_gen_top_i_signal_gen_i_ctrl_i_en_reg_r3_reg_r/CLK
                                       clock pessimism             -0.324     2.712    
                  SLICE_X86Y112        SRL16E (Hold_B6LUT_SLICEM_CLK_D)
                                                                    0.029     2.741    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_r3_reg[17]_srl3___inst_signal_gen_top_i_signal_gen_i_ctrl_i_en_reg_r3_reg_r
  ---------------------------------------------------------------------------------
                                       required time                         -2.741    
                                       arrival time                           2.753    
  ---------------------------------------------------------------------------------
                                       slack                                  0.012    

Slack (MET) :             0.014ns  (arrival time - required time)
  Source:                 d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[199]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[2].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_common.i_stream_poff_gen.poff_channel_in/opt_has_pipe.first_q_reg[23]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC0_CLK rise@0.000ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        0.320ns  (logic 0.058ns (18.125%)  route 0.262ns (81.875%))
  Logic Levels:           0  
  Clock Path Skew:        0.244ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.085ns
    Source Clock Delay      (SCD):    2.580ns
    Clock Pessimism Removal (CPR):    0.261ns
  Clock Net Delay (Source):      2.059ns (routing 1.015ns, distribution 1.044ns)
  Clock Net Delay (Destination): 2.412ns (routing 1.120ns, distribution 1.292ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.059     2.580    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/aclk
                  SLICE_X94Y124        FDRE                                         r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[199]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X94Y124        FDRE (Prop_GFF_SLICEM_C_Q)
                                                                    0.058     2.638 r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[199]/Q
                                       net (fo=1, routed)           0.262     2.900    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[2].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_common.i_stream_poff_gen.poff_channel_in/s_axis_phase_tdata[23]
    Routing       SLICE_X98Y110        FDRE                                         r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[2].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_common.i_stream_poff_gen.poff_channel_in/opt_has_pipe.first_q_reg[23]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.412     3.085    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[2].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_common.i_stream_poff_gen.poff_channel_in/aclk
                  SLICE_X98Y110        FDRE                                         r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[2].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_common.i_stream_poff_gen.poff_channel_in/opt_has_pipe.first_q_reg[23]/C
                                       clock pessimism             -0.261     2.824    
                  SLICE_X98Y110        FDRE (Hold_BFF2_SLICEL_C_D)
                                                                    0.062     2.886    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[2].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_common.i_stream_poff_gen.poff_channel_in/opt_has_pipe.first_q_reg[23]
  ---------------------------------------------------------------------------------
                                       required time                         -2.886    
                                       arrival time                           2.900    
  ---------------------------------------------------------------------------------
                                       slack                                  0.014    

Slack (MET) :             0.014ns  (arrival time - required time)
  Source:                 d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[0].g_non_symmetric.g_data_array.g_data[1].g_data_casc_buff.i_data_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][0]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[0].g_non_symmetric.g_data_array.g_data[2].g_data_casc_buff.i_data_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][0]_srl1/D
                            (rising edge-triggered cell SRL16E clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC0_CLK rise@0.000ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        0.178ns  (logic 0.058ns (32.510%)  route 0.120ns (67.490%))
  Logic Levels:           0  
  Clock Path Skew:        0.135ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.035ns
    Source Clock Delay      (SCD):    2.582ns
    Clock Pessimism Removal (CPR):    0.318ns
  Clock Net Delay (Source):      2.061ns (routing 1.015ns, distribution 1.046ns)
  Clock Net Delay (Destination): 2.362ns (routing 1.120ns, distribution 1.242ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.061     2.582    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[0].g_non_symmetric.g_data_array.g_data[1].g_data_casc_buff.i_data_casc_buff/g_buff.i_buff/aclk
                  SLICE_X87Y125        FDRE                                         r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[0].g_non_symmetric.g_data_array.g_data[1].g_data_casc_buff.i_data_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][0]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X87Y125        FDRE (Prop_AFF_SLICEM_C_Q)
                                                                    0.058     2.640 r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[0].g_non_symmetric.g_data_array.g_data[1].g_data_casc_buff.i_data_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][0]/Q
                                       net (fo=5, routed)           0.120     2.760    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[0].g_non_symmetric.g_data_array.g_data[2].g_data_casc_buff.i_data_casc_buff/g_buff.i_buff/A[0]
    Routing       SLICE_X89Y126        SRL16E                                       r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[0].g_non_symmetric.g_data_array.g_data[2].g_data_casc_buff.i_data_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][0]_srl1/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.362     3.035    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[0].g_non_symmetric.g_data_array.g_data[2].g_data_casc_buff.i_data_casc_buff/g_buff.i_buff/aclk
                  SLICE_X89Y126        SRL16E                                       r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[0].g_non_symmetric.g_data_array.g_data[2].g_data_casc_buff.i_data_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][0]_srl1/CLK
                                       clock pessimism             -0.318     2.717    
                  SLICE_X89Y126        SRL16E (Hold_A6LUT_SLICEM_CLK_D)
                                                                    0.029     2.746    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[0].g_non_symmetric.g_data_array.g_data[2].g_data_casc_buff.i_data_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][0]_srl1
  ---------------------------------------------------------------------------------
                                       required time                         -2.746    
                                       arrival time                           2.760    
  ---------------------------------------------------------------------------------
                                       slack                                  0.014    

Slack (MET) :             0.016ns  (arrival time - required time)
  Source:                 d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[1].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms/opt_has_pipe.first_q_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[1].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ms/opt_has_pipe.first_q_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC0_CLK rise@0.000ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        0.190ns  (logic 0.093ns (48.856%)  route 0.097ns (51.144%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        0.114ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.056ns
    Source Clock Delay      (SCD):    2.616ns
    Clock Pessimism Removal (CPR):    0.326ns
  Clock Net Delay (Source):      2.095ns (routing 1.015ns, distribution 1.080ns)
  Clock Net Delay (Destination): 2.383ns (routing 1.120ns, distribution 1.263ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.095     2.616    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[1].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms/aclk
                  SLICE_X98Y154        FDRE                                         r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[1].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms/opt_has_pipe.first_q_reg[0]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X98Y154        FDRE (Prop_AFF_SLICEL_C_Q)
                                                                    0.058     2.674 r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[1].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms/opt_has_pipe.first_q_reg[0]/Q
                                       net (fo=6, routed)           0.061     2.735    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[1].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.cos_ms1[0]
    Routing       SLICE_X99Y154                                                     r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[1].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/plusOp_inferred__2/opt_has_pipe.first_q[4]_i_1/I2
    Routing       SLICE_X99Y154        LUT6 (Prop_D6LUT_SLICEM_I2_O)
                                                                    0.035     2.770 r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[1].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/plusOp_inferred__2/opt_has_pipe.first_q[4]_i_1/O
                                       net (fo=1, routed)           0.036     2.806    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[1].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ms/D[4]
    Routing       SLICE_X99Y154        FDRE                                         r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[1].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ms/opt_has_pipe.first_q_reg[4]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.383     3.056    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[1].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ms/aclk
                  SLICE_X99Y154        FDRE                                         r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[1].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ms/opt_has_pipe.first_q_reg[4]/C
                                       clock pessimism             -0.326     2.730    
                  SLICE_X99Y154        FDRE (Hold_DFF_SLICEM_C_D)
                                                                    0.060     2.790    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[1].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ms/opt_has_pipe.first_q_reg[4]
  ---------------------------------------------------------------------------------
                                       required time                         -2.790    
                                       arrival time                           2.806    
  ---------------------------------------------------------------------------------
                                       slack                                  0.016    

Slack (MET) :             0.023ns  (arrival time - required time)
  Source:                 d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[0].phase_v1_r1_reg[0][22]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[54]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC0_CLK rise@0.000ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        0.193ns  (logic 0.060ns (31.088%)  route 0.133ns (68.912%))
  Logic Levels:           0  
  Clock Path Skew:        0.108ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.024ns
    Source Clock Delay      (SCD):    2.592ns
    Clock Pessimism Removal (CPR):    0.324ns
  Clock Net Delay (Source):      2.071ns (routing 1.015ns, distribution 1.056ns)
  Clock Net Delay (Destination): 2.351ns (routing 1.120ns, distribution 1.231ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.071     2.592    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
                  SLICE_X92Y116        FDRE                                         r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[0].phase_v1_r1_reg[0][22]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X92Y116        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                                    0.060     2.652 r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[0].phase_v1_r1_reg[0][22]/Q
                                       net (fo=1, routed)           0.133     2.785    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_phase[0].phase_v1_r1_reg[0][22]
    Routing       SLICE_X95Y116        FDRE                                         r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[54]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.351     3.024    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/aclk
                  SLICE_X95Y116        FDRE                                         r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[54]/C
                                       clock pessimism             -0.324     2.700    
                  SLICE_X95Y116        FDRE (Hold_GFF2_SLICEL_C_D)
                                                                    0.062     2.762    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[54]
  ---------------------------------------------------------------------------------
                                       required time                         -2.762    
                                       arrival time                           2.785    
  ---------------------------------------------------------------------------------
                                       slack                                  0.023    

Slack (MET) :             0.023ns  (arrival time - required time)
  Source:                 d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[2].env_real_latency_reg_i/shift_r_reg[0][4]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[2].env_real_latency_reg_i/GEN_reg[1].shift_r_reg[1][4]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC0_CLK rise@0.000ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        0.269ns  (logic 0.058ns (21.561%)  route 0.211ns (78.439%))
  Logic Levels:           0  
  Clock Path Skew:        0.184ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.066ns
    Source Clock Delay      (SCD):    2.561ns
    Clock Pessimism Removal (CPR):    0.321ns
  Clock Net Delay (Source):      2.040ns (routing 1.015ns, distribution 1.025ns)
  Clock Net Delay (Destination): 2.393ns (routing 1.120ns, distribution 1.273ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.040     2.561    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[2].env_real_latency_reg_i/aclk
                  SLICE_X96Y157        FDRE                                         r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[2].env_real_latency_reg_i/shift_r_reg[0][4]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X96Y157        FDRE (Prop_EFF_SLICEM_C_Q)
                                                                    0.058     2.619 r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[2].env_real_latency_reg_i/shift_r_reg[0][4]/Q
                                       net (fo=1, routed)           0.211     2.830    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[2].env_real_latency_reg_i/shift_r_reg_n_0_[0][4]
    Routing       SLICE_X97Y164        FDRE                                         r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[2].env_real_latency_reg_i/GEN_reg[1].shift_r_reg[1][4]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.393     3.066    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[2].env_real_latency_reg_i/aclk
                  SLICE_X97Y164        FDRE                                         r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[2].env_real_latency_reg_i/GEN_reg[1].shift_r_reg[1][4]/C
                                       clock pessimism             -0.321     2.745    
                  SLICE_X97Y164        FDRE (Hold_AFF2_SLICEM_C_D)
                                                                    0.062     2.807    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[2].env_real_latency_reg_i/GEN_reg[1].shift_r_reg[1][4]
  ---------------------------------------------------------------------------------
                                       required time                         -2.807    
                                       arrival time                           2.830    
  ---------------------------------------------------------------------------------
                                       slack                                  0.023    

Slack (MET) :             0.023ns  (arrival time - required time)
  Source:                 d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[226]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[2].dds_i/U0/i_synth/has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC0_CLK rise@0.000ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        0.324ns  (logic 0.058ns (17.889%)  route 0.266ns (82.111%))
  Logic Levels:           0  
  Clock Path Skew:        0.241ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.087ns
    Source Clock Delay      (SCD):    2.585ns
    Clock Pessimism Removal (CPR):    0.261ns
  Clock Net Delay (Source):      2.064ns (routing 1.015ns, distribution 1.049ns)
  Clock Net Delay (Destination): 2.414ns (routing 1.120ns, distribution 1.294ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.064     2.585    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/aclk
                  SLICE_X93Y120        FDRE                                         r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[226]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X93Y120        FDRE (Prop_BFF_SLICEM_C_Q)
                                                                    0.058     2.643 r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[226]/Q
                                       net (fo=8, routed)           0.266     2.909    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[2].dds_i/U0/i_synth/s_axis_phase_tdata[10]
    Routing       SLICE_X103Y111       FDRE                                         r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[2].dds_i/U0/i_synth/has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[10]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.414     3.087    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[2].dds_i/U0/i_synth/aclk
                  SLICE_X103Y111       FDRE                                         r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[2].dds_i/U0/i_synth/has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[10]/C
                                       clock pessimism             -0.261     2.826    
                  SLICE_X103Y111       FDRE (Hold_EFF_SLICEM_C_D)
                                                                    0.060     2.886    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[2].dds_i/U0/i_synth/has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[10]
  ---------------------------------------------------------------------------------
                                       required time                         -2.886    
                                       arrival time                           2.909    
  ---------------------------------------------------------------------------------
                                       slack                                  0.023    

Slack (MET) :             0.025ns  (arrival time - required time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][12]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/fifo_i/mem_i/RAM_reg_0_15_0_13/RAMG/I
                            (rising edge-triggered cell RAMD32 clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC0_CLK rise@0.000ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        0.273ns  (logic 0.058ns (21.245%)  route 0.215ns (78.755%))
  Logic Levels:           0  
  Clock Path Skew:        0.170ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.067ns
    Source Clock Delay      (SCD):    2.573ns
    Clock Pessimism Removal (CPR):    0.324ns
  Clock Net Delay (Source):      2.052ns (routing 1.015ns, distribution 1.037ns)
  Clock Net Delay (Destination): 2.394ns (routing 1.120ns, distribution 1.274ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.052     2.573    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
                  SLICE_X81Y96         FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][12]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X81Y96         FDCE (Prop_CFF_SLICEL_C_Q)
                                                                    0.058     2.631 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][12]/Q
                                       net (fo=1, routed)           0.215     2.846    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/fifo_i/mem_i/RAM_reg_0_15_0_13/DIG0
    Routing       SLICE_X83Y110        RAMD32                                       r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/fifo_i/mem_i/RAM_reg_0_15_0_13/RAMG/I
  ---------------------------------------------------------------------------------    -------------------

                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.394     3.067    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/fifo_i/mem_i/RAM_reg_0_15_0_13/WCLK
                  SLICE_X83Y110        RAMD32                                       r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/fifo_i/mem_i/RAM_reg_0_15_0_13/RAMG/CLK
                                       clock pessimism             -0.324     2.743    
                  SLICE_X83Y110        RAMD32 (Hold_G5LUT_SLICEM_CLK_I)
                                                                    0.078     2.821    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/fifo_i/mem_i/RAM_reg_0_15_0_13/RAMG
  ---------------------------------------------------------------------------------
                                       required time                         -2.821    
                                       arrival time                           2.846    
  ---------------------------------------------------------------------------------
                                       slack                                  0.025    

Slack (MET) :             0.025ns  (arrival time - required time)
  Source:                 d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/fifo_dout_r_reg[54]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_r3_reg[22]_srl3___inst_signal_gen_top_i_signal_gen_i_ctrl_i_en_reg_r3_reg_r/D
                            (rising edge-triggered cell SRL16E clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC0_CLK rise@0.000ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        0.169ns  (logic 0.060ns (35.503%)  route 0.109ns (64.497%))
  Logic Levels:           0  
  Clock Path Skew:        0.124ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.037ns
    Source Clock Delay      (SCD):    2.588ns
    Clock Pessimism Removal (CPR):    0.324ns
  Clock Net Delay (Source):      2.067ns (routing 1.015ns, distribution 1.052ns)
  Clock Net Delay (Destination): 2.364ns (routing 1.120ns, distribution 1.244ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.067     2.588    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
                  SLICE_X85Y111        FDRE                                         r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/fifo_dout_r_reg[54]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X85Y111        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                                    0.060     2.648 r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/fifo_dout_r_reg[54]/Q
                                       net (fo=1, routed)           0.109     2.757    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_int[22]
    Routing       SLICE_X86Y112        SRL16E                                       r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_r3_reg[22]_srl3___inst_signal_gen_top_i_signal_gen_i_ctrl_i_en_reg_r3_reg_r/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.364     3.037    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
                  SLICE_X86Y112        SRL16E                                       r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_r3_reg[22]_srl3___inst_signal_gen_top_i_signal_gen_i_ctrl_i_en_reg_r3_reg_r/CLK
                                       clock pessimism             -0.324     2.712    
                  SLICE_X86Y112        SRL16E (Hold_G6LUT_SLICEM_CLK_D)
                                                                    0.020     2.732    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_r3_reg[22]_srl3___inst_signal_gen_top_i_signal_gen_i_ctrl_i_en_reg_r3_reg_r
  ---------------------------------------------------------------------------------
                                       required time                         -2.732    
                                       arrival time                           2.757    
  ---------------------------------------------------------------------------------
                                       slack                                  0.025    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         RFDAC0_CLK
Waveform(ns):       { 0.000 1.220 }
Period(ns):         2.441
Sources:            { d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX }

Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location       Pin
Min Period        n/a     HSDAC/CLK_DAC       n/a            2.000         2.441       0.441      HSDAC_X0Y0     d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
Min Period        n/a     HSDAC/FABRIC_CLK    n/a            2.000         2.441       0.441      HSDAC_X0Y0     d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/FABRIC_CLK
Min Period        n/a     RAMB18E2/CLKBWRCLK  n/a            1.355         2.441       1.086      RAMB18_X8Y48   d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/mem_imag_i/RAM_reg_bram_0/CLKBWRCLK
Min Period        n/a     RAMB18E2/CLKBWRCLK  n/a            1.355         2.441       1.086      RAMB18_X8Y49   d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/mem_real_i/RAM_reg_bram_0/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKARDCLK  n/a            1.355         2.441       1.086      RAMB36_X8Y33   d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0/CLKARDCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.355         2.441       1.086      RAMB36_X8Y33   d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKARDCLK  n/a            1.355         2.441       1.086      RAMB36_X8Y34   d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1/CLKARDCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.355         2.441       1.086      RAMB36_X8Y34   d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKARDCLK  n/a            1.355         2.441       1.086      RAMB36_X10Y34  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[1].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0/CLKARDCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.355         2.441       1.086      RAMB36_X10Y34  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[1].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0/CLKBWRCLK
Low Pulse Width   Slow    HSDAC/CLK_DAC       n/a            0.800         1.220       0.420      HSDAC_X0Y0     d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
Low Pulse Width   Fast    HSDAC/CLK_DAC       n/a            0.800         1.220       0.420      HSDAC_X0Y0     d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
Low Pulse Width   Slow    HSDAC/FABRIC_CLK    n/a            0.800         1.220       0.420      HSDAC_X0Y0     d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/FABRIC_CLK
Low Pulse Width   Fast    HSDAC/FABRIC_CLK    n/a            0.800         1.221       0.421      HSDAC_X0Y0     d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/FABRIC_CLK
Low Pulse Width   Slow    RAMB18E2/CLKBWRCLK  n/a            0.542         1.221       0.679      RAMB18_X8Y48   d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/mem_imag_i/RAM_reg_bram_0/CLKBWRCLK
Low Pulse Width   Fast    RAMB18E2/CLKBWRCLK  n/a            0.542         1.220       0.678      RAMB18_X8Y48   d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/mem_imag_i/RAM_reg_bram_0/CLKBWRCLK
Low Pulse Width   Slow    RAMB18E2/CLKBWRCLK  n/a            0.542         1.220       0.678      RAMB18_X8Y49   d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/mem_real_i/RAM_reg_bram_0/CLKBWRCLK
Low Pulse Width   Fast    RAMB18E2/CLKBWRCLK  n/a            0.542         1.221       0.679      RAMB18_X8Y49   d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/mem_real_i/RAM_reg_bram_0/CLKBWRCLK
Low Pulse Width   Slow    RAMB36E2/CLKARDCLK  n/a            0.542         1.220       0.678      RAMB36_X8Y33   d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0/CLKARDCLK
Low Pulse Width   Fast    RAMB36E2/CLKARDCLK  n/a            0.542         1.220       0.678      RAMB36_X8Y33   d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0/CLKARDCLK
High Pulse Width  Slow    HSDAC/CLK_DAC       n/a            0.800         1.221       0.421      HSDAC_X0Y0     d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
High Pulse Width  Fast    HSDAC/CLK_DAC       n/a            0.800         1.221       0.421      HSDAC_X0Y0     d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
High Pulse Width  Slow    HSDAC/FABRIC_CLK    n/a            0.800         1.221       0.421      HSDAC_X0Y0     d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/FABRIC_CLK
High Pulse Width  Fast    HSDAC/FABRIC_CLK    n/a            0.800         1.220       0.420      HSDAC_X0Y0     d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/FABRIC_CLK
High Pulse Width  Slow    RAMB18E2/CLKBWRCLK  n/a            0.542         1.220       0.678      RAMB18_X8Y48   d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/mem_imag_i/RAM_reg_bram_0/CLKBWRCLK
High Pulse Width  Fast    RAMB18E2/CLKBWRCLK  n/a            0.542         1.221       0.679      RAMB18_X8Y48   d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/mem_imag_i/RAM_reg_bram_0/CLKBWRCLK
High Pulse Width  Slow    RAMB18E2/CLKBWRCLK  n/a            0.542         1.221       0.679      RAMB18_X8Y49   d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/mem_real_i/RAM_reg_bram_0/CLKBWRCLK
High Pulse Width  Fast    RAMB18E2/CLKBWRCLK  n/a            0.542         1.220       0.678      RAMB18_X8Y49   d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/mem_real_i/RAM_reg_bram_0/CLKBWRCLK
High Pulse Width  Slow    RAMB36E2/CLKARDCLK  n/a            0.542         1.221       0.679      RAMB36_X8Y33   d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0/CLKARDCLK
High Pulse Width  Fast    RAMB36E2/CLKARDCLK  n/a            0.542         1.220       0.678      RAMB36_X8Y33   d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0/CLKARDCLK



---------------------------------------------------------------------------------------------------
From Clock:  clk_pl_0
  To Clock:  clk_pl_0

Setup :            0  Failing Endpoints,  Worst Slack        0.630ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.007ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        3.400ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.630ns  (required time - arrival time)
  Source:                 d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/mem_reg_bram_0/CLKBWRCLK
                            (rising edge-triggered cell RAMB36E2 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_time_tagger_1/MEM0/FIFO_TAG/mem_reg_bram_144/DINPADINP[0]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        8.821ns  (logic 0.858ns (9.727%)  route 7.963ns (90.273%))
  Logic Levels:           0  
  Clock Path Skew:        -0.191ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.248ns = ( 12.248 - 10.000 ) 
    Source Clock Delay      (SCD):    2.556ns
    Clock Pessimism Removal (CPR):    0.117ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.330ns (routing 0.763ns, distribution 1.567ns)
  Clock Net Delay (Destination): 2.066ns (routing 0.690ns, distribution 1.376ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.330     2.556    d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/ps_clk
                  RAMB36_X6Y54         RAMB36E2                                     r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/mem_reg_bram_0/CLKBWRCLK
  ---------------------------------------------------------------------------------    -------------------
    Placement     RAMB36_X6Y54         RAMB36E2 (Prop_RAMB36E2_RAMB36_CLKBWRCLK_DOUTBDOUT[26])
                                                                    0.858     3.414 r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/mem_reg_bram_0/DOUTBDOUT[26]
                                       net (fo=64, routed)          7.963    11.377    d_1_i/qick_time_tagger_1/QTT/TAG_MEM/MEM0/data_s[26]
    New           RAMB36_X2Y2          RAMB36E2                                     r  d_1_i/qick_time_tagger_1/MEM0/FIFO_TAG/mem_reg_bram_144/DINPADINP[0]
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                   10.000    10.000 r  
                  PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.066    12.248    d_1_i/qick_time_tagger_1/ps_clk
                  RAMB36_X2Y2          RAMB36E2                                     r  d_1_i/qick_time_tagger_1/MEM0/FIFO_TAG/mem_reg_bram_144/CLKARDCLK
                                       clock pessimism              0.117    12.365    
                                       clock uncertainty           -0.130    12.235    
                  RAMB36_X2Y2          RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_DINPADINP[0])
                                                                   -0.228    12.007    d_1_i/qick_time_tagger_1/MEM0/FIFO_TAG/mem_reg_bram_144
  ---------------------------------------------------------------------------------
                                       required time                         12.007    
                                       arrival time                         -11.377    
  ---------------------------------------------------------------------------------
                                       slack                                  0.630    

Slack (MET) :             0.633ns  (required time - arrival time)
  Source:                 d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/mem_reg_bram_0/CLKBWRCLK
                            (rising edge-triggered cell RAMB36E2 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_time_tagger_1/MEM0/FIFO_TAG/mem_reg_bram_145/DINPADINP[0]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        8.824ns  (logic 0.858ns (9.724%)  route 7.966ns (90.276%))
  Logic Levels:           0  
  Clock Path Skew:        -0.186ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.253ns = ( 12.253 - 10.000 ) 
    Source Clock Delay      (SCD):    2.556ns
    Clock Pessimism Removal (CPR):    0.117ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.330ns (routing 0.763ns, distribution 1.567ns)
  Clock Net Delay (Destination): 2.071ns (routing 0.690ns, distribution 1.381ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.330     2.556    d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/ps_clk
                  RAMB36_X6Y54         RAMB36E2                                     r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/mem_reg_bram_0/CLKBWRCLK
  ---------------------------------------------------------------------------------    -------------------
    Placement     RAMB36_X6Y54         RAMB36E2 (Prop_RAMB36E2_RAMB36_CLKBWRCLK_DOUTBDOUT[26])
                                                                    0.858     3.414 r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/mem_reg_bram_0/DOUTBDOUT[26]
                                       net (fo=64, routed)          7.966    11.380    d_1_i/qick_time_tagger_1/QTT/TAG_MEM/MEM0/data_s[26]
    New           RAMB36_X2Y3          RAMB36E2                                     r  d_1_i/qick_time_tagger_1/MEM0/FIFO_TAG/mem_reg_bram_145/DINPADINP[0]
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                   10.000    10.000 r  
                  PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.071    12.253    d_1_i/qick_time_tagger_1/ps_clk
                  RAMB36_X2Y3          RAMB36E2                                     r  d_1_i/qick_time_tagger_1/MEM0/FIFO_TAG/mem_reg_bram_145/CLKARDCLK
                                       clock pessimism              0.117    12.370    
                                       clock uncertainty           -0.130    12.241    
                  RAMB36_X2Y3          RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_DINPADINP[0])
                                                                   -0.228    12.013    d_1_i/qick_time_tagger_1/MEM0/FIFO_TAG/mem_reg_bram_145
  ---------------------------------------------------------------------------------
                                       required time                         12.013    
                                       arrival time                         -11.380    
  ---------------------------------------------------------------------------------
                                       slack                                  0.633    

Slack (MET) :             0.728ns  (required time - arrival time)
  Source:                 d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/mem_reg_bram_0/CLKBWRCLK
                            (rising edge-triggered cell RAMB36E2 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_time_tagger_1/MEM0/FIFO_TAG/mem_reg_bram_146/DINPADINP[0]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        8.714ns  (logic 0.858ns (9.846%)  route 7.856ns (90.154%))
  Logic Levels:           0  
  Clock Path Skew:        -0.200ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.239ns = ( 12.239 - 10.000 ) 
    Source Clock Delay      (SCD):    2.556ns
    Clock Pessimism Removal (CPR):    0.117ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.330ns (routing 0.763ns, distribution 1.567ns)
  Clock Net Delay (Destination): 2.057ns (routing 0.690ns, distribution 1.367ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.330     2.556    d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/ps_clk
                  RAMB36_X6Y54         RAMB36E2                                     r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/mem_reg_bram_0/CLKBWRCLK
  ---------------------------------------------------------------------------------    -------------------
    Placement     RAMB36_X6Y54         RAMB36E2 (Prop_RAMB36E2_RAMB36_CLKBWRCLK_DOUTBDOUT[26])
                                                                    0.858     3.414 r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/mem_reg_bram_0/DOUTBDOUT[26]
                                       net (fo=64, routed)          7.856    11.270    d_1_i/qick_time_tagger_1/QTT/TAG_MEM/MEM0/data_s[26]
    New           RAMB36_X2Y4          RAMB36E2                                     r  d_1_i/qick_time_tagger_1/MEM0/FIFO_TAG/mem_reg_bram_146/DINPADINP[0]
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                   10.000    10.000 r  
                  PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.057    12.239    d_1_i/qick_time_tagger_1/ps_clk
                  RAMB36_X2Y4          RAMB36E2                                     r  d_1_i/qick_time_tagger_1/MEM0/FIFO_TAG/mem_reg_bram_146/CLKARDCLK
                                       clock pessimism              0.117    12.356    
                                       clock uncertainty           -0.130    12.226    
                  RAMB36_X2Y4          RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_DINPADINP[0])
                                                                   -0.228    11.998    d_1_i/qick_time_tagger_1/MEM0/FIFO_TAG/mem_reg_bram_146
  ---------------------------------------------------------------------------------
                                       required time                         11.998    
                                       arrival time                         -11.270    
  ---------------------------------------------------------------------------------
                                       slack                                  0.728    

Slack (MET) :             0.786ns  (required time - arrival time)
  Source:                 d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_cnt_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_time_tagger_1/SMP_FIFO_DC/SMP_FIFO/mem_reg_bram_159/DINADIN[0]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        8.691ns  (logic 0.244ns (2.808%)  route 8.447ns (97.192%))
  Logic Levels:           2  (LUT3=1 MUXF7=1)
  Clock Path Skew:        -0.102ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.391ns = ( 12.391 - 10.000 ) 
    Source Clock Delay      (SCD):    2.610ns
    Clock Pessimism Removal (CPR):    0.117ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.384ns (routing 0.763ns, distribution 1.621ns)
  Clock Net Delay (Destination): 2.209ns (routing 0.690ns, distribution 1.519ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.384     2.610    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/ps_clk
                  SLICE_X93Y137        FDCE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_cnt_reg[0]/C
  ---------------------------------------------------------------------------------    -------------------
    Placement     SLICE_X93Y137        FDCE (Prop_DFF_SLICEM_C_Q)
                                                                    0.078     2.688 r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_cnt_reg[0]/Q
                                       net (fo=38, routed)          0.269     2.957    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_cnt_reg[0]
    New           SLICE_X91Y138                                                     r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/mem_reg_bram_0_i_15__0/I1
    New           SLICE_X91Y138        LUT3 (Prop_D6LUT_SLICEL_I1_O)
                                                                    0.089     3.046 r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/mem_reg_bram_0_i_15__0/O
                                       net (fo=16, routed)          0.309     3.355    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/mem_reg_bram_0_i_15__0_n_0
    New           SLICE_X90Y137                                                     r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/mem_reg_bram_128_i_6/S
    New           SLICE_X90Y137        MUXF7 (Prop_F7MUX_CD_SLICEM_S_O)
                                                                    0.077     3.432 r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/mem_reg_bram_128_i_6/O
                                       net (fo=64, routed)          7.868    11.301    d_1_i/qick_time_tagger_1/inst_n_1843
    New           RAMB36_X1Y86         RAMB36E2                                     r  d_1_i/qick_time_tagger_1/SMP_FIFO_DC/SMP_FIFO/mem_reg_bram_159/DINADIN[0]
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                   10.000    10.000 r  
                  PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.209    12.391    d_1_i/qick_time_tagger_1/ps_clk
                  RAMB36_X1Y86         RAMB36E2                                     r  d_1_i/qick_time_tagger_1/SMP_FIFO_DC/SMP_FIFO/mem_reg_bram_159/CLKARDCLK
                                       clock pessimism              0.117    12.508    
                                       clock uncertainty           -0.130    12.378    
                  RAMB36_X1Y86         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_DINADIN[0])
                                                                   -0.291    12.087    d_1_i/qick_time_tagger_1/SMP_FIFO_DC/SMP_FIFO/mem_reg_bram_159
  ---------------------------------------------------------------------------------
                                       required time                         12.087    
                                       arrival time                         -11.301    
  ---------------------------------------------------------------------------------
                                       slack                                  0.786    

Slack (MET) :             0.795ns  (required time - arrival time)
  Source:                 d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/mem_reg_bram_0/CLKBWRCLK
                            (rising edge-triggered cell RAMB36E2 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_time_tagger_1/MEM0/FIFO_TAG/mem_reg_bram_147/DINPADINP[0]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        8.650ns  (logic 0.858ns (9.920%)  route 7.792ns (90.080%))
  Logic Levels:           0  
  Clock Path Skew:        -0.198ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.241ns = ( 12.241 - 10.000 ) 
    Source Clock Delay      (SCD):    2.556ns
    Clock Pessimism Removal (CPR):    0.117ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.330ns (routing 0.763ns, distribution 1.567ns)
  Clock Net Delay (Destination): 2.059ns (routing 0.690ns, distribution 1.369ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.330     2.556    d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/ps_clk
                  RAMB36_X6Y54         RAMB36E2                                     r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/mem_reg_bram_0/CLKBWRCLK
  ---------------------------------------------------------------------------------    -------------------
    Placement     RAMB36_X6Y54         RAMB36E2 (Prop_RAMB36E2_RAMB36_CLKBWRCLK_DOUTBDOUT[26])
                                                                    0.858     3.414 r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/mem_reg_bram_0/DOUTBDOUT[26]
                                       net (fo=64, routed)          7.792    11.206    d_1_i/qick_time_tagger_1/QTT/TAG_MEM/MEM0/data_s[26]
    New           RAMB36_X2Y5          RAMB36E2                                     r  d_1_i/qick_time_tagger_1/MEM0/FIFO_TAG/mem_reg_bram_147/DINPADINP[0]
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                   10.000    10.000 r  
                  PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.059    12.241    d_1_i/qick_time_tagger_1/ps_clk
                  RAMB36_X2Y5          RAMB36E2                                     r  d_1_i/qick_time_tagger_1/MEM0/FIFO_TAG/mem_reg_bram_147/CLKARDCLK
                                       clock pessimism              0.117    12.358    
                                       clock uncertainty           -0.130    12.229    
                  RAMB36_X2Y5          RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_DINPADINP[0])
                                                                   -0.228    12.001    d_1_i/qick_time_tagger_1/MEM0/FIFO_TAG/mem_reg_bram_147
  ---------------------------------------------------------------------------------
                                       required time                         12.001    
                                       arrival time                         -11.206    
  ---------------------------------------------------------------------------------
                                       slack                                  0.795    

Slack (MET) :             0.813ns  (required time - arrival time)
  Source:                 d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_cnt_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_time_tagger_0/SMP_FIFO_DC/SMP_FIFO/mem_reg_bram_103/DINADIN[4]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        8.770ns  (logic 0.294ns (3.352%)  route 8.476ns (96.648%))
  Logic Levels:           2  (LUT3=1 MUXF7=1)
  Clock Path Skew:        0.001ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.508ns = ( 12.508 - 10.000 ) 
    Source Clock Delay      (SCD):    2.624ns
    Clock Pessimism Removal (CPR):    0.117ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.398ns (routing 0.763ns, distribution 1.635ns)
  Clock Net Delay (Destination): 2.326ns (routing 0.690ns, distribution 1.636ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.398     2.624    d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/ps_clk
                  SLICE_X83Y102        FDCE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_cnt_reg[2]/C
  ---------------------------------------------------------------------------------    -------------------
    Placement     SLICE_X83Y102        FDCE (Prop_HFF_SLICEM_C_Q)
                                                                    0.079     2.703 r  d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_cnt_reg[2]/Q
                                       net (fo=4, routed)           0.117     2.819    d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_cnt_reg[2]
    New           SLICE_X83Y102                                                     r  d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/mem_reg_bram_0_i_15__0/I0
    New           SLICE_X83Y102        LUT3 (Prop_D6LUT_SLICEM_I0_O)
                                                                    0.145     2.964 r  d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/mem_reg_bram_0_i_15__0/O
                                       net (fo=16, routed)          0.225     3.190    d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/mem_reg_bram_0_i_15__0_n_0
    New           SLICE_X84Y101                                                     r  d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/mem_reg_bram_0_i_6/S
    New           SLICE_X84Y101        MUXF7 (Prop_F7MUX_CD_SLICEL_S_O)
                                                                    0.070     3.260 r  d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/mem_reg_bram_0_i_6/O
                                       net (fo=128, routed)         8.134    11.394    d_1_i/qick_time_tagger_0/inst_n_1847
    New           RAMB36_X11Y79        RAMB36E2                                     r  d_1_i/qick_time_tagger_0/SMP_FIFO_DC/SMP_FIFO/mem_reg_bram_103/DINADIN[4]
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                   10.000    10.000 r  
                  PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.326    12.508    d_1_i/qick_time_tagger_0/ps_clk
                  RAMB36_X11Y79        RAMB36E2                                     r  d_1_i/qick_time_tagger_0/SMP_FIFO_DC/SMP_FIFO/mem_reg_bram_103/CLKARDCLK
                                       clock pessimism              0.117    12.625    
                                       clock uncertainty           -0.130    12.495    
                  RAMB36_X11Y79        RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_DINADIN[4])
                                                                   -0.288    12.207    d_1_i/qick_time_tagger_0/SMP_FIFO_DC/SMP_FIFO/mem_reg_bram_103
  ---------------------------------------------------------------------------------
                                       required time                         12.207    
                                       arrival time                         -11.394    
  ---------------------------------------------------------------------------------
                                       slack                                  0.813    

Slack (MET) :             0.826ns  (required time - arrival time)
  Source:                 d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/mem_reg_bram_0/CLKBWRCLK
                            (rising edge-triggered cell RAMB36E2 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_time_tagger_1/MEM0/FIFO_TAG/mem_reg_bram_148/DINPADINP[0]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        8.601ns  (logic 0.858ns (9.975%)  route 7.743ns (90.025%))
  Logic Levels:           0  
  Clock Path Skew:        -0.215ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.224ns = ( 12.224 - 10.000 ) 
    Source Clock Delay      (SCD):    2.556ns
    Clock Pessimism Removal (CPR):    0.117ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.330ns (routing 0.763ns, distribution 1.567ns)
  Clock Net Delay (Destination): 2.042ns (routing 0.690ns, distribution 1.352ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.330     2.556    d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/ps_clk
                  RAMB36_X6Y54         RAMB36E2                                     r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/mem_reg_bram_0/CLKBWRCLK
  ---------------------------------------------------------------------------------    -------------------
    Placement     RAMB36_X6Y54         RAMB36E2 (Prop_RAMB36E2_RAMB36_CLKBWRCLK_DOUTBDOUT[26])
                                                                    0.858     3.414 r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/mem_reg_bram_0/DOUTBDOUT[26]
                                       net (fo=64, routed)          7.743    11.157    d_1_i/qick_time_tagger_1/QTT/TAG_MEM/MEM0/data_s[26]
    New           RAMB36_X2Y6          RAMB36E2                                     r  d_1_i/qick_time_tagger_1/MEM0/FIFO_TAG/mem_reg_bram_148/DINPADINP[0]
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                   10.000    10.000 r  
                  PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.042    12.224    d_1_i/qick_time_tagger_1/ps_clk
                  RAMB36_X2Y6          RAMB36E2                                     r  d_1_i/qick_time_tagger_1/MEM0/FIFO_TAG/mem_reg_bram_148/CLKARDCLK
                                       clock pessimism              0.117    12.341    
                                       clock uncertainty           -0.130    12.211    
                  RAMB36_X2Y6          RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_DINPADINP[0])
                                                                   -0.228    11.983    d_1_i/qick_time_tagger_1/MEM0/FIFO_TAG/mem_reg_bram_148
  ---------------------------------------------------------------------------------
                                       required time                         11.983    
                                       arrival time                         -11.157    
  ---------------------------------------------------------------------------------
                                       slack                                  0.826    

Slack (MET) :             0.844ns  (required time - arrival time)
  Source:                 d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_cnt_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_time_tagger_0/SMP_FIFO_DC/SMP_FIFO/mem_reg_bram_96/DINADIN[6]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        8.805ns  (logic 0.301ns (3.419%)  route 8.504ns (96.581%))
  Logic Levels:           2  (LUT3=1 MUXF7=1)
  Clock Path Skew:        0.022ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.529ns = ( 12.529 - 10.000 ) 
    Source Clock Delay      (SCD):    2.624ns
    Clock Pessimism Removal (CPR):    0.117ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.398ns (routing 0.763ns, distribution 1.635ns)
  Clock Net Delay (Destination): 2.347ns (routing 0.690ns, distribution 1.657ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.398     2.624    d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/ps_clk
                  SLICE_X83Y102        FDCE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_cnt_reg[2]/C
  ---------------------------------------------------------------------------------    -------------------
    Placement     SLICE_X83Y102        FDCE (Prop_HFF_SLICEM_C_Q)
                                                                    0.079     2.703 r  d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_cnt_reg[2]/Q
                                       net (fo=4, routed)           0.117     2.819    d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_cnt_reg[2]
    New           SLICE_X83Y102                                                     r  d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/mem_reg_bram_0_i_15__0/I0
    New           SLICE_X83Y102        LUT3 (Prop_D6LUT_SLICEM_I0_O)
                                                                    0.145     2.964 r  d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/mem_reg_bram_0_i_15__0/O
                                       net (fo=16, routed)          0.387     3.352    d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/mem_reg_bram_0_i_15__0_n_0
    New           SLICE_X86Y100                                                     r  d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/mem_reg_bram_0_i_4/S
    New           SLICE_X86Y100        MUXF7 (Prop_F7MUX_CD_SLICEM_S_O)
                                                                    0.077     3.429 r  d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/mem_reg_bram_0_i_4/O
                                       net (fo=128, routed)         8.000    11.428    d_1_i/qick_time_tagger_0/inst_n_1845
    New           RAMB36_X11Y72        RAMB36E2                                     r  d_1_i/qick_time_tagger_0/SMP_FIFO_DC/SMP_FIFO/mem_reg_bram_96/DINADIN[6]
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                   10.000    10.000 r  
                  PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.347    12.529    d_1_i/qick_time_tagger_0/ps_clk
                  RAMB36_X11Y72        RAMB36E2                                     r  d_1_i/qick_time_tagger_0/SMP_FIFO_DC/SMP_FIFO/mem_reg_bram_96/CLKARDCLK
                                       clock pessimism              0.117    12.646    
                                       clock uncertainty           -0.130    12.516    
                  RAMB36_X11Y72        RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_DINADIN[6])
                                                                   -0.244    12.272    d_1_i/qick_time_tagger_0/SMP_FIFO_DC/SMP_FIFO/mem_reg_bram_96
  ---------------------------------------------------------------------------------
                                       required time                         12.272    
                                       arrival time                         -11.428    
  ---------------------------------------------------------------------------------
                                       slack                                  0.844    

Slack (MET) :             0.844ns  (required time - arrival time)
  Source:                 d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_cnt_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_time_tagger_0/SMP_FIFO_DC/SMP_FIFO/mem_reg_bram_102/DINADIN[4]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        8.733ns  (logic 0.294ns (3.366%)  route 8.439ns (96.634%))
  Logic Levels:           2  (LUT3=1 MUXF7=1)
  Clock Path Skew:        -0.005ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.502ns = ( 12.502 - 10.000 ) 
    Source Clock Delay      (SCD):    2.624ns
    Clock Pessimism Removal (CPR):    0.117ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.398ns (routing 0.763ns, distribution 1.635ns)
  Clock Net Delay (Destination): 2.320ns (routing 0.690ns, distribution 1.630ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.398     2.624    d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/ps_clk
                  SLICE_X83Y102        FDCE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_cnt_reg[2]/C
  ---------------------------------------------------------------------------------    -------------------
    Placement     SLICE_X83Y102        FDCE (Prop_HFF_SLICEM_C_Q)
                                                                    0.079     2.703 r  d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_cnt_reg[2]/Q
                                       net (fo=4, routed)           0.117     2.819    d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_cnt_reg[2]
    New           SLICE_X83Y102                                                     r  d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/mem_reg_bram_0_i_15__0/I0
    New           SLICE_X83Y102        LUT3 (Prop_D6LUT_SLICEM_I0_O)
                                                                    0.145     2.964 r  d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/mem_reg_bram_0_i_15__0/O
                                       net (fo=16, routed)          0.225     3.190    d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/mem_reg_bram_0_i_15__0_n_0
    New           SLICE_X84Y101                                                     r  d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/mem_reg_bram_0_i_6/S
    New           SLICE_X84Y101        MUXF7 (Prop_F7MUX_CD_SLICEL_S_O)
                                                                    0.070     3.260 r  d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/mem_reg_bram_0_i_6/O
                                       net (fo=128, routed)         8.097    11.357    d_1_i/qick_time_tagger_0/inst_n_1847
    New           RAMB36_X11Y78        RAMB36E2                                     r  d_1_i/qick_time_tagger_0/SMP_FIFO_DC/SMP_FIFO/mem_reg_bram_102/DINADIN[4]
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                   10.000    10.000 r  
                  PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.320    12.502    d_1_i/qick_time_tagger_0/ps_clk
                  RAMB36_X11Y78        RAMB36E2                                     r  d_1_i/qick_time_tagger_0/SMP_FIFO_DC/SMP_FIFO/mem_reg_bram_102/CLKARDCLK
                                       clock pessimism              0.117    12.619    
                                       clock uncertainty           -0.130    12.489    
                  RAMB36_X11Y78        RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_DINADIN[4])
                                                                   -0.288    12.201    d_1_i/qick_time_tagger_0/SMP_FIFO_DC/SMP_FIFO/mem_reg_bram_102
  ---------------------------------------------------------------------------------
                                       required time                         12.201    
                                       arrival time                         -11.357    
  ---------------------------------------------------------------------------------
                                       slack                                  0.844    

Slack (MET) :             0.845ns  (required time - arrival time)
  Source:                 d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/mem_reg_bram_0/CLKBWRCLK
                            (rising edge-triggered cell RAMB36E2 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_time_tagger_1/MEM0/FIFO_TAG/mem_reg_bram_151/DINPADINP[0]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        8.607ns  (logic 0.858ns (9.968%)  route 7.749ns (90.032%))
  Logic Levels:           0  
  Clock Path Skew:        -0.190ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.249ns = ( 12.249 - 10.000 ) 
    Source Clock Delay      (SCD):    2.556ns
    Clock Pessimism Removal (CPR):    0.117ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.330ns (routing 0.763ns, distribution 1.567ns)
  Clock Net Delay (Destination): 2.067ns (routing 0.690ns, distribution 1.377ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.330     2.556    d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/ps_clk
                  RAMB36_X6Y54         RAMB36E2                                     r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/mem_reg_bram_0/CLKBWRCLK
  ---------------------------------------------------------------------------------    -------------------
    Placement     RAMB36_X6Y54         RAMB36E2 (Prop_RAMB36E2_RAMB36_CLKBWRCLK_DOUTBDOUT[26])
                                                                    0.858     3.414 r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/mem_reg_bram_0/DOUTBDOUT[26]
                                       net (fo=64, routed)          7.749    11.163    d_1_i/qick_time_tagger_1/QTT/TAG_MEM/MEM0/data_s[26]
    New           RAMB36_X2Y9          RAMB36E2                                     r  d_1_i/qick_time_tagger_1/MEM0/FIFO_TAG/mem_reg_bram_151/DINPADINP[0]
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                   10.000    10.000 r  
                  PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.067    12.249    d_1_i/qick_time_tagger_1/ps_clk
                  RAMB36_X2Y9          RAMB36E2                                     r  d_1_i/qick_time_tagger_1/MEM0/FIFO_TAG/mem_reg_bram_151/CLKARDCLK
                                       clock pessimism              0.117    12.366    
                                       clock uncertainty           -0.130    12.236    
                  RAMB36_X2Y9          RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_DINPADINP[0])
                                                                   -0.228    12.008    d_1_i/qick_time_tagger_1/MEM0/FIFO_TAG/mem_reg_bram_151
  ---------------------------------------------------------------------------------
                                       required time                         12.008    
                                       arrival time                         -11.163    
  ---------------------------------------------------------------------------------
                                       slack                                  0.845    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.007ns  (arrival time - required time)
  Source:                 d_1_i/axi_smc/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[56]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/switchboards/w_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe_reg[1][208]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.169ns  (logic 0.083ns (49.112%)  route 0.086ns (50.888%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        0.102ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.449ns
    Source Clock Delay      (SCD):    2.144ns
    Clock Pessimism Removal (CPR):    0.203ns
  Clock Net Delay (Source):      1.962ns (routing 0.690ns, distribution 1.272ns)
  Clock Net Delay (Destination): 2.223ns (routing 0.763ns, distribution 1.460ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.962     2.144    d_1_i/axi_smc/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/clka
                  SLICE_X45Y3          FDRE                                         r  d_1_i/axi_smc/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[56]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X45Y3          FDRE (Prop_AFF2_SLICEM_C_Q)
                                                                    0.060     2.204 r  d_1_i/axi_smc/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[56]/Q
                                       net (fo=1, routed)           0.062     2.266    d_1_i/axi_smc/inst/switchboards/w_switchboard/inst/gen_mi[0].inst_opipe_payld/s_sc_payld[196]
    Routing       SLICE_X44Y3                                                       r  d_1_i/axi_smc/inst/switchboards/w_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe[1][208]_i_1/I2
    Routing       SLICE_X44Y3          LUT4 (Prop_H6LUT_SLICEL_I2_O)
                                                                    0.023     2.289 r  d_1_i/axi_smc/inst/switchboards/w_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe[1][208]_i_1/O
                                       net (fo=1, routed)           0.024     2.313    d_1_i/axi_smc/inst/switchboards/w_switchboard/inst/gen_mi[0].inst_opipe_payld/m_sc_payld_comb[208]
    Routing       SLICE_X44Y3          FDRE                                         r  d_1_i/axi_smc/inst/switchboards/w_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe_reg[1][208]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.223     2.449    d_1_i/axi_smc/inst/switchboards/w_switchboard/inst/gen_mi[0].inst_opipe_payld/aclk
                  SLICE_X44Y3          FDRE                                         r  d_1_i/axi_smc/inst/switchboards/w_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe_reg[1][208]/C
                                       clock pessimism             -0.203     2.246    
                  SLICE_X44Y3          FDRE (Hold_HFF_SLICEL_C_D)
                                                                    0.060     2.306    d_1_i/axi_smc/inst/switchboards/w_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe_reg[1][208]
  ---------------------------------------------------------------------------------
                                       required time                         -2.306    
                                       arrival time                           2.313    
  ---------------------------------------------------------------------------------
                                       slack                                  0.007    

Slack (MET) :             0.007ns  (arrival time - required time)
  Source:                 d_1_i/axi_smc/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[84]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/switchboards/w_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe_reg[1][236]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.169ns  (logic 0.083ns (49.112%)  route 0.086ns (50.888%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        0.102ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.447ns
    Source Clock Delay      (SCD):    2.142ns
    Clock Pessimism Removal (CPR):    0.203ns
  Clock Net Delay (Source):      1.960ns (routing 0.690ns, distribution 1.270ns)
  Clock Net Delay (Destination): 2.221ns (routing 0.763ns, distribution 1.458ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.960     2.142    d_1_i/axi_smc/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/clka
                  SLICE_X45Y8          FDRE                                         r  d_1_i/axi_smc/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[84]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X45Y8          FDRE (Prop_AFF2_SLICEM_C_Q)
                                                                    0.060     2.202 r  d_1_i/axi_smc/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[84]/Q
                                       net (fo=1, routed)           0.062     2.264    d_1_i/axi_smc/inst/switchboards/w_switchboard/inst/gen_mi[0].inst_opipe_payld/s_sc_payld[224]
    Routing       SLICE_X44Y8                                                       r  d_1_i/axi_smc/inst/switchboards/w_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe[1][236]_i_1/I2
    Routing       SLICE_X44Y8          LUT4 (Prop_H6LUT_SLICEL_I2_O)
                                                                    0.023     2.287 r  d_1_i/axi_smc/inst/switchboards/w_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe[1][236]_i_1/O
                                       net (fo=1, routed)           0.024     2.311    d_1_i/axi_smc/inst/switchboards/w_switchboard/inst/gen_mi[0].inst_opipe_payld/m_sc_payld_comb[236]
    Routing       SLICE_X44Y8          FDRE                                         r  d_1_i/axi_smc/inst/switchboards/w_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe_reg[1][236]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.221     2.447    d_1_i/axi_smc/inst/switchboards/w_switchboard/inst/gen_mi[0].inst_opipe_payld/aclk
                  SLICE_X44Y8          FDRE                                         r  d_1_i/axi_smc/inst/switchboards/w_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe_reg[1][236]/C
                                       clock pessimism             -0.203     2.244    
                  SLICE_X44Y8          FDRE (Hold_HFF_SLICEL_C_D)
                                                                    0.060     2.304    d_1_i/axi_smc/inst/switchboards/w_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe_reg[1][236]
  ---------------------------------------------------------------------------------
                                       required time                         -2.304    
                                       arrival time                           2.311    
  ---------------------------------------------------------------------------------
                                       slack                                  0.007    

Slack (MET) :             0.007ns  (arrival time - required time)
  Source:                 d_1_i/axi_smc/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[90]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/switchboards/w_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe_reg[1][242]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.169ns  (logic 0.083ns (49.112%)  route 0.086ns (50.888%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        0.102ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.447ns
    Source Clock Delay      (SCD):    2.142ns
    Clock Pessimism Removal (CPR):    0.203ns
  Clock Net Delay (Source):      1.960ns (routing 0.690ns, distribution 1.270ns)
  Clock Net Delay (Destination): 2.221ns (routing 0.763ns, distribution 1.458ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.960     2.142    d_1_i/axi_smc/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/clka
                  SLICE_X45Y8          FDRE                                         r  d_1_i/axi_smc/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[90]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X45Y8          FDRE (Prop_DFF2_SLICEM_C_Q)
                                                                    0.061     2.203 r  d_1_i/axi_smc/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[90]/Q
                                       net (fo=1, routed)           0.062     2.265    d_1_i/axi_smc/inst/switchboards/w_switchboard/inst/gen_mi[0].inst_opipe_payld/s_sc_payld[230]
    Routing       SLICE_X44Y8                                                       r  d_1_i/axi_smc/inst/switchboards/w_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe[1][242]_i_1/I2
    Routing       SLICE_X44Y8          LUT4 (Prop_F6LUT_SLICEL_I2_O)
                                                                    0.022     2.287 r  d_1_i/axi_smc/inst/switchboards/w_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe[1][242]_i_1/O
                                       net (fo=1, routed)           0.024     2.311    d_1_i/axi_smc/inst/switchboards/w_switchboard/inst/gen_mi[0].inst_opipe_payld/m_sc_payld_comb[242]
    Routing       SLICE_X44Y8          FDRE                                         r  d_1_i/axi_smc/inst/switchboards/w_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe_reg[1][242]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.221     2.447    d_1_i/axi_smc/inst/switchboards/w_switchboard/inst/gen_mi[0].inst_opipe_payld/aclk
                  SLICE_X44Y8          FDRE                                         r  d_1_i/axi_smc/inst/switchboards/w_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe_reg[1][242]/C
                                       clock pessimism             -0.203     2.244    
                  SLICE_X44Y8          FDRE (Hold_FFF_SLICEL_C_D)
                                                                    0.060     2.304    d_1_i/axi_smc/inst/switchboards/w_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe_reg[1][242]
  ---------------------------------------------------------------------------------
                                       required time                         -2.304    
                                       arrival time                           2.311    
  ---------------------------------------------------------------------------------
                                       slack                                  0.007    

Slack (MET) :             0.009ns  (arrival time - required time)
  Source:                 d_1_i/axi_smc/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[150]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/switchboards/w_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe_reg[1][302]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.167ns  (logic 0.082ns (49.102%)  route 0.085ns (50.898%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        0.098ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.441ns
    Source Clock Delay      (SCD):    2.140ns
    Clock Pessimism Removal (CPR):    0.203ns
  Clock Net Delay (Source):      1.958ns (routing 0.690ns, distribution 1.268ns)
  Clock Net Delay (Destination): 2.215ns (routing 0.763ns, distribution 1.452ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.958     2.140    d_1_i/axi_smc/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/clka
                  SLICE_X45Y11         FDRE                                         r  d_1_i/axi_smc/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[150]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X45Y11         FDRE (Prop_FFF2_SLICEM_C_Q)
                                                                    0.060     2.200 r  d_1_i/axi_smc/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[150]/Q
                                       net (fo=1, routed)           0.062     2.262    d_1_i/axi_smc/inst/switchboards/w_switchboard/inst/gen_mi[0].inst_opipe_payld/s_sc_payld[290]
    Routing       SLICE_X44Y11                                                      r  d_1_i/axi_smc/inst/switchboards/w_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe[1][302]_i_1/I2
    Routing       SLICE_X44Y11         LUT4 (Prop_A6LUT_SLICEL_I2_O)
                                                                    0.022     2.284 r  d_1_i/axi_smc/inst/switchboards/w_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe[1][302]_i_1/O
                                       net (fo=1, routed)           0.023     2.307    d_1_i/axi_smc/inst/switchboards/w_switchboard/inst/gen_mi[0].inst_opipe_payld/m_sc_payld_comb[302]
    Routing       SLICE_X44Y11         FDRE                                         r  d_1_i/axi_smc/inst/switchboards/w_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe_reg[1][302]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.215     2.441    d_1_i/axi_smc/inst/switchboards/w_switchboard/inst/gen_mi[0].inst_opipe_payld/aclk
                  SLICE_X44Y11         FDRE                                         r  d_1_i/axi_smc/inst/switchboards/w_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe_reg[1][302]/C
                                       clock pessimism             -0.203     2.238    
                  SLICE_X44Y11         FDRE (Hold_AFF_SLICEL_C_D)
                                                                    0.060     2.298    d_1_i/axi_smc/inst/switchboards/w_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe_reg[1][302]
  ---------------------------------------------------------------------------------
                                       required time                         -2.298    
                                       arrival time                           2.307    
  ---------------------------------------------------------------------------------
                                       slack                                  0.009    

Slack (MET) :             0.010ns  (arrival time - required time)
  Source:                 d_1_i/axi_dma_qtt/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/sig_byte_cntr_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_dma_qtt/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_8/RAMA/I
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.240ns  (logic 0.060ns (25.024%)  route 0.180ns (74.976%))
  Logic Levels:           0  
  Clock Path Skew:        0.155ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.479ns
    Source Clock Delay      (SCD):    2.121ns
    Clock Pessimism Removal (CPR):    0.203ns
  Clock Net Delay (Source):      1.939ns (routing 0.690ns, distribution 1.249ns)
  Clock Net Delay (Destination): 2.253ns (routing 0.763ns, distribution 1.490ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.939     2.121    d_1_i/axi_dma_qtt/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/m_axi_s2mm_aclk
                  SLICE_X51Y45         FDRE                                         r  d_1_i/axi_dma_qtt/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/sig_byte_cntr_reg[0]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X51Y45         FDRE (Prop_AFF2_SLICEL_C_Q)
                                                                    0.060     2.181 r  d_1_i/axi_dma_qtt/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/sig_byte_cntr_reg[0]/Q
                                       net (fo=3, routed)           0.180     2.361    d_1_i/axi_dma_qtt/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_8/DIA0
    Routing       SLICE_X46Y44         RAMD32                                       r  d_1_i/axi_dma_qtt/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_8/RAMA/I
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.253     2.479    d_1_i/axi_dma_qtt/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_8/WCLK
                  SLICE_X46Y44         RAMD32                                       r  d_1_i/axi_dma_qtt/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_8/RAMA/CLK
                                       clock pessimism             -0.203     2.276    
                  SLICE_X46Y44         RAMD32 (Hold_A5LUT_SLICEM_CLK_I)
                                                                    0.075     2.351    d_1_i/axi_dma_qtt/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_8/RAMA
  ---------------------------------------------------------------------------------
                                       required time                         -2.351    
                                       arrival time                           2.361    
  ---------------------------------------------------------------------------------
                                       slack                                  0.010    

Slack (MET) :             0.012ns  (arrival time - required time)
  Source:                 d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[101]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/switchboards/w_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe_reg[1][101]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.179ns  (logic 0.081ns (45.251%)  route 0.098ns (54.749%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        0.107ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.461ns
    Source Clock Delay      (SCD):    2.151ns
    Clock Pessimism Removal (CPR):    0.203ns
  Clock Net Delay (Source):      1.969ns (routing 0.690ns, distribution 1.279ns)
  Clock Net Delay (Destination): 2.235ns (routing 0.763ns, distribution 1.472ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.969     2.151    d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/clka
                  SLICE_X41Y17         FDRE                                         r  d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[101]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X41Y17         FDRE (Prop_BFF_SLICEM_C_Q)
                                                                    0.058     2.209 r  d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[101]/Q
                                       net (fo=1, routed)           0.068     2.277    d_1_i/axi_smc/inst/switchboards/w_switchboard/inst/gen_mi[0].inst_opipe_payld/s_sc_payld[381]
    Routing       SLICE_X39Y16                                                      r  d_1_i/axi_smc/inst/switchboards/w_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe[1][101]_i_1/I0
    Routing       SLICE_X39Y16         LUT4 (Prop_H6LUT_SLICEM_I0_O)
                                                                    0.023     2.300 r  d_1_i/axi_smc/inst/switchboards/w_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe[1][101]_i_1/O
                                       net (fo=1, routed)           0.030     2.330    d_1_i/axi_smc/inst/switchboards/w_switchboard/inst/gen_mi[0].inst_opipe_payld/m_sc_payld_comb[101]
    Routing       SLICE_X39Y16         FDRE                                         r  d_1_i/axi_smc/inst/switchboards/w_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe_reg[1][101]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.235     2.461    d_1_i/axi_smc/inst/switchboards/w_switchboard/inst/gen_mi[0].inst_opipe_payld/aclk
                  SLICE_X39Y16         FDRE                                         r  d_1_i/axi_smc/inst/switchboards/w_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe_reg[1][101]/C
                                       clock pessimism             -0.203     2.258    
                  SLICE_X39Y16         FDRE (Hold_HFF_SLICEM_C_D)
                                                                    0.060     2.318    d_1_i/axi_smc/inst/switchboards/w_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe_reg[1][101]
  ---------------------------------------------------------------------------------
                                       required time                         -2.318    
                                       arrival time                           2.330    
  ---------------------------------------------------------------------------------
                                       slack                                  0.012    

Slack (MET) :             0.012ns  (arrival time - required time)
  Source:                 d_1_i/axi_dma_tproc/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_S2MM_MMAP_SKID_BUF/sig_data_reg_out_reg[73]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/s03_entry_pipeline/s03_mmu/inst/w_sreg/skid_buffer_reg[1098]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.184ns  (logic 0.058ns (31.522%)  route 0.126ns (68.478%))
  Logic Levels:           0  
  Clock Path Skew:        0.110ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.438ns
    Source Clock Delay      (SCD):    2.124ns
    Clock Pessimism Removal (CPR):    0.203ns
  Clock Net Delay (Source):      1.942ns (routing 0.690ns, distribution 1.252ns)
  Clock Net Delay (Destination): 2.212ns (routing 0.763ns, distribution 1.449ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.942     2.124    d_1_i/axi_dma_tproc/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_S2MM_MMAP_SKID_BUF/m_axi_s2mm_aclk
                  SLICE_X50Y18         FDRE                                         r  d_1_i/axi_dma_tproc/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_S2MM_MMAP_SKID_BUF/sig_data_reg_out_reg[73]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X50Y18         FDRE (Prop_HFF_SLICEL_C_Q)
                                                                    0.058     2.182 r  d_1_i/axi_dma_tproc/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_S2MM_MMAP_SKID_BUF/sig_data_reg_out_reg[73]/Q
                                       net (fo=2, routed)           0.126     2.308    d_1_i/axi_smc/inst/s03_entry_pipeline/s03_mmu/inst/w_sreg/D[74]
    Routing       SLICE_X46Y17         FDRE                                         r  d_1_i/axi_smc/inst/s03_entry_pipeline/s03_mmu/inst/w_sreg/skid_buffer_reg[1098]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.212     2.438    d_1_i/axi_smc/inst/s03_entry_pipeline/s03_mmu/inst/w_sreg/aclk
                  SLICE_X46Y17         FDRE                                         r  d_1_i/axi_smc/inst/s03_entry_pipeline/s03_mmu/inst/w_sreg/skid_buffer_reg[1098]/C
                                       clock pessimism             -0.203     2.235    
                  SLICE_X46Y17         FDRE (Hold_EFF2_SLICEM_C_D)
                                                                    0.062     2.297    d_1_i/axi_smc/inst/s03_entry_pipeline/s03_mmu/inst/w_sreg/skid_buffer_reg[1098]
  ---------------------------------------------------------------------------------
                                       required time                         -2.297    
                                       arrival time                           2.308    
  ---------------------------------------------------------------------------------
                                       slack                                  0.012    

Slack (MET) :             0.012ns  (arrival time - required time)
  Source:                 d_1_i/axi_smc/inst/s03_entry_pipeline/s03_mmu/inst/w_sreg/m_vector_i_reg[1130]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139/RAME_D1/I
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.198ns  (logic 0.061ns (30.808%)  route 0.137ns (69.192%))
  Logic Levels:           0  
  Clock Path Skew:        0.126ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.462ns
    Source Clock Delay      (SCD):    2.132ns
    Clock Pessimism Removal (CPR):    0.203ns
  Clock Net Delay (Source):      1.950ns (routing 0.690ns, distribution 1.260ns)
  Clock Net Delay (Destination): 2.236ns (routing 0.763ns, distribution 1.473ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.950     2.132    d_1_i/axi_smc/inst/s03_entry_pipeline/s03_mmu/inst/w_sreg/aclk
                  SLICE_X48Y18         FDRE                                         r  d_1_i/axi_smc/inst/s03_entry_pipeline/s03_mmu/inst/w_sreg/m_vector_i_reg[1130]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X48Y18         FDRE (Prop_DFF2_SLICEM_C_Q)
                                                                    0.061     2.193 r  d_1_i/axi_smc/inst/s03_entry_pipeline/s03_mmu/inst/w_sreg/m_vector_i_reg[1130]/Q
                                       net (fo=1, routed)           0.137     2.330    d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139/DIE1
    Routing       SLICE_X45Y18         RAMD32                                       r  d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139/RAME_D1/I
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.236     2.462    d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139/WCLK
                  SLICE_X45Y18         RAMD32                                       r  d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139/RAME_D1/CLK
                                       clock pessimism             -0.203     2.258    
                  SLICE_X45Y18         RAMD32 (Hold_E6LUT_SLICEM_CLK_I)
                                                                    0.060     2.318    d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139/RAME_D1
  ---------------------------------------------------------------------------------
                                       required time                         -2.318    
                                       arrival time                           2.330    
  ---------------------------------------------------------------------------------
                                       slack                                  0.012    

Slack (MET) :             0.012ns  (arrival time - required time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/r_rd_imm_dt_reg[29]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/r_x1_imm_dt_reg[29]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.240ns  (logic 0.058ns (24.117%)  route 0.182ns (75.883%))
  Logic Levels:           0  
  Clock Path Skew:        0.166ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.452ns
    Source Clock Delay      (SCD):    2.083ns
    Clock Pessimism Removal (CPR):    0.203ns
  Clock Net Delay (Source):      1.901ns (routing 0.690ns, distribution 1.211ns)
  Clock Net Delay (Destination): 2.226ns (routing 0.763ns, distribution 1.463ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.901     2.083    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/c_clk_i
                  SLICE_X58Y93         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/r_rd_imm_dt_reg[29]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X58Y93         FDRE (Prop_FFF_SLICEL_C_Q)
                                                                    0.058     2.141 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/r_rd_imm_dt_reg[29]/Q
                                       net (fo=13, routed)          0.182     2.323    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/r_rd_imm_dt[29]
    Routing       SLICE_X62Y94         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/r_x1_imm_dt_reg[29]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.226     2.452    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/c_clk_i
                  SLICE_X62Y94         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/r_x1_imm_dt_reg[29]/C
                                       clock pessimism             -0.203     2.249    
                  SLICE_X62Y94         FDRE (Hold_EFF2_SLICEL_C_D)
                                                                    0.062     2.311    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/r_x1_imm_dt_reg[29]
  ---------------------------------------------------------------------------------
                                       required time                         -2.311    
                                       arrival time                           2.323    
  ---------------------------------------------------------------------------------
                                       slack                                  0.012    

Slack (MET) :             0.013ns  (arrival time - required time)
  Source:                 d_1_i/axi_dma_tproc/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_S2MM_MMAP_SKID_BUF/sig_data_reg_out_reg[93]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/s03_entry_pipeline/s03_mmu/inst/w_sreg/skid_buffer_reg[1118]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.182ns  (logic 0.058ns (31.868%)  route 0.124ns (68.132%))
  Logic Levels:           0  
  Clock Path Skew:        0.107ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.433ns
    Source Clock Delay      (SCD):    2.122ns
    Clock Pessimism Removal (CPR):    0.203ns
  Clock Net Delay (Source):      1.940ns (routing 0.690ns, distribution 1.250ns)
  Clock Net Delay (Destination): 2.207ns (routing 0.763ns, distribution 1.444ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.940     2.122    d_1_i/axi_dma_tproc/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_S2MM_MMAP_SKID_BUF/m_axi_s2mm_aclk
                  SLICE_X50Y18         FDRE                                         r  d_1_i/axi_dma_tproc/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_S2MM_MMAP_SKID_BUF/sig_data_reg_out_reg[93]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X50Y18         FDRE (Prop_CFF_SLICEL_C_Q)
                                                                    0.058     2.180 r  d_1_i/axi_dma_tproc/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_S2MM_MMAP_SKID_BUF/sig_data_reg_out_reg[93]/Q
                                       net (fo=2, routed)           0.124     2.304    d_1_i/axi_smc/inst/s03_entry_pipeline/s03_mmu/inst/w_sreg/D[94]
    Routing       SLICE_X47Y17         FDRE                                         r  d_1_i/axi_smc/inst/s03_entry_pipeline/s03_mmu/inst/w_sreg/skid_buffer_reg[1118]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.207     2.433    d_1_i/axi_smc/inst/s03_entry_pipeline/s03_mmu/inst/w_sreg/aclk
                  SLICE_X47Y17         FDRE                                         r  d_1_i/axi_smc/inst/s03_entry_pipeline/s03_mmu/inst/w_sreg/skid_buffer_reg[1118]/C
                                       clock pessimism             -0.203     2.230    
                  SLICE_X47Y17         FDRE (Hold_GFF2_SLICEL_C_D)
                                                                    0.062     2.292    d_1_i/axi_smc/inst/s03_entry_pipeline/s03_mmu/inst/w_sreg/skid_buffer_reg[1118]
  ---------------------------------------------------------------------------------
                                       required time                         -2.292    
                                       arrival time                           2.304    
  ---------------------------------------------------------------------------------
                                       slack                                  0.013    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         clk_pl_0
Waveform(ns):       { 0.000 5.000 }
Period(ns):         10.000
Sources:            { d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0] }

Check Type        Corner  Lib Pin           Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location    Pin
Min Period        n/a     HSADC/DCLK        n/a            4.000         10.000      6.000      HSADC_X0Y0  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/DCLK
Min Period        n/a     HSADC/DCLK        n/a            4.000         10.000      6.000      HSADC_X0Y1  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/DCLK
Min Period        n/a     HSADC/DCLK        n/a            4.000         10.000      6.000      HSADC_X0Y2  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/DCLK
Min Period        n/a     HSADC/DCLK        n/a            4.000         10.000      6.000      HSADC_X0Y3  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/DCLK
Min Period        n/a     HSDAC/DCLK        n/a            4.000         10.000      6.000      HSDAC_X0Y0  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/DCLK
Min Period        n/a     HSDAC/DCLK        n/a            4.000         10.000      6.000      HSDAC_X0Y1  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/DCLK
Min Period        n/a     PS8/MAXIGP0ACLK   n/a            3.000         10.000      7.000      PS8_X0Y0    d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0ACLK
Min Period        n/a     PS8/SAXIGP0RCLK   n/a            3.000         10.000      7.000      PS8_X0Y0    d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/SAXIGP0RCLK
Min Period        n/a     PS8/SAXIGP0WCLK   n/a            3.000         10.000      7.000      PS8_X0Y0    d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/SAXIGP0WCLK
Min Period        n/a     HSADC/PLL_MONCLK  n/a            2.500         10.000      7.500      HSADC_X0Y0  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/PLL_MONCLK
Low Pulse Width   Slow    HSADC/DCLK        n/a            1.600         5.000       3.400      HSADC_X0Y0  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/DCLK
Low Pulse Width   Fast    HSADC/DCLK        n/a            1.600         5.000       3.400      HSADC_X0Y0  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/DCLK
Low Pulse Width   Slow    HSADC/DCLK        n/a            1.600         5.000       3.400      HSADC_X0Y1  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/DCLK
Low Pulse Width   Fast    HSADC/DCLK        n/a            1.600         5.000       3.400      HSADC_X0Y1  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/DCLK
Low Pulse Width   Slow    HSADC/DCLK        n/a            1.600         5.000       3.400      HSADC_X0Y2  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/DCLK
Low Pulse Width   Fast    HSADC/DCLK        n/a            1.600         5.000       3.400      HSADC_X0Y2  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/DCLK
Low Pulse Width   Slow    HSADC/DCLK        n/a            1.600         5.000       3.400      HSADC_X0Y3  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/DCLK
Low Pulse Width   Fast    HSADC/DCLK        n/a            1.600         5.000       3.400      HSADC_X0Y3  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/DCLK
Low Pulse Width   Slow    HSDAC/DCLK        n/a            1.600         5.000       3.400      HSDAC_X0Y0  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/DCLK
Low Pulse Width   Fast    HSDAC/DCLK        n/a            1.600         5.000       3.400      HSDAC_X0Y0  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/DCLK
High Pulse Width  Slow    HSADC/DCLK        n/a            1.600         5.000       3.400      HSADC_X0Y0  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/DCLK
High Pulse Width  Fast    HSADC/DCLK        n/a            1.600         5.000       3.400      HSADC_X0Y0  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/DCLK
High Pulse Width  Slow    HSADC/DCLK        n/a            1.600         5.000       3.400      HSADC_X0Y1  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/DCLK
High Pulse Width  Fast    HSADC/DCLK        n/a            1.600         5.000       3.400      HSADC_X0Y1  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/DCLK
High Pulse Width  Slow    HSADC/DCLK        n/a            1.600         5.000       3.400      HSADC_X0Y2  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/DCLK
High Pulse Width  Fast    HSADC/DCLK        n/a            1.600         5.000       3.400      HSADC_X0Y2  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/DCLK
High Pulse Width  Slow    HSADC/DCLK        n/a            1.600         5.000       3.400      HSADC_X0Y3  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/DCLK
High Pulse Width  Fast    HSADC/DCLK        n/a            1.600         5.000       3.400      HSADC_X0Y3  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/DCLK
High Pulse Width  Slow    HSDAC/DCLK        n/a            1.600         5.000       3.400      HSDAC_X0Y0  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/DCLK
High Pulse Width  Fast    HSDAC/DCLK        n/a            1.600         5.000       3.400      HSDAC_X0Y0  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/DCLK



---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  RFDAC0_CLK
  To Clock:  RFDAC0_CLK

Setup :            0  Failing Endpoints,  Worst Slack        0.552ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.142ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.552ns  (required time - arrival time)
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_3/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/time_abs_r_reg[42]/CLR
                            (recovery check against rising-edge clock RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            2.441ns  (RFDAC0_CLK rise@2.441ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        1.812ns  (logic 0.079ns (4.361%)  route 1.733ns (95.639%))
  Logic Levels:           0  
  Clock Path Skew:        0.024ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.694ns = ( 5.135 - 2.441 ) 
    Source Clock Delay      (SCD):    2.996ns
    Clock Pessimism Removal (CPR):    0.327ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.323ns (routing 1.120ns, distribution 1.203ns)
  Clock Net Delay (Destination): 2.173ns (routing 1.015ns, distribution 1.158ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.323     2.996    d_1_i/rst_dac0/U0/slowest_sync_clk
                  SLICE_X81Y112        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_3/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X81Y112        FDRE (Prop_AFF_SLICEL_C_Q)
                                                                    0.079     3.075 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_3/Q
                                       net (fo=162, routed)         1.733     4.808    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/peripheral_aresetn[0]_repN_3_alias
    Routing       SLICE_X80Y82         FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/time_abs_r_reg[42]/CLR  (IS_INVERTED)
  ---------------------------------------------------------------------------------    -------------------

                                       (clock RFDAC0_CLK rise edge)
                                                                    2.441     2.441 r  
                  HSDAC_X0Y0           HSDAC                        0.000     2.441 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.281     2.722 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.126     2.848    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     2.962 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.173     5.135    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
                  SLICE_X80Y82         FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/time_abs_r_reg[42]/C
                                       clock pessimism              0.327     5.461    
                                       clock uncertainty           -0.035     5.426    
                  SLICE_X80Y82         FDCE (Recov_EFF_SLICEL_C_CLR)
                                                                   -0.066     5.360    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/time_abs_r_reg[42]
  ---------------------------------------------------------------------------------
                                       required time                          5.360    
                                       arrival time                          -4.808    
  ---------------------------------------------------------------------------------
                                       slack                                  0.552    

Slack (MET) :             0.592ns  (required time - arrival time)
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_4/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][68]/CLR
                            (recovery check against rising-edge clock RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            2.441ns  (RFDAC0_CLK rise@2.441ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        1.655ns  (logic 0.081ns (4.895%)  route 1.574ns (95.105%))
  Logic Levels:           0  
  Clock Path Skew:        -0.093ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.590ns = ( 5.031 - 2.441 ) 
    Source Clock Delay      (SCD):    3.007ns
    Clock Pessimism Removal (CPR):    0.324ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.334ns (routing 1.120ns, distribution 1.214ns)
  Clock Net Delay (Destination): 2.069ns (routing 1.015ns, distribution 1.054ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.334     3.007    d_1_i/rst_dac0/U0/slowest_sync_clk
                  SLICE_X85Y113        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_4/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X85Y113        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                                    0.081     3.088 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_4/Q
                                       net (fo=151, routed)         1.574     4.662    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/peripheral_aresetn[0]_repN_4_alias
    Routing       SLICE_X81Y110        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][68]/CLR  (IS_INVERTED)
  ---------------------------------------------------------------------------------    -------------------

                                       (clock RFDAC0_CLK rise edge)
                                                                    2.441     2.441 r  
                  HSDAC_X0Y0           HSDAC                        0.000     2.441 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.281     2.722 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.126     2.848    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     2.962 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.069     5.031    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
                  SLICE_X81Y110        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][68]/C
                                       clock pessimism              0.324     5.355    
                                       clock uncertainty           -0.035     5.320    
                  SLICE_X81Y110        FDCE (Recov_DFF_SLICEL_C_CLR)
                                                                   -0.066     5.254    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][68]
  ---------------------------------------------------------------------------------
                                       required time                          5.254    
                                       arrival time                          -4.662    
  ---------------------------------------------------------------------------------
                                       slack                                  0.592    

Slack (MET) :             0.592ns  (required time - arrival time)
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_4/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][69]/CLR
                            (recovery check against rising-edge clock RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            2.441ns  (RFDAC0_CLK rise@2.441ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        1.655ns  (logic 0.081ns (4.895%)  route 1.574ns (95.105%))
  Logic Levels:           0  
  Clock Path Skew:        -0.093ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.590ns = ( 5.031 - 2.441 ) 
    Source Clock Delay      (SCD):    3.007ns
    Clock Pessimism Removal (CPR):    0.324ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.334ns (routing 1.120ns, distribution 1.214ns)
  Clock Net Delay (Destination): 2.069ns (routing 1.015ns, distribution 1.054ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.334     3.007    d_1_i/rst_dac0/U0/slowest_sync_clk
                  SLICE_X85Y113        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_4/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X85Y113        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                                    0.081     3.088 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_4/Q
                                       net (fo=151, routed)         1.574     4.662    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/peripheral_aresetn[0]_repN_4_alias
    Routing       SLICE_X81Y110        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][69]/CLR  (IS_INVERTED)
  ---------------------------------------------------------------------------------    -------------------

                                       (clock RFDAC0_CLK rise edge)
                                                                    2.441     2.441 r  
                  HSDAC_X0Y0           HSDAC                        0.000     2.441 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.281     2.722 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.126     2.848    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     2.962 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.069     5.031    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
                  SLICE_X81Y110        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][69]/C
                                       clock pessimism              0.324     5.355    
                                       clock uncertainty           -0.035     5.320    
                  SLICE_X81Y110        FDCE (Recov_DFF2_SLICEL_C_CLR)
                                                                   -0.066     5.254    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][69]
  ---------------------------------------------------------------------------------
                                       required time                          5.254    
                                       arrival time                          -4.662    
  ---------------------------------------------------------------------------------
                                       slack                                  0.592    

Slack (MET) :             0.592ns  (required time - arrival time)
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_4/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][98]/CLR
                            (recovery check against rising-edge clock RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            2.441ns  (RFDAC0_CLK rise@2.441ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        1.655ns  (logic 0.081ns (4.895%)  route 1.574ns (95.105%))
  Logic Levels:           0  
  Clock Path Skew:        -0.093ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.590ns = ( 5.031 - 2.441 ) 
    Source Clock Delay      (SCD):    3.007ns
    Clock Pessimism Removal (CPR):    0.324ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.334ns (routing 1.120ns, distribution 1.214ns)
  Clock Net Delay (Destination): 2.069ns (routing 1.015ns, distribution 1.054ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.334     3.007    d_1_i/rst_dac0/U0/slowest_sync_clk
                  SLICE_X85Y113        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_4/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X85Y113        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                                    0.081     3.088 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_4/Q
                                       net (fo=151, routed)         1.574     4.662    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/peripheral_aresetn[0]_repN_4_alias
    Routing       SLICE_X81Y110        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][98]/CLR  (IS_INVERTED)
  ---------------------------------------------------------------------------------    -------------------

                                       (clock RFDAC0_CLK rise edge)
                                                                    2.441     2.441 r  
                  HSDAC_X0Y0           HSDAC                        0.000     2.441 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.281     2.722 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.126     2.848    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     2.962 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.069     5.031    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
                  SLICE_X81Y110        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][98]/C
                                       clock pessimism              0.324     5.355    
                                       clock uncertainty           -0.035     5.320    
                  SLICE_X81Y110        FDCE (Recov_CFF_SLICEL_C_CLR)
                                                                   -0.066     5.254    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][98]
  ---------------------------------------------------------------------------------
                                       required time                          5.254    
                                       arrival time                          -4.662    
  ---------------------------------------------------------------------------------
                                       slack                                  0.592    

Slack (MET) :             0.592ns  (required time - arrival time)
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_4/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][99]/CLR
                            (recovery check against rising-edge clock RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            2.441ns  (RFDAC0_CLK rise@2.441ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        1.655ns  (logic 0.081ns (4.895%)  route 1.574ns (95.105%))
  Logic Levels:           0  
  Clock Path Skew:        -0.093ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.590ns = ( 5.031 - 2.441 ) 
    Source Clock Delay      (SCD):    3.007ns
    Clock Pessimism Removal (CPR):    0.324ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.334ns (routing 1.120ns, distribution 1.214ns)
  Clock Net Delay (Destination): 2.069ns (routing 1.015ns, distribution 1.054ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.334     3.007    d_1_i/rst_dac0/U0/slowest_sync_clk
                  SLICE_X85Y113        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_4/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X85Y113        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                                    0.081     3.088 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_4/Q
                                       net (fo=151, routed)         1.574     4.662    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/peripheral_aresetn[0]_repN_4_alias
    Routing       SLICE_X81Y110        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][99]/CLR  (IS_INVERTED)
  ---------------------------------------------------------------------------------    -------------------

                                       (clock RFDAC0_CLK rise edge)
                                                                    2.441     2.441 r  
                  HSDAC_X0Y0           HSDAC                        0.000     2.441 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.281     2.722 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.126     2.848    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     2.962 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.069     5.031    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
                  SLICE_X81Y110        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][99]/C
                                       clock pessimism              0.324     5.355    
                                       clock uncertainty           -0.035     5.320    
                  SLICE_X81Y110        FDCE (Recov_CFF2_SLICEL_C_CLR)
                                                                   -0.066     5.254    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][99]
  ---------------------------------------------------------------------------------
                                       required time                          5.254    
                                       arrival time                          -4.662    
  ---------------------------------------------------------------------------------
                                       slack                                  0.592    

Slack (MET) :             0.595ns  (required time - arrival time)
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_4/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][132]/CLR
                            (recovery check against rising-edge clock RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            2.441ns  (RFDAC0_CLK rise@2.441ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        1.654ns  (logic 0.081ns (4.898%)  route 1.573ns (95.102%))
  Logic Levels:           0  
  Clock Path Skew:        -0.091ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.592ns = ( 5.033 - 2.441 ) 
    Source Clock Delay      (SCD):    3.007ns
    Clock Pessimism Removal (CPR):    0.324ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.334ns (routing 1.120ns, distribution 1.214ns)
  Clock Net Delay (Destination): 2.071ns (routing 1.015ns, distribution 1.056ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.334     3.007    d_1_i/rst_dac0/U0/slowest_sync_clk
                  SLICE_X85Y113        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_4/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X85Y113        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                                    0.081     3.088 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_4/Q
                                       net (fo=151, routed)         1.573     4.661    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/peripheral_aresetn[0]_repN_4_alias
    Routing       SLICE_X81Y110        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][132]/CLR  (IS_INVERTED)
  ---------------------------------------------------------------------------------    -------------------

                                       (clock RFDAC0_CLK rise edge)
                                                                    2.441     2.441 r  
                  HSDAC_X0Y0           HSDAC                        0.000     2.441 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.281     2.722 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.126     2.848    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     2.962 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.071     5.033    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
                  SLICE_X81Y110        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][132]/C
                                       clock pessimism              0.324     5.357    
                                       clock uncertainty           -0.035     5.322    
                  SLICE_X81Y110        FDCE (Recov_HFF_SLICEL_C_CLR)
                                                                   -0.066     5.256    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][132]
  ---------------------------------------------------------------------------------
                                       required time                          5.256    
                                       arrival time                          -4.661    
  ---------------------------------------------------------------------------------
                                       slack                                  0.595    

Slack (MET) :             0.595ns  (required time - arrival time)
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_4/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][133]/CLR
                            (recovery check against rising-edge clock RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            2.441ns  (RFDAC0_CLK rise@2.441ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        1.654ns  (logic 0.081ns (4.898%)  route 1.573ns (95.102%))
  Logic Levels:           0  
  Clock Path Skew:        -0.091ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.592ns = ( 5.033 - 2.441 ) 
    Source Clock Delay      (SCD):    3.007ns
    Clock Pessimism Removal (CPR):    0.324ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.334ns (routing 1.120ns, distribution 1.214ns)
  Clock Net Delay (Destination): 2.071ns (routing 1.015ns, distribution 1.056ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.334     3.007    d_1_i/rst_dac0/U0/slowest_sync_clk
                  SLICE_X85Y113        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_4/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X85Y113        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                                    0.081     3.088 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_4/Q
                                       net (fo=151, routed)         1.573     4.661    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/peripheral_aresetn[0]_repN_4_alias
    Routing       SLICE_X81Y110        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][133]/CLR  (IS_INVERTED)
  ---------------------------------------------------------------------------------    -------------------

                                       (clock RFDAC0_CLK rise edge)
                                                                    2.441     2.441 r  
                  HSDAC_X0Y0           HSDAC                        0.000     2.441 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.281     2.722 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.126     2.848    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     2.962 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.071     5.033    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
                  SLICE_X81Y110        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][133]/C
                                       clock pessimism              0.324     5.357    
                                       clock uncertainty           -0.035     5.322    
                  SLICE_X81Y110        FDCE (Recov_HFF2_SLICEL_C_CLR)
                                                                   -0.066     5.256    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][133]
  ---------------------------------------------------------------------------------
                                       required time                          5.256    
                                       arrival time                          -4.661    
  ---------------------------------------------------------------------------------
                                       slack                                  0.595    

Slack (MET) :             0.650ns  (required time - arrival time)
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_2/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/time_abs_r_reg[12]/CLR
                            (recovery check against rising-edge clock RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            2.441ns  (RFDAC0_CLK rise@2.441ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        1.622ns  (logic 0.077ns (4.748%)  route 1.545ns (95.252%))
  Logic Levels:           0  
  Clock Path Skew:        -0.068ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.594ns = ( 5.035 - 2.441 ) 
    Source Clock Delay      (SCD):    2.986ns
    Clock Pessimism Removal (CPR):    0.324ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.313ns (routing 1.120ns, distribution 1.193ns)
  Clock Net Delay (Destination): 2.073ns (routing 1.015ns, distribution 1.058ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.313     2.986    d_1_i/rst_dac0/U0/slowest_sync_clk
                  SLICE_X82Y83         FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_2/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X82Y83         FDRE (Prop_AFF_SLICEM_C_Q)
                                                                    0.077     3.063 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_2/Q
                                       net (fo=31, routed)          1.545     4.608    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/peripheral_aresetn[0]_repN_2_alias
    Routing       SLICE_X81Y69         FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/time_abs_r_reg[12]/CLR  (IS_INVERTED)
  ---------------------------------------------------------------------------------    -------------------

                                       (clock RFDAC0_CLK rise edge)
                                                                    2.441     2.441 r  
                  HSDAC_X0Y0           HSDAC                        0.000     2.441 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.281     2.722 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.126     2.848    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     2.962 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.073     5.035    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
                  SLICE_X81Y69         FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/time_abs_r_reg[12]/C
                                       clock pessimism              0.324     5.359    
                                       clock uncertainty           -0.035     5.324    
                  SLICE_X81Y69         FDCE (Recov_AFF_SLICEL_C_CLR)
                                                                   -0.066     5.258    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/time_abs_r_reg[12]
  ---------------------------------------------------------------------------------
                                       required time                          5.258    
                                       arrival time                          -4.608    
  ---------------------------------------------------------------------------------
                                       slack                                  0.650    

Slack (MET) :             0.660ns  (required time - arrival time)
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_4/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][62]/CLR
                            (recovery check against rising-edge clock RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            2.441ns  (RFDAC0_CLK rise@2.441ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        1.586ns  (logic 0.081ns (5.106%)  route 1.505ns (94.894%))
  Logic Levels:           0  
  Clock Path Skew:        -0.093ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.590ns = ( 5.031 - 2.441 ) 
    Source Clock Delay      (SCD):    3.007ns
    Clock Pessimism Removal (CPR):    0.324ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.334ns (routing 1.120ns, distribution 1.214ns)
  Clock Net Delay (Destination): 2.069ns (routing 1.015ns, distribution 1.054ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.334     3.007    d_1_i/rst_dac0/U0/slowest_sync_clk
                  SLICE_X85Y113        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_4/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X85Y113        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                                    0.081     3.088 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_4/Q
                                       net (fo=151, routed)         1.505     4.593    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/peripheral_aresetn[0]_repN_4_alias
    Routing       SLICE_X81Y109        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][62]/CLR  (IS_INVERTED)
  ---------------------------------------------------------------------------------    -------------------

                                       (clock RFDAC0_CLK rise edge)
                                                                    2.441     2.441 r  
                  HSDAC_X0Y0           HSDAC                        0.000     2.441 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.281     2.722 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.126     2.848    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     2.962 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.069     5.031    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
                  SLICE_X81Y109        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][62]/C
                                       clock pessimism              0.324     5.355    
                                       clock uncertainty           -0.035     5.320    
                  SLICE_X81Y109        FDCE (Recov_DFF_SLICEL_C_CLR)
                                                                   -0.066     5.254    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][62]
  ---------------------------------------------------------------------------------
                                       required time                          5.254    
                                       arrival time                          -4.593    
  ---------------------------------------------------------------------------------
                                       slack                                  0.660    

Slack (MET) :             0.660ns  (required time - arrival time)
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_4/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][63]/CLR
                            (recovery check against rising-edge clock RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            2.441ns  (RFDAC0_CLK rise@2.441ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        1.586ns  (logic 0.081ns (5.106%)  route 1.505ns (94.894%))
  Logic Levels:           0  
  Clock Path Skew:        -0.093ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.590ns = ( 5.031 - 2.441 ) 
    Source Clock Delay      (SCD):    3.007ns
    Clock Pessimism Removal (CPR):    0.324ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.334ns (routing 1.120ns, distribution 1.214ns)
  Clock Net Delay (Destination): 2.069ns (routing 1.015ns, distribution 1.054ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.334     3.007    d_1_i/rst_dac0/U0/slowest_sync_clk
                  SLICE_X85Y113        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_4/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X85Y113        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                                    0.081     3.088 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_4/Q
                                       net (fo=151, routed)         1.505     4.593    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/peripheral_aresetn[0]_repN_4_alias
    Routing       SLICE_X81Y109        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][63]/CLR  (IS_INVERTED)
  ---------------------------------------------------------------------------------    -------------------

                                       (clock RFDAC0_CLK rise edge)
                                                                    2.441     2.441 r  
                  HSDAC_X0Y0           HSDAC                        0.000     2.441 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.281     2.722 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.126     2.848    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     2.962 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.069     5.031    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
                  SLICE_X81Y109        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][63]/C
                                       clock pessimism              0.324     5.355    
                                       clock uncertainty           -0.035     5.320    
                  SLICE_X81Y109        FDCE (Recov_DFF2_SLICEL_C_CLR)
                                                                   -0.066     5.254    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][63]
  ---------------------------------------------------------------------------------
                                       required time                          5.254    
                                       arrival time                          -4.593    
  ---------------------------------------------------------------------------------
                                       slack                                  0.660    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.142ns  (arrival time - required time)
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_11/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][34]/CLR
                            (removal check against rising-edge clock RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (RFDAC0_CLK rise@0.000ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        0.132ns  (logic 0.039ns (29.600%)  route 0.093ns (70.400%))
  Logic Levels:           0  
  Clock Path Skew:        0.010ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.966ns
    Source Clock Delay      (SCD):    1.695ns
    Clock Pessimism Removal (CPR):    0.261ns
  Clock Net Delay (Source):      1.346ns (routing 0.607ns, distribution 0.739ns)
  Clock Net Delay (Destination): 1.518ns (routing 0.684ns, distribution 0.834ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        1.346     1.695    d_1_i/rst_dac0/U0/slowest_sync_clk
                  SLICE_X80Y108        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_11/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X80Y108        FDRE (Prop_EFF_SLICEL_C_Q)
                                                                    0.039     1.734 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_11/Q
                                       net (fo=46, routed)          0.093     1.826    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/peripheral_aresetn[0]_repN_11_alias
    Routing       SLICE_X80Y108        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][34]/CLR  (IS_INVERTED)
  ---------------------------------------------------------------------------------    -------------------

                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        1.518     1.966    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
                  SLICE_X80Y108        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][34]/C
                                       clock pessimism             -0.261     1.705    
                  SLICE_X80Y108        FDCE (Remov_DFF_SLICEL_C_CLR)
                                                                   -0.020     1.685    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][34]
  ---------------------------------------------------------------------------------
                                       required time                         -1.685    
                                       arrival time                           1.826    
  ---------------------------------------------------------------------------------
                                       slack                                  0.142    

Slack (MET) :             0.142ns  (arrival time - required time)
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_11/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][35]/CLR
                            (removal check against rising-edge clock RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (RFDAC0_CLK rise@0.000ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        0.132ns  (logic 0.039ns (29.600%)  route 0.093ns (70.400%))
  Logic Levels:           0  
  Clock Path Skew:        0.010ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.966ns
    Source Clock Delay      (SCD):    1.695ns
    Clock Pessimism Removal (CPR):    0.261ns
  Clock Net Delay (Source):      1.346ns (routing 0.607ns, distribution 0.739ns)
  Clock Net Delay (Destination): 1.518ns (routing 0.684ns, distribution 0.834ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        1.346     1.695    d_1_i/rst_dac0/U0/slowest_sync_clk
                  SLICE_X80Y108        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_11/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X80Y108        FDRE (Prop_EFF_SLICEL_C_Q)
                                                                    0.039     1.734 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_11/Q
                                       net (fo=46, routed)          0.093     1.826    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/peripheral_aresetn[0]_repN_11_alias
    Routing       SLICE_X80Y108        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][35]/CLR  (IS_INVERTED)
  ---------------------------------------------------------------------------------    -------------------

                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        1.518     1.966    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
                  SLICE_X80Y108        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][35]/C
                                       clock pessimism             -0.261     1.705    
                  SLICE_X80Y108        FDCE (Remov_DFF2_SLICEL_C_CLR)
                                                                   -0.020     1.685    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][35]
  ---------------------------------------------------------------------------------
                                       required time                         -1.685    
                                       arrival time                           1.826    
  ---------------------------------------------------------------------------------
                                       slack                                  0.142    

Slack (MET) :             0.171ns  (arrival time - required time)
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_11/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][76]/CLR
                            (removal check against rising-edge clock RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (RFDAC0_CLK rise@0.000ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        0.160ns  (logic 0.039ns (24.451%)  route 0.121ns (75.549%))
  Logic Levels:           0  
  Clock Path Skew:        0.009ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.958ns
    Source Clock Delay      (SCD):    1.695ns
    Clock Pessimism Removal (CPR):    0.255ns
  Clock Net Delay (Source):      1.346ns (routing 0.607ns, distribution 0.739ns)
  Clock Net Delay (Destination): 1.510ns (routing 0.684ns, distribution 0.826ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        1.346     1.695    d_1_i/rst_dac0/U0/slowest_sync_clk
                  SLICE_X80Y108        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_11/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X80Y108        FDRE (Prop_EFF_SLICEL_C_Q)
                                                                    0.039     1.734 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_11/Q
                                       net (fo=46, routed)          0.121     1.854    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/peripheral_aresetn[0]_repN_11_alias
    Routing       SLICE_X80Y110        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][76]/CLR  (IS_INVERTED)
  ---------------------------------------------------------------------------------    -------------------

                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        1.510     1.958    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
                  SLICE_X80Y110        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][76]/C
                                       clock pessimism             -0.255     1.704    
                  SLICE_X80Y110        FDCE (Remov_DFF_SLICEL_C_CLR)
                                                                   -0.020     1.684    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][76]
  ---------------------------------------------------------------------------------
                                       required time                         -1.684    
                                       arrival time                           1.854    
  ---------------------------------------------------------------------------------
                                       slack                                  0.171    

Slack (MET) :             0.171ns  (arrival time - required time)
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_11/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][77]/CLR
                            (removal check against rising-edge clock RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (RFDAC0_CLK rise@0.000ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        0.160ns  (logic 0.039ns (24.451%)  route 0.121ns (75.549%))
  Logic Levels:           0  
  Clock Path Skew:        0.009ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.958ns
    Source Clock Delay      (SCD):    1.695ns
    Clock Pessimism Removal (CPR):    0.255ns
  Clock Net Delay (Source):      1.346ns (routing 0.607ns, distribution 0.739ns)
  Clock Net Delay (Destination): 1.510ns (routing 0.684ns, distribution 0.826ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        1.346     1.695    d_1_i/rst_dac0/U0/slowest_sync_clk
                  SLICE_X80Y108        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_11/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X80Y108        FDRE (Prop_EFF_SLICEL_C_Q)
                                                                    0.039     1.734 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_11/Q
                                       net (fo=46, routed)          0.121     1.854    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/peripheral_aresetn[0]_repN_11_alias
    Routing       SLICE_X80Y110        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][77]/CLR  (IS_INVERTED)
  ---------------------------------------------------------------------------------    -------------------

                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        1.510     1.958    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
                  SLICE_X80Y110        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][77]/C
                                       clock pessimism             -0.255     1.704    
                  SLICE_X80Y110        FDCE (Remov_DFF2_SLICEL_C_CLR)
                                                                   -0.020     1.684    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][77]
  ---------------------------------------------------------------------------------
                                       required time                         -1.684    
                                       arrival time                           1.854    
  ---------------------------------------------------------------------------------
                                       slack                                  0.171    

Slack (MET) :             0.186ns  (arrival time - required time)
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_1/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][70]/CLR
                            (removal check against rising-edge clock RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (RFDAC0_CLK rise@0.000ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        0.184ns  (logic 0.038ns (20.689%)  route 0.146ns (79.311%))
  Logic Levels:           0  
  Clock Path Skew:        0.017ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.963ns
    Source Clock Delay      (SCD):    1.691ns
    Clock Pessimism Removal (CPR):    0.255ns
  Clock Net Delay (Source):      1.342ns (routing 0.607ns, distribution 0.735ns)
  Clock Net Delay (Destination): 1.515ns (routing 0.684ns, distribution 0.831ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        1.342     1.691    d_1_i/rst_dac0/U0/slowest_sync_clk
                  SLICE_X78Y101        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_1/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X78Y101        FDRE (Prop_EFF_SLICEM_C_Q)
                                                                    0.038     1.729 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_1/Q
                                       net (fo=156, routed)         0.146     1.875    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/peripheral_aresetn[0]_repN_1_alias
    Routing       SLICE_X78Y104        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][70]/CLR  (IS_INVERTED)
  ---------------------------------------------------------------------------------    -------------------

                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        1.515     1.963    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
                  SLICE_X78Y104        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][70]/C
                                       clock pessimism             -0.255     1.708    
                  SLICE_X78Y104        FDCE (Remov_HFF_SLICEM_C_CLR)
                                                                   -0.020     1.688    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][70]
  ---------------------------------------------------------------------------------
                                       required time                         -1.688    
                                       arrival time                           1.875    
  ---------------------------------------------------------------------------------
                                       slack                                  0.186    

Slack (MET) :             0.186ns  (arrival time - required time)
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_1/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][71]/CLR
                            (removal check against rising-edge clock RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (RFDAC0_CLK rise@0.000ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        0.184ns  (logic 0.038ns (20.689%)  route 0.146ns (79.311%))
  Logic Levels:           0  
  Clock Path Skew:        0.017ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.963ns
    Source Clock Delay      (SCD):    1.691ns
    Clock Pessimism Removal (CPR):    0.255ns
  Clock Net Delay (Source):      1.342ns (routing 0.607ns, distribution 0.735ns)
  Clock Net Delay (Destination): 1.515ns (routing 0.684ns, distribution 0.831ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        1.342     1.691    d_1_i/rst_dac0/U0/slowest_sync_clk
                  SLICE_X78Y101        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_1/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X78Y101        FDRE (Prop_EFF_SLICEM_C_Q)
                                                                    0.038     1.729 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_1/Q
                                       net (fo=156, routed)         0.146     1.875    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/peripheral_aresetn[0]_repN_1_alias
    Routing       SLICE_X78Y104        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][71]/CLR  (IS_INVERTED)
  ---------------------------------------------------------------------------------    -------------------

                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        1.515     1.963    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
                  SLICE_X78Y104        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][71]/C
                                       clock pessimism             -0.255     1.708    
                  SLICE_X78Y104        FDCE (Remov_HFF2_SLICEM_C_CLR)
                                                                   -0.020     1.688    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][71]
  ---------------------------------------------------------------------------------
                                       required time                         -1.688    
                                       arrival time                           1.875    
  ---------------------------------------------------------------------------------
                                       slack                                  0.186    

Slack (MET) :             0.208ns  (arrival time - required time)
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_4/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][90]/CLR
                            (removal check against rising-edge clock RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (RFDAC0_CLK rise@0.000ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        0.235ns  (logic 0.041ns (17.422%)  route 0.194ns (82.578%))
  Logic Levels:           0  
  Clock Path Skew:        0.048ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.888ns
    Source Clock Delay      (SCD):    1.621ns
    Clock Pessimism Removal (CPR):    0.220ns
  Clock Net Delay (Source):      1.272ns (routing 0.607ns, distribution 0.665ns)
  Clock Net Delay (Destination): 1.440ns (routing 0.684ns, distribution 0.756ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        1.272     1.621    d_1_i/rst_dac0/U0/slowest_sync_clk
                  SLICE_X85Y113        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_4/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X85Y113        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                                    0.041     1.662 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_4/Q
                                       net (fo=151, routed)         0.194     1.856    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/peripheral_aresetn[0]_repN_4_alias
    Routing       SLICE_X81Y113        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][90]/CLR  (IS_INVERTED)
  ---------------------------------------------------------------------------------    -------------------

                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        1.440     1.888    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
                  SLICE_X81Y113        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][90]/C
                                       clock pessimism             -0.220     1.668    
                  SLICE_X81Y113        FDCE (Remov_BFF_SLICEL_C_CLR)
                                                                   -0.020     1.648    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][90]
  ---------------------------------------------------------------------------------
                                       required time                         -1.648    
                                       arrival time                           1.856    
  ---------------------------------------------------------------------------------
                                       slack                                  0.208    

Slack (MET) :             0.208ns  (arrival time - required time)
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_4/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][91]/CLR
                            (removal check against rising-edge clock RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (RFDAC0_CLK rise@0.000ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        0.235ns  (logic 0.041ns (17.422%)  route 0.194ns (82.578%))
  Logic Levels:           0  
  Clock Path Skew:        0.048ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.888ns
    Source Clock Delay      (SCD):    1.621ns
    Clock Pessimism Removal (CPR):    0.220ns
  Clock Net Delay (Source):      1.272ns (routing 0.607ns, distribution 0.665ns)
  Clock Net Delay (Destination): 1.440ns (routing 0.684ns, distribution 0.756ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        1.272     1.621    d_1_i/rst_dac0/U0/slowest_sync_clk
                  SLICE_X85Y113        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_4/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X85Y113        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                                    0.041     1.662 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_4/Q
                                       net (fo=151, routed)         0.194     1.856    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/peripheral_aresetn[0]_repN_4_alias
    Routing       SLICE_X81Y113        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][91]/CLR  (IS_INVERTED)
  ---------------------------------------------------------------------------------    -------------------

                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        1.440     1.888    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
                  SLICE_X81Y113        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][91]/C
                                       clock pessimism             -0.220     1.668    
                  SLICE_X81Y113        FDCE (Remov_BFF2_SLICEL_C_CLR)
                                                                   -0.020     1.648    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][91]
  ---------------------------------------------------------------------------------
                                       required time                         -1.648    
                                       arrival time                           1.856    
  ---------------------------------------------------------------------------------
                                       slack                                  0.208    

Slack (MET) :             0.208ns  (arrival time - required time)
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_4/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][94]/CLR
                            (removal check against rising-edge clock RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (RFDAC0_CLK rise@0.000ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        0.235ns  (logic 0.041ns (17.422%)  route 0.194ns (82.578%))
  Logic Levels:           0  
  Clock Path Skew:        0.048ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.888ns
    Source Clock Delay      (SCD):    1.621ns
    Clock Pessimism Removal (CPR):    0.220ns
  Clock Net Delay (Source):      1.272ns (routing 0.607ns, distribution 0.665ns)
  Clock Net Delay (Destination): 1.440ns (routing 0.684ns, distribution 0.756ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        1.272     1.621    d_1_i/rst_dac0/U0/slowest_sync_clk
                  SLICE_X85Y113        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_4/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X85Y113        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                                    0.041     1.662 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_4/Q
                                       net (fo=151, routed)         0.194     1.856    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/peripheral_aresetn[0]_repN_4_alias
    Routing       SLICE_X81Y113        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][94]/CLR  (IS_INVERTED)
  ---------------------------------------------------------------------------------    -------------------

                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        1.440     1.888    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
                  SLICE_X81Y113        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][94]/C
                                       clock pessimism             -0.220     1.668    
                  SLICE_X81Y113        FDCE (Remov_AFF_SLICEL_C_CLR)
                                                                   -0.020     1.648    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][94]
  ---------------------------------------------------------------------------------
                                       required time                         -1.648    
                                       arrival time                           1.856    
  ---------------------------------------------------------------------------------
                                       slack                                  0.208    

Slack (MET) :             0.208ns  (arrival time - required time)
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_4/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][95]/CLR
                            (removal check against rising-edge clock RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (RFDAC0_CLK rise@0.000ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        0.235ns  (logic 0.041ns (17.422%)  route 0.194ns (82.578%))
  Logic Levels:           0  
  Clock Path Skew:        0.048ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.888ns
    Source Clock Delay      (SCD):    1.621ns
    Clock Pessimism Removal (CPR):    0.220ns
  Clock Net Delay (Source):      1.272ns (routing 0.607ns, distribution 0.665ns)
  Clock Net Delay (Destination): 1.440ns (routing 0.684ns, distribution 0.756ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        1.272     1.621    d_1_i/rst_dac0/U0/slowest_sync_clk
                  SLICE_X85Y113        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_4/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X85Y113        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                                    0.041     1.662 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_4/Q
                                       net (fo=151, routed)         0.194     1.856    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/peripheral_aresetn[0]_repN_4_alias
    Routing       SLICE_X81Y113        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][95]/CLR  (IS_INVERTED)
  ---------------------------------------------------------------------------------    -------------------

                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        1.440     1.888    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
                  SLICE_X81Y113        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][95]/C
                                       clock pessimism             -0.220     1.668    
                  SLICE_X81Y113        FDCE (Remov_AFF2_SLICEL_C_CLR)
                                                                   -0.020     1.648    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][95]
  ---------------------------------------------------------------------------------
                                       required time                         -1.648    
                                       arrival time                           1.856    
  ---------------------------------------------------------------------------------
                                       slack                                  0.208    





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  clk_out1_d_1_clk_adc0_x2_0
  To Clock:  clk_out1_d_1_clk_adc0_x2_0

Setup :            0  Failing Endpoints,  Worst Slack        1.854ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.147ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.854ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_1/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/clr_fifo_ack_reg/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            3.906ns  (clk_out1_d_1_clk_adc0_x2_0 rise@3.906ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        1.868ns  (logic 0.076ns (4.068%)  route 1.792ns (95.932%))
  Logic Levels:           0  
  Clock Path Skew:        -0.059ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.936ns = ( 9.842 - 3.906 ) 
    Source Clock Delay      (SCD):    5.831ns
    Clock Pessimism Removal (CPR):    -0.164ns
  Clock Uncertainty:      0.059ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.095ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.742ns (routing 1.754ns, distribution 0.988ns)
  Clock Net Delay (Destination): 2.518ns (routing 1.589ns, distribution 0.929ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.416     2.943    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                   -0.127     2.816 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.245     3.061    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.028     3.089 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.742     5.831    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
                  SLICE_X72Y168        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_1/C
  ---------------------------------------------------------------------------------    -------------------
    Placement     SLICE_X72Y168        FDRE (Prop_EFF_SLICEM_C_Q)
                                                                    0.076     5.907 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_1/Q
                                       net (fo=176, routed)         1.792     7.699    d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/peripheral_aresetn[0]_repN_1_alias
    Moved         SLICE_X63Y255        FDCE                                         f  d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/clr_fifo_ack_reg/CLR  (IS_INVERTED)
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    3.906     3.906 r  
                  HSADC_X0Y1           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.162     6.454    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                    0.630     7.084 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.216     7.300    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.024     7.324 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.518     9.842    d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/adc_clk
                  SLICE_X63Y255        FDCE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/clr_fifo_ack_reg/C
                                       clock pessimism             -0.164     9.678    
                                       clock uncertainty           -0.059     9.619    
                  SLICE_X63Y255        FDCE (Recov_DFF_SLICEM_C_CLR)
                                                                   -0.066     9.553    d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/clr_fifo_ack_reg
  ---------------------------------------------------------------------------------
                                       required time                          9.553    
                                       arrival time                          -7.699    
  ---------------------------------------------------------------------------------
                                       slack                                  1.854    

Slack (MET) :             1.854ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_1/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/clr_fifo_req_reg/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            3.906ns  (clk_out1_d_1_clk_adc0_x2_0 rise@3.906ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        1.868ns  (logic 0.076ns (4.068%)  route 1.792ns (95.932%))
  Logic Levels:           0  
  Clock Path Skew:        -0.059ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.936ns = ( 9.842 - 3.906 ) 
    Source Clock Delay      (SCD):    5.831ns
    Clock Pessimism Removal (CPR):    -0.164ns
  Clock Uncertainty:      0.059ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.095ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.742ns (routing 1.754ns, distribution 0.988ns)
  Clock Net Delay (Destination): 2.518ns (routing 1.589ns, distribution 0.929ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.416     2.943    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                   -0.127     2.816 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.245     3.061    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.028     3.089 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.742     5.831    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
                  SLICE_X72Y168        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_1/C
  ---------------------------------------------------------------------------------    -------------------
    Placement     SLICE_X72Y168        FDRE (Prop_EFF_SLICEM_C_Q)
                                                                    0.076     5.907 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_1/Q
                                       net (fo=176, routed)         1.792     7.699    d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/peripheral_aresetn[0]_repN_1_alias
    Moved         SLICE_X63Y255        FDCE                                         f  d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/clr_fifo_req_reg/CLR  (IS_INVERTED)
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    3.906     3.906 r  
                  HSADC_X0Y1           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.162     6.454    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                    0.630     7.084 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.216     7.300    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.024     7.324 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.518     9.842    d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/adc_clk
                  SLICE_X63Y255        FDCE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/clr_fifo_req_reg/C
                                       clock pessimism             -0.164     9.678    
                                       clock uncertainty           -0.059     9.619    
                  SLICE_X63Y255        FDCE (Recov_DFF2_SLICEM_C_CLR)
                                                                   -0.066     9.553    d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/clr_fifo_req_reg
  ---------------------------------------------------------------------------------
                                       required time                          9.553    
                                       arrival time                          -7.699    
  ---------------------------------------------------------------------------------
                                       slack                                  1.854    

Slack (MET) :             1.865ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_1/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_bin_2r_reg[9]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            3.906ns  (clk_out1_d_1_clk_adc0_x2_0 rise@3.906ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        1.853ns  (logic 0.076ns (4.101%)  route 1.777ns (95.899%))
  Logic Levels:           0  
  Clock Path Skew:        -0.063ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.932ns = ( 9.838 - 3.906 ) 
    Source Clock Delay      (SCD):    5.831ns
    Clock Pessimism Removal (CPR):    -0.164ns
  Clock Uncertainty:      0.059ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.095ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.742ns (routing 1.754ns, distribution 0.988ns)
  Clock Net Delay (Destination): 2.514ns (routing 1.589ns, distribution 0.925ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.416     2.943    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                   -0.127     2.816 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.245     3.061    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.028     3.089 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.742     5.831    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
                  SLICE_X72Y168        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_1/C
  ---------------------------------------------------------------------------------    -------------------
    Placement     SLICE_X72Y168        FDRE (Prop_EFF_SLICEM_C_Q)
                                                                    0.076     5.907 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_1/Q
                                       net (fo=176, routed)         1.777     7.684    d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/peripheral_aresetn[0]_repN_1_alias
    Placement     SLICE_X64Y255        FDCE                                         f  d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_bin_2r_reg[9]/CLR  (IS_INVERTED)
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    3.906     3.906 r  
                  HSADC_X0Y1           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.162     6.454    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                    0.630     7.084 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.216     7.300    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.024     7.324 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.514     9.838    d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/adc_clk
                  SLICE_X64Y255        FDCE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_bin_2r_reg[9]/C
                                       clock pessimism             -0.164     9.674    
                                       clock uncertainty           -0.059     9.615    
                  SLICE_X64Y255        FDCE (Recov_DFF2_SLICEL_C_CLR)
                                                                   -0.066     9.549    d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_bin_2r_reg[9]
  ---------------------------------------------------------------------------------
                                       required time                          9.549    
                                       arrival time                          -7.684    
  ---------------------------------------------------------------------------------
                                       slack                                  1.865    

Slack (MET) :             1.868ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_1/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/clr_rd_r_reg/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            3.906ns  (clk_out1_d_1_clk_adc0_x2_0 rise@3.906ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        1.852ns  (logic 0.076ns (4.104%)  route 1.776ns (95.896%))
  Logic Levels:           0  
  Clock Path Skew:        -0.061ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.934ns = ( 9.840 - 3.906 ) 
    Source Clock Delay      (SCD):    5.831ns
    Clock Pessimism Removal (CPR):    -0.164ns
  Clock Uncertainty:      0.059ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.095ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.742ns (routing 1.754ns, distribution 0.988ns)
  Clock Net Delay (Destination): 2.516ns (routing 1.589ns, distribution 0.927ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.416     2.943    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                   -0.127     2.816 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.245     3.061    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.028     3.089 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.742     5.831    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
                  SLICE_X72Y168        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_1/C
  ---------------------------------------------------------------------------------    -------------------
    Placement     SLICE_X72Y168        FDRE (Prop_EFF_SLICEM_C_Q)
                                                                    0.076     5.907 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_1/Q
                                       net (fo=176, routed)         1.776     7.683    d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/peripheral_aresetn[0]_repN_1_alias
    Placement     SLICE_X64Y255        FDCE                                         f  d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/clr_rd_r_reg/CLR  (IS_INVERTED)
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    3.906     3.906 r  
                  HSADC_X0Y1           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.162     6.454    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                    0.630     7.084 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.216     7.300    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.024     7.324 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.516     9.840    d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/adc_clk
                  SLICE_X64Y255        FDCE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/clr_rd_r_reg/C
                                       clock pessimism             -0.164     9.676    
                                       clock uncertainty           -0.059     9.617    
                  SLICE_X64Y255        FDCE (Recov_EFF_SLICEL_C_CLR)
                                                                   -0.066     9.551    d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/clr_rd_r_reg
  ---------------------------------------------------------------------------------
                                       required time                          9.551    
                                       arrival time                          -7.683    
  ---------------------------------------------------------------------------------
                                       slack                                  1.868    

Slack (MET) :             1.868ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_1/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/clr_rd_rdc_reg/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            3.906ns  (clk_out1_d_1_clk_adc0_x2_0 rise@3.906ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        1.852ns  (logic 0.076ns (4.104%)  route 1.776ns (95.896%))
  Logic Levels:           0  
  Clock Path Skew:        -0.061ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.934ns = ( 9.840 - 3.906 ) 
    Source Clock Delay      (SCD):    5.831ns
    Clock Pessimism Removal (CPR):    -0.164ns
  Clock Uncertainty:      0.059ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.095ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.742ns (routing 1.754ns, distribution 0.988ns)
  Clock Net Delay (Destination): 2.516ns (routing 1.589ns, distribution 0.927ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.416     2.943    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                   -0.127     2.816 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.245     3.061    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.028     3.089 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.742     5.831    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
                  SLICE_X72Y168        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_1/C
  ---------------------------------------------------------------------------------    -------------------
    Placement     SLICE_X72Y168        FDRE (Prop_EFF_SLICEM_C_Q)
                                                                    0.076     5.907 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_1/Q
                                       net (fo=176, routed)         1.776     7.683    d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/peripheral_aresetn[0]_repN_1_alias
    Placement     SLICE_X64Y255        FDCE                                         f  d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/clr_rd_rdc_reg/CLR  (IS_INVERTED)
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    3.906     3.906 r  
                  HSADC_X0Y1           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.162     6.454    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                    0.630     7.084 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.216     7.300    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.024     7.324 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.516     9.840    d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/adc_clk
                  SLICE_X64Y255        FDCE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/clr_rd_rdc_reg/C
                                       clock pessimism             -0.164     9.676    
                                       clock uncertainty           -0.059     9.617    
                  SLICE_X64Y255        FDCE (Recov_EFF2_SLICEL_C_CLR)
                                                                   -0.066     9.551    d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/clr_rd_rdc_reg
  ---------------------------------------------------------------------------------
                                       required time                          9.551    
                                       arrival time                          -7.683    
  ---------------------------------------------------------------------------------
                                       slack                                  1.868    

Slack (MET) :             1.990ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_1/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_bin_2r_reg[4]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            3.906ns  (clk_out1_d_1_clk_adc0_x2_0 rise@3.906ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        1.721ns  (logic 0.076ns (4.416%)  route 1.645ns (95.584%))
  Logic Levels:           0  
  Clock Path Skew:        -0.070ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.925ns = ( 9.831 - 3.906 ) 
    Source Clock Delay      (SCD):    5.831ns
    Clock Pessimism Removal (CPR):    -0.164ns
  Clock Uncertainty:      0.059ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.095ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.742ns (routing 1.754ns, distribution 0.988ns)
  Clock Net Delay (Destination): 2.507ns (routing 1.589ns, distribution 0.918ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.416     2.943    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                   -0.127     2.816 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.245     3.061    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.028     3.089 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.742     5.831    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
                  SLICE_X72Y168        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_1/C
  ---------------------------------------------------------------------------------    -------------------
    Placement     SLICE_X72Y168        FDRE (Prop_EFF_SLICEM_C_Q)
                                                                    0.076     5.907 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_1/Q
                                       net (fo=176, routed)         1.645     7.552    d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/peripheral_aresetn[0]_repN_1_alias
    Placement     SLICE_X64Y252        FDCE                                         f  d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_bin_2r_reg[4]/CLR  (IS_INVERTED)
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    3.906     3.906 r  
                  HSADC_X0Y1           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.162     6.454    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                    0.630     7.084 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.216     7.300    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.024     7.324 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.507     9.831    d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/adc_clk
                  SLICE_X64Y252        FDCE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_bin_2r_reg[4]/C
                                       clock pessimism             -0.164     9.667    
                                       clock uncertainty           -0.059     9.608    
                  SLICE_X64Y252        FDCE (Recov_DFF_SLICEL_C_CLR)
                                                                   -0.066     9.542    d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_bin_2r_reg[4]
  ---------------------------------------------------------------------------------
                                       required time                          9.542    
                                       arrival time                          -7.552    
  ---------------------------------------------------------------------------------
                                       slack                                  1.990    

Slack (MET) :             1.990ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_1/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_bin_2r_reg[5]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            3.906ns  (clk_out1_d_1_clk_adc0_x2_0 rise@3.906ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        1.721ns  (logic 0.076ns (4.416%)  route 1.645ns (95.584%))
  Logic Levels:           0  
  Clock Path Skew:        -0.070ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.925ns = ( 9.831 - 3.906 ) 
    Source Clock Delay      (SCD):    5.831ns
    Clock Pessimism Removal (CPR):    -0.164ns
  Clock Uncertainty:      0.059ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.095ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.742ns (routing 1.754ns, distribution 0.988ns)
  Clock Net Delay (Destination): 2.507ns (routing 1.589ns, distribution 0.918ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.416     2.943    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                   -0.127     2.816 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.245     3.061    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.028     3.089 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.742     5.831    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
                  SLICE_X72Y168        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_1/C
  ---------------------------------------------------------------------------------    -------------------
    Placement     SLICE_X72Y168        FDRE (Prop_EFF_SLICEM_C_Q)
                                                                    0.076     5.907 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_1/Q
                                       net (fo=176, routed)         1.645     7.552    d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/peripheral_aresetn[0]_repN_1_alias
    Placement     SLICE_X64Y252        FDCE                                         f  d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_bin_2r_reg[5]/CLR  (IS_INVERTED)
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    3.906     3.906 r  
                  HSADC_X0Y1           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.162     6.454    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                    0.630     7.084 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.216     7.300    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.024     7.324 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.507     9.831    d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/adc_clk
                  SLICE_X64Y252        FDCE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_bin_2r_reg[5]/C
                                       clock pessimism             -0.164     9.667    
                                       clock uncertainty           -0.059     9.608    
                  SLICE_X64Y252        FDCE (Recov_DFF2_SLICEL_C_CLR)
                                                                   -0.066     9.542    d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_bin_2r_reg[5]
  ---------------------------------------------------------------------------------
                                       required time                          9.542    
                                       arrival time                          -7.552    
  ---------------------------------------------------------------------------------
                                       slack                                  1.990    

Slack (MET) :             1.990ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_1/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_bin_r_reg[5]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            3.906ns  (clk_out1_d_1_clk_adc0_x2_0 rise@3.906ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        1.721ns  (logic 0.076ns (4.416%)  route 1.645ns (95.584%))
  Logic Levels:           0  
  Clock Path Skew:        -0.070ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.925ns = ( 9.831 - 3.906 ) 
    Source Clock Delay      (SCD):    5.831ns
    Clock Pessimism Removal (CPR):    -0.164ns
  Clock Uncertainty:      0.059ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.095ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.742ns (routing 1.754ns, distribution 0.988ns)
  Clock Net Delay (Destination): 2.507ns (routing 1.589ns, distribution 0.918ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.416     2.943    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                   -0.127     2.816 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.245     3.061    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.028     3.089 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.742     5.831    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
                  SLICE_X72Y168        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_1/C
  ---------------------------------------------------------------------------------    -------------------
    Placement     SLICE_X72Y168        FDRE (Prop_EFF_SLICEM_C_Q)
                                                                    0.076     5.907 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_1/Q
                                       net (fo=176, routed)         1.645     7.552    d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/peripheral_aresetn[0]_repN_1_alias
    Placement     SLICE_X64Y252        FDCE                                         f  d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_bin_r_reg[5]/CLR  (IS_INVERTED)
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    3.906     3.906 r  
                  HSADC_X0Y1           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.162     6.454    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                    0.630     7.084 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.216     7.300    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.024     7.324 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.507     9.831    d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/adc_clk
                  SLICE_X64Y252        FDCE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_bin_r_reg[5]/C
                                       clock pessimism             -0.164     9.667    
                                       clock uncertainty           -0.059     9.608    
                  SLICE_X64Y252        FDCE (Recov_CFF_SLICEL_C_CLR)
                                                                   -0.066     9.542    d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_bin_r_reg[5]
  ---------------------------------------------------------------------------------
                                       required time                          9.542    
                                       arrival time                          -7.552    
  ---------------------------------------------------------------------------------
                                       slack                                  1.990    

Slack (MET) :             1.990ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_1/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_gray_r_reg[4]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            3.906ns  (clk_out1_d_1_clk_adc0_x2_0 rise@3.906ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        1.721ns  (logic 0.076ns (4.416%)  route 1.645ns (95.584%))
  Logic Levels:           0  
  Clock Path Skew:        -0.070ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.925ns = ( 9.831 - 3.906 ) 
    Source Clock Delay      (SCD):    5.831ns
    Clock Pessimism Removal (CPR):    -0.164ns
  Clock Uncertainty:      0.059ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.095ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.742ns (routing 1.754ns, distribution 0.988ns)
  Clock Net Delay (Destination): 2.507ns (routing 1.589ns, distribution 0.918ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.416     2.943    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                   -0.127     2.816 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.245     3.061    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.028     3.089 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.742     5.831    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
                  SLICE_X72Y168        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_1/C
  ---------------------------------------------------------------------------------    -------------------
    Placement     SLICE_X72Y168        FDRE (Prop_EFF_SLICEM_C_Q)
                                                                    0.076     5.907 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_1/Q
                                       net (fo=176, routed)         1.645     7.552    d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/peripheral_aresetn[0]_repN_1_alias
    Placement     SLICE_X64Y252        FDCE                                         f  d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_gray_r_reg[4]/CLR  (IS_INVERTED)
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    3.906     3.906 r  
                  HSADC_X0Y1           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.162     6.454    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                    0.630     7.084 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.216     7.300    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.024     7.324 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.507     9.831    d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/adc_clk
                  SLICE_X64Y252        FDCE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_gray_r_reg[4]/C
                                       clock pessimism             -0.164     9.667    
                                       clock uncertainty           -0.059     9.608    
                  SLICE_X64Y252        FDCE (Recov_CFF2_SLICEL_C_CLR)
                                                                   -0.066     9.542    d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_gray_r_reg[4]
  ---------------------------------------------------------------------------------
                                       required time                          9.542    
                                       arrival time                          -7.552    
  ---------------------------------------------------------------------------------
                                       slack                                  1.990    

Slack (MET) :             2.044ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_1/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_bin_2r_reg[6]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            3.906ns  (clk_out1_d_1_clk_adc0_x2_0 rise@3.906ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        1.667ns  (logic 0.076ns (4.560%)  route 1.591ns (95.440%))
  Logic Levels:           0  
  Clock Path Skew:        -0.069ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.926ns = ( 9.832 - 3.906 ) 
    Source Clock Delay      (SCD):    5.831ns
    Clock Pessimism Removal (CPR):    -0.164ns
  Clock Uncertainty:      0.059ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.095ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.742ns (routing 1.754ns, distribution 0.988ns)
  Clock Net Delay (Destination): 2.508ns (routing 1.589ns, distribution 0.919ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.416     2.943    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                   -0.127     2.816 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.245     3.061    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.028     3.089 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.742     5.831    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
                  SLICE_X72Y168        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_1/C
  ---------------------------------------------------------------------------------    -------------------
    Placement     SLICE_X72Y168        FDRE (Prop_EFF_SLICEM_C_Q)
                                                                    0.076     5.907 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_1/Q
                                       net (fo=176, routed)         1.591     7.498    d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/peripheral_aresetn[0]_repN_1_alias
    Placement     SLICE_X65Y255        FDCE                                         f  d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_bin_2r_reg[6]/CLR  (IS_INVERTED)
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    3.906     3.906 r  
                  HSADC_X0Y1           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.162     6.454    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                    0.630     7.084 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.216     7.300    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.024     7.324 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.508     9.832    d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/adc_clk
                  SLICE_X65Y255        FDCE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_bin_2r_reg[6]/C
                                       clock pessimism             -0.164     9.668    
                                       clock uncertainty           -0.059     9.608    
                  SLICE_X65Y255        FDCE (Recov_DFF_SLICEL_C_CLR)
                                                                   -0.066     9.542    d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_bin_2r_reg[6]
  ---------------------------------------------------------------------------------
                                       required time                          9.542    
                                       arrival time                          -7.498    
  ---------------------------------------------------------------------------------
                                       slack                                  2.044    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.147ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_4/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/gcc_wr_ptr/count_bin_r_reg[0]/PRE
                            (removal check against rising-edge clock clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.138ns  (logic 0.038ns (27.482%)  route 0.100ns (72.518%))
  Logic Levels:           0  
  Clock Path Skew:        0.011ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.535ns
    Source Clock Delay      (SCD):    3.577ns
    Clock Pessimism Removal (CPR):    -0.053ns
  Clock Net Delay (Source):      1.589ns (routing 0.960ns, distribution 0.629ns)
  Clock Net Delay (Destination): 1.786ns (routing 1.079ns, distribution 0.707ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           1.332     1.595    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                    0.230     1.825 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.146     1.971    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.017     1.988 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        1.589     3.577    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
                  SLICE_X87Y137        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_4/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X87Y137        FDRE (Prop_EFF_SLICEM_C_Q)
                                                                    0.038     3.615 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_4/Q
                                       net (fo=61, routed)          0.100     3.715    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/gcc_wr_ptr/peripheral_aresetn[0]_repN_4_alias
    Routing       SLICE_X88Y138        FDPE                                         f  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/gcc_wr_ptr/count_bin_r_reg[0]/PRE  (IS_INVERTED)
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           1.507     1.859    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                   -0.295     1.564 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.166     1.730    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.019     1.749 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        1.786     3.535    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/gcc_wr_ptr/adc_clk
                  SLICE_X88Y138        FDPE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/gcc_wr_ptr/count_bin_r_reg[0]/C
                                       clock pessimism              0.053     3.588    
                  SLICE_X88Y138        FDPE (Remov_DFF_SLICEL_C_PRE)
                                                                   -0.020     3.568    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/gcc_wr_ptr/count_bin_r_reg[0]
  ---------------------------------------------------------------------------------
                                       required time                         -3.568    
                                       arrival time                           3.715    
  ---------------------------------------------------------------------------------
                                       slack                                  0.147    

Slack (MET) :             0.147ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_4/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/gcc_wr_ptr/count_bin_r_reg[2]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.138ns  (logic 0.038ns (27.482%)  route 0.100ns (72.518%))
  Logic Levels:           0  
  Clock Path Skew:        0.011ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.535ns
    Source Clock Delay      (SCD):    3.577ns
    Clock Pessimism Removal (CPR):    -0.053ns
  Clock Net Delay (Source):      1.589ns (routing 0.960ns, distribution 0.629ns)
  Clock Net Delay (Destination): 1.786ns (routing 1.079ns, distribution 0.707ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           1.332     1.595    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                    0.230     1.825 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.146     1.971    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.017     1.988 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        1.589     3.577    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
                  SLICE_X87Y137        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_4/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X87Y137        FDRE (Prop_EFF_SLICEM_C_Q)
                                                                    0.038     3.615 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_4/Q
                                       net (fo=61, routed)          0.100     3.715    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/gcc_wr_ptr/peripheral_aresetn[0]_repN_4_alias
    Routing       SLICE_X88Y138        FDCE                                         f  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/gcc_wr_ptr/count_bin_r_reg[2]/CLR  (IS_INVERTED)
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           1.507     1.859    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                   -0.295     1.564 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.166     1.730    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.019     1.749 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        1.786     3.535    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/gcc_wr_ptr/adc_clk
                  SLICE_X88Y138        FDCE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/gcc_wr_ptr/count_bin_r_reg[2]/C
                                       clock pessimism              0.053     3.588    
                  SLICE_X88Y138        FDCE (Remov_CFF_SLICEL_C_CLR)
                                                                   -0.020     3.568    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/gcc_wr_ptr/count_bin_r_reg[2]
  ---------------------------------------------------------------------------------
                                       required time                         -3.568    
                                       arrival time                           3.715    
  ---------------------------------------------------------------------------------
                                       slack                                  0.147    

Slack (MET) :             0.147ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_4/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/gcc_wr_ptr/count_bin_r_reg[4]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.138ns  (logic 0.038ns (27.482%)  route 0.100ns (72.518%))
  Logic Levels:           0  
  Clock Path Skew:        0.011ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.535ns
    Source Clock Delay      (SCD):    3.577ns
    Clock Pessimism Removal (CPR):    -0.053ns
  Clock Net Delay (Source):      1.589ns (routing 0.960ns, distribution 0.629ns)
  Clock Net Delay (Destination): 1.786ns (routing 1.079ns, distribution 0.707ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           1.332     1.595    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                    0.230     1.825 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.146     1.971    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.017     1.988 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        1.589     3.577    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
                  SLICE_X87Y137        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_4/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X87Y137        FDRE (Prop_EFF_SLICEM_C_Q)
                                                                    0.038     3.615 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_4/Q
                                       net (fo=61, routed)          0.100     3.715    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/gcc_wr_ptr/peripheral_aresetn[0]_repN_4_alias
    Routing       SLICE_X88Y138        FDCE                                         f  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/gcc_wr_ptr/count_bin_r_reg[4]/CLR  (IS_INVERTED)
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           1.507     1.859    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                   -0.295     1.564 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.166     1.730    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.019     1.749 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        1.786     3.535    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/gcc_wr_ptr/adc_clk
                  SLICE_X88Y138        FDCE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/gcc_wr_ptr/count_bin_r_reg[4]/C
                                       clock pessimism              0.053     3.588    
                  SLICE_X88Y138        FDCE (Remov_BFF_SLICEL_C_CLR)
                                                                   -0.020     3.568    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/gcc_wr_ptr/count_bin_r_reg[4]
  ---------------------------------------------------------------------------------
                                       required time                         -3.568    
                                       arrival time                           3.715    
  ---------------------------------------------------------------------------------
                                       slack                                  0.147    

Slack (MET) :             0.147ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_4/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/gcc_wr_ptr/count_gray_r_reg[0]/PRE
                            (removal check against rising-edge clock clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.138ns  (logic 0.038ns (27.482%)  route 0.100ns (72.518%))
  Logic Levels:           0  
  Clock Path Skew:        0.011ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.535ns
    Source Clock Delay      (SCD):    3.577ns
    Clock Pessimism Removal (CPR):    -0.053ns
  Clock Net Delay (Source):      1.589ns (routing 0.960ns, distribution 0.629ns)
  Clock Net Delay (Destination): 1.786ns (routing 1.079ns, distribution 0.707ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           1.332     1.595    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                    0.230     1.825 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.146     1.971    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.017     1.988 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        1.589     3.577    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
                  SLICE_X87Y137        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_4/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X87Y137        FDRE (Prop_EFF_SLICEM_C_Q)
                                                                    0.038     3.615 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_4/Q
                                       net (fo=61, routed)          0.100     3.715    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/gcc_wr_ptr/peripheral_aresetn[0]_repN_4_alias
    Routing       SLICE_X88Y138        FDPE                                         f  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/gcc_wr_ptr/count_gray_r_reg[0]/PRE  (IS_INVERTED)
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           1.507     1.859    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                   -0.295     1.564 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.166     1.730    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.019     1.749 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        1.786     3.535    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/gcc_wr_ptr/adc_clk
                  SLICE_X88Y138        FDPE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/gcc_wr_ptr/count_gray_r_reg[0]/C
                                       clock pessimism              0.053     3.588    
                  SLICE_X88Y138        FDPE (Remov_DFF2_SLICEL_C_PRE)
                                                                   -0.020     3.568    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/gcc_wr_ptr/count_gray_r_reg[0]
  ---------------------------------------------------------------------------------
                                       required time                         -3.568    
                                       arrival time                           3.715    
  ---------------------------------------------------------------------------------
                                       slack                                  0.147    

Slack (MET) :             0.147ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_4/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/gcc_wr_ptr/count_gray_r_reg[1]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.138ns  (logic 0.038ns (27.482%)  route 0.100ns (72.518%))
  Logic Levels:           0  
  Clock Path Skew:        0.011ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.535ns
    Source Clock Delay      (SCD):    3.577ns
    Clock Pessimism Removal (CPR):    -0.053ns
  Clock Net Delay (Source):      1.589ns (routing 0.960ns, distribution 0.629ns)
  Clock Net Delay (Destination): 1.786ns (routing 1.079ns, distribution 0.707ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           1.332     1.595    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                    0.230     1.825 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.146     1.971    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.017     1.988 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        1.589     3.577    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
                  SLICE_X87Y137        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_4/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X87Y137        FDRE (Prop_EFF_SLICEM_C_Q)
                                                                    0.038     3.615 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_4/Q
                                       net (fo=61, routed)          0.100     3.715    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/gcc_wr_ptr/peripheral_aresetn[0]_repN_4_alias
    Routing       SLICE_X88Y138        FDCE                                         f  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/gcc_wr_ptr/count_gray_r_reg[1]/CLR  (IS_INVERTED)
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           1.507     1.859    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                   -0.295     1.564 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.166     1.730    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.019     1.749 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        1.786     3.535    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/gcc_wr_ptr/adc_clk
                  SLICE_X88Y138        FDCE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/gcc_wr_ptr/count_gray_r_reg[1]/C
                                       clock pessimism              0.053     3.588    
                  SLICE_X88Y138        FDCE (Remov_CFF2_SLICEL_C_CLR)
                                                                   -0.020     3.568    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/gcc_wr_ptr/count_gray_r_reg[1]
  ---------------------------------------------------------------------------------
                                       required time                         -3.568    
                                       arrival time                           3.715    
  ---------------------------------------------------------------------------------
                                       slack                                  0.147    

Slack (MET) :             0.147ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_4/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/gcc_wr_ptr/count_gray_r_reg[3]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.138ns  (logic 0.038ns (27.482%)  route 0.100ns (72.518%))
  Logic Levels:           0  
  Clock Path Skew:        0.011ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.535ns
    Source Clock Delay      (SCD):    3.577ns
    Clock Pessimism Removal (CPR):    -0.053ns
  Clock Net Delay (Source):      1.589ns (routing 0.960ns, distribution 0.629ns)
  Clock Net Delay (Destination): 1.786ns (routing 1.079ns, distribution 0.707ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           1.332     1.595    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                    0.230     1.825 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.146     1.971    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.017     1.988 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        1.589     3.577    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
                  SLICE_X87Y137        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_4/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X87Y137        FDRE (Prop_EFF_SLICEM_C_Q)
                                                                    0.038     3.615 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_4/Q
                                       net (fo=61, routed)          0.100     3.715    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/gcc_wr_ptr/peripheral_aresetn[0]_repN_4_alias
    Routing       SLICE_X88Y138        FDCE                                         f  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/gcc_wr_ptr/count_gray_r_reg[3]/CLR  (IS_INVERTED)
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           1.507     1.859    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                   -0.295     1.564 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.166     1.730    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.019     1.749 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        1.786     3.535    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/gcc_wr_ptr/adc_clk
                  SLICE_X88Y138        FDCE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/gcc_wr_ptr/count_gray_r_reg[3]/C
                                       clock pessimism              0.053     3.588    
                  SLICE_X88Y138        FDCE (Remov_AFF_SLICEL_C_CLR)
                                                                   -0.020     3.568    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/gcc_wr_ptr/count_gray_r_reg[3]
  ---------------------------------------------------------------------------------
                                       required time                         -3.568    
                                       arrival time                           3.715    
  ---------------------------------------------------------------------------------
                                       slack                                  0.147    

Slack (MET) :             0.160ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_3/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/gcc_wr_ptr/count_gray_2r_reg[4]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.157ns  (logic 0.037ns (23.593%)  route 0.120ns (76.407%))
  Logic Levels:           0  
  Clock Path Skew:        0.017ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.551ns
    Source Clock Delay      (SCD):    3.586ns
    Clock Pessimism Removal (CPR):    -0.051ns
  Clock Net Delay (Source):      1.598ns (routing 0.960ns, distribution 0.638ns)
  Clock Net Delay (Destination): 1.802ns (routing 1.079ns, distribution 0.723ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           1.332     1.595    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                    0.230     1.825 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.146     1.971    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.017     1.988 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        1.598     3.586    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
                  SLICE_X83Y105        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_3/C
  ---------------------------------------------------------------------------------    -------------------
    Placement     SLICE_X83Y105        FDRE (Prop_FFF_SLICEM_C_Q)
                                                                    0.037     3.623 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_3/Q
                                       net (fo=150, routed)         0.120     3.743    d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/gcc_wr_ptr/peripheral_aresetn[0]_repN_3_alias
    Placement     SLICE_X84Y104        FDCE                                         f  d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/gcc_wr_ptr/count_gray_2r_reg[4]/CLR  (IS_INVERTED)
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           1.507     1.859    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                   -0.295     1.564 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.166     1.730    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.019     1.749 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        1.802     3.551    d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/gcc_wr_ptr/adc_clk
                  SLICE_X84Y104        FDCE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/gcc_wr_ptr/count_gray_2r_reg[4]/C
                                       clock pessimism              0.051     3.603    
                  SLICE_X84Y104        FDCE (Remov_BFF_SLICEL_C_CLR)
                                                                   -0.020     3.583    d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/gcc_wr_ptr/count_gray_2r_reg[4]
  ---------------------------------------------------------------------------------
                                       required time                         -3.583    
                                       arrival time                           3.743    
  ---------------------------------------------------------------------------------
                                       slack                                  0.160    

Slack (MET) :             0.160ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_3/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/gcc_wr_ptr/count_gray_2r_reg[5]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.157ns  (logic 0.037ns (23.593%)  route 0.120ns (76.407%))
  Logic Levels:           0  
  Clock Path Skew:        0.017ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.551ns
    Source Clock Delay      (SCD):    3.586ns
    Clock Pessimism Removal (CPR):    -0.051ns
  Clock Net Delay (Source):      1.598ns (routing 0.960ns, distribution 0.638ns)
  Clock Net Delay (Destination): 1.802ns (routing 1.079ns, distribution 0.723ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           1.332     1.595    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                    0.230     1.825 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.146     1.971    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.017     1.988 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        1.598     3.586    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
                  SLICE_X83Y105        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_3/C
  ---------------------------------------------------------------------------------    -------------------
    Placement     SLICE_X83Y105        FDRE (Prop_FFF_SLICEM_C_Q)
                                                                    0.037     3.623 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_3/Q
                                       net (fo=150, routed)         0.120     3.743    d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/gcc_wr_ptr/peripheral_aresetn[0]_repN_3_alias
    Placement     SLICE_X84Y104        FDCE                                         f  d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/gcc_wr_ptr/count_gray_2r_reg[5]/CLR  (IS_INVERTED)
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           1.507     1.859    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                   -0.295     1.564 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.166     1.730    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.019     1.749 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        1.802     3.551    d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/gcc_wr_ptr/adc_clk
                  SLICE_X84Y104        FDCE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/gcc_wr_ptr/count_gray_2r_reg[5]/C
                                       clock pessimism              0.051     3.603    
                  SLICE_X84Y104        FDCE (Remov_BFF2_SLICEL_C_CLR)
                                                                   -0.020     3.583    d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/gcc_wr_ptr/count_gray_2r_reg[5]
  ---------------------------------------------------------------------------------
                                       required time                         -3.583    
                                       arrival time                           3.743    
  ---------------------------------------------------------------------------------
                                       slack                                  0.160    

Slack (MET) :             0.160ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_3/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/gcc_wr_ptr/count_gray_r_reg[3]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.157ns  (logic 0.037ns (23.593%)  route 0.120ns (76.407%))
  Logic Levels:           0  
  Clock Path Skew:        0.017ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.551ns
    Source Clock Delay      (SCD):    3.586ns
    Clock Pessimism Removal (CPR):    -0.051ns
  Clock Net Delay (Source):      1.598ns (routing 0.960ns, distribution 0.638ns)
  Clock Net Delay (Destination): 1.802ns (routing 1.079ns, distribution 0.723ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           1.332     1.595    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                    0.230     1.825 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.146     1.971    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.017     1.988 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        1.598     3.586    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
                  SLICE_X83Y105        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_3/C
  ---------------------------------------------------------------------------------    -------------------
    Placement     SLICE_X83Y105        FDRE (Prop_FFF_SLICEM_C_Q)
                                                                    0.037     3.623 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_3/Q
                                       net (fo=150, routed)         0.120     3.743    d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/gcc_wr_ptr/peripheral_aresetn[0]_repN_3_alias
    Placement     SLICE_X84Y104        FDCE                                         f  d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/gcc_wr_ptr/count_gray_r_reg[3]/CLR  (IS_INVERTED)
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           1.507     1.859    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                   -0.295     1.564 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.166     1.730    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.019     1.749 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        1.802     3.551    d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/gcc_wr_ptr/adc_clk
                  SLICE_X84Y104        FDCE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/gcc_wr_ptr/count_gray_r_reg[3]/C
                                       clock pessimism              0.051     3.603    
                  SLICE_X84Y104        FDCE (Remov_AFF_SLICEL_C_CLR)
                                                                   -0.020     3.583    d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/gcc_wr_ptr/count_gray_r_reg[3]
  ---------------------------------------------------------------------------------
                                       required time                         -3.583    
                                       arrival time                           3.743    
  ---------------------------------------------------------------------------------
                                       slack                                  0.160    

Slack (MET) :             0.162ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_4/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/gcc_wr_ptr/count_gray_2r_reg[1]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.162ns  (logic 0.038ns (23.454%)  route 0.124ns (76.546%))
  Logic Levels:           0  
  Clock Path Skew:        0.020ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.543ns
    Source Clock Delay      (SCD):    3.577ns
    Clock Pessimism Removal (CPR):    -0.053ns
  Clock Net Delay (Source):      1.589ns (routing 0.960ns, distribution 0.629ns)
  Clock Net Delay (Destination): 1.794ns (routing 1.079ns, distribution 0.715ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           1.332     1.595    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                    0.230     1.825 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.146     1.971    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.017     1.988 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        1.589     3.577    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
                  SLICE_X87Y137        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_4/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X87Y137        FDRE (Prop_EFF_SLICEM_C_Q)
                                                                    0.038     3.615 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_4/Q
                                       net (fo=61, routed)          0.124     3.739    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/gcc_wr_ptr/peripheral_aresetn[0]_repN_4_alias
    Moved         SLICE_X88Y139        FDCE                                         f  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/gcc_wr_ptr/count_gray_2r_reg[1]/CLR  (IS_INVERTED)
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           1.507     1.859    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                   -0.295     1.564 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.166     1.730    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.019     1.749 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        1.794     3.543    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/gcc_wr_ptr/adc_clk
                  SLICE_X88Y139        FDCE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/gcc_wr_ptr/count_gray_2r_reg[1]/C
                                       clock pessimism              0.053     3.596    
                  SLICE_X88Y139        FDCE (Remov_GFF2_SLICEL_C_CLR)
                                                                   -0.020     3.576    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/gcc_wr_ptr/count_gray_2r_reg[1]
  ---------------------------------------------------------------------------------
                                       required time                         -3.576    
                                       arrival time                           3.739    
  ---------------------------------------------------------------------------------
                                       slack                                  0.162    





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  clk_pl_0
  To Clock:  clk_pl_0

Setup :            0  Failing Endpoints,  Worst Slack        0.614ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.230ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.614ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[10]_rep__49/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        8.978ns  (logic 0.081ns (0.902%)  route 8.897ns (99.098%))
  Logic Levels:           0  
  Clock Path Skew:        -0.212ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.269ns = ( 12.269 - 10.000 ) 
    Source Clock Delay      (SCD):    2.602ns
    Clock Pessimism Removal (CPR):    0.121ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.376ns (routing 0.763ns, distribution 1.613ns)
  Clock Net Delay (Destination): 2.087ns (routing 0.690ns, distribution 1.397ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.376     2.602    d_1_i/rst_100/U0/slowest_sync_clk
                  SLICE_X85Y80         FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
  ---------------------------------------------------------------------------------    -------------------
    Placement     SLICE_X85Y80         FDRE (Prop_AFF2_SLICEL_C_Q)
                                                                    0.081     2.683 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/Q
                                       net (fo=5138, routed)        8.897    11.580    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/peripheral_aresetn[0]_bufg_place_replica
    New           SLICE_X85Y215        FDCE                                         f  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[10]_rep__49/CLR  (IS_INVERTED)
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                   10.000    10.000 r  
                  PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.087    12.269    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/ps_clk
                  SLICE_X85Y215        FDCE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[10]_rep__49/C
                                       clock pessimism              0.121    12.390    
                                       clock uncertainty           -0.130    12.260    
                  SLICE_X85Y215        FDCE (Recov_AFF_SLICEL_C_CLR)
                                                                   -0.066    12.194    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[10]_rep__49
  ---------------------------------------------------------------------------------
                                       required time                         12.194    
                                       arrival time                         -11.580    
  ---------------------------------------------------------------------------------
                                       slack                                  0.614    

Slack (MET) :             0.614ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[6]_rep__18/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        8.978ns  (logic 0.081ns (0.902%)  route 8.897ns (99.098%))
  Logic Levels:           0  
  Clock Path Skew:        -0.212ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.269ns = ( 12.269 - 10.000 ) 
    Source Clock Delay      (SCD):    2.602ns
    Clock Pessimism Removal (CPR):    0.121ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.376ns (routing 0.763ns, distribution 1.613ns)
  Clock Net Delay (Destination): 2.087ns (routing 0.690ns, distribution 1.397ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.376     2.602    d_1_i/rst_100/U0/slowest_sync_clk
                  SLICE_X85Y80         FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
  ---------------------------------------------------------------------------------    -------------------
    Placement     SLICE_X85Y80         FDRE (Prop_AFF2_SLICEL_C_Q)
                                                                    0.081     2.683 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/Q
                                       net (fo=5138, routed)        8.897    11.580    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/peripheral_aresetn[0]_bufg_place_replica
    New           SLICE_X85Y215        FDCE                                         f  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[6]_rep__18/CLR  (IS_INVERTED)
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                   10.000    10.000 r  
                  PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.087    12.269    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/ps_clk
                  SLICE_X85Y215        FDCE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[6]_rep__18/C
                                       clock pessimism              0.121    12.390    
                                       clock uncertainty           -0.130    12.260    
                  SLICE_X85Y215        FDCE (Recov_AFF2_SLICEL_C_CLR)
                                                                   -0.066    12.194    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[6]_rep__18
  ---------------------------------------------------------------------------------
                                       required time                         12.194    
                                       arrival time                         -11.580    
  ---------------------------------------------------------------------------------
                                       slack                                  0.614    

Slack (MET) :             0.614ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[9]_rep__49/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        8.978ns  (logic 0.081ns (0.902%)  route 8.897ns (99.098%))
  Logic Levels:           0  
  Clock Path Skew:        -0.212ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.269ns = ( 12.269 - 10.000 ) 
    Source Clock Delay      (SCD):    2.602ns
    Clock Pessimism Removal (CPR):    0.121ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.376ns (routing 0.763ns, distribution 1.613ns)
  Clock Net Delay (Destination): 2.087ns (routing 0.690ns, distribution 1.397ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.376     2.602    d_1_i/rst_100/U0/slowest_sync_clk
                  SLICE_X85Y80         FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
  ---------------------------------------------------------------------------------    -------------------
    Placement     SLICE_X85Y80         FDRE (Prop_AFF2_SLICEL_C_Q)
                                                                    0.081     2.683 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/Q
                                       net (fo=5138, routed)        8.897    11.580    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/peripheral_aresetn[0]_bufg_place_replica
    New           SLICE_X85Y215        FDCE                                         f  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[9]_rep__49/CLR  (IS_INVERTED)
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                   10.000    10.000 r  
                  PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.087    12.269    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/ps_clk
                  SLICE_X85Y215        FDCE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[9]_rep__49/C
                                       clock pessimism              0.121    12.390    
                                       clock uncertainty           -0.130    12.260    
                  SLICE_X85Y215        FDCE (Recov_BFF_SLICEL_C_CLR)
                                                                   -0.066    12.194    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[9]_rep__49
  ---------------------------------------------------------------------------------
                                       required time                         12.194    
                                       arrival time                         -11.580    
  ---------------------------------------------------------------------------------
                                       slack                                  0.614    

Slack (MET) :             0.651ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[10]_rep__150/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        8.812ns  (logic 0.081ns (0.919%)  route 8.731ns (99.081%))
  Logic Levels:           0  
  Clock Path Skew:        -0.341ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.140ns = ( 12.140 - 10.000 ) 
    Source Clock Delay      (SCD):    2.602ns
    Clock Pessimism Removal (CPR):    0.121ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.376ns (routing 0.763ns, distribution 1.613ns)
  Clock Net Delay (Destination): 1.958ns (routing 0.690ns, distribution 1.268ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.376     2.602    d_1_i/rst_100/U0/slowest_sync_clk
                  SLICE_X85Y80         FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
  ---------------------------------------------------------------------------------    -------------------
    Placement     SLICE_X85Y80         FDRE (Prop_AFF2_SLICEL_C_Q)
                                                                    0.081     2.683 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/Q
                                       net (fo=5138, routed)        8.731    11.414    d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/peripheral_aresetn[0]_bufg_place_replica
    New           SLICE_X67Y215        FDCE                                         f  d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[10]_rep__150/CLR  (IS_INVERTED)
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                   10.000    10.000 r  
                  PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.958    12.140    d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/ps_clk
                  SLICE_X67Y215        FDCE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[10]_rep__150/C
                                       clock pessimism              0.121    12.261    
                                       clock uncertainty           -0.130    12.131    
                  SLICE_X67Y215        FDCE (Recov_EFF_SLICEM_C_CLR)
                                                                   -0.066    12.065    d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[10]_rep__150
  ---------------------------------------------------------------------------------
                                       required time                         12.065    
                                       arrival time                         -11.414    
  ---------------------------------------------------------------------------------
                                       slack                                  0.651    

Slack (MET) :             0.651ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[12]_rep__91/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        8.812ns  (logic 0.081ns (0.919%)  route 8.731ns (99.081%))
  Logic Levels:           0  
  Clock Path Skew:        -0.341ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.140ns = ( 12.140 - 10.000 ) 
    Source Clock Delay      (SCD):    2.602ns
    Clock Pessimism Removal (CPR):    0.121ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.376ns (routing 0.763ns, distribution 1.613ns)
  Clock Net Delay (Destination): 1.958ns (routing 0.690ns, distribution 1.268ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.376     2.602    d_1_i/rst_100/U0/slowest_sync_clk
                  SLICE_X85Y80         FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
  ---------------------------------------------------------------------------------    -------------------
    Placement     SLICE_X85Y80         FDRE (Prop_AFF2_SLICEL_C_Q)
                                                                    0.081     2.683 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/Q
                                       net (fo=5138, routed)        8.731    11.414    d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/peripheral_aresetn[0]_bufg_place_replica
    New           SLICE_X67Y215        FDCE                                         f  d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[12]_rep__91/CLR  (IS_INVERTED)
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                   10.000    10.000 r  
                  PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.958    12.140    d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/ps_clk
                  SLICE_X67Y215        FDCE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[12]_rep__91/C
                                       clock pessimism              0.121    12.261    
                                       clock uncertainty           -0.130    12.131    
                  SLICE_X67Y215        FDCE (Recov_EFF2_SLICEM_C_CLR)
                                                                   -0.066    12.065    d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[12]_rep__91
  ---------------------------------------------------------------------------------
                                       required time                         12.065    
                                       arrival time                         -11.414    
  ---------------------------------------------------------------------------------
                                       slack                                  0.651    

Slack (MET) :             0.658ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[10]_rep__56/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        8.933ns  (logic 0.081ns (0.907%)  route 8.852ns (99.093%))
  Logic Levels:           0  
  Clock Path Skew:        -0.213ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.268ns = ( 12.268 - 10.000 ) 
    Source Clock Delay      (SCD):    2.602ns
    Clock Pessimism Removal (CPR):    0.121ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.376ns (routing 0.763ns, distribution 1.613ns)
  Clock Net Delay (Destination): 2.086ns (routing 0.690ns, distribution 1.396ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.376     2.602    d_1_i/rst_100/U0/slowest_sync_clk
                  SLICE_X85Y80         FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
  ---------------------------------------------------------------------------------    -------------------
    Placement     SLICE_X85Y80         FDRE (Prop_AFF2_SLICEL_C_Q)
                                                                    0.081     2.683 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/Q
                                       net (fo=5138, routed)        8.852    11.535    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/peripheral_aresetn[0]_bufg_place_replica
    New           SLICE_X85Y214        FDCE                                         f  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[10]_rep__56/CLR  (IS_INVERTED)
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                   10.000    10.000 r  
                  PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.086    12.268    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/ps_clk
                  SLICE_X85Y214        FDCE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[10]_rep__56/C
                                       clock pessimism              0.121    12.389    
                                       clock uncertainty           -0.130    12.259    
                  SLICE_X85Y214        FDCE (Recov_AFF_SLICEL_C_CLR)
                                                                   -0.066    12.193    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[10]_rep__56
  ---------------------------------------------------------------------------------
                                       required time                         12.193    
                                       arrival time                         -11.535    
  ---------------------------------------------------------------------------------
                                       slack                                  0.658    

Slack (MET) :             0.658ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[6]_rep__49/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        8.933ns  (logic 0.081ns (0.907%)  route 8.852ns (99.093%))
  Logic Levels:           0  
  Clock Path Skew:        -0.213ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.268ns = ( 12.268 - 10.000 ) 
    Source Clock Delay      (SCD):    2.602ns
    Clock Pessimism Removal (CPR):    0.121ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.376ns (routing 0.763ns, distribution 1.613ns)
  Clock Net Delay (Destination): 2.086ns (routing 0.690ns, distribution 1.396ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.376     2.602    d_1_i/rst_100/U0/slowest_sync_clk
                  SLICE_X85Y80         FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
  ---------------------------------------------------------------------------------    -------------------
    Placement     SLICE_X85Y80         FDRE (Prop_AFF2_SLICEL_C_Q)
                                                                    0.081     2.683 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/Q
                                       net (fo=5138, routed)        8.852    11.535    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/peripheral_aresetn[0]_bufg_place_replica
    New           SLICE_X85Y214        FDCE                                         f  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[6]_rep__49/CLR  (IS_INVERTED)
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                   10.000    10.000 r  
                  PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.086    12.268    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/ps_clk
                  SLICE_X85Y214        FDCE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[6]_rep__49/C
                                       clock pessimism              0.121    12.389    
                                       clock uncertainty           -0.130    12.259    
                  SLICE_X85Y214        FDCE (Recov_AFF2_SLICEL_C_CLR)
                                                                   -0.066    12.193    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[6]_rep__49
  ---------------------------------------------------------------------------------
                                       required time                         12.193    
                                       arrival time                         -11.535    
  ---------------------------------------------------------------------------------
                                       slack                                  0.658    

Slack (MET) :             0.658ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[9]_rep__56/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        8.933ns  (logic 0.081ns (0.907%)  route 8.852ns (99.093%))
  Logic Levels:           0  
  Clock Path Skew:        -0.213ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.268ns = ( 12.268 - 10.000 ) 
    Source Clock Delay      (SCD):    2.602ns
    Clock Pessimism Removal (CPR):    0.121ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.376ns (routing 0.763ns, distribution 1.613ns)
  Clock Net Delay (Destination): 2.086ns (routing 0.690ns, distribution 1.396ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.376     2.602    d_1_i/rst_100/U0/slowest_sync_clk
                  SLICE_X85Y80         FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
  ---------------------------------------------------------------------------------    -------------------
    Placement     SLICE_X85Y80         FDRE (Prop_AFF2_SLICEL_C_Q)
                                                                    0.081     2.683 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/Q
                                       net (fo=5138, routed)        8.852    11.535    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/peripheral_aresetn[0]_bufg_place_replica
    New           SLICE_X85Y214        FDCE                                         f  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[9]_rep__56/CLR  (IS_INVERTED)
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                   10.000    10.000 r  
                  PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.086    12.268    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/ps_clk
                  SLICE_X85Y214        FDCE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[9]_rep__56/C
                                       clock pessimism              0.121    12.389    
                                       clock uncertainty           -0.130    12.259    
                  SLICE_X85Y214        FDCE (Recov_BFF_SLICEL_C_CLR)
                                                                   -0.066    12.193    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[9]_rep__56
  ---------------------------------------------------------------------------------
                                       required time                         12.193    
                                       arrival time                         -11.535    
  ---------------------------------------------------------------------------------
                                       slack                                  0.658    

Slack (MET) :             0.663ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[10]_rep__134/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        8.799ns  (logic 0.081ns (0.921%)  route 8.718ns (99.079%))
  Logic Levels:           0  
  Clock Path Skew:        -0.342ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.139ns = ( 12.139 - 10.000 ) 
    Source Clock Delay      (SCD):    2.602ns
    Clock Pessimism Removal (CPR):    0.121ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.376ns (routing 0.763ns, distribution 1.613ns)
  Clock Net Delay (Destination): 1.957ns (routing 0.690ns, distribution 1.267ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.376     2.602    d_1_i/rst_100/U0/slowest_sync_clk
                  SLICE_X85Y80         FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
  ---------------------------------------------------------------------------------    -------------------
    Placement     SLICE_X85Y80         FDRE (Prop_AFF2_SLICEL_C_Q)
                                                                    0.081     2.683 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/Q
                                       net (fo=5138, routed)        8.718    11.401    d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/peripheral_aresetn[0]_bufg_place_replica
    New           SLICE_X68Y215        FDCE                                         f  d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[10]_rep__134/CLR  (IS_INVERTED)
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                   10.000    10.000 r  
                  PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.957    12.139    d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/ps_clk
                  SLICE_X68Y215        FDCE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[10]_rep__134/C
                                       clock pessimism              0.121    12.260    
                                       clock uncertainty           -0.130    12.130    
                  SLICE_X68Y215        FDCE (Recov_EFF_SLICEL_C_CLR)
                                                                   -0.066    12.064    d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[10]_rep__134
  ---------------------------------------------------------------------------------
                                       required time                         12.064    
                                       arrival time                         -11.401    
  ---------------------------------------------------------------------------------
                                       slack                                  0.663    

Slack (MET) :             0.663ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[12]_rep__107/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        8.799ns  (logic 0.081ns (0.921%)  route 8.718ns (99.079%))
  Logic Levels:           0  
  Clock Path Skew:        -0.342ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.139ns = ( 12.139 - 10.000 ) 
    Source Clock Delay      (SCD):    2.602ns
    Clock Pessimism Removal (CPR):    0.121ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.376ns (routing 0.763ns, distribution 1.613ns)
  Clock Net Delay (Destination): 1.957ns (routing 0.690ns, distribution 1.267ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.376     2.602    d_1_i/rst_100/U0/slowest_sync_clk
                  SLICE_X85Y80         FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
  ---------------------------------------------------------------------------------    -------------------
    Placement     SLICE_X85Y80         FDRE (Prop_AFF2_SLICEL_C_Q)
                                                                    0.081     2.683 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/Q
                                       net (fo=5138, routed)        8.718    11.401    d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/peripheral_aresetn[0]_bufg_place_replica
    New           SLICE_X68Y215        FDCE                                         f  d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[12]_rep__107/CLR  (IS_INVERTED)
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                   10.000    10.000 r  
                  PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.957    12.139    d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/ps_clk
                  SLICE_X68Y215        FDCE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[12]_rep__107/C
                                       clock pessimism              0.121    12.260    
                                       clock uncertainty           -0.130    12.130    
                  SLICE_X68Y215        FDCE (Recov_EFF2_SLICEL_C_CLR)
                                                                   -0.066    12.064    d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[12]_rep__107
  ---------------------------------------------------------------------------------
                                       required time                         12.064    
                                       arrival time                         -11.401    
  ---------------------------------------------------------------------------------
                                       slack                                  0.663    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.230ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_o_i_reg/PRE
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.231ns  (logic 0.077ns (33.377%)  route 0.154ns (66.623%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.021ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.552ns
    Source Clock Delay      (SCD):    1.366ns
    Clock Pessimism Removal (CPR):    0.166ns
  Clock Net Delay (Source):      1.246ns (routing 0.414ns, distribution 0.832ns)
  Clock Net Delay (Destination): 1.405ns (routing 0.463ns, distribution 0.942ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.246     1.366    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
                  SLICE_X30Y70         FDRE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X30Y70         FDRE (Prop_FFF_SLICEM_C_Q)
                                                                    0.037     1.403 f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/Q
                                       net (fo=2, routed)           0.028     1.430    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[1]
    Routing       SLICE_X30Y70                                                      f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/I0
    Routing       SLICE_X30Y70         LUT3 (Prop_G6LUT_SLICEM_I0_O)
                                                                    0.040     1.470 f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                                       net (fo=32, routed)          0.126     1.596    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg_0
    Routing       SLICE_X30Y71         FDPE                                         f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_o_i_reg/PRE
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.405     1.552    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/clk
                  SLICE_X30Y71         FDPE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_o_i_reg/C
                                       clock pessimism             -0.166     1.387    
                  SLICE_X30Y71         FDPE (Remov_DFF2_SLICEM_C_PRE)
                                                                   -0.020     1.367    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_o_i_reg
  ---------------------------------------------------------------------------------
                                       required time                         -1.367    
                                       arrival time                           1.596    
  ---------------------------------------------------------------------------------
                                       slack                                  0.230    

Slack (MET) :             0.230ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[0]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.231ns  (logic 0.077ns (33.377%)  route 0.154ns (66.623%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.021ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.552ns
    Source Clock Delay      (SCD):    1.366ns
    Clock Pessimism Removal (CPR):    0.166ns
  Clock Net Delay (Source):      1.246ns (routing 0.414ns, distribution 0.832ns)
  Clock Net Delay (Destination): 1.405ns (routing 0.463ns, distribution 0.942ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.246     1.366    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
                  SLICE_X30Y70         FDRE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X30Y70         FDRE (Prop_FFF_SLICEM_C_Q)
                                                                    0.037     1.403 f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/Q
                                       net (fo=2, routed)           0.028     1.430    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[1]
    Routing       SLICE_X30Y70                                                      f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/I0
    Routing       SLICE_X30Y70         LUT3 (Prop_G6LUT_SLICEM_I0_O)
                                                                    0.040     1.470 f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                                       net (fo=32, routed)          0.126     1.596    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg_0
    Routing       SLICE_X30Y71         FDCE                                         f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[0]/CLR
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.405     1.552    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/clk
                  SLICE_X30Y71         FDCE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[0]/C
                                       clock pessimism             -0.166     1.387    
                  SLICE_X30Y71         FDCE (Remov_CFF_SLICEM_C_CLR)
                                                                   -0.020     1.367    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[0]
  ---------------------------------------------------------------------------------
                                       required time                         -1.367    
                                       arrival time                           1.596    
  ---------------------------------------------------------------------------------
                                       slack                                  0.230    

Slack (MET) :             0.230ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[1]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.231ns  (logic 0.077ns (33.377%)  route 0.154ns (66.623%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.021ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.552ns
    Source Clock Delay      (SCD):    1.366ns
    Clock Pessimism Removal (CPR):    0.166ns
  Clock Net Delay (Source):      1.246ns (routing 0.414ns, distribution 0.832ns)
  Clock Net Delay (Destination): 1.405ns (routing 0.463ns, distribution 0.942ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.246     1.366    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
                  SLICE_X30Y70         FDRE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X30Y70         FDRE (Prop_FFF_SLICEM_C_Q)
                                                                    0.037     1.403 f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/Q
                                       net (fo=2, routed)           0.028     1.430    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[1]
    Routing       SLICE_X30Y70                                                      f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/I0
    Routing       SLICE_X30Y70         LUT3 (Prop_G6LUT_SLICEM_I0_O)
                                                                    0.040     1.470 f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                                       net (fo=32, routed)          0.126     1.596    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg_0
    Routing       SLICE_X30Y71         FDCE                                         f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[1]/CLR
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.405     1.552    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/clk
                  SLICE_X30Y71         FDCE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[1]/C
                                       clock pessimism             -0.166     1.387    
                  SLICE_X30Y71         FDCE (Remov_CFF2_SLICEM_C_CLR)
                                                                   -0.020     1.367    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[1]
  ---------------------------------------------------------------------------------
                                       required time                         -1.367    
                                       arrival time                           1.596    
  ---------------------------------------------------------------------------------
                                       slack                                  0.230    

Slack (MET) :             0.230ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.231ns  (logic 0.077ns (33.377%)  route 0.154ns (66.623%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.021ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.552ns
    Source Clock Delay      (SCD):    1.366ns
    Clock Pessimism Removal (CPR):    0.166ns
  Clock Net Delay (Source):      1.246ns (routing 0.414ns, distribution 0.832ns)
  Clock Net Delay (Destination): 1.405ns (routing 0.463ns, distribution 0.942ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.246     1.366    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
                  SLICE_X30Y70         FDRE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X30Y70         FDRE (Prop_FFF_SLICEM_C_Q)
                                                                    0.037     1.403 f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/Q
                                       net (fo=2, routed)           0.028     1.430    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[1]
    Routing       SLICE_X30Y70                                                      f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/I0
    Routing       SLICE_X30Y70         LUT3 (Prop_G6LUT_SLICEM_I0_O)
                                                                    0.040     1.470 f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                                       net (fo=32, routed)          0.126     1.596    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg_0
    Routing       SLICE_X30Y71         FDCE                                         f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg/CLR
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.405     1.552    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/clk
                  SLICE_X30Y71         FDCE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg/C
                                       clock pessimism             -0.166     1.387    
                  SLICE_X30Y71         FDCE (Remov_BFF2_SLICEM_C_CLR)
                                                                   -0.020     1.367    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg
  ---------------------------------------------------------------------------------
                                       required time                         -1.367    
                                       arrival time                           1.596    
  ---------------------------------------------------------------------------------
                                       slack                                  0.230    

Slack (MET) :             0.230ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_fb_i_reg/PRE
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.230ns  (logic 0.077ns (33.522%)  route 0.153ns (66.478%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.020ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.551ns
    Source Clock Delay      (SCD):    1.366ns
    Clock Pessimism Removal (CPR):    0.166ns
  Clock Net Delay (Source):      1.246ns (routing 0.414ns, distribution 0.832ns)
  Clock Net Delay (Destination): 1.404ns (routing 0.463ns, distribution 0.941ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.246     1.366    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
                  SLICE_X30Y70         FDRE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X30Y70         FDRE (Prop_FFF_SLICEM_C_Q)
                                                                    0.037     1.403 f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/Q
                                       net (fo=2, routed)           0.028     1.430    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[1]
    Routing       SLICE_X30Y70                                                      f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/I0
    Routing       SLICE_X30Y70         LUT3 (Prop_G6LUT_SLICEM_I0_O)
                                                                    0.040     1.470 f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                                       net (fo=32, routed)          0.125     1.595    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg_0
    Routing       SLICE_X30Y71         FDPE                                         f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_fb_i_reg/PRE
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.404     1.551    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/clk
                  SLICE_X30Y71         FDPE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_fb_i_reg/C
                                       clock pessimism             -0.166     1.386    
                  SLICE_X30Y71         FDPE (Remov_EFF_SLICEM_C_PRE)
                                                                   -0.020     1.366    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_fb_i_reg
  ---------------------------------------------------------------------------------
                                       required time                         -1.366    
                                       arrival time                           1.595    
  ---------------------------------------------------------------------------------
                                       slack                                  0.230    

Slack (MET) :             0.230ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i_reg/PRE
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.230ns  (logic 0.077ns (33.522%)  route 0.153ns (66.478%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.020ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.551ns
    Source Clock Delay      (SCD):    1.366ns
    Clock Pessimism Removal (CPR):    0.166ns
  Clock Net Delay (Source):      1.246ns (routing 0.414ns, distribution 0.832ns)
  Clock Net Delay (Destination): 1.404ns (routing 0.463ns, distribution 0.941ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.246     1.366    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
                  SLICE_X30Y70         FDRE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X30Y70         FDRE (Prop_FFF_SLICEM_C_Q)
                                                                    0.037     1.403 f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/Q
                                       net (fo=2, routed)           0.028     1.430    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[1]
    Routing       SLICE_X30Y70                                                      f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/I0
    Routing       SLICE_X30Y70         LUT3 (Prop_G6LUT_SLICEM_I0_O)
                                                                    0.040     1.470 f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                                       net (fo=32, routed)          0.125     1.595    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg_0
    Routing       SLICE_X30Y71         FDPE                                         f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i_reg/PRE
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.404     1.551    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/clk
                  SLICE_X30Y71         FDPE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i_reg/C
                                       clock pessimism             -0.166     1.386    
                  SLICE_X30Y71         FDPE (Remov_EFF2_SLICEM_C_PRE)
                                                                   -0.020     1.366    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i_reg
  ---------------------------------------------------------------------------------
                                       required time                         -1.366    
                                       arrival time                           1.595    
  ---------------------------------------------------------------------------------
                                       slack                                  0.230    

Slack (MET) :             0.230ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_i_reg/PRE
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.230ns  (logic 0.077ns (33.522%)  route 0.153ns (66.478%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.020ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.551ns
    Source Clock Delay      (SCD):    1.366ns
    Clock Pessimism Removal (CPR):    0.166ns
  Clock Net Delay (Source):      1.246ns (routing 0.414ns, distribution 0.832ns)
  Clock Net Delay (Destination): 1.404ns (routing 0.463ns, distribution 0.941ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.246     1.366    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
                  SLICE_X30Y70         FDRE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X30Y70         FDRE (Prop_FFF_SLICEM_C_Q)
                                                                    0.037     1.403 f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/Q
                                       net (fo=2, routed)           0.028     1.430    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[1]
    Routing       SLICE_X30Y70                                                      f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/I0
    Routing       SLICE_X30Y70         LUT3 (Prop_G6LUT_SLICEM_I0_O)
                                                                    0.040     1.470 f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                                       net (fo=32, routed)          0.125     1.595    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg_0
    Routing       SLICE_X30Y71         FDPE                                         f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_i_reg/PRE
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.404     1.551    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/clk
                  SLICE_X30Y71         FDPE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_i_reg/C
                                       clock pessimism             -0.166     1.386    
                  SLICE_X30Y71         FDPE (Remov_FFF_SLICEM_C_PRE)
                                                                   -0.020     1.366    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_i_reg
  ---------------------------------------------------------------------------------
                                       required time                         -1.366    
                                       arrival time                           1.595    
  ---------------------------------------------------------------------------------
                                       slack                                  0.230    

Slack (MET) :             0.230ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg/PRE
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.230ns  (logic 0.077ns (33.522%)  route 0.153ns (66.478%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.020ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.551ns
    Source Clock Delay      (SCD):    1.366ns
    Clock Pessimism Removal (CPR):    0.166ns
  Clock Net Delay (Source):      1.246ns (routing 0.414ns, distribution 0.832ns)
  Clock Net Delay (Destination): 1.404ns (routing 0.463ns, distribution 0.941ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.246     1.366    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
                  SLICE_X30Y70         FDRE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X30Y70         FDRE (Prop_FFF_SLICEM_C_Q)
                                                                    0.037     1.403 f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/Q
                                       net (fo=2, routed)           0.028     1.430    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[1]
    Routing       SLICE_X30Y70                                                      f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/I0
    Routing       SLICE_X30Y70         LUT3 (Prop_G6LUT_SLICEM_I0_O)
                                                                    0.040     1.470 f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                                       net (fo=32, routed)          0.125     1.595    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg_0
    Routing       SLICE_X30Y71         FDPE                                         f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg/PRE
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.404     1.551    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/clk
                  SLICE_X30Y71         FDPE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg/C
                                       clock pessimism             -0.166     1.386    
                  SLICE_X30Y71         FDPE (Remov_FFF2_SLICEM_C_PRE)
                                                                   -0.020     1.366    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg
  ---------------------------------------------------------------------------------
                                       required time                         -1.366    
                                       arrival time                           1.595    
  ---------------------------------------------------------------------------------
                                       slack                                  0.230    

Slack (MET) :             0.230ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_reg/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.230ns  (logic 0.077ns (33.522%)  route 0.153ns (66.478%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.020ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.551ns
    Source Clock Delay      (SCD):    1.366ns
    Clock Pessimism Removal (CPR):    0.166ns
  Clock Net Delay (Source):      1.246ns (routing 0.414ns, distribution 0.832ns)
  Clock Net Delay (Destination): 1.404ns (routing 0.463ns, distribution 0.941ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.246     1.366    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
                  SLICE_X30Y70         FDRE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X30Y70         FDRE (Prop_FFF_SLICEM_C_Q)
                                                                    0.037     1.403 f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/Q
                                       net (fo=2, routed)           0.028     1.430    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[1]
    Routing       SLICE_X30Y70                                                      f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/I0
    Routing       SLICE_X30Y70         LUT3 (Prop_G6LUT_SLICEM_I0_O)
                                                                    0.040     1.470 f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                                       net (fo=32, routed)          0.125     1.595    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/AR[0]
    Routing       SLICE_X30Y71         FDCE                                         f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_reg/CLR
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.404     1.551    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/clk
                  SLICE_X30Y71         FDCE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_reg/C
                                       clock pessimism             -0.166     1.386    
                  SLICE_X30Y71         FDCE (Remov_GFF_SLICEM_C_CLR)
                                                                   -0.020     1.366    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_reg
  ---------------------------------------------------------------------------------
                                       required time                         -1.366    
                                       arrival time                           1.595    
  ---------------------------------------------------------------------------------
                                       slack                                  0.230    

Slack (MET) :             0.233ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[3]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.265ns  (logic 0.077ns (29.069%)  route 0.188ns (70.931%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.052ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.554ns
    Source Clock Delay      (SCD):    1.366ns
    Clock Pessimism Removal (CPR):    0.137ns
  Clock Net Delay (Source):      1.246ns (routing 0.414ns, distribution 0.832ns)
  Clock Net Delay (Destination): 1.407ns (routing 0.463ns, distribution 0.944ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.246     1.366    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
                  SLICE_X30Y70         FDRE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X30Y70         FDRE (Prop_FFF_SLICEM_C_Q)
                                                                    0.037     1.403 f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/Q
                                       net (fo=2, routed)           0.028     1.430    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[1]
    Routing       SLICE_X30Y70                                                      f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/I0
    Routing       SLICE_X30Y70         LUT3 (Prop_G6LUT_SLICEM_I0_O)
                                                                    0.040     1.470 f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                                       net (fo=32, routed)          0.160     1.630    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[4]_1
    Routing       SLICE_X31Y71         FDCE                                         f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[3]/CLR
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.407     1.554    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/clk
                  SLICE_X31Y71         FDCE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[3]/C
                                       clock pessimism             -0.137     1.417    
                  SLICE_X31Y71         FDCE (Remov_DFF_SLICEM_C_CLR)
                                                                   -0.020     1.397    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[3]
  ---------------------------------------------------------------------------------
                                       required time                         -1.397    
                                       arrival time                           1.630    
  ---------------------------------------------------------------------------------
                                       slack                                  0.233    





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  
  To Clock:  RFDAC0_CLK

Max Delay             1 Endpoint
Min Delay             1 Endpoint
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                            (internal pin)
  Destination:            d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.112ns  (logic 0.088ns (4.166%)  route 2.024ns (95.834%))
  Logic Levels:           1  (LUT1=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.168ns (routing 1.015ns, distribution 1.153ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
    Routing       PS8_X0Y0             PS8                          0.000     0.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                                       net (fo=4, routed)           1.824     1.824    d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/ext_reset_in
    Routing       SLICE_X79Y122                                                     f  d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1/I0
    Routing       SLICE_X79Y122        LUT1 (Prop_D6LUT_SLICEM_I0_O)
                                                                    0.088     1.912 r  d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1/O
                                       net (fo=1, routed)           0.200     2.112    d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/exr_d1
    Routing       SLICE_X79Y122        FDRE                                         r  d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.168     2.689    d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/slowest_sync_clk
                  SLICE_X79Y122        FDRE                                         r  d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                            (internal pin)
  Destination:            d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.003ns  (logic 0.035ns (3.488%)  route 0.968ns (96.512%))
  Logic Levels:           1  (LUT1=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.499ns (routing 0.684ns, distribution 0.815ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
    Routing       PS8_X0Y0             PS8                          0.000     0.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                                       net (fo=4, routed)           0.888     0.888    d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/ext_reset_in
    Routing       SLICE_X79Y122                                                     f  d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1/I0
    Routing       SLICE_X79Y122        LUT1 (Prop_D6LUT_SLICEM_I0_O)
                                                                    0.035     0.923 r  d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1/O
                                       net (fo=1, routed)           0.080     1.003    d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/exr_d1
    Routing       SLICE_X79Y122        FDRE                                         r  d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        1.499     1.947    d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/slowest_sync_clk
                  SLICE_X79Y122        FDRE                                         r  d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_pl_0
  To Clock:  RFDAC0_CLK

Max Delay           412 Endpoints
Min Delay           412 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac0_done_i_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac0_done_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.429ns  (logic 0.078ns (5.458%)  route 1.351ns (94.542%))
  Logic Levels:           0  
  Clock Path Skew:        -0.051ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.737ns
    Source Clock Delay      (SCD):    2.788ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.562ns (routing 0.763ns, distribution 1.799ns)
  Clock Net Delay (Destination): 2.216ns (routing 1.015ns, distribution 1.201ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.562     2.788    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
                  SLICE_X115Y118       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac0_done_i_reg/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X115Y118       FDRE (Prop_BFF_SLICEM_C_Q)
                                                                    0.078     2.866 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac0_done_i_reg/Q
                                       net (fo=1, routed)           1.351     4.217    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac0_done_i/src_in
    Routing       SLICE_X117Y268       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac0_done_i/syncstages_ff_reg[0]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.216     2.737    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac0_done_i/dest_clk
                  SLICE_X117Y268       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac0_done_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[5].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[5].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.660ns  (logic 0.079ns (11.964%)  route 0.581ns (88.036%))
  Logic Levels:           0  
  Clock Path Skew:        0.207ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.713ns
    Source Clock Delay      (SCD):    2.505ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.279ns (routing 0.763ns, distribution 1.516ns)
  Clock Net Delay (Destination): 2.192ns (routing 1.015ns, distribution 1.177ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.279     2.505    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[5].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_clk
                  SLICE_X77Y78         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[5].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X77Y78         FDRE (Prop_CFF_SLICEL_C_Q)
                                                                    0.079     2.584 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[5].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/Q
                                       net (fo=2, routed)           0.581     3.166    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[5].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/src_rst
    Routing       SLICE_X74Y80         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[5].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.192     2.713    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[5].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/dest_clk
                  SLICE_X74Y80         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[5].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_PORT[0].data_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_PORT[0].data_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.487ns  (logic 0.078ns (16.007%)  route 0.409ns (83.993%))
  Logic Levels:           0  
  Clock Path Skew:        0.247ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.739ns
    Source Clock Delay      (SCD):    2.492ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.266ns (routing 0.763ns, distribution 1.503ns)
  Clock Net Delay (Destination): 2.218ns (routing 1.015ns, distribution 1.203ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.266     2.492    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_PORT[0].data_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_clk
                  SLICE_X69Y72         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_PORT[0].data_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X69Y72         FDRE (Prop_DFF_SLICEM_C_Q)
                                                                    0.078     2.570 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_PORT[0].data_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/Q
                                       net (fo=2, routed)           0.409     2.980    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_PORT[0].data_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/src_rst
    Routing       SLICE_X71Y75         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_PORT[0].data_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.218     2.739    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_PORT[0].data_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/dest_clk
                  SLICE_X71Y75         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_PORT[0].data_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[2].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[2].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.413ns  (logic 0.078ns (18.873%)  route 0.335ns (81.127%))
  Logic Levels:           0  
  Clock Path Skew:        0.188ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.716ns
    Source Clock Delay      (SCD):    2.528ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.302ns (routing 0.763ns, distribution 1.539ns)
  Clock Net Delay (Destination): 2.195ns (routing 1.015ns, distribution 1.180ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.302     2.528    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[2].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_clk
                  SLICE_X78Y60         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[2].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X78Y60         FDRE (Prop_DFF_SLICEM_C_Q)
                                                                    0.078     2.606 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[2].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/Q
                                       net (fo=2, routed)           0.335     2.942    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[2].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/src_rst
    Routing       SLICE_X78Y66         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[2].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.195     2.716    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[2].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/dest_clk
                  SLICE_X78Y66         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[2].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_PORT[0].wave_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_PORT[0].wave_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.426ns  (logic 0.079ns (18.543%)  route 0.347ns (81.457%))
  Logic Levels:           0  
  Clock Path Skew:        0.230ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.733ns
    Source Clock Delay      (SCD):    2.503ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.277ns (routing 0.763ns, distribution 1.514ns)
  Clock Net Delay (Destination): 2.212ns (routing 1.015ns, distribution 1.197ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.277     2.503    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_PORT[0].wave_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_clk
                  SLICE_X68Y62         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_PORT[0].wave_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X68Y62         FDRE (Prop_DFF_SLICEL_C_Q)
                                                                    0.079     2.582 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_PORT[0].wave_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/Q
                                       net (fo=2, routed)           0.347     2.929    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_PORT[0].wave_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/src_rst
    Routing       SLICE_X69Y69         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_PORT[0].wave_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.212     2.733    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_PORT[0].wave_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/dest_clk
                  SLICE_X69Y69         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_PORT[0].wave_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[0].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[0].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.392ns  (logic 0.079ns (20.156%)  route 0.313ns (79.844%))
  Logic Levels:           0  
  Clock Path Skew:        0.235ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.729ns
    Source Clock Delay      (SCD):    2.494ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.268ns (routing 0.763ns, distribution 1.505ns)
  Clock Net Delay (Destination): 2.208ns (routing 1.015ns, distribution 1.193ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.268     2.494    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[0].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_clk
                  SLICE_X72Y67         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[0].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X72Y67         FDRE (Prop_HFF_SLICEM_C_Q)
                                                                    0.079     2.573 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[0].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/Q
                                       net (fo=2, routed)           0.313     2.886    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[0].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/src_rst
    Routing       SLICE_X72Y67         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[0].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.208     2.729    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[0].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/dest_clk
                  SLICE_X72Y67         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[0].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[1].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[1].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.367ns  (logic 0.079ns (21.549%)  route 0.288ns (78.451%))
  Logic Levels:           0  
  Clock Path Skew:        0.190ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.702ns
    Source Clock Delay      (SCD):    2.512ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.286ns (routing 0.763ns, distribution 1.523ns)
  Clock Net Delay (Destination): 2.181ns (routing 1.015ns, distribution 1.166ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.286     2.512    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[1].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_clk
                  SLICE_X79Y76         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[1].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X79Y76         FDRE (Prop_HFF_SLICEM_C_Q)
                                                                    0.079     2.591 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[1].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/Q
                                       net (fo=2, routed)           0.288     2.879    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[1].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/src_rst
    Routing       SLICE_X79Y76         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[1].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.181     2.702    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[1].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/dest_clk
                  SLICE_X79Y76         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[1].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[3].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[3].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.351ns  (logic 0.079ns (22.507%)  route 0.272ns (77.493%))
  Logic Levels:           0  
  Clock Path Skew:        0.194ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.706ns
    Source Clock Delay      (SCD):    2.512ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.286ns (routing 0.763ns, distribution 1.523ns)
  Clock Net Delay (Destination): 2.185ns (routing 1.015ns, distribution 1.170ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.286     2.512    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[3].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_clk
                  SLICE_X78Y72         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[3].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X78Y72         FDRE (Prop_HFF_SLICEM_C_Q)
                                                                    0.079     2.591 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[3].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/Q
                                       net (fo=2, routed)           0.272     2.863    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[3].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/src_rst
    Routing       SLICE_X78Y72         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[3].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.185     2.706    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[3].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/dest_clk
                  SLICE_X78Y72         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[3].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[4].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[4].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.283ns  (logic 0.079ns (27.887%)  route 0.204ns (72.113%))
  Logic Levels:           0  
  Clock Path Skew:        0.217ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.716ns
    Source Clock Delay      (SCD):    2.499ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.273ns (routing 0.763ns, distribution 1.510ns)
  Clock Net Delay (Destination): 2.195ns (routing 1.015ns, distribution 1.180ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.273     2.499    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[4].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_clk
                  SLICE_X77Y73         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[4].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X77Y73         FDRE (Prop_DFF_SLICEL_C_Q)
                                                                    0.079     2.578 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[4].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/Q
                                       net (fo=2, routed)           0.204     2.782    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[4].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/src_rst
    Routing       SLICE_X77Y73         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[4].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.195     2.716    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[4].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/dest_clk
                  SLICE_X77Y73         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[4].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/FSM_sequential_core_st_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/data_cdc_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.597ns  (logic 0.762ns (16.576%)  route 3.835ns (83.424%))
  Logic Levels:           6  (LUT2=1 LUT3=2 LUT4=1 LUT5=2)
  Clock Path Skew:        0.179ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.700ns
    Source Clock Delay      (SCD):    2.521ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.295ns (routing 0.763ns, distribution 1.532ns)
  Clock Net Delay (Destination): 2.179ns (routing 1.015ns, distribution 1.164ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.295     2.521    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/c_clk_i
                  SLICE_X77Y105        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/FSM_sequential_core_st_reg[0]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X77Y105        FDRE (Prop_GFF_SLICEL_C_Q)
                                                                    0.079     2.600 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/FSM_sequential_core_st_reg[0]/Q
                                       net (fo=8, routed)           0.167     2.766    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/core_st[0]
    Routing       SLICE_X76Y105                                                     r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/FSM_sequential_core_st[1]_i_4/I0
    Routing       SLICE_X76Y105        LUT2 (Prop_F6LUT_SLICEM_I0_O)
                                                                    0.098     2.864 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/FSM_sequential_core_st[1]_i_4/O
                                       net (fo=382, routed)         0.989     3.853    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[1].trig_fifo_inst/qp1_en_o_INST_0_i_2_0
    Routing       SLICE_X72Y76                                                      r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[1].trig_fifo_inst/qp1_en_o_INST_0_i_4/I3
    Routing       SLICE_X72Y76         LUT5 (Prop_E6LUT_SLICEM_I3_O)
                                                                    0.148     4.001 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[1].trig_fifo_inst/qp1_en_o_INST_0_i_4/O
                                       net (fo=4, routed)           0.239     4.240    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[3].trig_fifo_inst/AXI_DB.xreg_TPROC_DEBUG_reg[11]
    Routing       SLICE_X69Y76                                                      f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[3].trig_fifo_inst/qp1_en_o_INST_0_i_2/I1
    Routing       SLICE_X69Y76         LUT5 (Prop_H6LUT_SLICEM_I1_O)
                                                                    0.090     4.330 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[3].trig_fifo_inst/qp1_en_o_INST_0_i_2/O
                                       net (fo=3, routed)           0.673     5.004    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/some_fifo_full
    Routing       SLICE_X76Y105                                                     f  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/qp1_en_o_INST_0_i_1/I0
    Routing       SLICE_X76Y105        LUT4 (Prop_C5LUT_SLICEM_I0_O)
                                                                    0.159     5.163 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/qp1_en_o_INST_0_i_1/O
                                       net (fo=402, routed)         0.856     6.018    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/core_en
    Routing       SLICE_X62Y99                                                      r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/data_cdc[3]_i_2/I1
    Routing       SLICE_X62Y99         LUT3 (Prop_H6LUT_SLICEL_I1_O)
                                                                    0.099     6.117 f  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/data_cdc[3]_i_2/O
                                       net (fo=33, routed)          0.243     6.360    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/data_cdc_reg[3]_0
    Routing       SLICE_X64Y105                                                     f  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/data_cdc[3]_i_1/I2
    Routing       SLICE_X64Y105        LUT3 (Prop_F6LUT_SLICEL_I2_O)
                                                                    0.089     6.449 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/data_cdc[3]_i_1/O
                                       net (fo=33, routed)          0.668     7.118    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/E[0]
    Routing       SLICE_X77Y105        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/data_cdc_reg[3]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.179     2.700    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/t_clk_i
                  SLICE_X77Y105        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/data_cdc_reg[3]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_PORT[0].data_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_PORT[0].data_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][6]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.098ns  (logic 0.039ns (39.796%)  route 0.059ns (60.204%))
  Logic Levels:           0  
  Clock Path Skew:        0.638ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.988ns
    Source Clock Delay      (SCD):    1.350ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.230ns (routing 0.414ns, distribution 0.816ns)
  Clock Net Delay (Destination): 1.540ns (routing 0.684ns, distribution 0.856ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.230     1.350    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_PORT[0].data_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk
                  SLICE_X68Y73         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_PORT[0].data_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[6]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X68Y73         FDRE (Prop_CFF_SLICEL_C_Q)
                                                                    0.039     1.389 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_PORT[0].data_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[6]/Q
                                       net (fo=1, routed)           0.059     1.448    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_PORT[0].data_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[6]
    Routing       SLICE_X68Y73         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_PORT[0].data_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][6]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        1.540     1.988    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_PORT[0].data_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk
                  SLICE_X68Y73         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_PORT[0].data_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][6]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[4].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[4].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.097ns  (logic 0.039ns (40.206%)  route 0.058ns (59.794%))
  Logic Levels:           0  
  Clock Path Skew:        0.616ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.985ns
    Source Clock Delay      (SCD):    1.369ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.249ns (routing 0.414ns, distribution 0.835ns)
  Clock Net Delay (Destination): 1.537ns (routing 0.684ns, distribution 0.853ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.249     1.369    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[4].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk
                  SLICE_X73Y74         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[4].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[1]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X73Y74         FDRE (Prop_HFF2_SLICEL_C_Q)
                                                                    0.039     1.408 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[4].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[1]/Q
                                       net (fo=1, routed)           0.058     1.466    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[4].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[1]
    Routing       SLICE_X73Y75         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[4].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        1.537     1.985    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[4].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk
                  SLICE_X73Y75         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[4].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[3].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[3].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.101ns  (logic 0.038ns (37.624%)  route 0.063ns (62.376%))
  Logic Levels:           0  
  Clock Path Skew:        0.611ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.978ns
    Source Clock Delay      (SCD):    1.368ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.248ns (routing 0.414ns, distribution 0.834ns)
  Clock Net Delay (Destination): 1.530ns (routing 0.684ns, distribution 0.846ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.248     1.368    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[3].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk
                  SLICE_X72Y76         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[3].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[4]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X72Y76         FDRE (Prop_CFF_SLICEM_C_Q)
                                                                    0.038     1.406 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[3].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[4]/Q
                                       net (fo=1, routed)           0.063     1.469    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[3].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[4]
    Routing       SLICE_X72Y76         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[3].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        1.530     1.978    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[3].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk
                  SLICE_X72Y76         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[3].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_PORT[0].data_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_PORT[0].data_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][7]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.121ns  (logic 0.040ns (33.058%)  route 0.081ns (66.942%))
  Logic Levels:           0  
  Clock Path Skew:        0.638ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.988ns
    Source Clock Delay      (SCD):    1.350ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.230ns (routing 0.414ns, distribution 0.816ns)
  Clock Net Delay (Destination): 1.540ns (routing 0.684ns, distribution 0.856ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.230     1.350    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_PORT[0].data_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk
                  SLICE_X68Y73         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_PORT[0].data_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[7]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X68Y73         FDRE (Prop_CFF2_SLICEL_C_Q)
                                                                    0.040     1.390 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_PORT[0].data_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[7]/Q
                                       net (fo=1, routed)           0.081     1.471    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_PORT[0].data_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[7]
    Routing       SLICE_X68Y73         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_PORT[0].data_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][7]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        1.540     1.988    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_PORT[0].data_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk
                  SLICE_X68Y73         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_PORT[0].data_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][7]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[3].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[8]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[3].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][8]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.118ns  (logic 0.039ns (33.051%)  route 0.079ns (66.949%))
  Logic Levels:           0  
  Clock Path Skew:        0.629ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.984ns
    Source Clock Delay      (SCD):    1.355ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.235ns (routing 0.414ns, distribution 0.821ns)
  Clock Net Delay (Destination): 1.536ns (routing 0.684ns, distribution 0.852ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.235     1.355    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[3].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk
                  SLICE_X71Y77         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[3].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[8]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X71Y77         FDRE (Prop_AFF_SLICEL_C_Q)
                                                                    0.039     1.394 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[3].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[8]/Q
                                       net (fo=1, routed)           0.079     1.473    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[3].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[8]
    Routing       SLICE_X71Y77         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[3].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][8]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        1.536     1.984    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[3].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk
                  SLICE_X71Y77         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[3].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][8]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[1].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[1].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][6]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.101ns  (logic 0.038ns (37.624%)  route 0.063ns (62.376%))
  Logic Levels:           0  
  Clock Path Skew:        0.591ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.965ns
    Source Clock Delay      (SCD):    1.375ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.255ns (routing 0.414ns, distribution 0.841ns)
  Clock Net Delay (Destination): 1.517ns (routing 0.684ns, distribution 0.833ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.255     1.375    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[1].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk
                  SLICE_X76Y82         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[1].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[6]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X76Y82         FDRE (Prop_CFF_SLICEM_C_Q)
                                                                    0.038     1.413 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[1].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[6]/Q
                                       net (fo=1, routed)           0.063     1.476    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[1].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[6]
    Routing       SLICE_X76Y82         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[1].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][6]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        1.517     1.965    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[1].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk
                  SLICE_X76Y82         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[1].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][6]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[1].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[1].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.107ns  (logic 0.039ns (36.449%)  route 0.068ns (63.551%))
  Logic Levels:           0  
  Clock Path Skew:        0.597ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.971ns
    Source Clock Delay      (SCD):    1.375ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.255ns (routing 0.414ns, distribution 0.841ns)
  Clock Net Delay (Destination): 1.523ns (routing 0.684ns, distribution 0.839ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.255     1.375    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[1].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk
                  SLICE_X76Y82         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[1].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[0]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X76Y82         FDRE (Prop_DFF_SLICEM_C_Q)
                                                                    0.039     1.414 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[1].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[0]/Q
                                       net (fo=1, routed)           0.068     1.482    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[1].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[0]
    Routing       SLICE_X76Y81         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[1].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        1.523     1.971    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[1].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk
                  SLICE_X76Y81         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[1].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_PORT[0].wave_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[8]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_PORT[0].wave_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][8]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.121ns  (logic 0.039ns (32.231%)  route 0.082ns (67.769%))
  Logic Levels:           0  
  Clock Path Skew:        0.622ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.983ns
    Source Clock Delay      (SCD):    1.362ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.242ns (routing 0.414ns, distribution 0.828ns)
  Clock Net Delay (Destination): 1.535ns (routing 0.684ns, distribution 0.851ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.242     1.362    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_PORT[0].wave_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk
                  SLICE_X71Y69         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_PORT[0].wave_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[8]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X71Y69         FDRE (Prop_AFF_SLICEL_C_Q)
                                                                    0.039     1.401 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_PORT[0].wave_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[8]/Q
                                       net (fo=1, routed)           0.082     1.483    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_PORT[0].wave_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[8]
    Routing       SLICE_X71Y69         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_PORT[0].wave_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][8]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        1.535     1.983    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_PORT[0].wave_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk
                  SLICE_X71Y69         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_PORT[0].wave_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][8]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_PORT[0].data_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_PORT[0].data_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.133ns  (logic 0.041ns (30.827%)  route 0.092ns (69.173%))
  Logic Levels:           0  
  Clock Path Skew:        0.628ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.981ns
    Source Clock Delay      (SCD):    1.353ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.233ns (routing 0.414ns, distribution 0.819ns)
  Clock Net Delay (Destination): 1.533ns (routing 0.684ns, distribution 0.849ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.233     1.353    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_PORT[0].data_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk
                  SLICE_X66Y72         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_PORT[0].data_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[1]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X66Y72         FDRE (Prop_DFF2_SLICEM_C_Q)
                                                                    0.041     1.394 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_PORT[0].data_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[1]/Q
                                       net (fo=1, routed)           0.092     1.486    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_PORT[0].data_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[1]
    Routing       SLICE_X66Y72         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_PORT[0].data_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        1.533     1.981    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_PORT[0].data_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk
                  SLICE_X66Y72         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_PORT[0].data_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[0].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[8]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[0].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][8]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.118ns  (logic 0.039ns (33.051%)  route 0.079ns (66.949%))
  Logic Levels:           0  
  Clock Path Skew:        0.608ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.978ns
    Source Clock Delay      (SCD):    1.371ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.251ns (routing 0.414ns, distribution 0.837ns)
  Clock Net Delay (Destination): 1.530ns (routing 0.684ns, distribution 0.846ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.251     1.371    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[0].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk
                  SLICE_X74Y61         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[0].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[8]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X74Y61         FDRE (Prop_AFF_SLICEL_C_Q)
                                                                    0.039     1.410 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[0].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[8]/Q
                                       net (fo=1, routed)           0.079     1.489    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[0].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[8]
    Routing       SLICE_X74Y61         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[0].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][8]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        1.530     1.978    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[0].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk
                  SLICE_X74Y61         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[0].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][8]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  
  To Clock:  clk_out1_d_1_clk_adc0_x2_0

Max Delay             1 Endpoint
Min Delay             1 Endpoint
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                            (internal pin)
  Destination:            d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.153ns  (logic 0.066ns (2.093%)  route 3.087ns (97.907%))
  Logic Levels:           1  (LUT1=1)
  Clock Uncertainty:      0.139ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.094ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Destination): 2.479ns (routing 1.589ns, distribution 0.890ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
    Routing       PS8_X0Y0             PS8                          0.000     0.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                                       net (fo=4, routed)           2.326     2.326    d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/ext_reset_in
    Routing       SLICE_X81Y122                                                     f  d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1/I0
    Routing       SLICE_X81Y122        LUT1 (Prop_D5LUT_SLICEL_I0_O)
                                                                    0.066     2.392 r  d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1/O
                                       net (fo=1, routed)           0.761     3.153    d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/exr_d1
    Routing       SLICE_X79Y125        FDRE                                         r  d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.162     2.548    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                    0.630     3.178 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.216     3.394    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.024     3.418 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.479     5.897    d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/slowest_sync_clk
                  SLICE_X79Y125        FDRE                                         r  d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                            (internal pin)
  Destination:            d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.528ns  (logic 0.020ns (1.309%)  route 1.508ns (98.691%))
  Logic Levels:           1  (LUT1=1)
  Clock Uncertainty:      0.139ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.094ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Destination): 1.721ns (routing 1.079ns, distribution 0.642ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
    Routing       PS8_X0Y0             PS8                          0.000     0.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                                       net (fo=4, routed)           1.140     1.140    d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/ext_reset_in
    Routing       SLICE_X81Y122                                                     f  d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1/I0
    Routing       SLICE_X81Y122        LUT1 (Prop_D5LUT_SLICEL_I0_O)
                                                                    0.020     1.160 r  d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1/O
                                       net (fo=1, routed)           0.368     1.528    d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/exr_d1
    Routing       SLICE_X79Y125        FDRE                                         r  d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           1.507     1.859    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                   -0.295     1.564 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.166     1.730    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.019     1.749 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        1.721     3.470    d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/slowest_sync_clk
                  SLICE_X79Y125        FDRE                                         r  d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFDAC0_CLK
  To Clock:  clk_out1_d_1_clk_adc0_x2_0

Max Delay             2 Endpoints
Min Delay             2 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[4]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/CMD/sync_cmd/data_rcd_reg[6]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.647ns  (logic 0.079ns (12.205%)  route 0.568ns (87.795%))
  Logic Levels:           0  
  Clock Path Skew:        2.772ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.911ns
    Source Clock Delay      (SCD):    3.139ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.145ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.094ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      2.466ns (routing 1.120ns, distribution 1.346ns)
  Clock Net Delay (Destination): 2.493ns (routing 1.589ns, distribution 0.904ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.466     3.139    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
                  SLICE_X77Y83         FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[4]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X77Y83         FDCE (Prop_DFF_SLICEL_C_Q)
                                                                    0.079     3.218 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[4]/Q
                                       net (fo=2, routed)           0.568     3.786    d_1_i/qick_time_tagger_0/inst/CMD/sync_cmd/data_rcd_reg[6]_0[5]
    Routing       SLICE_X77Y115        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/CMD/sync_cmd/data_rcd_reg[6]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.162     2.548    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                    0.630     3.178 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.216     3.394    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.024     3.418 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.493     5.911    d_1_i/qick_time_tagger_0/inst/CMD/sync_cmd/adc_clk
                  SLICE_X77Y115        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/CMD/sync_cmd/data_rcd_reg[6]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[5]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_time_tagger_1/inst/CMD/sync_cmd/data_rcd_reg[6]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.655ns  (logic 0.079ns (12.056%)  route 0.576ns (87.944%))
  Logic Levels:           0  
  Clock Path Skew:        2.797ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.912ns
    Source Clock Delay      (SCD):    3.115ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.145ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.094ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      2.442ns (routing 1.120ns, distribution 1.322ns)
  Clock Net Delay (Destination): 2.494ns (routing 1.589ns, distribution 0.905ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.442     3.115    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
                  SLICE_X78Y84         FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[5]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X78Y84         FDCE (Prop_HFF_SLICEM_C_Q)
                                                                    0.079     3.194 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[5]/Q
                                       net (fo=2, routed)           0.576     3.770    d_1_i/qick_time_tagger_1/inst/CMD/sync_cmd/data_rcd_reg[6]_0[5]
    Routing       SLICE_X76Y119        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/CMD/sync_cmd/data_rcd_reg[6]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.162     2.548    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                    0.630     3.178 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.216     3.394    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.024     3.418 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.494     5.912    d_1_i/qick_time_tagger_1/inst/CMD/sync_cmd/adc_clk
                  SLICE_X76Y119        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/CMD/sync_cmd/data_rcd_reg[6]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[4]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/CMD/sync_cmd/data_rcd_reg[6]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.306ns  (logic 0.039ns (12.741%)  route 0.267ns (87.259%))
  Logic Levels:           0  
  Clock Path Skew:        1.795ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.490ns
    Source Clock Delay      (SCD):    1.696ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.145ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.094ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      1.347ns (routing 0.607ns, distribution 0.740ns)
  Clock Net Delay (Destination): 1.741ns (routing 1.079ns, distribution 0.662ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        1.347     1.696    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
                  SLICE_X77Y83         FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[4]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X77Y83         FDCE (Prop_DFF_SLICEL_C_Q)
                                                                    0.039     1.735 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[4]/Q
                                       net (fo=2, routed)           0.267     2.002    d_1_i/qick_time_tagger_0/inst/CMD/sync_cmd/data_rcd_reg[6]_0[5]
    Routing       SLICE_X77Y115        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/CMD/sync_cmd/data_rcd_reg[6]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           1.507     1.859    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                   -0.295     1.564 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.166     1.730    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.019     1.749 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        1.741     3.490    d_1_i/qick_time_tagger_0/inst/CMD/sync_cmd/adc_clk
                  SLICE_X77Y115        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/CMD/sync_cmd/data_rcd_reg[6]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[5]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_time_tagger_1/inst/CMD/sync_cmd/data_rcd_reg[6]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.316ns  (logic 0.039ns (12.338%)  route 0.277ns (87.662%))
  Logic Levels:           0  
  Clock Path Skew:        1.803ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.489ns
    Source Clock Delay      (SCD):    1.687ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.145ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.094ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      1.338ns (routing 0.607ns, distribution 0.731ns)
  Clock Net Delay (Destination): 1.740ns (routing 1.079ns, distribution 0.661ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        1.338     1.687    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
                  SLICE_X78Y84         FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[5]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X78Y84         FDCE (Prop_HFF_SLICEM_C_Q)
                                                                    0.039     1.726 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[5]/Q
                                       net (fo=2, routed)           0.277     2.003    d_1_i/qick_time_tagger_1/inst/CMD/sync_cmd/data_rcd_reg[6]_0[5]
    Routing       SLICE_X76Y119        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/CMD/sync_cmd/data_rcd_reg[6]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           1.507     1.859    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                   -0.295     1.564 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.166     1.730    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.019     1.749 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        1.740     3.489    d_1_i/qick_time_tagger_1/inst/CMD/sync_cmd/adc_clk
                  SLICE_X76Y119        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/CMD/sync_cmd/data_rcd_reg[6]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_pl_0
  To Clock:  clk_out1_d_1_clk_adc0_x2_0

Max Delay           653 Endpoints
Min Delay           653 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/adc1_done_i_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc1_done_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.309ns  (logic 0.078ns (25.243%)  route 0.231ns (74.757%))
  Logic Levels:           0  
  Clock Path Skew:        3.382ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.125ns
    Source Clock Delay      (SCD):    2.743ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      2.517ns (routing 0.763ns, distribution 1.754ns)
  Clock Net Delay (Destination): 2.707ns (routing 1.589ns, distribution 1.118ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.517     2.743    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
                  SLICE_X112Y98        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/adc1_done_i_reg/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X112Y98        FDRE (Prop_DFF_SLICEM_C_Q)
                                                                    0.078     2.821 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/adc1_done_i_reg/Q
                                       net (fo=1, routed)           0.231     3.052    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc1_done_i/src_in
    Routing       SLICE_X110Y98        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc1_done_i/syncstages_ff_reg[0]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.162     2.548    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                    0.630     3.178 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.216     3.394    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.024     3.418 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.707     6.125    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc1_done_i/dest_clk
                  SLICE_X110Y98        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc1_done_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_time_tagger_0/inst/CMD/xpm_cdc_handshake_core/src_sendd_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/CMD/xpm_cdc_handshake_core/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.343ns  (logic 0.076ns (22.155%)  route 0.267ns (77.845%))
  Logic Levels:           0  
  Clock Path Skew:        3.388ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.886ns
    Source Clock Delay      (SCD):    2.497ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      2.271ns (routing 0.763ns, distribution 1.508ns)
  Clock Net Delay (Destination): 2.468ns (routing 1.589ns, distribution 0.879ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.271     2.497    d_1_i/qick_time_tagger_0/inst/CMD/xpm_cdc_handshake_core/src_clk
                  SLICE_X70Y115        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/CMD/xpm_cdc_handshake_core/src_sendd_ff_reg/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X70Y115        FDRE (Prop_EFF_SLICEM_C_Q)
                                                                    0.076     2.573 r  d_1_i/qick_time_tagger_0/inst/CMD/xpm_cdc_handshake_core/src_sendd_ff_reg/Q
                                       net (fo=2, routed)           0.267     2.840    d_1_i/qick_time_tagger_0/inst/CMD/xpm_cdc_handshake_core/xpm_cdc_single_src2dest_inst/src_in
    Routing       SLICE_X71Y115        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/CMD/xpm_cdc_handshake_core/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.162     2.548    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                    0.630     3.178 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.216     3.394    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.024     3.418 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.468     5.886    d_1_i/qick_time_tagger_0/inst/CMD/xpm_cdc_handshake_core/xpm_cdc_single_src2dest_inst/dest_clk
                  SLICE_X71Y115        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/CMD/xpm_cdc_handshake_core/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/src_sendd_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.329ns  (logic 0.079ns (24.042%)  route 0.250ns (75.958%))
  Logic Levels:           0  
  Clock Path Skew:        3.439ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.886ns
    Source Clock Delay      (SCD):    2.447ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      2.221ns (routing 0.763ns, distribution 1.458ns)
  Clock Net Delay (Destination): 2.468ns (routing 1.589ns, distribution 0.879ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.221     2.447    d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/src_clk
                  SLICE_X64Y114        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/src_sendd_ff_reg/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X64Y114        FDRE (Prop_AFF_SLICEL_C_Q)
                                                                    0.079     2.526 r  d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/src_sendd_ff_reg/Q
                                       net (fo=2, routed)           0.250     2.776    d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/xpm_cdc_single_src2dest_inst/src_in
    Routing       SLICE_X65Y116        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.162     2.548    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                    0.630     3.178 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.216     3.394    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.024     3.418 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.468     5.886    d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/xpm_cdc_single_src2dest_inst/dest_clk
                  SLICE_X65Y116        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_time_tagger_1/inst/AXI_REG/slv_reg1_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/mem_reg_bram_0/DINADIN[9]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.125ns  (logic 0.360ns (11.521%)  route 2.765ns (88.479%))
  Logic Levels:           2  (LUT3=1 LUT6=1)
  Clock Path Skew:        3.447ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.932ns
    Source Clock Delay      (SCD):    2.485ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      2.259ns (routing 0.763ns, distribution 1.496ns)
  Clock Net Delay (Destination): 2.514ns (routing 1.589ns, distribution 0.925ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.259     2.485    d_1_i/qick_time_tagger_1/inst/AXI_REG/ps_clk
                  SLICE_X72Y124        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/AXI_REG/slv_reg1_reg[3]/C
  ---------------------------------------------------------------------------------    -------------------
    Placement     SLICE_X72Y124        FDRE (Prop_EFF2_SLICEM_C_Q)
                                                                    0.079     2.564 r  d_1_i/qick_time_tagger_1/inst/AXI_REG/slv_reg1_reg[3]/Q
                                       net (fo=67, routed)          2.101     4.665    d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/ind_bit_reg[2]_0[2]
    Placement     SLICE_X67Y267                                                     r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/mem_reg_bram_0_i_60/I2
    Routing       SLICE_X67Y267        LUT6 (Prop_G6LUT_SLICEM_I2_O)
                                                                    0.123     4.788 r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/mem_reg_bram_0_i_60/O
                                       net (fo=2, routed)           0.351     5.139    d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/mem_reg_bram_0_i_60_n_0
    Routing       SLICE_X64Y268                                                     r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/mem_reg_bram_0_i_23__0/I0
    Routing       SLICE_X64Y268        LUT3 (Prop_C5LUT_SLICEL_I0_O)
                                                                    0.158     5.297 r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/mem_reg_bram_0_i_23__0/O
                                       net (fo=1, routed)           0.313     5.610    d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/DINADIN[9]
    Routing       RAMB36_X6Y54         RAMB36E2                                     r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/mem_reg_bram_0/DINADIN[9]
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.162     2.548    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                    0.630     3.178 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.216     3.394    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.024     3.418 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.514     5.932    d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/adc_clk
                  RAMB36_X6Y54         RAMB36E2                                     r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/mem_reg_bram_0/CLKARDCLK

Slack:                    inf
  Source:                 d_1_i/qick_time_tagger_1/inst/AXI_REG/slv_reg1_reg[10]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/SMP[7].ftr_smp_reg[7][16]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.133ns  (logic 0.474ns (15.128%)  route 2.659ns (84.872%))
  Logic Levels:           3  (CARRY8=2 LUT6=1)
  Clock Path Skew:        3.605ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.080ns
    Source Clock Delay      (SCD):    2.475ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      2.249ns (routing 0.763ns, distribution 1.486ns)
  Clock Net Delay (Destination): 2.662ns (routing 1.589ns, distribution 1.073ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.249     2.475    d_1_i/qick_time_tagger_1/inst/AXI_REG/ps_clk
                  SLICE_X69Y118        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/AXI_REG/slv_reg1_reg[10]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X69Y118        FDRE (Prop_EFF_SLICEM_C_Q)
                                                                    0.076     2.551 r  d_1_i/qick_time_tagger_1/inst/AXI_REG/slv_reg1_reg[10]/Q
                                       net (fo=148, routed)         2.595     5.146    d_1_i/qick_time_tagger_1/inst/AXI_REG/axi_reg_CFG[10]
    Routing       SLICE_X97Y128                                                     r  d_1_i/qick_time_tagger_1/inst/AXI_REG/SMP[7].ftr_smp[7][15]_i_17/I1
    Routing       SLICE_X97Y128        LUT6 (Prop_A6LUT_SLICEM_I1_O)
                                                                    0.150     5.296 r  d_1_i/qick_time_tagger_1/inst/AXI_REG/SMP[7].ftr_smp[7][15]_i_17/O
                                       net (fo=1, routed)           0.013     5.309    d_1_i/qick_time_tagger_1/inst/AXI_REG/SMP[7].ftr_smp[7][15]_i_17_n_0
    Routing       SLICE_X97Y128                                                     r  d_1_i/qick_time_tagger_1/inst/AXI_REG/SMP[7].ftr_smp_reg[7][15]_i_1/S[0]
    Routing       SLICE_X97Y128        CARRY8 (Prop_CARRY8_SLICEM_S[0]_CO[7])
                                                                    0.192     5.501 r  d_1_i/qick_time_tagger_1/inst/AXI_REG/SMP[7].ftr_smp_reg[7][15]_i_1/CO[7]
                                       net (fo=1, routed)           0.026     5.527    d_1_i/qick_time_tagger_1/inst/AXI_REG/SMP[7].ftr_smp_reg[7][15]_i_1_n_0
    Routing       SLICE_X97Y129                                                     r  d_1_i/qick_time_tagger_1/inst/AXI_REG/SMP[7].ftr_smp_reg[7][16]_i_1/CI
    Routing       SLICE_X97Y129        CARRY8 (Prop_CARRY8_SLICEM_CI_O[0])
                                                                    0.056     5.583 r  d_1_i/qick_time_tagger_1/inst/AXI_REG/SMP[7].ftr_smp_reg[7][16]_i_1/O[0]
                                       net (fo=1, routed)           0.025     5.608    d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/SMP[7].ftr_smp_reg[7][16]_0[16]
    Routing       SLICE_X97Y129        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/SMP[7].ftr_smp_reg[7][16]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.162     2.548    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                    0.630     3.178 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.216     3.394    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.024     3.418 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.662     6.080    d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/adc_clk
                  SLICE_X97Y129        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/SMP[7].ftr_smp_reg[7][16]/C

Slack:                    inf
  Source:                 d_1_i/qick_time_tagger_1/inst/AXI_REG/slv_reg1_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/mem_reg_bram_0/DINADIN[27]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.120ns  (logic 0.342ns (10.961%)  route 2.778ns (89.039%))
  Logic Levels:           2  (LUT3=1 LUT6=1)
  Clock Path Skew:        3.447ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.932ns
    Source Clock Delay      (SCD):    2.485ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      2.259ns (routing 0.763ns, distribution 1.496ns)
  Clock Net Delay (Destination): 2.514ns (routing 1.589ns, distribution 0.925ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.259     2.485    d_1_i/qick_time_tagger_1/inst/AXI_REG/ps_clk
                  SLICE_X72Y124        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/AXI_REG/slv_reg1_reg[2]/C
  ---------------------------------------------------------------------------------    -------------------
    Placement     SLICE_X72Y124        FDRE (Prop_EFF_SLICEM_C_Q)
                                                                    0.076     2.561 r  d_1_i/qick_time_tagger_1/inst/AXI_REG/slv_reg1_reg[2]/Q
                                       net (fo=96, routed)          2.204     4.766    d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/ind_bit_reg[2]_0[1]
    Placement     SLICE_X63Y269                                                     r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/mem_reg_bram_0_i_34/I4
    Routing       SLICE_X63Y269        LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                                    0.125     4.891 r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/mem_reg_bram_0_i_34/O
                                       net (fo=2, routed)           0.263     5.154    d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/mem_reg_bram_0_i_34_n_0
    Routing       SLICE_X65Y269                                                     r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/mem_reg_bram_0_i_5__0/I2
    Routing       SLICE_X65Y269        LUT3 (Prop_B5LUT_SLICEL_I2_O)
                                                                    0.141     5.295 r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/mem_reg_bram_0_i_5__0/O
                                       net (fo=1, routed)           0.311     5.606    d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/DINADIN[27]
    Routing       RAMB36_X6Y54         RAMB36E2                                     r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/mem_reg_bram_0/DINADIN[27]
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.162     2.548    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                    0.630     3.178 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.216     3.394    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.024     3.418 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.514     5.932    d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/adc_clk
                  RAMB36_X6Y54         RAMB36E2                                     r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/mem_reg_bram_0/CLKARDCLK

Slack:                    inf
  Source:                 d_1_i/qick_time_tagger_1/inst/AXI_REG/slv_reg1_reg[10]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/SMP[7].ftr_smp_reg[7][15]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.101ns  (logic 0.467ns (15.058%)  route 2.634ns (84.942%))
  Logic Levels:           2  (CARRY8=1 LUT6=1)
  Clock Path Skew:        3.604ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.079ns
    Source Clock Delay      (SCD):    2.475ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      2.249ns (routing 0.763ns, distribution 1.486ns)
  Clock Net Delay (Destination): 2.661ns (routing 1.589ns, distribution 1.072ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.249     2.475    d_1_i/qick_time_tagger_1/inst/AXI_REG/ps_clk
                  SLICE_X69Y118        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/AXI_REG/slv_reg1_reg[10]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X69Y118        FDRE (Prop_EFF_SLICEM_C_Q)
                                                                    0.076     2.551 r  d_1_i/qick_time_tagger_1/inst/AXI_REG/slv_reg1_reg[10]/Q
                                       net (fo=148, routed)         2.595     5.146    d_1_i/qick_time_tagger_1/inst/AXI_REG/axi_reg_CFG[10]
    Routing       SLICE_X97Y128                                                     r  d_1_i/qick_time_tagger_1/inst/AXI_REG/SMP[7].ftr_smp[7][15]_i_17/I1
    Routing       SLICE_X97Y128        LUT6 (Prop_A6LUT_SLICEM_I1_O)
                                                                    0.150     5.296 r  d_1_i/qick_time_tagger_1/inst/AXI_REG/SMP[7].ftr_smp[7][15]_i_17/O
                                       net (fo=1, routed)           0.013     5.309    d_1_i/qick_time_tagger_1/inst/AXI_REG/SMP[7].ftr_smp[7][15]_i_17_n_0
    Routing       SLICE_X97Y128                                                     r  d_1_i/qick_time_tagger_1/inst/AXI_REG/SMP[7].ftr_smp_reg[7][15]_i_1/S[0]
    Routing       SLICE_X97Y128        CARRY8 (Prop_CARRY8_SLICEM_S[0]_O[7])
                                                                    0.241     5.550 r  d_1_i/qick_time_tagger_1/inst/AXI_REG/SMP[7].ftr_smp_reg[7][15]_i_1/O[7]
                                       net (fo=1, routed)           0.026     5.576    d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/SMP[7].ftr_smp_reg[7][16]_0[15]
    Routing       SLICE_X97Y128        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/SMP[7].ftr_smp_reg[7][15]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.162     2.548    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                    0.630     3.178 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.216     3.394    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.024     3.418 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.661     6.079    d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/adc_clk
                  SLICE_X97Y128        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/SMP[7].ftr_smp_reg[7][15]/C

Slack:                    inf
  Source:                 d_1_i/qick_time_tagger_1/inst/AXI_REG/slv_reg1_reg[10]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/SMP[7].ftr_smp_reg[7][13]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.099ns  (logic 0.466ns (15.035%)  route 2.633ns (84.965%))
  Logic Levels:           2  (CARRY8=1 LUT6=1)
  Clock Path Skew:        3.604ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.079ns
    Source Clock Delay      (SCD):    2.475ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      2.249ns (routing 0.763ns, distribution 1.486ns)
  Clock Net Delay (Destination): 2.661ns (routing 1.589ns, distribution 1.072ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.249     2.475    d_1_i/qick_time_tagger_1/inst/AXI_REG/ps_clk
                  SLICE_X69Y118        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/AXI_REG/slv_reg1_reg[10]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X69Y118        FDRE (Prop_EFF_SLICEM_C_Q)
                                                                    0.076     2.551 r  d_1_i/qick_time_tagger_1/inst/AXI_REG/slv_reg1_reg[10]/Q
                                       net (fo=148, routed)         2.595     5.146    d_1_i/qick_time_tagger_1/inst/AXI_REG/axi_reg_CFG[10]
    Routing       SLICE_X97Y128                                                     r  d_1_i/qick_time_tagger_1/inst/AXI_REG/SMP[7].ftr_smp[7][15]_i_17/I1
    Routing       SLICE_X97Y128        LUT6 (Prop_A6LUT_SLICEM_I1_O)
                                                                    0.150     5.296 r  d_1_i/qick_time_tagger_1/inst/AXI_REG/SMP[7].ftr_smp[7][15]_i_17/O
                                       net (fo=1, routed)           0.013     5.309    d_1_i/qick_time_tagger_1/inst/AXI_REG/SMP[7].ftr_smp[7][15]_i_17_n_0
    Routing       SLICE_X97Y128                                                     r  d_1_i/qick_time_tagger_1/inst/AXI_REG/SMP[7].ftr_smp_reg[7][15]_i_1/S[0]
    Routing       SLICE_X97Y128        CARRY8 (Prop_CARRY8_SLICEM_S[0]_O[5])
                                                                    0.240     5.549 r  d_1_i/qick_time_tagger_1/inst/AXI_REG/SMP[7].ftr_smp_reg[7][15]_i_1/O[5]
                                       net (fo=1, routed)           0.025     5.574    d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/SMP[7].ftr_smp_reg[7][16]_0[13]
    Routing       SLICE_X97Y128        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/SMP[7].ftr_smp_reg[7][13]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.162     2.548    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                    0.630     3.178 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.216     3.394    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.024     3.418 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.661     6.079    d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/adc_clk
                  SLICE_X97Y128        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/SMP[7].ftr_smp_reg[7][13]/C

Slack:                    inf
  Source:                 d_1_i/qick_time_tagger_1/inst/AXI_REG/slv_reg1_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/mem_reg_bram_0/DINADIN[31]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.082ns  (logic 0.325ns (10.544%)  route 2.757ns (89.456%))
  Logic Levels:           2  (LUT3=1 LUT6=1)
  Clock Path Skew:        3.447ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.932ns
    Source Clock Delay      (SCD):    2.485ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      2.259ns (routing 0.763ns, distribution 1.496ns)
  Clock Net Delay (Destination): 2.514ns (routing 1.589ns, distribution 0.925ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.259     2.485    d_1_i/qick_time_tagger_1/inst/AXI_REG/ps_clk
                  SLICE_X72Y124        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/AXI_REG/slv_reg1_reg[2]/C
  ---------------------------------------------------------------------------------    -------------------
    Placement     SLICE_X72Y124        FDRE (Prop_EFF_SLICEM_C_Q)
                                                                    0.076     2.561 r  d_1_i/qick_time_tagger_1/inst/AXI_REG/slv_reg1_reg[2]/Q
                                       net (fo=96, routed)          2.204     4.766    d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/ind_bit_reg[2]_0[1]
    Placement     SLICE_X63Y269                                                     r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/mem_reg_bram_0_i_34/I4
    Routing       SLICE_X63Y269        LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                                    0.125     4.891 r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/mem_reg_bram_0_i_34/O
                                       net (fo=2, routed)           0.263     5.154    d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/mem_reg_bram_0_i_34_n_0
    Routing       SLICE_X65Y269                                                     r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/mem_reg_bram_0_i_1__0/I0
    Routing       SLICE_X65Y269        LUT3 (Prop_B6LUT_SLICEL_I0_O)
                                                                    0.124     5.278 r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/mem_reg_bram_0_i_1__0/O
                                       net (fo=1, routed)           0.290     5.568    d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/DINADIN[31]
    Routing       RAMB36_X6Y54         RAMB36E2                                     r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/mem_reg_bram_0/DINADIN[31]
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.162     2.548    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                    0.630     3.178 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.216     3.394    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.024     3.418 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.514     5.932    d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/adc_clk
                  RAMB36_X6Y54         RAMB36E2                                     r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/mem_reg_bram_0/CLKARDCLK

Slack:                    inf
  Source:                 d_1_i/qick_time_tagger_1/inst/AXI_REG/slv_reg1_reg[10]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/SMP[7].ftr_smp_reg[7][14]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.086ns  (logic 0.452ns (14.645%)  route 2.634ns (85.355%))
  Logic Levels:           2  (CARRY8=1 LUT6=1)
  Clock Path Skew:        3.604ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.079ns
    Source Clock Delay      (SCD):    2.475ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      2.249ns (routing 0.763ns, distribution 1.486ns)
  Clock Net Delay (Destination): 2.661ns (routing 1.589ns, distribution 1.072ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.249     2.475    d_1_i/qick_time_tagger_1/inst/AXI_REG/ps_clk
                  SLICE_X69Y118        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/AXI_REG/slv_reg1_reg[10]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X69Y118        FDRE (Prop_EFF_SLICEM_C_Q)
                                                                    0.076     2.551 r  d_1_i/qick_time_tagger_1/inst/AXI_REG/slv_reg1_reg[10]/Q
                                       net (fo=148, routed)         2.595     5.146    d_1_i/qick_time_tagger_1/inst/AXI_REG/axi_reg_CFG[10]
    Routing       SLICE_X97Y128                                                     r  d_1_i/qick_time_tagger_1/inst/AXI_REG/SMP[7].ftr_smp[7][15]_i_17/I1
    Routing       SLICE_X97Y128        LUT6 (Prop_A6LUT_SLICEM_I1_O)
                                                                    0.150     5.296 r  d_1_i/qick_time_tagger_1/inst/AXI_REG/SMP[7].ftr_smp[7][15]_i_17/O
                                       net (fo=1, routed)           0.013     5.309    d_1_i/qick_time_tagger_1/inst/AXI_REG/SMP[7].ftr_smp[7][15]_i_17_n_0
    Routing       SLICE_X97Y128                                                     r  d_1_i/qick_time_tagger_1/inst/AXI_REG/SMP[7].ftr_smp_reg[7][15]_i_1/S[0]
    Routing       SLICE_X97Y128        CARRY8 (Prop_CARRY8_SLICEM_S[0]_O[6])
                                                                    0.226     5.535 r  d_1_i/qick_time_tagger_1/inst/AXI_REG/SMP[7].ftr_smp_reg[7][15]_i_1/O[6]
                                       net (fo=1, routed)           0.026     5.561    d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/SMP[7].ftr_smp_reg[7][16]_0[14]
    Routing       SLICE_X97Y128        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/SMP[7].ftr_smp_reg[7][14]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.162     2.548    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                    0.630     3.178 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.216     3.394    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.024     3.418 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.661     6.079    d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/adc_clk
                  SLICE_X97Y128        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/SMP[7].ftr_smp_reg[7][14]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/src_hsdata_ff_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/dest_hsdata_ff_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.097ns  (logic 0.040ns (41.237%)  route 0.057ns (58.763%))
  Logic Levels:           0  
  Clock Path Skew:        2.110ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.459ns
    Source Clock Delay      (SCD):    1.350ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      1.230ns (routing 0.414ns, distribution 0.816ns)
  Clock Net Delay (Destination): 1.710ns (routing 1.079ns, distribution 0.631ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.230     1.350    d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/src_clk
                  SLICE_X68Y123        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/src_hsdata_ff_reg[4]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X68Y123        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                                    0.040     1.390 r  d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/src_hsdata_ff_reg[4]/Q
                                       net (fo=1, routed)           0.057     1.447    d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/src_hsdata_ff[4]
    Routing       SLICE_X68Y124        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/dest_hsdata_ff_reg[4]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           1.507     1.859    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                   -0.295     1.564 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.166     1.730    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.019     1.749 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        1.710     3.459    d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/dest_clk
                  SLICE_X68Y124        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/dest_hsdata_ff_reg[4]/C

Slack:                    inf
  Source:                 d_1_i/qick_time_tagger_0/inst/CMD/xpm_cdc_handshake_core/src_hsdata_ff_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/CMD/xpm_cdc_handshake_core/dest_hsdata_ff_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.107ns  (logic 0.038ns (35.514%)  route 0.069ns (64.486%))
  Logic Levels:           0  
  Clock Path Skew:        2.120ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.480ns
    Source Clock Delay      (SCD):    1.361ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      1.241ns (routing 0.414ns, distribution 0.827ns)
  Clock Net Delay (Destination): 1.731ns (routing 1.079ns, distribution 0.652ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.241     1.361    d_1_i/qick_time_tagger_0/inst/CMD/xpm_cdc_handshake_core/src_clk
                  SLICE_X69Y116        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/CMD/xpm_cdc_handshake_core/src_hsdata_ff_reg[3]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X69Y116        FDRE (Prop_BFF_SLICEM_C_Q)
                                                                    0.038     1.399 r  d_1_i/qick_time_tagger_0/inst/CMD/xpm_cdc_handshake_core/src_hsdata_ff_reg[3]/Q
                                       net (fo=1, routed)           0.069     1.468    d_1_i/qick_time_tagger_0/inst/CMD/xpm_cdc_handshake_core/src_hsdata_ff[3]
    Routing       SLICE_X70Y116        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/CMD/xpm_cdc_handshake_core/dest_hsdata_ff_reg[3]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           1.507     1.859    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                   -0.295     1.564 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.166     1.730    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.019     1.749 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        1.731     3.480    d_1_i/qick_time_tagger_0/inst/CMD/xpm_cdc_handshake_core/dest_clk
                  SLICE_X70Y116        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/CMD/xpm_cdc_handshake_core/dest_hsdata_ff_reg[3]/C

Slack:                    inf
  Source:                 d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/src_hsdata_ff_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/dest_hsdata_ff_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.120ns  (logic 0.039ns (32.500%)  route 0.081ns (67.500%))
  Logic Levels:           0  
  Clock Path Skew:        2.110ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.459ns
    Source Clock Delay      (SCD):    1.350ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      1.230ns (routing 0.414ns, distribution 0.816ns)
  Clock Net Delay (Destination): 1.710ns (routing 1.079ns, distribution 0.631ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.230     1.350    d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/src_clk
                  SLICE_X68Y123        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/src_hsdata_ff_reg[3]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X68Y123        FDRE (Prop_AFF_SLICEL_C_Q)
                                                                    0.039     1.389 r  d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/src_hsdata_ff_reg[3]/Q
                                       net (fo=1, routed)           0.081     1.470    d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/src_hsdata_ff[3]
    Routing       SLICE_X68Y124        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/dest_hsdata_ff_reg[3]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           1.507     1.859    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                   -0.295     1.564 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.166     1.730    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.019     1.749 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        1.710     3.459    d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/dest_clk
                  SLICE_X68Y124        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/dest_hsdata_ff_reg[3]/C

Slack:                    inf
  Source:                 d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/src_hsdata_ff_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/dest_hsdata_ff_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.124ns  (logic 0.039ns (31.452%)  route 0.085ns (68.548%))
  Logic Levels:           0  
  Clock Path Skew:        2.110ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.459ns
    Source Clock Delay      (SCD):    1.350ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      1.230ns (routing 0.414ns, distribution 0.816ns)
  Clock Net Delay (Destination): 1.710ns (routing 1.079ns, distribution 0.631ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.230     1.350    d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/src_clk
                  SLICE_X68Y123        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/src_hsdata_ff_reg[7]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X68Y123        FDRE (Prop_BFF_SLICEL_C_Q)
                                                                    0.039     1.389 r  d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/src_hsdata_ff_reg[7]/Q
                                       net (fo=1, routed)           0.085     1.474    d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/src_hsdata_ff[7]
    Routing       SLICE_X68Y124        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/dest_hsdata_ff_reg[7]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           1.507     1.859    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                   -0.295     1.564 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.166     1.730    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.019     1.749 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        1.710     3.459    d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/dest_clk
                  SLICE_X68Y124        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/dest_hsdata_ff_reg[7]/C

Slack:                    inf
  Source:                 d_1_i/qick_time_tagger_0/inst/CMD/xpm_cdc_handshake_core/src_hsdata_ff_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/CMD/xpm_cdc_handshake_core/dest_hsdata_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.118ns  (logic 0.038ns (32.203%)  route 0.080ns (67.797%))
  Logic Levels:           0  
  Clock Path Skew:        2.118ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.480ns
    Source Clock Delay      (SCD):    1.362ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      1.242ns (routing 0.414ns, distribution 0.828ns)
  Clock Net Delay (Destination): 1.731ns (routing 1.079ns, distribution 0.652ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.242     1.362    d_1_i/qick_time_tagger_0/inst/CMD/xpm_cdc_handshake_core/src_clk
                  SLICE_X70Y116        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/CMD/xpm_cdc_handshake_core/src_hsdata_ff_reg[0]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X70Y116        FDRE (Prop_EFF_SLICEM_C_Q)
                                                                    0.038     1.400 r  d_1_i/qick_time_tagger_0/inst/CMD/xpm_cdc_handshake_core/src_hsdata_ff_reg[0]/Q
                                       net (fo=1, routed)           0.080     1.480    d_1_i/qick_time_tagger_0/inst/CMD/xpm_cdc_handshake_core/src_hsdata_ff[0]
    Routing       SLICE_X70Y116        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/CMD/xpm_cdc_handshake_core/dest_hsdata_ff_reg[0]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           1.507     1.859    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                   -0.295     1.564 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.166     1.730    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.019     1.749 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        1.731     3.480    d_1_i/qick_time_tagger_0/inst/CMD/xpm_cdc_handshake_core/dest_clk
                  SLICE_X70Y116        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/CMD/xpm_cdc_handshake_core/dest_hsdata_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/src_sendd_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.146ns  (logic 0.039ns (26.765%)  route 0.107ns (73.235%))
  Logic Levels:           0  
  Clock Path Skew:        2.131ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.472ns
    Source Clock Delay      (SCD):    1.342ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      1.222ns (routing 0.414ns, distribution 0.808ns)
  Clock Net Delay (Destination): 1.723ns (routing 1.079ns, distribution 0.644ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.222     1.342    d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/src_clk
                  SLICE_X64Y114        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/src_sendd_ff_reg/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X64Y114        FDRE (Prop_AFF_SLICEL_C_Q)
                                                                    0.039     1.381 r  d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/src_sendd_ff_reg/Q
                                       net (fo=2, routed)           0.107     1.487    d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/xpm_cdc_single_src2dest_inst/src_in
    Routing       SLICE_X65Y116        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           1.507     1.859    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                   -0.295     1.564 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.166     1.730    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.019     1.749 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        1.723     3.472    d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/xpm_cdc_single_src2dest_inst/dest_clk
                  SLICE_X65Y116        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/src_hsdata_ff_reg[32]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/dest_hsdata_ff_reg[32]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.147ns  (logic 0.038ns (25.850%)  route 0.109ns (74.150%))
  Logic Levels:           0  
  Clock Path Skew:        2.108ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.453ns
    Source Clock Delay      (SCD):    1.345ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      1.225ns (routing 0.414ns, distribution 0.811ns)
  Clock Net Delay (Destination): 1.704ns (routing 1.079ns, distribution 0.625ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.225     1.345    d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/src_clk
                  SLICE_X67Y125        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/src_hsdata_ff_reg[32]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X67Y125        FDRE (Prop_AFF_SLICEM_C_Q)
                                                                    0.038     1.383 r  d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/src_hsdata_ff_reg[32]/Q
                                       net (fo=1, routed)           0.109     1.492    d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/src_hsdata_ff[32]
    Routing       SLICE_X67Y125        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/dest_hsdata_ff_reg[32]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           1.507     1.859    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                   -0.295     1.564 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.166     1.730    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.019     1.749 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        1.704     3.453    d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/dest_clk
                  SLICE_X67Y125        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/dest_hsdata_ff_reg[32]/C

Slack:                    inf
  Source:                 d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/src_hsdata_ff_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/dest_hsdata_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.147ns  (logic 0.038ns (25.850%)  route 0.109ns (74.150%))
  Logic Levels:           0  
  Clock Path Skew:        2.105ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.454ns
    Source Clock Delay      (SCD):    1.349ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      1.229ns (routing 0.414ns, distribution 0.815ns)
  Clock Net Delay (Destination): 1.705ns (routing 1.079ns, distribution 0.626ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.229     1.349    d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/src_clk
                  SLICE_X67Y120        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/src_hsdata_ff_reg[0]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X67Y120        FDRE (Prop_AFF_SLICEM_C_Q)
                                                                    0.038     1.387 r  d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/src_hsdata_ff_reg[0]/Q
                                       net (fo=1, routed)           0.109     1.496    d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/src_hsdata_ff[0]
    Routing       SLICE_X67Y120        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/dest_hsdata_ff_reg[0]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           1.507     1.859    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                   -0.295     1.564 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.166     1.730    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.019     1.749 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        1.705     3.454    d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/dest_clk
                  SLICE_X67Y120        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/dest_hsdata_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_time_tagger_0/inst/CMD/xpm_cdc_handshake_core/src_hsdata_ff_reg[8]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/CMD/xpm_cdc_handshake_core/dest_hsdata_ff_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.137ns  (logic 0.039ns (28.467%)  route 0.098ns (71.533%))
  Logic Levels:           0  
  Clock Path Skew:        2.118ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.480ns
    Source Clock Delay      (SCD):    1.362ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      1.242ns (routing 0.414ns, distribution 0.828ns)
  Clock Net Delay (Destination): 1.731ns (routing 1.079ns, distribution 0.652ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.242     1.362    d_1_i/qick_time_tagger_0/inst/CMD/xpm_cdc_handshake_core/src_clk
                  SLICE_X70Y116        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/CMD/xpm_cdc_handshake_core/src_hsdata_ff_reg[8]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X70Y116        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                                    0.039     1.401 r  d_1_i/qick_time_tagger_0/inst/CMD/xpm_cdc_handshake_core/src_hsdata_ff_reg[8]/Q
                                       net (fo=1, routed)           0.098     1.499    d_1_i/qick_time_tagger_0/inst/CMD/xpm_cdc_handshake_core/src_hsdata_ff[8]
    Routing       SLICE_X70Y116        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/CMD/xpm_cdc_handshake_core/dest_hsdata_ff_reg[8]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           1.507     1.859    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                   -0.295     1.564 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.166     1.730    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.019     1.749 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        1.731     3.480    d_1_i/qick_time_tagger_0/inst/CMD/xpm_cdc_handshake_core/dest_clk
                  SLICE_X70Y116        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/CMD/xpm_cdc_handshake_core/dest_hsdata_ff_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/qick_time_tagger_0/inst/CMD/xpm_cdc_handshake_core/src_hsdata_ff_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/CMD/xpm_cdc_handshake_core/dest_hsdata_ff_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.138ns  (logic 0.039ns (28.261%)  route 0.099ns (71.739%))
  Logic Levels:           0  
  Clock Path Skew:        2.118ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.480ns
    Source Clock Delay      (SCD):    1.362ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      1.242ns (routing 0.414ns, distribution 0.828ns)
  Clock Net Delay (Destination): 1.731ns (routing 1.079ns, distribution 0.652ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.242     1.362    d_1_i/qick_time_tagger_0/inst/CMD/xpm_cdc_handshake_core/src_clk
                  SLICE_X70Y116        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/CMD/xpm_cdc_handshake_core/src_hsdata_ff_reg[4]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X70Y116        FDRE (Prop_GFF_SLICEM_C_Q)
                                                                    0.039     1.401 r  d_1_i/qick_time_tagger_0/inst/CMD/xpm_cdc_handshake_core/src_hsdata_ff_reg[4]/Q
                                       net (fo=1, routed)           0.099     1.500    d_1_i/qick_time_tagger_0/inst/CMD/xpm_cdc_handshake_core/src_hsdata_ff[4]
    Routing       SLICE_X70Y116        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/CMD/xpm_cdc_handshake_core/dest_hsdata_ff_reg[4]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           1.507     1.859    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                   -0.295     1.564 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.166     1.730    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.019     1.749 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        1.731     3.480    d_1_i/qick_time_tagger_0/inst/CMD/xpm_cdc_handshake_core/dest_clk
                  SLICE_X70Y116        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/CMD/xpm_cdc_handshake_core/dest_hsdata_ff_reg[4]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  
  To Clock:  clk_pl_0

Max Delay           101 Endpoints
Min Delay           101 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                            (internal pin)
  Destination:            d_1_i/rst_100/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.712ns  (logic 0.050ns (1.844%)  route 2.662ns (98.156%))
  Logic Levels:           1  (LUT1=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.123ns (routing 0.690ns, distribution 1.433ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
    Routing       PS8_X0Y0             PS8                          0.000     0.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                                       net (fo=4, routed)           2.326     2.326    d_1_i/rst_100/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/ext_reset_in
    Routing       SLICE_X81Y122                                                     f  d_1_i/rst_100/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1/I0
    Routing       SLICE_X81Y122        LUT1 (Prop_D6LUT_SLICEL_I0_O)
                                                                    0.050     2.376 r  d_1_i/rst_100/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1/O
                                       net (fo=1, routed)           0.336     2.712    d_1_i/rst_100/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/exr_d1
    Routing       SLICE_X82Y115        FDRE                                         r  d_1_i/rst_100/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.123     2.305    d_1_i/rst_100/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/slowest_sync_clk
                  SLICE_X82Y115        FDRE                                         r  d_1_i/rst_100/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_DAC3[15]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac13_fifo_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.500ns  (logic 0.000ns (0.000%)  route 2.500ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.259ns (routing 0.690ns, distribution 1.569ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_DAC3[15]
                                       net (fo=1, routed)           2.500     2.500    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac13_fifo_irq/src_in
    Routing       SLICE_X117Y102       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac13_fifo_irq/syncstages_ff_reg[0]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.259     2.441    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac13_fifo_irq/dest_clk
                  SLICE_X117Y102       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac13_fifo_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_DAC1[14]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac11_data_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.471ns  (logic 0.000ns (0.000%)  route 2.471ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.258ns (routing 0.690ns, distribution 1.568ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_DAC1[14]
                                       net (fo=1, routed)           2.471     2.471    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac11_data_irq/src_in
    Routing       SLICE_X114Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac11_data_irq/syncstages_ff_reg[0]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.258     2.440    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac11_data_irq/dest_clk
                  SLICE_X114Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac11_data_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_DAC2[15]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac12_fifo_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.423ns  (logic 0.000ns (0.000%)  route 2.423ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.261ns (routing 0.690ns, distribution 1.571ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_DAC2[15]
                                       net (fo=1, routed)           2.423     2.423    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac12_fifo_irq/src_in
    Routing       SLICE_X115Y101       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac12_fifo_irq/syncstages_ff_reg[0]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.261     2.443    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac12_fifo_irq/dest_clk
                  SLICE_X115Y101       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac12_fifo_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_DAC3[14]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac13_data_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.338ns  (logic 0.000ns (0.000%)  route 2.338ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.272ns (routing 0.690ns, distribution 1.582ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_DAC3[14]
                                       net (fo=1, routed)           2.338     2.338    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac13_data_irq/src_in
    Routing       SLICE_X113Y106       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac13_data_irq/syncstages_ff_reg[0]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.272     2.454    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac13_data_irq/dest_clk
                  SLICE_X113Y106       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac13_data_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_DAC2[14]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac12_data_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.239ns  (logic 0.000ns (0.000%)  route 2.239ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.258ns (routing 0.690ns, distribution 1.568ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_DAC2[14]
                                       net (fo=1, routed)           2.239     2.239    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac12_data_irq/src_in
    Routing       SLICE_X117Y101       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac12_data_irq/syncstages_ff_reg[0]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.258     2.440    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac12_data_irq/dest_clk
                  SLICE_X117Y101       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac12_data_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[1]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_supplies_up_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.210ns  (logic 0.000ns (0.000%)  route 2.210ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.262ns (routing 0.690ns, distribution 1.572ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[1]
                                       net (fo=2, routed)           2.210     2.210    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_supplies_up_i/src_in
    Routing       SLICE_X110Y120       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_supplies_up_i/syncstages_ff_reg[0]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.262     2.444    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_supplies_up_i/dest_clk
                  SLICE_X110Y120       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_supplies_up_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_DAC1[15]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac11_fifo_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.193ns  (logic 0.000ns (0.000%)  route 2.193ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.262ns (routing 0.690ns, distribution 1.572ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_DAC1[15]
                                       net (fo=1, routed)           2.193     2.193    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac11_fifo_irq/src_in
    Routing       SLICE_X118Y100       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac11_fifo_irq/syncstages_ff_reg[0]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.262     2.444    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac11_fifo_irq/dest_clk
                  SLICE_X118Y100       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac11_fifo_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_DAC0[15]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac10_fifo_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.112ns  (logic 0.000ns (0.000%)  route 2.112ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.261ns (routing 0.690ns, distribution 1.571ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_DAC0[15]
                                       net (fo=1, routed)           2.112     2.112    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac10_fifo_irq/src_in
    Routing       SLICE_X112Y105       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac10_fifo_irq/syncstages_ff_reg[0]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.261     2.443    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac10_fifo_irq/dest_clk
                  SLICE_X112Y105       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac10_fifo_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_DAC3[14]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac03_data_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.089ns  (logic 0.000ns (0.000%)  route 2.089ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.264ns (routing 0.690ns, distribution 1.574ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_DAC3[14]
                                       net (fo=1, routed)           2.089     2.089    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac03_data_irq/src_in
    Routing       SLICE_X118Y102       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac03_data_irq/syncstages_ff_reg[0]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.264     2.446    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac03_data_irq/dest_clk
                  SLICE_X118Y102       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac03_data_irq/syncstages_ff_reg[0]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_ADC1[14]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc11_data_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.154ns  (logic 0.000ns (0.000%)  route 0.154ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.564ns (routing 0.463ns, distribution 1.101ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_ADC1[14]
                                       net (fo=1, routed)           0.154     0.154    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc11_data_irq/src_in
    Routing       SLICE_X117Y80        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc11_data_irq/syncstages_ff_reg[0]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.564     1.711    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc11_data_irq/dest_clk
                  SLICE_X117Y80        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc11_data_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_ADC1[15]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc11_fifo_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.199ns  (logic 0.000ns (0.000%)  route 0.199ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.570ns (routing 0.463ns, distribution 1.107ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_ADC1[15]
                                       net (fo=1, routed)           0.199     0.199    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc11_fifo_irq/src_in
    Routing       SLICE_X114Y81        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc11_fifo_irq/syncstages_ff_reg[0]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.570     1.717    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc11_fifo_irq/dest_clk
                  SLICE_X114Y81        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc11_fifo_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_ADC1[2]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc11_over_vol/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.204ns  (logic 0.000ns (0.000%)  route 0.204ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.565ns (routing 0.463ns, distribution 1.102ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_ADC1[2]
                                       net (fo=1, routed)           0.204     0.204    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc11_over_vol/src_in
    Routing       SLICE_X116Y77        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc11_over_vol/syncstages_ff_reg[0]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.565     1.712    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc11_over_vol/dest_clk
                  SLICE_X116Y77        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc11_over_vol/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_ADC3[15]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc03_fifo_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.216ns  (logic 0.000ns (0.000%)  route 0.216ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.567ns (routing 0.463ns, distribution 1.104ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_ADC3[15]
                                       net (fo=1, routed)           0.216     0.216    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc03_fifo_irq/src_in
    Routing       SLICE_X117Y75        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc03_fifo_irq/syncstages_ff_reg[0]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.567     1.714    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc03_fifo_irq/dest_clk
                  SLICE_X117Y75        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc03_fifo_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_ADC1[3]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc11_over_range/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.222ns  (logic 0.000ns (0.000%)  route 0.222ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.568ns (routing 0.463ns, distribution 1.105ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_ADC1[3]
                                       net (fo=1, routed)           0.222     0.222    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc11_over_range/src_in
    Routing       SLICE_X115Y76        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc11_over_range/syncstages_ff_reg[0]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.568     1.715    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc11_over_range/dest_clk
                  SLICE_X115Y76        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc11_over_range/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_ADC2[15]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc02_fifo_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.234ns  (logic 0.000ns (0.000%)  route 0.234ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.568ns (routing 0.463ns, distribution 1.105ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_ADC2[15]
                                       net (fo=1, routed)           0.234     0.234    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc02_fifo_irq/src_in
    Routing       SLICE_X117Y70        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc02_fifo_irq/syncstages_ff_reg[0]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.568     1.715    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc02_fifo_irq/dest_clk
                  SLICE_X117Y70        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc02_fifo_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_ADC2[3]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc02_over_range/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.234ns  (logic 0.000ns (0.000%)  route 0.234ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.578ns (routing 0.463ns, distribution 1.115ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_ADC2[3]
                                       net (fo=1, routed)           0.234     0.234    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc02_over_range/src_in
    Routing       SLICE_X117Y66        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc02_over_range/syncstages_ff_reg[0]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.578     1.725    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc02_over_range/dest_clk
                  SLICE_X117Y66        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc02_over_range/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_ADC3[14]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc03_data_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.235ns  (logic 0.000ns (0.000%)  route 0.235ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.576ns (routing 0.463ns, distribution 1.113ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_ADC3[14]
                                       net (fo=1, routed)           0.235     0.235    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc03_data_irq/src_in
    Routing       SLICE_X117Y73        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc03_data_irq/syncstages_ff_reg[0]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.576     1.723    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc03_data_irq/dest_clk
                  SLICE_X117Y73        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc03_data_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_ADC0[2]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc10_over_vol/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.240ns  (logic 0.000ns (0.000%)  route 0.240ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.569ns (routing 0.463ns, distribution 1.106ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_ADC0[2]
                                       net (fo=1, routed)           0.240     0.240    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc10_over_vol/src_in
    Routing       SLICE_X115Y75        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc10_over_vol/syncstages_ff_reg[0]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.569     1.716    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc10_over_vol/dest_clk
                  SLICE_X115Y75        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc10_over_vol/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_ADC2[2]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc12_over_vol/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.248ns  (logic 0.000ns (0.000%)  route 0.248ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.566ns (routing 0.463ns, distribution 1.103ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_ADC2[2]
                                       net (fo=1, routed)           0.248     0.248    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc12_over_vol/src_in
    Routing       SLICE_X118Y82        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc12_over_vol/syncstages_ff_reg[0]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.566     1.713    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc12_over_vol/dest_clk
                  SLICE_X118Y82        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc12_over_vol/syncstages_ff_reg[0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFADC0_CLK
  To Clock:  clk_pl_0

Max Delay             8 Endpoints
Min Delay             8 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.875ns  (logic 1.297ns (45.113%)  route 1.578ns (54.887%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        2.429ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.429ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.247ns (routing 0.690ns, distribution 1.557ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFADC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[8])
                                                                    0.788     0.788 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[8]
                                       net (fo=1, routed)           0.720     1.508    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc0_common_stat[8]
    Routing       SLICE_X117Y82                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_20/I4
    Routing       SLICE_X117Y82        LUT5 (Prop_F6LUT_SLICEL_I4_O)
                                                                    0.148     1.656 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_20/O
                                       net (fo=1, routed)           0.381     2.037    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_20_n_0
    Routing       SLICE_X116Y90                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_9/I5
    Routing       SLICE_X116Y90        LUT6 (Prop_C6LUT_SLICEL_I5_O)
                                                                    0.088     2.125 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_9/O
                                       net (fo=1, routed)           0.155     2.280    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_9_n_0
    Routing       SLICE_X116Y94                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_3/I3
    Routing       SLICE_X116Y94        LUT6 (Prop_H6LUT_SLICEL_I3_O)
                                                                    0.150     2.430 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_3/O
                                       net (fo=1, routed)           0.272     2.702    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_3_n_0
    Routing       SLICE_X111Y94                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/I1
    Routing       SLICE_X111Y94        LUT6 (Prop_C6LUT_SLICEL_I1_O)
                                                                    0.123     2.825 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                                       net (fo=1, routed)           0.050     2.875    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    Routing       SLICE_X111Y94        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.247     2.429    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X111Y94        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.476ns  (logic 0.919ns (37.116%)  route 1.557ns (62.884%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        2.445ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.445ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.263ns (routing 0.690ns, distribution 1.573ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFADC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[10])
                                                                    0.536     0.536 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[10]
                                       net (fo=1, routed)           0.790     1.326    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc0_common_stat[10]
    Routing       SLICE_X117Y83                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_25/I4
    Routing       SLICE_X117Y83        LUT5 (Prop_E6LUT_SLICEL_I4_O)
                                                                    0.035     1.361 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_25/O
                                       net (fo=1, routed)           0.057     1.418    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_25_n_0
    Routing       SLICE_X117Y83                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_11/I5
    Routing       SLICE_X117Y83        LUT6 (Prop_F6LUT_SLICEL_I5_O)
                                                                    0.148     1.566 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_11/O
                                       net (fo=1, routed)           0.444     2.010    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_11_n_0
    Routing       SLICE_X116Y96                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_3/I3
    Routing       SLICE_X116Y96        LUT6 (Prop_G6LUT_SLICEL_I3_O)
                                                                    0.149     2.159 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_3/O
                                       net (fo=1, routed)           0.194     2.353    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_3_n_0
    Routing       SLICE_X113Y96                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/I1
    Routing       SLICE_X113Y96        LUT6 (Prop_D6LUT_SLICEM_I1_O)
                                                                    0.051     2.404 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                                       net (fo=1, routed)           0.072     2.476    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    Routing       SLICE_X113Y96        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.263     2.445    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X113Y96        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.424ns  (logic 0.910ns (37.541%)  route 1.514ns (62.459%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        2.441ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.441ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.259ns (routing 0.690ns, distribution 1.569ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFADC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[11])
                                                                    0.588     0.588 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[11]
                                       net (fo=1, routed)           0.754     1.342    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc0_common_stat[11]
    Routing       SLICE_X117Y85                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_26/I4
    Routing       SLICE_X117Y85        LUT5 (Prop_H6LUT_SLICEL_I4_O)
                                                                    0.036     1.378 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_26/O
                                       net (fo=1, routed)           0.089     1.467    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_26_n_0
    Routing       SLICE_X117Y85                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_11/I5
    Routing       SLICE_X117Y85        LUT6 (Prop_D6LUT_SLICEL_I5_O)
                                                                    0.099     1.566 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_11/O
                                       net (fo=1, routed)           0.374     1.940    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_11_n_0
    Routing       SLICE_X116Y94                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_3/I3
    Routing       SLICE_X116Y94        LUT6 (Prop_D6LUT_SLICEL_I3_O)
                                                                    0.099     2.039 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_3/O
                                       net (fo=1, routed)           0.225     2.264    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_3_n_0
    Routing       SLICE_X113Y93                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/I1
    Routing       SLICE_X113Y93        LUT6 (Prop_D6LUT_SLICEM_I1_O)
                                                                    0.088     2.352 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                                       net (fo=1, routed)           0.072     2.424    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    Routing       SLICE_X113Y93        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.259     2.441    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X113Y93        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.417ns  (logic 1.141ns (47.207%)  route 1.276ns (52.793%))
  Logic Levels:           3  (LUT5=2 LUT6=1)
  Clock Path Skew:        2.423ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.423ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.241ns (routing 0.690ns, distribution 1.551ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFADC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[13])
                                                                    0.771     0.771 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[13]
                                       net (fo=1, routed)           0.696     1.467    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc0_common_stat[13]
    Routing       SLICE_X117Y82                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_11/I4
    Routing       SLICE_X117Y82        LUT5 (Prop_G6LUT_SLICEL_I4_O)
                                                                    0.123     1.590 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_11/O
                                       net (fo=1, routed)           0.353     1.943    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_11_n_0
    Routing       SLICE_X116Y91                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_3/I2
    Routing       SLICE_X116Y91        LUT5 (Prop_D6LUT_SLICEL_I2_O)
                                                                    0.146     2.089 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_3/O
                                       net (fo=1, routed)           0.169     2.258    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_3_n_0
    Routing       SLICE_X112Y91                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/I1
    Routing       SLICE_X112Y91        LUT6 (Prop_H6LUT_SLICEM_I1_O)
                                                                    0.101     2.359 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                                       net (fo=1, routed)           0.058     2.417    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    Routing       SLICE_X112Y91        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.241     2.423    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X112Y91        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.372ns  (logic 0.855ns (36.046%)  route 1.517ns (63.954%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        2.429ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.429ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.247ns (routing 0.690ns, distribution 1.557ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFADC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[9])
                                                                    0.532     0.532 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[9]
                                       net (fo=1, routed)           0.696     1.228    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc0_common_stat[9]
    Routing       SLICE_X117Y82                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_29/I4
    Routing       SLICE_X117Y82        LUT5 (Prop_E6LUT_SLICEL_I4_O)
                                                                    0.035     1.263 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_29/O
                                       net (fo=1, routed)           0.168     1.431    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_29_n_0
    Routing       SLICE_X117Y87                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_13/I5
    Routing       SLICE_X117Y87        LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                                    0.150     1.581 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_13/O
                                       net (fo=1, routed)           0.318     1.899    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_13_n_0
    Routing       SLICE_X116Y94                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_3/I2
    Routing       SLICE_X116Y94        LUT6 (Prop_G6LUT_SLICEL_I2_O)
                                                                    0.050     1.949 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_3/O
                                       net (fo=1, routed)           0.269     2.218    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_3_n_0
    Routing       SLICE_X112Y95                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/I1
    Routing       SLICE_X112Y95        LUT6 (Prop_C6LUT_SLICEM_I1_O)
                                                                    0.088     2.306 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                                       net (fo=1, routed)           0.066     2.372    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    Routing       SLICE_X112Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.247     2.429    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X112Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.326ns  (logic 1.064ns (45.744%)  route 1.262ns (54.256%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        2.432ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.432ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.250ns (routing 0.690ns, distribution 1.560ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFADC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[14])
                                                                    0.698     0.698 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[14]
                                       net (fo=1, routed)           0.744     1.442    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc0_common_stat[14]
    Routing       SLICE_X116Y80                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_12/I0
    Routing       SLICE_X116Y80        LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                                    0.146     1.588 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_12/O
                                       net (fo=1, routed)           0.221     1.809    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_12_n_0
    Routing       SLICE_X116Y85                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_3/I1
    Routing       SLICE_X116Y85        LUT6 (Prop_H6LUT_SLICEL_I1_O)
                                                                    0.124     1.933 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_3/O
                                       net (fo=1, routed)           0.247     2.180    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_3_n_0
    Routing       SLICE_X114Y91                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/I1
    Routing       SLICE_X114Y91        LUT6 (Prop_C6LUT_SLICEL_I1_O)
                                                                    0.096     2.276 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                                       net (fo=1, routed)           0.050     2.326    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    Routing       SLICE_X114Y91        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.250     2.432    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X114Y91        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.211ns  (logic 0.849ns (38.399%)  route 1.362ns (61.601%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        2.435ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.435ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.253ns (routing 0.690ns, distribution 1.563ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFADC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[12])
                                                                    0.611     0.611 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[12]
                                       net (fo=1, routed)           0.736     1.347    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc0_common_stat[12]
    Routing       SLICE_X117Y82                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_15/I4
    Routing       SLICE_X117Y82        LUT5 (Prop_H6LUT_SLICEL_I4_O)
                                                                    0.051     1.398 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_15/O
                                       net (fo=1, routed)           0.313     1.711    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_15_n_0
    Routing       SLICE_X116Y91                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_4/I2
    Routing       SLICE_X116Y91        LUT6 (Prop_H6LUT_SLICEL_I2_O)
                                                                    0.150     1.861 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_4/O
                                       net (fo=1, routed)           0.241     2.102    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_4_n_0
    Routing       SLICE_X113Y95                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/I3
    Routing       SLICE_X113Y95        LUT6 (Prop_D6LUT_SLICEM_I3_O)
                                                                    0.037     2.139 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                                       net (fo=1, routed)           0.072     2.211    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    Routing       SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.253     2.435    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.143ns  (logic 0.862ns (40.224%)  route 1.281ns (59.776%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        2.435ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.435ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.253ns (routing 0.690ns, distribution 1.563ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFADC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[15])
                                                                    0.525     0.525 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[15]
                                       net (fo=1, routed)           0.761     1.286    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc0_common_stat[15]
    Routing       SLICE_X116Y80                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_15/I1
    Routing       SLICE_X116Y80        LUT6 (Prop_H6LUT_SLICEL_I1_O)
                                                                    0.150     1.436 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_15/O
                                       net (fo=1, routed)           0.153     1.589    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_15_n_0
    Routing       SLICE_X116Y86                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_5/I1
    Routing       SLICE_X116Y86        LUT6 (Prop_F6LUT_SLICEL_I1_O)
                                                                    0.089     1.678 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_5/O
                                       net (fo=1, routed)           0.301     1.979    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_5_n_0
    Routing       SLICE_X113Y95                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/I3
    Routing       SLICE_X113Y95        LUT6 (Prop_C6LUT_SLICEM_I3_O)
                                                                    0.098     2.077 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                                       net (fo=1, routed)           0.066     2.143    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    Routing       SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.253     2.435    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.011ns  (logic 0.385ns (38.081%)  route 0.626ns (61.919%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        1.707ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.707ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.560ns (routing 0.463ns, distribution 1.097ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFADC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[15])
                                                                    0.250     0.250 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[15]
                                       net (fo=1, routed)           0.370     0.620    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc0_common_stat[15]
    Routing       SLICE_X116Y80                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_15/I1
    Routing       SLICE_X116Y80        LUT6 (Prop_H6LUT_SLICEL_I1_O)
                                                                    0.060     0.680 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_15/O
                                       net (fo=1, routed)           0.082     0.762    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_15_n_0
    Routing       SLICE_X116Y86                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_5/I1
    Routing       SLICE_X116Y86        LUT6 (Prop_F6LUT_SLICEL_I1_O)
                                                                    0.035     0.797 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_5/O
                                       net (fo=1, routed)           0.150     0.947    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_5_n_0
    Routing       SLICE_X113Y95                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/I3
    Routing       SLICE_X113Y95        LUT6 (Prop_C6LUT_SLICEM_I3_O)
                                                                    0.040     0.987 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                                       net (fo=1, routed)           0.024     1.011    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    Routing       SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.560     1.707    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.016ns  (logic 0.391ns (38.484%)  route 0.625ns (61.516%))
  Logic Levels:           3  (LUT5=2 LUT6=1)
  Clock Path Skew:        1.698ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.698ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.551ns (routing 0.463ns, distribution 1.088ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFADC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[13])
                                                                    0.241     0.241 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[13]
                                       net (fo=1, routed)           0.339     0.580    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc0_common_stat[13]
    Routing       SLICE_X117Y82                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_11/I4
    Routing       SLICE_X117Y82        LUT5 (Prop_G6LUT_SLICEL_I4_O)
                                                                    0.050     0.630 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_11/O
                                       net (fo=1, routed)           0.178     0.808    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_11_n_0
    Routing       SLICE_X116Y91                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_3/I2
    Routing       SLICE_X116Y91        LUT5 (Prop_D6LUT_SLICEL_I2_O)
                                                                    0.059     0.867 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_3/O
                                       net (fo=1, routed)           0.087     0.954    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_3_n_0
    Routing       SLICE_X112Y91                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/I1
    Routing       SLICE_X112Y91        LUT6 (Prop_H6LUT_SLICEM_I1_O)
                                                                    0.041     0.995 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                                       net (fo=1, routed)           0.021     1.016    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    Routing       SLICE_X112Y91        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.551     1.698    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X112Y91        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.034ns  (logic 0.371ns (35.880%)  route 0.663ns (64.120%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        1.707ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.707ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.560ns (routing 0.463ns, distribution 1.097ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFADC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[12])
                                                                    0.274     0.274 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[12]
                                       net (fo=1, routed)           0.359     0.633    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc0_common_stat[12]
    Routing       SLICE_X117Y82                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_15/I4
    Routing       SLICE_X117Y82        LUT5 (Prop_H6LUT_SLICEL_I4_O)
                                                                    0.023     0.656 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_15/O
                                       net (fo=1, routed)           0.157     0.813    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_15_n_0
    Routing       SLICE_X116Y91                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_4/I2
    Routing       SLICE_X116Y91        LUT6 (Prop_H6LUT_SLICEL_I2_O)
                                                                    0.060     0.873 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_4/O
                                       net (fo=1, routed)           0.121     0.994    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_4_n_0
    Routing       SLICE_X113Y95                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/I3
    Routing       SLICE_X113Y95        LUT6 (Prop_D6LUT_SLICEM_I3_O)
                                                                    0.014     1.008 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                                       net (fo=1, routed)           0.026     1.034    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    Routing       SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.560     1.707    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.053ns  (logic 0.434ns (41.216%)  route 0.619ns (58.784%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        1.705ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.705ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.558ns (routing 0.463ns, distribution 1.095ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFADC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[14])
                                                                    0.285     0.285 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[14]
                                       net (fo=1, routed)           0.366     0.651    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc0_common_stat[14]
    Routing       SLICE_X116Y80                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_12/I0
    Routing       SLICE_X116Y80        LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                                    0.059     0.710 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_12/O
                                       net (fo=1, routed)           0.110     0.820    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_12_n_0
    Routing       SLICE_X116Y85                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_3/I1
    Routing       SLICE_X116Y85        LUT6 (Prop_H6LUT_SLICEL_I1_O)
                                                                    0.050     0.870 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_3/O
                                       net (fo=1, routed)           0.126     0.996    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_3_n_0
    Routing       SLICE_X114Y91                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/I1
    Routing       SLICE_X114Y91        LUT6 (Prop_C6LUT_SLICEL_I1_O)
                                                                    0.040     1.036 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                                       net (fo=1, routed)           0.017     1.053    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    Routing       SLICE_X114Y91        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.558     1.705    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X114Y91        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.107ns  (logic 0.359ns (32.430%)  route 0.748ns (67.570%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.702ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.702ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.555ns (routing 0.463ns, distribution 1.092ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFADC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[9])
                                                                    0.228     0.228 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[9]
                                       net (fo=1, routed)           0.342     0.570    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc0_common_stat[9]
    Routing       SLICE_X117Y82                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_29/I4
    Routing       SLICE_X117Y82        LUT5 (Prop_E6LUT_SLICEL_I4_O)
                                                                    0.014     0.584 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_29/O
                                       net (fo=1, routed)           0.089     0.673    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_29_n_0
    Routing       SLICE_X117Y87                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_13/I5
    Routing       SLICE_X117Y87        LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                                    0.060     0.733 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_13/O
                                       net (fo=1, routed)           0.160     0.893    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_13_n_0
    Routing       SLICE_X116Y94                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_3/I2
    Routing       SLICE_X116Y94        LUT6 (Prop_G6LUT_SLICEL_I2_O)
                                                                    0.022     0.915 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_3/O
                                       net (fo=1, routed)           0.133     1.048    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_3_n_0
    Routing       SLICE_X112Y95                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/I1
    Routing       SLICE_X112Y95        LUT6 (Prop_C6LUT_SLICEM_I1_O)
                                                                    0.035     1.083 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                                       net (fo=1, routed)           0.024     1.107    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    Routing       SLICE_X112Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.555     1.702    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X112Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.129ns  (logic 0.382ns (33.835%)  route 0.747ns (66.165%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.717ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.717ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.570ns (routing 0.463ns, distribution 1.107ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFADC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[10])
                                                                    0.227     0.227 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[10]
                                       net (fo=1, routed)           0.385     0.612    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc0_common_stat[10]
    Routing       SLICE_X117Y83                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_25/I4
    Routing       SLICE_X117Y83        LUT5 (Prop_E6LUT_SLICEL_I4_O)
                                                                    0.014     0.626 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_25/O
                                       net (fo=1, routed)           0.031     0.657    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_25_n_0
    Routing       SLICE_X117Y83                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_11/I5
    Routing       SLICE_X117Y83        LUT6 (Prop_F6LUT_SLICEL_I5_O)
                                                                    0.059     0.716 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_11/O
                                       net (fo=1, routed)           0.207     0.923    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_11_n_0
    Routing       SLICE_X116Y96                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_3/I3
    Routing       SLICE_X116Y96        LUT6 (Prop_G6LUT_SLICEL_I3_O)
                                                                    0.060     0.983 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_3/O
                                       net (fo=1, routed)           0.098     1.081    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_3_n_0
    Routing       SLICE_X113Y96                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/I1
    Routing       SLICE_X113Y96        LUT6 (Prop_D6LUT_SLICEM_I1_O)
                                                                    0.022     1.103 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                                       net (fo=1, routed)           0.026     1.129    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    Routing       SLICE_X113Y96        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.570     1.717    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X113Y96        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.147ns  (logic 0.397ns (34.612%)  route 0.750ns (65.388%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.715ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.715ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.568ns (routing 0.463ns, distribution 1.105ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFADC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[11])
                                                                    0.265     0.265 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[11]
                                       net (fo=1, routed)           0.372     0.637    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc0_common_stat[11]
    Routing       SLICE_X117Y85                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_26/I4
    Routing       SLICE_X117Y85        LUT5 (Prop_H6LUT_SLICEL_I4_O)
                                                                    0.015     0.652 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_26/O
                                       net (fo=1, routed)           0.047     0.699    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_26_n_0
    Routing       SLICE_X117Y85                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_11/I5
    Routing       SLICE_X117Y85        LUT6 (Prop_D6LUT_SLICEL_I5_O)
                                                                    0.041     0.740 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_11/O
                                       net (fo=1, routed)           0.191     0.931    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_11_n_0
    Routing       SLICE_X116Y94                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_3/I3
    Routing       SLICE_X116Y94        LUT6 (Prop_D6LUT_SLICEL_I3_O)
                                                                    0.041     0.972 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_3/O
                                       net (fo=1, routed)           0.114     1.086    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_3_n_0
    Routing       SLICE_X113Y93                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/I1
    Routing       SLICE_X113Y93        LUT6 (Prop_D6LUT_SLICEM_I1_O)
                                                                    0.035     1.121 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                                       net (fo=1, routed)           0.026     1.147    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    Routing       SLICE_X113Y93        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.568     1.715    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X113Y93        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.232ns  (logic 0.441ns (35.795%)  route 0.791ns (64.205%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.700ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.700ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.553ns (routing 0.463ns, distribution 1.090ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFADC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[8])
                                                                    0.237     0.237 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[8]
                                       net (fo=1, routed)           0.351     0.588    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc0_common_stat[8]
    Routing       SLICE_X117Y82                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_20/I4
    Routing       SLICE_X117Y82        LUT5 (Prop_F6LUT_SLICEL_I4_O)
                                                                    0.059     0.647 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_20/O
                                       net (fo=1, routed)           0.197     0.844    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_20_n_0
    Routing       SLICE_X116Y90                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_9/I5
    Routing       SLICE_X116Y90        LUT6 (Prop_C6LUT_SLICEL_I5_O)
                                                                    0.035     0.879 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_9/O
                                       net (fo=1, routed)           0.086     0.965    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_9_n_0
    Routing       SLICE_X116Y94                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_3/I3
    Routing       SLICE_X116Y94        LUT6 (Prop_H6LUT_SLICEL_I3_O)
                                                                    0.060     1.025 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_3/O
                                       net (fo=1, routed)           0.140     1.165    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_3_n_0
    Routing       SLICE_X111Y94                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/I1
    Routing       SLICE_X111Y94        LUT6 (Prop_C6LUT_SLICEL_I1_O)
                                                                    0.050     1.215 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                                       net (fo=1, routed)           0.017     1.232    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    Routing       SLICE_X111Y94        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.553     1.700    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X111Y94        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFADC1_CLK
  To Clock:  clk_pl_0

Max Delay             8 Endpoints
Min Delay             8 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@3.906ns period=7.812ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.587ns  (logic 1.127ns (43.564%)  route 1.460ns (56.436%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        2.423ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.423ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.241ns (routing 0.690ns, distribution 1.551ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFADC1_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[13])
                                                                    0.771     0.771 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[13]
                                       net (fo=1, routed)           0.797     1.568    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc1_common_stat[13]
    Routing       SLICE_X113Y87                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_31/I3
    Routing       SLICE_X113Y87        LUT6 (Prop_H6LUT_SLICEM_I3_O)
                                                                    0.152     1.720 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_31/O
                                       net (fo=1, routed)           0.286     2.006    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_31_n_0
    Routing       SLICE_X111Y87                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_18/I5
    Routing       SLICE_X111Y87        LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                                    0.099     2.105 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_18/O
                                       net (fo=1, routed)           0.228     2.333    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_18_n_0
    Routing       SLICE_X112Y90                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_4/I5
    Placement     SLICE_X112Y90        LUT6 (Prop_G6LUT_SLICEM_I5_O)
                                                                    0.052     2.385 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_4/O
                                       net (fo=1, routed)           0.091     2.476    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_4_n_0
    Placement     SLICE_X112Y91                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/I2
    Routing       SLICE_X112Y91        LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                                    0.053     2.529 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                                       net (fo=1, routed)           0.058     2.587    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    Routing       SLICE_X112Y91        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.241     2.423    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X112Y91        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@3.906ns period=7.812ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.472ns  (logic 0.962ns (38.916%)  route 1.510ns (61.084%))
  Logic Levels:           5  (LUT6=5)
  Clock Path Skew:        2.435ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.435ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.253ns (routing 0.690ns, distribution 1.563ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFADC1_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[15])
                                                                    0.525     0.525 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[15]
                                       net (fo=1, routed)           0.714     1.239    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc1_common_stat[15]
    Routing       SLICE_X111Y86                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_81/I2
    Routing       SLICE_X111Y86        LUT6 (Prop_G6LUT_SLICEL_I2_O)
                                                                    0.149     1.388 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_81/O
                                       net (fo=1, routed)           0.139     1.527    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_81_n_0
    Routing       SLICE_X111Y86                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_52/I2
    Routing       SLICE_X111Y86        LUT6 (Prop_C6LUT_SLICEL_I2_O)
                                                                    0.050     1.577 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_52/O
                                       net (fo=1, routed)           0.089     1.666    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_52_n_0
    Routing       SLICE_X111Y86                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_20/I2
    Routing       SLICE_X111Y86        LUT6 (Prop_H6LUT_SLICEL_I2_O)
                                                                    0.090     1.756 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_20/O
                                       net (fo=1, routed)           0.365     2.121    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_20_n_0
    Routing       SLICE_X114Y94                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_6/I0
    Routing       SLICE_X114Y94        LUT6 (Prop_G6LUT_SLICEL_I0_O)
                                                                    0.097     2.218 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_6/O
                                       net (fo=1, routed)           0.137     2.355    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_6_n_0
    Routing       SLICE_X113Y95                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/I4
    Routing       SLICE_X113Y95        LUT6 (Prop_C6LUT_SLICEM_I4_O)
                                                                    0.051     2.406 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                                       net (fo=1, routed)           0.066     2.472    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    Routing       SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.253     2.435    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@3.906ns period=7.812ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.161ns  (logic 0.980ns (45.349%)  route 1.181ns (54.651%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        2.441ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.441ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.259ns (routing 0.690ns, distribution 1.569ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFADC1_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[11])
                                                                    0.588     0.588 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[11]
                                       net (fo=1, routed)           0.601     1.189    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc1_common_stat[11]
    Routing       SLICE_X110Y86                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_33/I3
    Routing       SLICE_X110Y86        LUT6 (Prop_G6LUT_SLICEM_I3_O)
                                                                    0.150     1.339 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_33/O
                                       net (fo=1, routed)           0.047     1.386    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_33_n_0
    Routing       SLICE_X110Y86                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_17/I2
    Routing       SLICE_X110Y86        LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                                    0.101     1.487 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_17/O
                                       net (fo=1, routed)           0.377     1.864    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_17_n_0
    Routing       SLICE_X113Y93                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_5/I0
    Placement     SLICE_X113Y93        LUT6 (Prop_H6LUT_SLICEM_I0_O)
                                                                    0.090     1.954 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_5/O
                                       net (fo=1, routed)           0.084     2.038    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_5_n_0
    Placement     SLICE_X113Y93                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/I4
    Routing       SLICE_X113Y93        LUT6 (Prop_D6LUT_SLICEM_I4_O)
                                                                    0.051     2.089 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                                       net (fo=1, routed)           0.072     2.161    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    Routing       SLICE_X113Y93        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.259     2.441    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X113Y93        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@3.906ns period=7.812ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.118ns  (logic 0.960ns (45.326%)  route 1.158ns (54.674%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        2.432ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.432ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.250ns (routing 0.690ns, distribution 1.560ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFADC1_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[14])
                                                                    0.698     0.698 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[14]
                                       net (fo=1, routed)           0.592     1.290    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc1_common_stat[14]
    Routing       SLICE_X112Y86                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_53/I2
    Routing       SLICE_X112Y86        LUT6 (Prop_B6LUT_SLICEM_I2_O)
                                                                    0.125     1.415 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_53/O
                                       net (fo=1, routed)           0.094     1.509    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_53_n_0
    Routing       SLICE_X112Y86                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_24/I1
    Routing       SLICE_X112Y86        LUT6 (Prop_C6LUT_SLICEM_I1_O)
                                                                    0.037     1.546 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_24/O
                                       net (fo=1, routed)           0.313     1.859    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_24_n_0
    Routing       SLICE_X114Y89                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6/I4
    Routing       SLICE_X114Y89        LUT6 (Prop_G6LUT_SLICEL_I4_O)
                                                                    0.050     1.909 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6/O
                                       net (fo=1, routed)           0.109     2.018    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6_n_0
    Routing       SLICE_X114Y91                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/I4
    Routing       SLICE_X114Y91        LUT6 (Prop_C6LUT_SLICEL_I4_O)
                                                                    0.050     2.068 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                                       net (fo=1, routed)           0.050     2.118    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    Routing       SLICE_X114Y91        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.250     2.432    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X114Y91        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@3.906ns period=7.812ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.109ns  (logic 1.231ns (58.369%)  route 0.878ns (41.631%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        2.429ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.429ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.247ns (routing 0.690ns, distribution 1.557ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFADC1_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[8])
                                                                    0.788     0.788 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[8]
                                       net (fo=1, routed)           0.406     1.194    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc1_common_stat[8]
    Routing       SLICE_X116Y92                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_24/I3
    Routing       SLICE_X116Y92        LUT6 (Prop_F6LUT_SLICEL_I3_O)
                                                                    0.148     1.342 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_24/O
                                       net (fo=1, routed)           0.194     1.536    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_24_n_0
    Routing       SLICE_X111Y92                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_13/I2
    Routing       SLICE_X111Y92        LUT6 (Prop_B6LUT_SLICEL_I2_O)
                                                                    0.148     1.684 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_13/O
                                       net (fo=1, routed)           0.088     1.772    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_13_n_0
    Routing       SLICE_X111Y93                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_5/I0
    Routing       SLICE_X111Y93        LUT6 (Prop_G6LUT_SLICEL_I0_O)
                                                                    0.097     1.869 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_5/O
                                       net (fo=1, routed)           0.140     2.009    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_5_n_0
    Routing       SLICE_X111Y94                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/I4
    Routing       SLICE_X111Y94        LUT6 (Prop_C6LUT_SLICEL_I4_O)
                                                                    0.050     2.059 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                                       net (fo=1, routed)           0.050     2.109    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    Routing       SLICE_X111Y94        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.247     2.429    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X111Y94        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@3.906ns period=7.812ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.008ns  (logic 1.010ns (50.299%)  route 0.998ns (49.701%))
  Logic Levels:           4  (LUT3=1 LUT6=3)
  Clock Path Skew:        2.435ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.435ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.253ns (routing 0.690ns, distribution 1.563ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFADC1_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[12])
                                                                    0.611     0.611 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[12]
                                       net (fo=1, routed)           0.524     1.135    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc1_common_stat[12]
    Routing       SLICE_X112Y89                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_36/I3
    Routing       SLICE_X112Y89        LUT6 (Prop_H6LUT_SLICEM_I3_O)
                                                                    0.125     1.260 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_36/O
                                       net (fo=1, routed)           0.061     1.321    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_36_n_0
    Routing       SLICE_X112Y89                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_18/I5
    Routing       SLICE_X112Y89        LUT6 (Prop_B6LUT_SLICEM_I5_O)
                                                                    0.149     1.470 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_18/O
                                       net (fo=1, routed)           0.148     1.618    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_18_n_0
    Routing       SLICE_X112Y92                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_5/I1
    Routing       SLICE_X112Y92        LUT3 (Prop_F6LUT_SLICEM_I1_O)
                                                                    0.037     1.655 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_5/O
                                       net (fo=1, routed)           0.193     1.848    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_5_n_0
    Routing       SLICE_X113Y95                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/I4
    Routing       SLICE_X113Y95        LUT6 (Prop_D6LUT_SLICEM_I4_O)
                                                                    0.088     1.936 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                                       net (fo=1, routed)           0.072     2.008    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    Routing       SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.253     2.435    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@3.906ns period=7.812ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.919ns  (logic 0.970ns (50.547%)  route 0.949ns (49.453%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        2.429ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.429ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.247ns (routing 0.690ns, distribution 1.557ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFADC1_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[9])
                                                                    0.532     0.532 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[9]
                                       net (fo=1, routed)           0.645     1.177    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc1_common_stat[9]
    Routing       SLICE_X112Y90                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_36/I3
    Routing       SLICE_X112Y90        LUT6 (Prop_A6LUT_SLICEM_I3_O)
                                                                    0.150     1.327 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_36/O
                                       net (fo=1, routed)           0.044     1.371    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_36_n_0
    Routing       SLICE_X112Y90                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_20/I2
    Routing       SLICE_X112Y90        LUT6 (Prop_B6LUT_SLICEM_I2_O)
                                                                    0.089     1.460 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_20/O
                                       net (fo=1, routed)           0.099     1.559    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_20_n_0
    Routing       SLICE_X112Y92                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_6/I5
    Routing       SLICE_X112Y92        LUT6 (Prop_H6LUT_SLICEM_I5_O)
                                                                    0.101     1.660 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_6/O
                                       net (fo=1, routed)           0.095     1.755    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_6_n_0
    Routing       SLICE_X112Y95                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/I4
    Routing       SLICE_X112Y95        LUT6 (Prop_C6LUT_SLICEM_I4_O)
                                                                    0.098     1.853 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                                       net (fo=1, routed)           0.066     1.919    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    Routing       SLICE_X112Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.247     2.429    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X112Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@3.906ns period=7.812ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.872ns  (logic 0.872ns (46.581%)  route 1.000ns (53.419%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        2.445ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.445ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.263ns (routing 0.690ns, distribution 1.573ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFADC1_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[10])
                                                                    0.536     0.536 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[10]
                                       net (fo=1, routed)           0.482     1.018    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc1_common_stat[10]
    Routing       SLICE_X111Y92                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_29/I3
    Placement     SLICE_X111Y92        LUT6 (Prop_G6LUT_SLICEL_I3_O)
                                                                    0.097     1.115 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_29/O
                                       net (fo=1, routed)           0.044     1.159    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_29_n_0
    Placement     SLICE_X111Y92                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_15/I2
    Routing       SLICE_X111Y92        LUT6 (Prop_H6LUT_SLICEL_I2_O)
                                                                    0.051     1.210 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_15/O
                                       net (fo=1, routed)           0.212     1.422    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_15_n_0
    Routing       SLICE_X113Y92                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_5/I0
    Routing       SLICE_X113Y92        LUT6 (Prop_G6LUT_SLICEM_I0_O)
                                                                    0.100     1.522 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_5/O
                                       net (fo=1, routed)           0.190     1.712    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_5_n_0
    Routing       SLICE_X113Y96                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/I4
    Routing       SLICE_X113Y96        LUT6 (Prop_D6LUT_SLICEM_I4_O)
                                                                    0.088     1.800 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                                       net (fo=1, routed)           0.072     1.872    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    Routing       SLICE_X113Y96        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.263     2.445    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X113Y96        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@3.906ns period=7.812ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.837ns  (logic 0.418ns (49.940%)  route 0.419ns (50.060%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        1.700ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.700ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.553ns (routing 0.463ns, distribution 1.090ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFADC1_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[8])
                                                                    0.237     0.237 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[8]
                                       net (fo=1, routed)           0.184     0.421    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc1_common_stat[8]
    Routing       SLICE_X116Y92                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_24/I3
    Routing       SLICE_X116Y92        LUT6 (Prop_F6LUT_SLICEL_I3_O)
                                                                    0.059     0.480 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_24/O
                                       net (fo=1, routed)           0.100     0.580    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_24_n_0
    Routing       SLICE_X111Y92                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_13/I2
    Routing       SLICE_X111Y92        LUT6 (Prop_B6LUT_SLICEL_I2_O)
                                                                    0.060     0.640 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_13/O
                                       net (fo=1, routed)           0.047     0.687    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_13_n_0
    Routing       SLICE_X111Y93                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_5/I0
    Routing       SLICE_X111Y93        LUT6 (Prop_G6LUT_SLICEL_I0_O)
                                                                    0.040     0.727 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_5/O
                                       net (fo=1, routed)           0.071     0.798    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_5_n_0
    Routing       SLICE_X111Y94                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/I4
    Routing       SLICE_X111Y94        LUT6 (Prop_C6LUT_SLICEL_I4_O)
                                                                    0.022     0.820 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                                       net (fo=1, routed)           0.017     0.837    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    Routing       SLICE_X111Y94        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.553     1.700    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X111Y94        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@3.906ns period=7.812ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.839ns  (logic 0.404ns (48.153%)  route 0.435ns (51.847%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        1.702ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.702ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.555ns (routing 0.463ns, distribution 1.092ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFADC1_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[9])
                                                                    0.228     0.228 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[9]
                                       net (fo=1, routed)           0.285     0.513    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc1_common_stat[9]
    Routing       SLICE_X112Y90                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_36/I3
    Routing       SLICE_X112Y90        LUT6 (Prop_A6LUT_SLICEM_I3_O)
                                                                    0.060     0.573 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_36/O
                                       net (fo=1, routed)           0.024     0.597    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_36_n_0
    Routing       SLICE_X112Y90                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_20/I2
    Routing       SLICE_X112Y90        LUT6 (Prop_B6LUT_SLICEM_I2_O)
                                                                    0.035     0.632 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_20/O
                                       net (fo=1, routed)           0.052     0.684    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_20_n_0
    Routing       SLICE_X112Y92                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_6/I5
    Routing       SLICE_X112Y92        LUT6 (Prop_H6LUT_SLICEM_I5_O)
                                                                    0.041     0.725 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_6/O
                                       net (fo=1, routed)           0.050     0.775    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_6_n_0
    Routing       SLICE_X112Y95                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/I4
    Routing       SLICE_X112Y95        LUT6 (Prop_C6LUT_SLICEM_I4_O)
                                                                    0.040     0.815 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                                       net (fo=1, routed)           0.024     0.839    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    Routing       SLICE_X112Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.555     1.702    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X112Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@3.906ns period=7.812ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.843ns  (logic 0.365ns (43.298%)  route 0.478ns (56.702%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        1.717ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.717ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.570ns (routing 0.463ns, distribution 1.107ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFADC1_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[10])
                                                                    0.227     0.227 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[10]
                                       net (fo=1, routed)           0.224     0.451    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc1_common_stat[10]
    Routing       SLICE_X111Y92                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_29/I3
    Placement     SLICE_X111Y92        LUT6 (Prop_G6LUT_SLICEL_I3_O)
                                                                    0.040     0.491 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_29/O
                                       net (fo=1, routed)           0.024     0.515    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_29_n_0
    Placement     SLICE_X111Y92                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_15/I2
    Routing       SLICE_X111Y92        LUT6 (Prop_H6LUT_SLICEL_I2_O)
                                                                    0.023     0.538 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_15/O
                                       net (fo=1, routed)           0.106     0.644    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_15_n_0
    Routing       SLICE_X113Y92                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_5/I0
    Routing       SLICE_X113Y92        LUT6 (Prop_G6LUT_SLICEM_I0_O)
                                                                    0.040     0.684 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_5/O
                                       net (fo=1, routed)           0.098     0.782    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_5_n_0
    Routing       SLICE_X113Y96                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/I4
    Routing       SLICE_X113Y96        LUT6 (Prop_D6LUT_SLICEM_I4_O)
                                                                    0.035     0.817 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                                       net (fo=1, routed)           0.026     0.843    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    Routing       SLICE_X113Y96        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.570     1.717    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X113Y96        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@3.906ns period=7.812ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.921ns  (logic 0.434ns (47.123%)  route 0.487ns (52.877%))
  Logic Levels:           4  (LUT3=1 LUT6=3)
  Clock Path Skew:        1.707ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.707ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.560ns (routing 0.463ns, distribution 1.097ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFADC1_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[12])
                                                                    0.274     0.274 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[12]
                                       net (fo=1, routed)           0.246     0.520    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc1_common_stat[12]
    Routing       SLICE_X112Y89                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_36/I3
    Routing       SLICE_X112Y89        LUT6 (Prop_H6LUT_SLICEM_I3_O)
                                                                    0.051     0.571 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_36/O
                                       net (fo=1, routed)           0.034     0.605    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_36_n_0
    Routing       SLICE_X112Y89                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_18/I5
    Routing       SLICE_X112Y89        LUT6 (Prop_B6LUT_SLICEM_I5_O)
                                                                    0.060     0.665 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_18/O
                                       net (fo=1, routed)           0.080     0.745    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_18_n_0
    Routing       SLICE_X112Y92                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_5/I1
    Routing       SLICE_X112Y92        LUT3 (Prop_F6LUT_SLICEM_I1_O)
                                                                    0.014     0.759 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_5/O
                                       net (fo=1, routed)           0.101     0.860    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_5_n_0
    Routing       SLICE_X113Y95                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/I4
    Routing       SLICE_X113Y95        LUT6 (Prop_D6LUT_SLICEM_I4_O)
                                                                    0.035     0.895 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                                       net (fo=1, routed)           0.026     0.921    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    Routing       SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.560     1.707    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@3.906ns period=7.812ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.956ns  (logic 0.393ns (41.109%)  route 0.563ns (58.891%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        1.705ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.705ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.558ns (routing 0.463ns, distribution 1.095ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFADC1_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[14])
                                                                    0.285     0.285 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[14]
                                       net (fo=1, routed)           0.287     0.572    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc1_common_stat[14]
    Routing       SLICE_X112Y86                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_53/I2
    Routing       SLICE_X112Y86        LUT6 (Prop_B6LUT_SLICEM_I2_O)
                                                                    0.050     0.622 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_53/O
                                       net (fo=1, routed)           0.044     0.666    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_53_n_0
    Routing       SLICE_X112Y86                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_24/I1
    Routing       SLICE_X112Y86        LUT6 (Prop_C6LUT_SLICEM_I1_O)
                                                                    0.014     0.680 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_24/O
                                       net (fo=1, routed)           0.157     0.837    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_24_n_0
    Routing       SLICE_X114Y89                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6/I4
    Routing       SLICE_X114Y89        LUT6 (Prop_G6LUT_SLICEL_I4_O)
                                                                    0.022     0.859 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6/O
                                       net (fo=1, routed)           0.058     0.917    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6_n_0
    Routing       SLICE_X114Y91                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/I4
    Routing       SLICE_X114Y91        LUT6 (Prop_C6LUT_SLICEL_I4_O)
                                                                    0.022     0.939 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                                       net (fo=1, routed)           0.017     0.956    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    Routing       SLICE_X114Y91        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.558     1.705    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X114Y91        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@3.906ns period=7.812ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.975ns  (logic 0.423ns (43.385%)  route 0.552ns (56.615%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        1.715ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.715ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.568ns (routing 0.463ns, distribution 1.105ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFADC1_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[11])
                                                                    0.265     0.265 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[11]
                                       net (fo=1, routed)           0.293     0.558    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc1_common_stat[11]
    Routing       SLICE_X110Y86                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_33/I3
    Routing       SLICE_X110Y86        LUT6 (Prop_G6LUT_SLICEM_I3_O)
                                                                    0.060     0.618 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_33/O
                                       net (fo=1, routed)           0.026     0.644    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_33_n_0
    Routing       SLICE_X110Y86                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_17/I2
    Routing       SLICE_X110Y86        LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                                    0.041     0.685 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_17/O
                                       net (fo=1, routed)           0.165     0.850    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_17_n_0
    Routing       SLICE_X113Y93                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_5/I0
    Placement     SLICE_X113Y93        LUT6 (Prop_H6LUT_SLICEM_I0_O)
                                                                    0.035     0.885 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_5/O
                                       net (fo=1, routed)           0.042     0.927    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_5_n_0
    Placement     SLICE_X113Y93                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/I4
    Routing       SLICE_X113Y93        LUT6 (Prop_D6LUT_SLICEM_I4_O)
                                                                    0.022     0.949 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                                       net (fo=1, routed)           0.026     0.975    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    Routing       SLICE_X113Y93        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.568     1.715    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X113Y93        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@3.906ns period=7.812ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.066ns  (logic 0.388ns (36.398%)  route 0.678ns (63.602%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        1.698ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.698ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.551ns (routing 0.463ns, distribution 1.088ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFADC1_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[13])
                                                                    0.241     0.241 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[13]
                                       net (fo=1, routed)           0.367     0.608    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc1_common_stat[13]
    Routing       SLICE_X113Y87                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_31/I3
    Routing       SLICE_X113Y87        LUT6 (Prop_H6LUT_SLICEM_I3_O)
                                                                    0.061     0.669 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_31/O
                                       net (fo=1, routed)           0.119     0.788    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_31_n_0
    Routing       SLICE_X111Y87                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_18/I5
    Routing       SLICE_X111Y87        LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                                    0.041     0.829 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_18/O
                                       net (fo=1, routed)           0.120     0.949    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_18_n_0
    Routing       SLICE_X112Y90                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_4/I5
    Placement     SLICE_X112Y90        LUT6 (Prop_G6LUT_SLICEM_I5_O)
                                                                    0.022     0.971 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_4/O
                                       net (fo=1, routed)           0.051     1.022    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_4_n_0
    Placement     SLICE_X112Y91                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/I2
    Routing       SLICE_X112Y91        LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                                    0.023     1.045 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                                       net (fo=1, routed)           0.021     1.066    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    Routing       SLICE_X112Y91        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.551     1.698    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X112Y91        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@3.906ns period=7.812ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.163ns  (logic 0.429ns (36.887%)  route 0.734ns (63.113%))
  Logic Levels:           5  (LUT6=5)
  Clock Path Skew:        1.707ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.707ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.560ns (routing 0.463ns, distribution 1.097ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFADC1_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[15])
                                                                    0.250     0.250 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[15]
                                       net (fo=1, routed)           0.351     0.601    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc1_common_stat[15]
    Routing       SLICE_X111Y86                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_81/I2
    Routing       SLICE_X111Y86        LUT6 (Prop_G6LUT_SLICEL_I2_O)
                                                                    0.060     0.661 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_81/O
                                       net (fo=1, routed)           0.065     0.726    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_81_n_0
    Routing       SLICE_X111Y86                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_52/I2
    Routing       SLICE_X111Y86        LUT6 (Prop_C6LUT_SLICEL_I2_O)
                                                                    0.022     0.748 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_52/O
                                       net (fo=1, routed)           0.042     0.790    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_52_n_0
    Routing       SLICE_X111Y86                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_20/I2
    Routing       SLICE_X111Y86        LUT6 (Prop_H6LUT_SLICEL_I2_O)
                                                                    0.035     0.825 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_20/O
                                       net (fo=1, routed)           0.184     1.009    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_20_n_0
    Routing       SLICE_X114Y94                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_6/I0
    Routing       SLICE_X114Y94        LUT6 (Prop_G6LUT_SLICEL_I0_O)
                                                                    0.040     1.049 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_6/O
                                       net (fo=1, routed)           0.068     1.117    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_6_n_0
    Routing       SLICE_X113Y95                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/I4
    Routing       SLICE_X113Y95        LUT6 (Prop_C6LUT_SLICEM_I4_O)
                                                                    0.022     1.139 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                                       net (fo=1, routed)           0.024     1.163    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    Routing       SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.560     1.707    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFADC2_CLK
  To Clock:  clk_pl_0

Max Delay             8 Endpoints
Min Delay             8 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.105ns  (logic 1.162ns (37.424%)  route 1.943ns (62.576%))
  Logic Levels:           5  (LUT4=2 LUT6=3)
  Clock Path Skew:        2.429ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.429ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.247ns (routing 0.690ns, distribution 1.557ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFADC2_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[8])
                                                                    0.788     0.788 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[8]
                                       net (fo=1, routed)           1.090     1.878    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc2_common_stat[8]
    Routing       SLICE_X114Y90                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_27/I0
    Routing       SLICE_X114Y90        LUT4 (Prop_E6LUT_SLICEL_I0_O)
                                                                    0.035     1.913 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_27/O
                                       net (fo=1, routed)           0.192     2.105    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_27_n_0
    Routing       SLICE_X114Y90                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_26/I0
    Routing       SLICE_X114Y90        LUT4 (Prop_F6LUT_SLICEL_I0_O)
                                                                    0.148     2.253 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_26/O
                                       net (fo=1, routed)           0.269     2.522    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_26_n_0
    Routing       SLICE_X113Y92                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_14/I1
    Routing       SLICE_X113Y92        LUT6 (Prop_B6LUT_SLICEM_I1_O)
                                                                    0.052     2.574 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_14/O
                                       net (fo=1, routed)           0.202     2.776    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_14_n_0
    Routing       SLICE_X111Y93                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_5/I2
    Routing       SLICE_X111Y93        LUT6 (Prop_G6LUT_SLICEL_I2_O)
                                                                    0.089     2.865 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_5/O
                                       net (fo=1, routed)           0.140     3.005    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_5_n_0
    Routing       SLICE_X111Y94                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/I4
    Routing       SLICE_X111Y94        LUT6 (Prop_C6LUT_SLICEL_I4_O)
                                                                    0.050     3.055 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                                       net (fo=1, routed)           0.050     3.105    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    Routing       SLICE_X111Y94        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.247     2.429    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X111Y94        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.525ns  (logic 1.035ns (40.990%)  route 1.490ns (59.010%))
  Logic Levels:           5  (LUT4=1 LUT5=1 LUT6=3)
  Clock Path Skew:        2.432ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.432ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.250ns (routing 0.690ns, distribution 1.560ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFADC2_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[14])
                                                                    0.698     0.698 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[14]
                                       net (fo=1, routed)           1.110     1.808    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc2_common_stat[14]
    Routing       SLICE_X115Y88                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_68/I2
    Placement     SLICE_X115Y88        LUT4 (Prop_F6LUT_SLICEM_I2_O)
                                                                    0.037     1.845 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_68/O
                                       net (fo=1, routed)           0.040     1.885    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_68_n_0
    Placement     SLICE_X115Y88                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_46/I2
    Routing       SLICE_X115Y88        LUT5 (Prop_G6LUT_SLICEM_I2_O)
                                                                    0.037     1.922 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_46/O
                                       net (fo=1, routed)           0.090     2.012    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_46_n_0
    Routing       SLICE_X114Y88                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_22/I2
    Routing       SLICE_X114Y88        LUT6 (Prop_H6LUT_SLICEL_I2_O)
                                                                    0.090     2.102 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_22/O
                                       net (fo=1, routed)           0.091     2.193    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_22_n_0
    Routing       SLICE_X114Y89                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6/I2
    Routing       SLICE_X114Y89        LUT6 (Prop_G6LUT_SLICEL_I2_O)
                                                                    0.123     2.316 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6/O
                                       net (fo=1, routed)           0.109     2.425    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6_n_0
    Routing       SLICE_X114Y91                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/I4
    Routing       SLICE_X114Y91        LUT6 (Prop_C6LUT_SLICEL_I4_O)
                                                                    0.050     2.475 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                                       net (fo=1, routed)           0.050     2.525    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    Routing       SLICE_X114Y91        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.250     2.432    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X114Y91        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.494ns  (logic 0.916ns (36.728%)  route 1.578ns (63.272%))
  Logic Levels:           5  (LUT4=2 LUT6=3)
  Clock Path Skew:        2.445ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.445ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.263ns (routing 0.690ns, distribution 1.573ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFADC2_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[10])
                                                                    0.536     0.536 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[10]
                                       net (fo=1, routed)           0.974     1.510    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc2_common_stat[10]
    Routing       SLICE_X113Y88                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_32/I0
    Routing       SLICE_X113Y88        LUT4 (Prop_B6LUT_SLICEM_I0_O)
                                                                    0.052     1.562 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_32/O
                                       net (fo=1, routed)           0.085     1.647    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_32_n_0
    Routing       SLICE_X113Y89                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_31/I0
    Routing       SLICE_X113Y89        LUT4 (Prop_C6LUT_SLICEM_I0_O)
                                                                    0.051     1.698 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_31/O
                                       net (fo=1, routed)           0.215     1.913    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_31_n_0
    Routing       SLICE_X113Y92                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_16/I1
    Placement     SLICE_X113Y92        LUT6 (Prop_H6LUT_SLICEM_I1_O)
                                                                    0.152     2.065 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_16/O
                                       net (fo=1, routed)           0.042     2.107    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_16_n_0
    Placement     SLICE_X113Y92                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_5/I2
    Routing       SLICE_X113Y92        LUT6 (Prop_G6LUT_SLICEM_I2_O)
                                                                    0.037     2.144 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_5/O
                                       net (fo=1, routed)           0.190     2.334    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_5_n_0
    Routing       SLICE_X113Y96                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/I4
    Routing       SLICE_X113Y96        LUT6 (Prop_D6LUT_SLICEM_I4_O)
                                                                    0.088     2.422 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                                       net (fo=1, routed)           0.072     2.494    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    Routing       SLICE_X113Y96        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.263     2.445    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X113Y96        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.466ns  (logic 0.836ns (33.901%)  route 1.630ns (66.099%))
  Logic Levels:           5  (LUT4=1 LUT5=1 LUT6=3)
  Clock Path Skew:        2.435ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.435ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.253ns (routing 0.690ns, distribution 1.563ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFADC2_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[15])
                                                                    0.525     0.525 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[15]
                                       net (fo=1, routed)           1.012     1.537    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc2_common_stat[15]
    Routing       SLICE_X115Y89                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_88/I2
    Routing       SLICE_X115Y89        LUT4 (Prop_B6LUT_SLICEM_I2_O)
                                                                    0.037     1.574 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_88/O
                                       net (fo=1, routed)           0.091     1.665    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_88_n_0
    Routing       SLICE_X115Y89                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_57/I2
    Routing       SLICE_X115Y89        LUT5 (Prop_C6LUT_SLICEM_I2_O)
                                                                    0.098     1.763 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_57/O
                                       net (fo=1, routed)           0.137     1.900    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_57_n_0
    Routing       SLICE_X114Y88                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_21/I1
    Routing       SLICE_X114Y88        LUT6 (Prop_D6LUT_SLICEL_I1_O)
                                                                    0.036     1.936 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_21/O
                                       net (fo=1, routed)           0.187     2.123    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_21_n_0
    Routing       SLICE_X114Y94                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_6/I1
    Routing       SLICE_X114Y94        LUT6 (Prop_G6LUT_SLICEL_I1_O)
                                                                    0.089     2.212 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_6/O
                                       net (fo=1, routed)           0.137     2.349    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_6_n_0
    Routing       SLICE_X113Y95                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/I4
    Routing       SLICE_X113Y95        LUT6 (Prop_C6LUT_SLICEM_I4_O)
                                                                    0.051     2.400 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                                       net (fo=1, routed)           0.066     2.466    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    Routing       SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.253     2.435    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.461ns  (logic 1.085ns (44.088%)  route 1.376ns (55.912%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        2.423ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.423ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.241ns (routing 0.690ns, distribution 1.551ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFADC2_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[13])
                                                                    0.771     0.771 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[13]
                                       net (fo=1, routed)           0.995     1.766    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc2_common_stat[13]
    Routing       SLICE_X113Y89                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_29/I4
    Routing       SLICE_X113Y89        LUT5 (Prop_D6LUT_SLICEM_I4_O)
                                                                    0.037     1.803 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_29/O
                                       net (fo=1, routed)           0.045     1.848    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_29_n_0
    Routing       SLICE_X113Y89                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_15/I5
    Routing       SLICE_X113Y89        LUT6 (Prop_H6LUT_SLICEM_I5_O)
                                                                    0.101     1.949 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_15/O
                                       net (fo=1, routed)           0.187     2.136    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_15_n_0
    Routing       SLICE_X112Y90                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_4/I2
    Placement     SLICE_X112Y90        LUT6 (Prop_G6LUT_SLICEM_I2_O)
                                                                    0.123     2.259 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_4/O
                                       net (fo=1, routed)           0.091     2.350    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_4_n_0
    Placement     SLICE_X112Y91                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/I2
    Routing       SLICE_X112Y91        LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                                    0.053     2.403 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                                       net (fo=1, routed)           0.058     2.461    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    Routing       SLICE_X112Y91        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.241     2.423    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X112Y91        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.315ns  (logic 0.947ns (40.907%)  route 1.368ns (59.093%))
  Logic Levels:           4  (LUT3=1 LUT6=3)
  Clock Path Skew:        2.435ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.435ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.253ns (routing 0.690ns, distribution 1.563ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFADC2_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[12])
                                                                    0.611     0.611 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[12]
                                       net (fo=1, routed)           0.909     1.520    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc2_common_stat[12]
    Routing       SLICE_X113Y91                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_35/I3
    Routing       SLICE_X113Y91        LUT6 (Prop_D6LUT_SLICEM_I3_O)
                                                                    0.037     1.557 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_35/O
                                       net (fo=1, routed)           0.087     1.644    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_35_n_0
    Routing       SLICE_X113Y92                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_17/I0
    Routing       SLICE_X113Y92        LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                                    0.088     1.732 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_17/O
                                       net (fo=1, routed)           0.107     1.839    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_17_n_0
    Routing       SLICE_X112Y92                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_5/I0
    Routing       SLICE_X112Y92        LUT3 (Prop_F6LUT_SLICEM_I0_O)
                                                                    0.123     1.962 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_5/O
                                       net (fo=1, routed)           0.193     2.155    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_5_n_0
    Routing       SLICE_X113Y95                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/I4
    Routing       SLICE_X113Y95        LUT6 (Prop_D6LUT_SLICEM_I4_O)
                                                                    0.088     2.243 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                                       net (fo=1, routed)           0.072     2.315    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    Routing       SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.253     2.435    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.221ns  (logic 0.877ns (39.487%)  route 1.344ns (60.513%))
  Logic Levels:           5  (LUT4=2 LUT6=3)
  Clock Path Skew:        2.441ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.441ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.259ns (routing 0.690ns, distribution 1.569ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFADC2_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[11])
                                                                    0.588     0.588 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[11]
                                       net (fo=1, routed)           0.912     1.500    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc2_common_stat[11]
    Routing       SLICE_X114Y90                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_39/I0
    Routing       SLICE_X114Y90        LUT4 (Prop_G6LUT_SLICEL_I0_O)
                                                                    0.050     1.550 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_39/O
                                       net (fo=1, routed)           0.043     1.593    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_39_n_0
    Routing       SLICE_X114Y90                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_35/I0
    Routing       SLICE_X114Y90        LUT4 (Prop_H6LUT_SLICEL_I0_O)
                                                                    0.099     1.692 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_35/O
                                       net (fo=1, routed)           0.096     1.788    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_35_n_0
    Routing       SLICE_X114Y92                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_18/I1
    Routing       SLICE_X114Y92        LUT6 (Prop_G6LUT_SLICEL_I1_O)
                                                                    0.050     1.838 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_18/O
                                       net (fo=1, routed)           0.137     1.975    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_18_n_0
    Routing       SLICE_X113Y93                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_5/I2
    Placement     SLICE_X113Y93        LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                                    0.039     2.014 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_5/O
                                       net (fo=1, routed)           0.084     2.098    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_5_n_0
    Placement     SLICE_X113Y93                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/I4
    Routing       SLICE_X113Y93        LUT6 (Prop_D6LUT_SLICEM_I4_O)
                                                                    0.051     2.149 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                                       net (fo=1, routed)           0.072     2.221    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    Routing       SLICE_X113Y93        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.259     2.441    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X113Y93        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.179ns  (logic 0.803ns (36.852%)  route 1.376ns (63.148%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        2.429ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.429ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.247ns (routing 0.690ns, distribution 1.557ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFADC2_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[9])
                                                                    0.532     0.532 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[9]
                                       net (fo=1, routed)           0.988     1.520    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc2_common_stat[9]
    Routing       SLICE_X114Y91                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_33/I4
    Routing       SLICE_X114Y91        LUT5 (Prop_F6LUT_SLICEL_I4_O)
                                                                    0.097     1.617 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_33/O
                                       net (fo=1, routed)           0.126     1.743    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_33_n_0
    Routing       SLICE_X113Y92                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_19/I3
    Placement     SLICE_X113Y92        LUT6 (Prop_F6LUT_SLICEM_I3_O)
                                                                    0.037     1.780 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_19/O
                                       net (fo=1, routed)           0.101     1.881    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_19_n_0
    Placement     SLICE_X112Y92                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_6/I3
    Routing       SLICE_X112Y92        LUT6 (Prop_H6LUT_SLICEM_I3_O)
                                                                    0.039     1.920 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_6/O
                                       net (fo=1, routed)           0.095     2.015    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_6_n_0
    Routing       SLICE_X112Y95                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/I4
    Routing       SLICE_X112Y95        LUT6 (Prop_C6LUT_SLICEM_I4_O)
                                                                    0.098     2.113 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                                       net (fo=1, routed)           0.066     2.179    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    Routing       SLICE_X112Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.247     2.429    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X112Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.021ns  (logic 0.337ns (33.007%)  route 0.684ns (66.993%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.702ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.702ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.555ns (routing 0.463ns, distribution 1.092ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFADC2_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[9])
                                                                    0.228     0.228 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[9]
                                       net (fo=1, routed)           0.489     0.717    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc2_common_stat[9]
    Routing       SLICE_X114Y91                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_33/I4
    Routing       SLICE_X114Y91        LUT5 (Prop_F6LUT_SLICEL_I4_O)
                                                                    0.040     0.757 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_33/O
                                       net (fo=1, routed)           0.066     0.823    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_33_n_0
    Routing       SLICE_X113Y92                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_19/I3
    Placement     SLICE_X113Y92        LUT6 (Prop_F6LUT_SLICEM_I3_O)
                                                                    0.014     0.837 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_19/O
                                       net (fo=1, routed)           0.055     0.892    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_19_n_0
    Placement     SLICE_X112Y92                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_6/I3
    Routing       SLICE_X112Y92        LUT6 (Prop_H6LUT_SLICEM_I3_O)
                                                                    0.015     0.907 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_6/O
                                       net (fo=1, routed)           0.050     0.957    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_6_n_0
    Routing       SLICE_X112Y95                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/I4
    Routing       SLICE_X112Y95        LUT6 (Prop_C6LUT_SLICEM_I4_O)
                                                                    0.040     0.997 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                                       net (fo=1, routed)           0.024     1.021    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    Routing       SLICE_X112Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.555     1.702    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X112Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.049ns  (logic 0.387ns (36.892%)  route 0.662ns (63.108%))
  Logic Levels:           5  (LUT4=2 LUT6=3)
  Clock Path Skew:        1.715ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.715ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.568ns (routing 0.463ns, distribution 1.105ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFADC2_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[11])
                                                                    0.265     0.265 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[11]
                                       net (fo=1, routed)           0.449     0.714    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc2_common_stat[11]
    Routing       SLICE_X114Y90                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_39/I0
    Routing       SLICE_X114Y90        LUT4 (Prop_G6LUT_SLICEL_I0_O)
                                                                    0.022     0.736 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_39/O
                                       net (fo=1, routed)           0.024     0.760    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_39_n_0
    Routing       SLICE_X114Y90                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_35/I0
    Routing       SLICE_X114Y90        LUT4 (Prop_H6LUT_SLICEL_I0_O)
                                                                    0.041     0.801 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_35/O
                                       net (fo=1, routed)           0.051     0.852    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_35_n_0
    Routing       SLICE_X114Y92                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_18/I1
    Routing       SLICE_X114Y92        LUT6 (Prop_G6LUT_SLICEL_I1_O)
                                                                    0.022     0.874 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_18/O
                                       net (fo=1, routed)           0.070     0.944    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_18_n_0
    Routing       SLICE_X113Y93                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_5/I2
    Placement     SLICE_X113Y93        LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                                    0.015     0.959 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_5/O
                                       net (fo=1, routed)           0.042     1.001    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_5_n_0
    Placement     SLICE_X113Y93                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/I4
    Routing       SLICE_X113Y93        LUT6 (Prop_D6LUT_SLICEM_I4_O)
                                                                    0.022     1.023 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                                       net (fo=1, routed)           0.026     1.049    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    Routing       SLICE_X113Y93        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.568     1.715    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X113Y93        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.058ns  (logic 0.369ns (34.877%)  route 0.689ns (65.123%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.698ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.698ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.551ns (routing 0.463ns, distribution 1.088ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFADC2_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[13])
                                                                    0.241     0.241 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[13]
                                       net (fo=1, routed)           0.495     0.736    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc2_common_stat[13]
    Routing       SLICE_X113Y89                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_29/I4
    Routing       SLICE_X113Y89        LUT5 (Prop_D6LUT_SLICEM_I4_O)
                                                                    0.014     0.750 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_29/O
                                       net (fo=1, routed)           0.025     0.775    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_29_n_0
    Routing       SLICE_X113Y89                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_15/I5
    Routing       SLICE_X113Y89        LUT6 (Prop_H6LUT_SLICEM_I5_O)
                                                                    0.041     0.816 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_15/O
                                       net (fo=1, routed)           0.097     0.913    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_15_n_0
    Routing       SLICE_X112Y90                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_4/I2
    Placement     SLICE_X112Y90        LUT6 (Prop_G6LUT_SLICEM_I2_O)
                                                                    0.050     0.963 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_4/O
                                       net (fo=1, routed)           0.051     1.014    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_4_n_0
    Placement     SLICE_X112Y91                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/I2
    Routing       SLICE_X112Y91        LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                                    0.023     1.037 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                                       net (fo=1, routed)           0.021     1.058    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    Routing       SLICE_X112Y91        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.551     1.698    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X112Y91        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.088ns  (logic 0.408ns (37.500%)  route 0.680ns (62.500%))
  Logic Levels:           4  (LUT3=1 LUT6=3)
  Clock Path Skew:        1.707ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.707ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.560ns (routing 0.463ns, distribution 1.097ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFADC2_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[12])
                                                                    0.274     0.274 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[12]
                                       net (fo=1, routed)           0.448     0.722    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc2_common_stat[12]
    Routing       SLICE_X113Y91                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_35/I3
    Routing       SLICE_X113Y91        LUT6 (Prop_D6LUT_SLICEM_I3_O)
                                                                    0.014     0.736 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_35/O
                                       net (fo=1, routed)           0.047     0.783    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_35_n_0
    Routing       SLICE_X113Y92                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_17/I0
    Routing       SLICE_X113Y92        LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                                    0.035     0.818 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_17/O
                                       net (fo=1, routed)           0.058     0.876    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_17_n_0
    Routing       SLICE_X112Y92                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_5/I0
    Routing       SLICE_X112Y92        LUT3 (Prop_F6LUT_SLICEM_I0_O)
                                                                    0.050     0.926 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_5/O
                                       net (fo=1, routed)           0.101     1.027    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_5_n_0
    Routing       SLICE_X113Y95                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/I4
    Routing       SLICE_X113Y95        LUT6 (Prop_D6LUT_SLICEM_I4_O)
                                                                    0.035     1.062 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                                       net (fo=1, routed)           0.026     1.088    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    Routing       SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.560     1.707    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.134ns  (logic 0.420ns (37.037%)  route 0.714ns (62.963%))
  Logic Levels:           5  (LUT4=1 LUT5=1 LUT6=3)
  Clock Path Skew:        1.705ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.705ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.558ns (routing 0.463ns, distribution 1.095ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFADC2_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[14])
                                                                    0.285     0.285 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[14]
                                       net (fo=1, routed)           0.519     0.804    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc2_common_stat[14]
    Routing       SLICE_X115Y88                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_68/I2
    Placement     SLICE_X115Y88        LUT4 (Prop_F6LUT_SLICEM_I2_O)
                                                                    0.014     0.818 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_68/O
                                       net (fo=1, routed)           0.023     0.841    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_68_n_0
    Placement     SLICE_X115Y88                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_46/I2
    Routing       SLICE_X115Y88        LUT5 (Prop_G6LUT_SLICEM_I2_O)
                                                                    0.014     0.855 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_46/O
                                       net (fo=1, routed)           0.048     0.903    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_46_n_0
    Routing       SLICE_X114Y88                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_22/I2
    Routing       SLICE_X114Y88        LUT6 (Prop_H6LUT_SLICEL_I2_O)
                                                                    0.035     0.938 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_22/O
                                       net (fo=1, routed)           0.049     0.987    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_22_n_0
    Routing       SLICE_X114Y89                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6/I2
    Routing       SLICE_X114Y89        LUT6 (Prop_G6LUT_SLICEL_I2_O)
                                                                    0.050     1.037 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6/O
                                       net (fo=1, routed)           0.058     1.095    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6_n_0
    Routing       SLICE_X114Y91                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/I4
    Routing       SLICE_X114Y91        LUT6 (Prop_C6LUT_SLICEL_I4_O)
                                                                    0.022     1.117 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                                       net (fo=1, routed)           0.017     1.134    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    Routing       SLICE_X114Y91        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.558     1.705    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X114Y91        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.149ns  (logic 0.375ns (32.637%)  route 0.774ns (67.363%))
  Logic Levels:           5  (LUT4=1 LUT5=1 LUT6=3)
  Clock Path Skew:        1.707ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.707ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.560ns (routing 0.463ns, distribution 1.097ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFADC2_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[15])
                                                                    0.250     0.250 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[15]
                                       net (fo=1, routed)           0.472     0.722    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc2_common_stat[15]
    Routing       SLICE_X115Y89                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_88/I2
    Routing       SLICE_X115Y89        LUT4 (Prop_B6LUT_SLICEM_I2_O)
                                                                    0.014     0.736 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_88/O
                                       net (fo=1, routed)           0.044     0.780    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_88_n_0
    Routing       SLICE_X115Y89                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_57/I2
    Routing       SLICE_X115Y89        LUT5 (Prop_C6LUT_SLICEM_I2_O)
                                                                    0.040     0.820 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_57/O
                                       net (fo=1, routed)           0.072     0.892    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_57_n_0
    Routing       SLICE_X114Y88                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_21/I1
    Routing       SLICE_X114Y88        LUT6 (Prop_D6LUT_SLICEL_I1_O)
                                                                    0.014     0.906 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_21/O
                                       net (fo=1, routed)           0.094     1.000    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_21_n_0
    Routing       SLICE_X114Y94                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_6/I1
    Routing       SLICE_X114Y94        LUT6 (Prop_G6LUT_SLICEL_I1_O)
                                                                    0.035     1.035 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_6/O
                                       net (fo=1, routed)           0.068     1.103    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_6_n_0
    Routing       SLICE_X113Y95                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/I4
    Routing       SLICE_X113Y95        LUT6 (Prop_C6LUT_SLICEM_I4_O)
                                                                    0.022     1.125 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                                       net (fo=1, routed)           0.024     1.149    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    Routing       SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.560     1.707    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.166ns  (logic 0.381ns (32.676%)  route 0.785ns (67.324%))
  Logic Levels:           5  (LUT4=2 LUT6=3)
  Clock Path Skew:        1.717ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.717ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.570ns (routing 0.463ns, distribution 1.107ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFADC2_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[10])
                                                                    0.227     0.227 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[10]
                                       net (fo=1, routed)           0.482     0.709    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc2_common_stat[10]
    Routing       SLICE_X113Y88                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_32/I0
    Routing       SLICE_X113Y88        LUT4 (Prop_B6LUT_SLICEM_I0_O)
                                                                    0.022     0.731 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_32/O
                                       net (fo=1, routed)           0.047     0.778    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_32_n_0
    Routing       SLICE_X113Y89                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_31/I0
    Routing       SLICE_X113Y89        LUT4 (Prop_C6LUT_SLICEM_I0_O)
                                                                    0.022     0.800 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_31/O
                                       net (fo=1, routed)           0.108     0.908    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_31_n_0
    Routing       SLICE_X113Y92                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_16/I1
    Placement     SLICE_X113Y92        LUT6 (Prop_H6LUT_SLICEM_I1_O)
                                                                    0.061     0.969 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_16/O
                                       net (fo=1, routed)           0.024     0.993    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_16_n_0
    Placement     SLICE_X113Y92                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_5/I2
    Routing       SLICE_X113Y92        LUT6 (Prop_G6LUT_SLICEM_I2_O)
                                                                    0.014     1.007 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_5/O
                                       net (fo=1, routed)           0.098     1.105    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_5_n_0
    Routing       SLICE_X113Y96                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/I4
    Routing       SLICE_X113Y96        LUT6 (Prop_D6LUT_SLICEM_I4_O)
                                                                    0.035     1.140 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                                       net (fo=1, routed)           0.026     1.166    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    Routing       SLICE_X113Y96        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.570     1.717    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X113Y96        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.311ns  (logic 0.389ns (29.672%)  route 0.922ns (70.328%))
  Logic Levels:           5  (LUT4=2 LUT6=3)
  Clock Path Skew:        1.700ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.700ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.553ns (routing 0.463ns, distribution 1.090ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFADC2_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[8])
                                                                    0.237     0.237 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[8]
                                       net (fo=1, routed)           0.518     0.755    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc2_common_stat[8]
    Routing       SLICE_X114Y90                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_27/I0
    Routing       SLICE_X114Y90        LUT4 (Prop_E6LUT_SLICEL_I0_O)
                                                                    0.014     0.769 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_27/O
                                       net (fo=1, routed)           0.078     0.847    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_27_n_0
    Routing       SLICE_X114Y90                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_26/I0
    Routing       SLICE_X114Y90        LUT4 (Prop_F6LUT_SLICEL_I0_O)
                                                                    0.059     0.906 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_26/O
                                       net (fo=1, routed)           0.133     1.039    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_26_n_0
    Routing       SLICE_X113Y92                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_14/I1
    Routing       SLICE_X113Y92        LUT6 (Prop_B6LUT_SLICEM_I1_O)
                                                                    0.022     1.061 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_14/O
                                       net (fo=1, routed)           0.105     1.166    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_14_n_0
    Routing       SLICE_X111Y93                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_5/I2
    Routing       SLICE_X111Y93        LUT6 (Prop_G6LUT_SLICEL_I2_O)
                                                                    0.035     1.201 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_5/O
                                       net (fo=1, routed)           0.071     1.272    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_5_n_0
    Routing       SLICE_X111Y94                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/I4
    Routing       SLICE_X111Y94        LUT6 (Prop_C6LUT_SLICEL_I4_O)
                                                                    0.022     1.294 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                                       net (fo=1, routed)           0.017     1.311    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    Routing       SLICE_X111Y94        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.553     1.700    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X111Y94        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFADC3_CLK
  To Clock:  clk_pl_0

Max Delay             8 Endpoints
Min Delay             8 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.821ns  (logic 1.038ns (36.795%)  route 1.783ns (63.205%))
  Logic Levels:           4  (LUT4=1 LUT5=1 LUT6=2)
  Clock Path Skew:        2.429ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.429ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.247ns (routing 0.690ns, distribution 1.557ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFADC3_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[8])
                                                                    0.788     0.788 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[8]
                                       net (fo=1, routed)           1.280     2.068    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc3_common_stat[8]
    Routing       SLICE_X116Y97                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_21/I3
    Routing       SLICE_X116Y97        LUT5 (Prop_B6LUT_SLICEL_I3_O)
                                                                    0.090     2.158 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_21/O
                                       net (fo=1, routed)           0.139     2.297    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_21_n_0
    Routing       SLICE_X116Y97                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_12/I2
    Placement     SLICE_X116Y97        LUT6 (Prop_C6LUT_SLICEL_I2_O)
                                                                    0.035     2.332 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_12/O
                                       net (fo=1, routed)           0.043     2.375    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_12_n_0
    Placement     SLICE_X116Y97                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_4/I1
    Routing       SLICE_X116Y97        LUT4 (Prop_A6LUT_SLICEL_I1_O)
                                                                    0.090     2.465 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_4/O
                                       net (fo=1, routed)           0.271     2.736    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_4_n_0
    Routing       SLICE_X111Y94                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/I3
    Routing       SLICE_X111Y94        LUT6 (Prop_C6LUT_SLICEL_I3_O)
                                                                    0.035     2.771 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                                       net (fo=1, routed)           0.050     2.821    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    Routing       SLICE_X111Y94        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.247     2.429    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X111Y94        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.791ns  (logic 1.059ns (37.943%)  route 1.732ns (62.057%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        2.423ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.423ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.241ns (routing 0.690ns, distribution 1.551ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFADC3_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[13])
                                                                    0.771     0.771 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[13]
                                       net (fo=1, routed)           1.281     2.052    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc3_common_stat[13]
    Routing       SLICE_X115Y93                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_32/I4
    Routing       SLICE_X115Y93        LUT5 (Prop_F6LUT_SLICEM_I4_O)
                                                                    0.051     2.103 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_32/O
                                       net (fo=1, routed)           0.137     2.240    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_32_n_0
    Routing       SLICE_X114Y93                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_19/I5
    Routing       SLICE_X114Y93        LUT6 (Prop_C6LUT_SLICEL_I5_O)
                                                                    0.050     2.290 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_19/O
                                       net (fo=1, routed)           0.058     2.348    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_19_n_0
    Routing       SLICE_X114Y93                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_5/I0
    Routing       SLICE_X114Y93        LUT5 (Prop_F6LUT_SLICEL_I0_O)
                                                                    0.148     2.496 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_5/O
                                       net (fo=1, routed)           0.198     2.694    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_5_n_0
    Routing       SLICE_X112Y91                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/I4
    Routing       SLICE_X112Y91        LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                                    0.039     2.733 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                                       net (fo=1, routed)           0.058     2.791    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    Routing       SLICE_X112Y91        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.241     2.423    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X112Y91        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.786ns  (logic 0.864ns (31.012%)  route 1.922ns (68.988%))
  Logic Levels:           5  (LUT4=1 LUT6=4)
  Clock Path Skew:        2.435ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.435ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.253ns (routing 0.690ns, distribution 1.563ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFADC3_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[15])
                                                                    0.525     0.525 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[15]
                                       net (fo=1, routed)           1.304     1.829    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc3_common_stat[15]
    Routing       SLICE_X117Y93                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_99/I0
    Routing       SLICE_X117Y93        LUT4 (Prop_B6LUT_SLICEL_I0_O)
                                                                    0.098     1.927 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_99/O
                                       net (fo=1, routed)           0.175     2.102    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_99_n_0
    Routing       SLICE_X117Y93                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_61/I4
    Routing       SLICE_X117Y93        LUT6 (Prop_D6LUT_SLICEL_I4_O)
                                                                    0.050     2.152 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_61/O
                                       net (fo=1, routed)           0.202     2.354    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_61_n_0
    Routing       SLICE_X114Y94                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_23/I1
    Placement     SLICE_X114Y94        LUT6 (Prop_H6LUT_SLICEL_I1_O)
                                                                    0.090     2.444 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_23/O
                                       net (fo=1, routed)           0.038     2.482    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_23_n_0
    Placement     SLICE_X114Y94                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_6/I4
    Routing       SLICE_X114Y94        LUT6 (Prop_G6LUT_SLICEL_I4_O)
                                                                    0.050     2.532 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_6/O
                                       net (fo=1, routed)           0.137     2.669    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_6_n_0
    Routing       SLICE_X113Y95                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/I4
    Routing       SLICE_X113Y95        LUT6 (Prop_C6LUT_SLICEM_I4_O)
                                                                    0.051     2.720 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                                       net (fo=1, routed)           0.066     2.786    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    Routing       SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.253     2.435    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.565ns  (logic 0.909ns (35.439%)  route 1.656ns (64.561%))
  Logic Levels:           4  (LUT4=1 LUT5=1 LUT6=2)
  Clock Path Skew:        2.445ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.445ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.263ns (routing 0.690ns, distribution 1.573ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFADC3_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[10])
                                                                    0.536     0.536 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[10]
                                       net (fo=1, routed)           1.362     1.898    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc3_common_stat[10]
    Routing       SLICE_X116Y96                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_27/I4
    Placement     SLICE_X116Y96        LUT5 (Prop_F6LUT_SLICEL_I4_O)
                                                                    0.148     2.046 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_27/O
                                       net (fo=1, routed)           0.039     2.085    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_27_n_0
    Placement     SLICE_X116Y96                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_14/I4
    Placement     SLICE_X116Y96        LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                                    0.036     2.121 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_14/O
                                       net (fo=1, routed)           0.040     2.161    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_14_n_0
    Placement     SLICE_X116Y96                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_4/I1
    Routing       SLICE_X116Y96        LUT4 (Prop_E6LUT_SLICEL_I1_O)
                                                                    0.090     2.251 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_4/O
                                       net (fo=1, routed)           0.143     2.394    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_4_n_0
    Routing       SLICE_X113Y96                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/I3
    Routing       SLICE_X113Y96        LUT6 (Prop_D6LUT_SLICEM_I3_O)
                                                                    0.099     2.493 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                                       net (fo=1, routed)           0.072     2.565    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    Routing       SLICE_X113Y96        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.263     2.445    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X113Y96        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.548ns  (logic 0.870ns (34.144%)  route 1.678ns (65.856%))
  Logic Levels:           4  (LUT4=1 LUT5=1 LUT6=2)
  Clock Path Skew:        2.441ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.441ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.259ns (routing 0.690ns, distribution 1.569ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFADC3_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[11])
                                                                    0.588     0.588 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[11]
                                       net (fo=1, routed)           1.273     1.861    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc3_common_stat[11]
    Routing       SLICE_X116Y97                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_30/I4
    Placement     SLICE_X116Y97        LUT5 (Prop_G6LUT_SLICEL_I4_O)
                                                                    0.035     1.896 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_30/O
                                       net (fo=1, routed)           0.087     1.983    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_30_n_0
    Placement     SLICE_X116Y97                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_15/I4
    Placement     SLICE_X116Y97        LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                                    0.036     2.019 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_15/O
                                       net (fo=1, routed)           0.037     2.056    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_15_n_0
    Placement     SLICE_X116Y97                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_4/I1
    Routing       SLICE_X116Y97        LUT4 (Prop_F6LUT_SLICEL_I1_O)
                                                                    0.089     2.145 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_4/O
                                       net (fo=1, routed)           0.209     2.354    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_4_n_0
    Routing       SLICE_X113Y93                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/I3
    Routing       SLICE_X113Y93        LUT6 (Prop_D6LUT_SLICEM_I3_O)
                                                                    0.122     2.476 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                                       net (fo=1, routed)           0.072     2.548    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    Routing       SLICE_X113Y93        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.259     2.441    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X113Y93        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.542ns  (logic 0.908ns (35.720%)  route 1.634ns (64.280%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        2.432ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.432ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.250ns (routing 0.690ns, distribution 1.560ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFADC3_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[14])
                                                                    0.698     0.698 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[14]
                                       net (fo=1, routed)           1.240     1.938    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc3_common_stat[14]
    Routing       SLICE_X117Y93                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_19/I1
    Routing       SLICE_X117Y93        LUT6 (Prop_H6LUT_SLICEL_I1_O)
                                                                    0.124     2.062 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_19/O
                                       net (fo=1, routed)           0.196     2.258    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_19_n_0
    Routing       SLICE_X114Y93                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_5/I4
    Routing       SLICE_X114Y93        LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                                    0.051     2.309 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_5/O
                                       net (fo=1, routed)           0.148     2.457    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_5_n_0
    Routing       SLICE_X114Y91                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/I3
    Routing       SLICE_X114Y91        LUT6 (Prop_C6LUT_SLICEL_I3_O)
                                                                    0.035     2.492 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                                       net (fo=1, routed)           0.050     2.542    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    Routing       SLICE_X114Y91        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.250     2.432    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X114Y91        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.535ns  (logic 0.967ns (38.146%)  route 1.568ns (61.854%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        2.429ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.429ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.247ns (routing 0.690ns, distribution 1.557ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFADC3_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[9])
                                                                    0.532     0.532 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[9]
                                       net (fo=1, routed)           1.240     1.772    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc3_common_stat[9]
    Routing       SLICE_X115Y96                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_31/I4
    Routing       SLICE_X115Y96        LUT5 (Prop_G6LUT_SLICEM_I4_O)
                                                                    0.123     1.895 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_31/O
                                       net (fo=1, routed)           0.047     1.942    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_31_n_0
    Routing       SLICE_X115Y96                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_16/I4
    Placement     SLICE_X115Y96        LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                                    0.101     2.043 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_16/O
                                       net (fo=1, routed)           0.041     2.084    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_16_n_0
    Placement     SLICE_X115Y96                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_5/I3
    Routing       SLICE_X115Y96        LUT5 (Prop_F6LUT_SLICEM_I3_O)
                                                                    0.088     2.172 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_5/O
                                       net (fo=1, routed)           0.174     2.346    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_5_n_0
    Routing       SLICE_X112Y95                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/I3
    Routing       SLICE_X112Y95        LUT6 (Prop_C6LUT_SLICEM_I3_O)
                                                                    0.123     2.469 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                                       net (fo=1, routed)           0.066     2.535    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    Routing       SLICE_X112Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.247     2.429    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X112Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.476ns  (logic 0.851ns (34.370%)  route 1.625ns (65.630%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        2.435ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.435ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.253ns (routing 0.690ns, distribution 1.563ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFADC3_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[12])
                                                                    0.611     0.611 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[12]
                                       net (fo=1, routed)           1.229     1.840    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc3_common_stat[12]
    Routing       SLICE_X116Y96                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_37/I4
    Routing       SLICE_X116Y96        LUT5 (Prop_B6LUT_SLICEL_I4_O)
                                                                    0.051     1.891 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_37/O
                                       net (fo=1, routed)           0.192     2.083    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_37_n_0
    Routing       SLICE_X113Y95                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_20/I5
    Placement     SLICE_X113Y95        LUT6 (Prop_H6LUT_SLICEM_I5_O)
                                                                    0.101     2.184 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_20/O
                                       net (fo=1, routed)           0.042     2.226    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_20_n_0
    Placement     SLICE_X113Y95                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_6/I3
    Routing       SLICE_X113Y95        LUT6 (Prop_G6LUT_SLICEM_I3_O)
                                                                    0.037     2.263 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_6/O
                                       net (fo=1, routed)           0.090     2.353    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_6_n_0
    Routing       SLICE_X113Y95                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/I5
    Routing       SLICE_X113Y95        LUT6 (Prop_D6LUT_SLICEM_I5_O)
                                                                    0.051     2.404 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                                       net (fo=1, routed)           0.072     2.476    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    Routing       SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.253     2.435    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.178ns  (logic 0.374ns (31.749%)  route 0.804ns (68.251%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.707ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.707ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.560ns (routing 0.463ns, distribution 1.097ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFADC3_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[12])
                                                                    0.274     0.274 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[12]
                                       net (fo=1, routed)           0.613     0.887    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc3_common_stat[12]
    Routing       SLICE_X116Y96                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_37/I4
    Routing       SLICE_X116Y96        LUT5 (Prop_B6LUT_SLICEL_I4_O)
                                                                    0.023     0.910 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_37/O
                                       net (fo=1, routed)           0.097     1.007    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_37_n_0
    Routing       SLICE_X113Y95                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_20/I5
    Placement     SLICE_X113Y95        LUT6 (Prop_H6LUT_SLICEM_I5_O)
                                                                    0.041     1.048 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_20/O
                                       net (fo=1, routed)           0.024     1.072    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_20_n_0
    Placement     SLICE_X113Y95                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_6/I3
    Routing       SLICE_X113Y95        LUT6 (Prop_G6LUT_SLICEM_I3_O)
                                                                    0.014     1.086 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_6/O
                                       net (fo=1, routed)           0.044     1.130    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_6_n_0
    Routing       SLICE_X113Y95                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/I5
    Routing       SLICE_X113Y95        LUT6 (Prop_D6LUT_SLICEM_I5_O)
                                                                    0.022     1.152 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                                       net (fo=1, routed)           0.026     1.178    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    Routing       SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.560     1.707    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.179ns  (logic 0.372ns (31.552%)  route 0.807ns (68.448%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        1.705ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.705ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.558ns (routing 0.463ns, distribution 1.095ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFADC3_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[14])
                                                                    0.285     0.285 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[14]
                                       net (fo=1, routed)           0.614     0.899    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc3_common_stat[14]
    Routing       SLICE_X117Y93                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_19/I1
    Routing       SLICE_X117Y93        LUT6 (Prop_H6LUT_SLICEL_I1_O)
                                                                    0.050     0.949 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_19/O
                                       net (fo=1, routed)           0.101     1.050    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_19_n_0
    Routing       SLICE_X114Y93                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_5/I4
    Routing       SLICE_X114Y93        LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                                    0.023     1.073 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_5/O
                                       net (fo=1, routed)           0.075     1.148    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_5_n_0
    Routing       SLICE_X114Y91                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/I3
    Routing       SLICE_X114Y91        LUT6 (Prop_C6LUT_SLICEL_I3_O)
                                                                    0.014     1.162 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                                       net (fo=1, routed)           0.017     1.179    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    Routing       SLICE_X114Y91        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.558     1.705    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X114Y91        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.189ns  (logic 0.404ns (33.978%)  route 0.785ns (66.022%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        1.702ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.702ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.555ns (routing 0.463ns, distribution 1.092ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFADC3_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[9])
                                                                    0.228     0.228 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[9]
                                       net (fo=1, routed)           0.618     0.846    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc3_common_stat[9]
    Routing       SLICE_X115Y96                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_31/I4
    Routing       SLICE_X115Y96        LUT5 (Prop_G6LUT_SLICEM_I4_O)
                                                                    0.050     0.896 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_31/O
                                       net (fo=1, routed)           0.026     0.922    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_31_n_0
    Routing       SLICE_X115Y96                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_16/I4
    Placement     SLICE_X115Y96        LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                                    0.041     0.963 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_16/O
                                       net (fo=1, routed)           0.024     0.987    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_16_n_0
    Placement     SLICE_X115Y96                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_5/I3
    Routing       SLICE_X115Y96        LUT5 (Prop_F6LUT_SLICEM_I3_O)
                                                                    0.035     1.022 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_5/O
                                       net (fo=1, routed)           0.093     1.115    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_5_n_0
    Routing       SLICE_X112Y95                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/I3
    Routing       SLICE_X112Y95        LUT6 (Prop_C6LUT_SLICEM_I3_O)
                                                                    0.050     1.165 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                                       net (fo=1, routed)           0.024     1.189    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    Routing       SLICE_X112Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.555     1.702    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X112Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.205ns  (logic 0.377ns (31.286%)  route 0.828ns (68.714%))
  Logic Levels:           4  (LUT4=1 LUT5=1 LUT6=2)
  Clock Path Skew:        1.717ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.717ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.570ns (routing 0.463ns, distribution 1.107ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFADC3_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[10])
                                                                    0.227     0.227 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[10]
                                       net (fo=1, routed)           0.684     0.911    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc3_common_stat[10]
    Routing       SLICE_X116Y96                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_27/I4
    Placement     SLICE_X116Y96        LUT5 (Prop_F6LUT_SLICEL_I4_O)
                                                                    0.059     0.970 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_27/O
                                       net (fo=1, routed)           0.021     0.991    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_27_n_0
    Placement     SLICE_X116Y96                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_14/I4
    Placement     SLICE_X116Y96        LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                                    0.015     1.006 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_14/O
                                       net (fo=1, routed)           0.023     1.029    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_14_n_0
    Placement     SLICE_X116Y96                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_4/I1
    Routing       SLICE_X116Y96        LUT4 (Prop_E6LUT_SLICEL_I1_O)
                                                                    0.035     1.064 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_4/O
                                       net (fo=1, routed)           0.074     1.138    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_4_n_0
    Routing       SLICE_X113Y96                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/I3
    Routing       SLICE_X113Y96        LUT6 (Prop_D6LUT_SLICEM_I3_O)
                                                                    0.041     1.179 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                                       net (fo=1, routed)           0.026     1.205    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    Routing       SLICE_X113Y96        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.570     1.717    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X113Y96        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.214ns  (logic 0.379ns (31.219%)  route 0.835ns (68.781%))
  Logic Levels:           4  (LUT4=1 LUT5=1 LUT6=2)
  Clock Path Skew:        1.715ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.715ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.568ns (routing 0.463ns, distribution 1.105ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFADC3_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[11])
                                                                    0.265     0.265 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[11]
                                       net (fo=1, routed)           0.638     0.903    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc3_common_stat[11]
    Routing       SLICE_X116Y97                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_30/I4
    Placement     SLICE_X116Y97        LUT5 (Prop_G6LUT_SLICEL_I4_O)
                                                                    0.014     0.917 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_30/O
                                       net (fo=1, routed)           0.042     0.959    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_30_n_0
    Placement     SLICE_X116Y97                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_15/I4
    Placement     SLICE_X116Y97        LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                                    0.015     0.974 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_15/O
                                       net (fo=1, routed)           0.021     0.995    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_15_n_0
    Placement     SLICE_X116Y97                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_4/I1
    Routing       SLICE_X116Y97        LUT4 (Prop_F6LUT_SLICEL_I1_O)
                                                                    0.035     1.030 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_4/O
                                       net (fo=1, routed)           0.108     1.138    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_4_n_0
    Routing       SLICE_X113Y93                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/I3
    Routing       SLICE_X113Y93        LUT6 (Prop_D6LUT_SLICEM_I3_O)
                                                                    0.050     1.188 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                                       net (fo=1, routed)           0.026     1.214    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    Routing       SLICE_X113Y93        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.568     1.715    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X113Y93        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.221ns  (logic 0.359ns (29.402%)  route 0.862ns (70.598%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        1.698ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.698ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.551ns (routing 0.463ns, distribution 1.088ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFADC3_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[13])
                                                                    0.241     0.241 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[13]
                                       net (fo=1, routed)           0.641     0.882    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc3_common_stat[13]
    Routing       SLICE_X115Y93                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_32/I4
    Routing       SLICE_X115Y93        LUT5 (Prop_F6LUT_SLICEM_I4_O)
                                                                    0.022     0.904 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_32/O
                                       net (fo=1, routed)           0.067     0.971    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_32_n_0
    Routing       SLICE_X114Y93                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_19/I5
    Routing       SLICE_X114Y93        LUT6 (Prop_C6LUT_SLICEL_I5_O)
                                                                    0.022     0.993 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_19/O
                                       net (fo=1, routed)           0.030     1.023    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_19_n_0
    Routing       SLICE_X114Y93                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_5/I0
    Routing       SLICE_X114Y93        LUT5 (Prop_F6LUT_SLICEL_I0_O)
                                                                    0.059     1.082 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_5/O
                                       net (fo=1, routed)           0.103     1.185    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_5_n_0
    Routing       SLICE_X112Y91                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/I4
    Routing       SLICE_X112Y91        LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                                    0.015     1.200 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                                       net (fo=1, routed)           0.021     1.221    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    Routing       SLICE_X112Y91        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.551     1.698    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X112Y91        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.225ns  (logic 0.336ns (27.429%)  route 0.889ns (72.571%))
  Logic Levels:           4  (LUT4=1 LUT5=1 LUT6=2)
  Clock Path Skew:        1.700ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.700ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.553ns (routing 0.463ns, distribution 1.090ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFADC3_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[8])
                                                                    0.237     0.237 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[8]
                                       net (fo=1, routed)           0.640     0.877    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc3_common_stat[8]
    Routing       SLICE_X116Y97                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_21/I3
    Routing       SLICE_X116Y97        LUT5 (Prop_B6LUT_SLICEL_I3_O)
                                                                    0.036     0.913 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_21/O
                                       net (fo=1, routed)           0.065     0.978    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_21_n_0
    Routing       SLICE_X116Y97                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_12/I2
    Placement     SLICE_X116Y97        LUT6 (Prop_C6LUT_SLICEL_I2_O)
                                                                    0.014     0.992 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_12/O
                                       net (fo=1, routed)           0.023     1.015    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_12_n_0
    Placement     SLICE_X116Y97                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_4/I1
    Routing       SLICE_X116Y97        LUT4 (Prop_A6LUT_SLICEL_I1_O)
                                                                    0.035     1.050 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_4/O
                                       net (fo=1, routed)           0.144     1.194    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_4_n_0
    Routing       SLICE_X111Y94                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/I3
    Routing       SLICE_X111Y94        LUT6 (Prop_C6LUT_SLICEL_I3_O)
                                                                    0.014     1.208 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                                       net (fo=1, routed)           0.017     1.225    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    Routing       SLICE_X111Y94        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.553     1.700    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X111Y94        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.313ns  (logic 0.392ns (29.855%)  route 0.921ns (70.145%))
  Logic Levels:           5  (LUT4=1 LUT6=4)
  Clock Path Skew:        1.707ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.707ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.560ns (routing 0.463ns, distribution 1.097ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFADC3_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[15])
                                                                    0.250     0.250 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[15]
                                       net (fo=1, routed)           0.632     0.882    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc3_common_stat[15]
    Routing       SLICE_X117Y93                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_99/I0
    Routing       SLICE_X117Y93        LUT4 (Prop_B6LUT_SLICEL_I0_O)
                                                                    0.041     0.923 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_99/O
                                       net (fo=1, routed)           0.070     0.993    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_99_n_0
    Routing       SLICE_X117Y93                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_61/I4
    Routing       SLICE_X117Y93        LUT6 (Prop_D6LUT_SLICEL_I4_O)
                                                                    0.022     1.015 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_61/O
                                       net (fo=1, routed)           0.106     1.121    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_61_n_0
    Routing       SLICE_X114Y94                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_23/I1
    Placement     SLICE_X114Y94        LUT6 (Prop_H6LUT_SLICEL_I1_O)
                                                                    0.035     1.156 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_23/O
                                       net (fo=1, routed)           0.021     1.177    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_23_n_0
    Placement     SLICE_X114Y94                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_6/I4
    Routing       SLICE_X114Y94        LUT6 (Prop_G6LUT_SLICEL_I4_O)
                                                                    0.022     1.199 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_6/O
                                       net (fo=1, routed)           0.068     1.267    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_6_n_0
    Routing       SLICE_X113Y95                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/I4
    Routing       SLICE_X113Y95        LUT6 (Prop_C6LUT_SLICEM_I4_O)
                                                                    0.022     1.289 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                                       net (fo=1, routed)           0.024     1.313    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    Routing       SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.560     1.707    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFDAC0_CLK
  To Clock:  clk_pl_0

Max Delay           154 Endpoints
Min Delay           154 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.875ns  (logic 1.408ns (36.335%)  route 2.467ns (63.665%))
  Logic Levels:           4  (LUT4=2 LUT5=1 LUT6=1)
  Clock Path Skew:        2.423ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.423ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.241ns (routing 0.690ns, distribution 1.551ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[13])
                                                                    1.059     1.059 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[13]
                                       net (fo=1, routed)           1.756     2.815    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac0_common_stat[13]
    Routing       SLICE_X114Y105                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_23/I4
    Routing       SLICE_X114Y105       LUT5 (Prop_H6LUT_SLICEL_I4_O)
                                                                    0.099     2.914 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_23/O
                                       net (fo=1, routed)           0.217     3.131    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_23_n_0
    Routing       SLICE_X111Y103                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_8/I3
    Routing       SLICE_X111Y103       LUT4 (Prop_B6LUT_SLICEL_I3_O)
                                                                    0.036     3.167 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_8/O
                                       net (fo=1, routed)           0.091     3.258    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_8_n_0
    Routing       SLICE_X111Y103                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_2/I3
    Routing       SLICE_X111Y103       LUT4 (Prop_D6LUT_SLICEL_I3_O)
                                                                    0.089     3.347 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_2/O
                                       net (fo=1, routed)           0.345     3.692    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_2_n_0
    Routing       SLICE_X112Y91                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/I0
    Routing       SLICE_X112Y91        LUT6 (Prop_H6LUT_SLICEM_I0_O)
                                                                    0.125     3.817 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                                       net (fo=1, routed)           0.058     3.875    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    Routing       SLICE_X112Y91        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.241     2.423    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X112Y91        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_PORT[0].wave_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_PORT[0].wave_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.734ns  (logic 0.079ns (10.760%)  route 0.655ns (89.240%))
  Logic Levels:           0  
  Clock Path Skew:        -0.932ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.206ns
    Source Clock Delay      (SCD):    3.138ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.465ns (routing 1.120ns, distribution 1.345ns)
  Clock Net Delay (Destination): 2.024ns (routing 0.690ns, distribution 1.334ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.465     3.138    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_PORT[0].wave_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/rd_clk
                  SLICE_X74Y69         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_PORT[0].wave_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X74Y69         FDRE (Prop_BFF_SLICEL_C_Q)
                                                                    0.079     3.217 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_PORT[0].wave_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/Q
                                       net (fo=36, routed)          0.655     3.872    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_PORT[0].wave_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/src_rst
    Routing       SLICE_X67Y62         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_PORT[0].wave_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.024     2.206    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_PORT[0].wave_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/dest_clk
                  SLICE_X67Y62         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_PORT[0].wave_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.885ns  (logic 0.080ns (9.039%)  route 0.805ns (90.961%))
  Logic Levels:           0  
  Clock Path Skew:        -0.539ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.427ns
    Source Clock Delay      (SCD):    2.966ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.293ns (routing 1.120ns, distribution 1.173ns)
  Clock Net Delay (Destination): 2.245ns (routing 0.690ns, distribution 1.555ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.293     2.966    d_1_i/rst_dac0/U0/slowest_sync_clk
                  SLICE_X94Y142        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X94Y142        FDRE (Prop_AFF2_SLICEM_C_Q)
                                                                    0.080     3.046 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                                       net (fo=2, routed)           0.805     3.851    d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/src_in
    Routing       SLICE_X109Y126       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/syncstages_ff_reg[0]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.245     2.427    d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/dest_clk
                  SLICE_X109Y126       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[0].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[0].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.630ns  (logic 0.078ns (12.380%)  route 0.552ns (87.620%))
  Logic Levels:           0  
  Clock Path Skew:        -0.946ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.212ns
    Source Clock Delay      (SCD):    3.158ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.485ns (routing 1.120ns, distribution 1.365ns)
  Clock Net Delay (Destination): 2.030ns (routing 0.690ns, distribution 1.340ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.485     3.158    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[0].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/rd_clk
                  SLICE_X76Y69         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[0].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X76Y69         FDRE (Prop_BFF_SLICEM_C_Q)
                                                                    0.078     3.236 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[0].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/Q
                                       net (fo=34, routed)          0.552     3.788    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[0].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/src_rst
    Routing       SLICE_X72Y66         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[0].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.030     2.212    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[0].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/dest_clk
                  SLICE_X72Y66         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[0].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.788ns  (logic 1.166ns (30.781%)  route 2.622ns (69.219%))
  Logic Levels:           5  (LUT4=1 LUT6=4)
  Clock Path Skew:        2.432ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.432ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.250ns (routing 0.690ns, distribution 1.560ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[14])
                                                                    0.779     0.779 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[14]
                                       net (fo=1, routed)           1.809     2.588    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac0_common_stat[14]
    Routing       SLICE_X116Y102                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_61/I0
    Routing       SLICE_X116Y102       LUT4 (Prop_E6LUT_SLICEL_I0_O)
                                                                    0.123     2.711 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_61/O
                                       net (fo=1, routed)           0.257     2.968    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_61_n_0
    Routing       SLICE_X116Y102                                                    f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_31/I0
    Routing       SLICE_X116Y102       LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                                    0.051     3.019 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_31/O
                                       net (fo=1, routed)           0.084     3.103    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_31_n_0
    Routing       SLICE_X116Y101                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_10/I4
    Routing       SLICE_X116Y101       LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                                    0.051     3.154 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_10/O
                                       net (fo=1, routed)           0.144     3.298    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_10_n_0
    Routing       SLICE_X113Y101                                                    f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_2/I4
    Routing       SLICE_X113Y101       LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                                    0.039     3.337 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_2/O
                                       net (fo=1, routed)           0.278     3.615    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_2_n_0
    Routing       SLICE_X114Y91                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/I0
    Routing       SLICE_X114Y91        LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                                    0.123     3.738 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                                       net (fo=1, routed)           0.050     3.788    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    Routing       SLICE_X114Y91        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.250     2.432    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X114Y91        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[5].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[5].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.595ns  (logic 0.079ns (13.276%)  route 0.516ns (86.724%))
  Logic Levels:           0  
  Clock Path Skew:        -0.915ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.214ns
    Source Clock Delay      (SCD):    3.129ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.456ns (routing 1.120ns, distribution 1.336ns)
  Clock Net Delay (Destination): 2.032ns (routing 0.690ns, distribution 1.342ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.456     3.129    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[5].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/rd_clk
                  SLICE_X74Y80         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[5].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X74Y80         FDRE (Prop_BFF_SLICEL_C_Q)
                                                                    0.079     3.208 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[5].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/Q
                                       net (fo=34, routed)          0.516     3.724    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[5].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/src_rst
    Routing       SLICE_X77Y78         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[5].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.032     2.214    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[5].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/dest_clk
                  SLICE_X77Y78         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[5].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_PORT[0].data_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_PORT[0].data_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.545ns  (logic 0.079ns (14.507%)  route 0.466ns (85.493%))
  Logic Levels:           0  
  Clock Path Skew:        -0.973ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.199ns
    Source Clock Delay      (SCD):    3.172ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.499ns (routing 1.120ns, distribution 1.379ns)
  Clock Net Delay (Destination): 2.017ns (routing 0.690ns, distribution 1.327ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.499     3.172    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_PORT[0].data_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/rd_clk
                  SLICE_X71Y75         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_PORT[0].data_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X71Y75         FDRE (Prop_GFF_SLICEL_C_Q)
                                                                    0.079     3.251 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_PORT[0].data_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/Q
                                       net (fo=34, routed)          0.466     3.717    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_PORT[0].data_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/src_rst
    Routing       SLICE_X69Y72         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_PORT[0].data_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.017     2.199    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_PORT[0].data_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/dest_clk
                  SLICE_X69Y72         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_PORT[0].data_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.676ns  (logic 1.015ns (27.612%)  route 2.661ns (72.388%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        2.441ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.441ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.259ns (routing 0.690ns, distribution 1.569ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[11])
                                                                    0.753     0.753 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[11]
                                       net (fo=1, routed)           1.934     2.687    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac0_common_stat[11]
    Routing       SLICE_X115Y103                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_25/I4
    Routing       SLICE_X115Y103       LUT5 (Prop_F6LUT_SLICEM_I4_O)
                                                                    0.051     2.738 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_25/O
                                       net (fo=1, routed)           0.160     2.898    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_25_n_0
    Routing       SLICE_X112Y103                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_8/I4
    Placement     SLICE_X112Y103       LUT6 (Prop_G6LUT_SLICEM_I4_O)
                                                                    0.123     3.021 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_8/O
                                       net (fo=1, routed)           0.090     3.111    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_8_n_0
    Placement     SLICE_X112Y103                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_2/I5
    Routing       SLICE_X112Y103       LUT6 (Prop_C6LUT_SLICEM_I5_O)
                                                                    0.051     3.162 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_2/O
                                       net (fo=1, routed)           0.405     3.567    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_2_n_0
    Routing       SLICE_X113Y93                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/I0
    Routing       SLICE_X113Y93        LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                                    0.037     3.604 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                                       net (fo=1, routed)           0.072     3.676    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    Routing       SLICE_X113Y93        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.259     2.441    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X113Y93        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[2].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[2].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.531ns  (logic 0.076ns (14.321%)  route 0.455ns (85.679%))
  Logic Levels:           0  
  Clock Path Skew:        -0.917ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.224ns
    Source Clock Delay      (SCD):    3.141ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.468ns (routing 1.120ns, distribution 1.348ns)
  Clock Net Delay (Destination): 2.042ns (routing 0.690ns, distribution 1.352ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.468     3.141    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[2].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/rd_clk
                  SLICE_X78Y66         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[2].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
  ---------------------------------------------------------------------------------    -------------------
    Placement     SLICE_X78Y66         FDRE (Prop_FFF_SLICEM_C_Q)
                                                                    0.076     3.217 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[2].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/Q
                                       net (fo=34, routed)          0.455     3.672    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[2].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/src_rst
    Placement     SLICE_X77Y60         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[2].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.042     2.224    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[2].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/dest_clk
                  SLICE_X77Y60         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[2].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.626ns  (logic 1.216ns (33.536%)  route 2.410ns (66.464%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        2.435ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.435ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.253ns (routing 0.690ns, distribution 1.563ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[15])
                                                                    0.840     0.840 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[15]
                                       net (fo=1, routed)           1.717     2.557    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac0_common_stat[15]
    Routing       SLICE_X116Y103                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_37/I4
    Placement     SLICE_X116Y103       LUT5 (Prop_C6LUT_SLICEL_I4_O)
                                                                    0.096     2.653 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_37/O
                                       net (fo=1, routed)           0.041     2.694    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_37_n_0
    Placement     SLICE_X116Y103                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_11/I2
    Routing       SLICE_X116Y103       LUT5 (Prop_D6LUT_SLICEL_I2_O)
                                                                    0.036     2.730 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_11/O
                                       net (fo=1, routed)           0.200     2.930    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_11_n_0
    Routing       SLICE_X114Y101                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_2/I4
    Routing       SLICE_X114Y101       LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                                    0.099     3.029 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_2/O
                                       net (fo=1, routed)           0.386     3.415    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_2_n_0
    Routing       SLICE_X113Y95                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/I0
    Routing       SLICE_X113Y95        LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                                    0.145     3.560 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                                       net (fo=1, routed)           0.066     3.626    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    Routing       SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.253     2.435    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.529ns  (logic 0.494ns (32.309%)  route 1.035ns (67.691%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        1.717ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.717ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.570ns (routing 0.463ns, distribution 1.107ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[10])
                                                                    0.375     0.375 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[10]
                                       net (fo=1, routed)           0.827     1.202    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac0_common_stat[10]
    Routing       SLICE_X114Y105                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_24/I4
    Placement     SLICE_X114Y105       LUT5 (Prop_C6LUT_SLICEL_I4_O)
                                                                    0.040     1.242 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_24/O
                                       net (fo=1, routed)           0.021     1.263    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_24_n_0
    Placement     SLICE_X114Y104                                                    f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_9/I4
    Placement     SLICE_X114Y104       LUT5 (Prop_G6LUT_SLICEL_I4_O)
                                                                    0.014     1.277 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_9/O
                                       net (fo=1, routed)           0.047     1.324    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_9_n_0
    Placement     SLICE_X113Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_2/I4
    Routing       SLICE_X113Y104       LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                                    0.015     1.339 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_2/O
                                       net (fo=1, routed)           0.114     1.453    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_2_n_0
    Routing       SLICE_X113Y96                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/I0
    Routing       SLICE_X113Y96        LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                                    0.050     1.503 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                                       net (fo=1, routed)           0.026     1.529    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    Routing       SLICE_X113Y96        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.570     1.717    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X113Y96        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.599ns  (logic 0.562ns (35.147%)  route 1.037ns (64.853%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.707ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.707ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.560ns (routing 0.463ns, distribution 1.097ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[12])
                                                                    0.386     0.386 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[12]
                                       net (fo=1, routed)           0.829     1.215    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac0_common_stat[12]
    Routing       SLICE_X113Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_29/I4
    Routing       SLICE_X113Y104       LUT5 (Prop_F6LUT_SLICEM_I4_O)
                                                                    0.050     1.265 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_29/O
                                       net (fo=1, routed)           0.050     1.315    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_29_n_0
    Routing       SLICE_X113Y103                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_11/I5
    Placement     SLICE_X113Y103       LUT6 (Prop_C6LUT_SLICEM_I5_O)
                                                                    0.050     1.365 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_11/O
                                       net (fo=1, routed)           0.022     1.387    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_11_n_0
    Placement     SLICE_X113Y103                                                    f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_2/I4
    Routing       SLICE_X113Y103       LUT6 (Prop_B6LUT_SLICEM_I4_O)
                                                                    0.035     1.422 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_2/O
                                       net (fo=1, routed)           0.110     1.532    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_2_n_0
    Routing       SLICE_X113Y95                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/I0
    Routing       SLICE_X113Y95        LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                                    0.041     1.573 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                                       net (fo=1, routed)           0.026     1.599    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    Routing       SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.560     1.707    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.641ns  (logic 0.466ns (28.397%)  route 1.175ns (71.603%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        1.702ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.702ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.555ns (routing 0.463ns, distribution 1.092ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[9])
                                                                    0.338     0.338 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[9]
                                       net (fo=1, routed)           0.856     1.194    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac0_common_stat[9]
    Routing       SLICE_X116Y103                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_25/I4
    Routing       SLICE_X116Y103       LUT5 (Prop_B6LUT_SLICEL_I4_O)
                                                                    0.060     1.254 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_25/O
                                       net (fo=1, routed)           0.072     1.326    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_25_n_0
    Routing       SLICE_X113Y103                                                    f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_10/I4
    Routing       SLICE_X113Y103       LUT5 (Prop_F6LUT_SLICEM_I4_O)
                                                                    0.014     1.340 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_10/O
                                       net (fo=1, routed)           0.116     1.456    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_10_n_0
    Routing       SLICE_X112Y102                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_2/I3
    Routing       SLICE_X112Y102       LUT6 (Prop_C6LUT_SLICEM_I3_O)
                                                                    0.040     1.496 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_2/O
                                       net (fo=1, routed)           0.107     1.603    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_2_n_0
    Routing       SLICE_X112Y95                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/I0
    Routing       SLICE_X112Y95        LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                                    0.014     1.617 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                                       net (fo=1, routed)           0.024     1.641    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    Routing       SLICE_X112Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.555     1.702    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X112Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.740ns  (logic 0.567ns (32.586%)  route 1.173ns (67.414%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        1.707ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.707ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.560ns (routing 0.463ns, distribution 1.097ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[15])
                                                                    0.413     0.413 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[15]
                                       net (fo=1, routed)           0.836     1.249    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac0_common_stat[15]
    Routing       SLICE_X116Y103                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_37/I4
    Placement     SLICE_X116Y103       LUT5 (Prop_C6LUT_SLICEL_I4_O)
                                                                    0.040     1.289 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_37/O
                                       net (fo=1, routed)           0.022     1.311    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_37_n_0
    Placement     SLICE_X116Y103                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_11/I2
    Routing       SLICE_X116Y103       LUT5 (Prop_D6LUT_SLICEL_I2_O)
                                                                    0.014     1.325 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_11/O
                                       net (fo=1, routed)           0.098     1.423    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_11_n_0
    Routing       SLICE_X114Y101                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_2/I4
    Routing       SLICE_X114Y101       LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                                    0.041     1.464 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_2/O
                                       net (fo=1, routed)           0.193     1.657    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_2_n_0
    Routing       SLICE_X113Y95                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/I0
    Routing       SLICE_X113Y95        LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                                    0.059     1.716 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                                       net (fo=1, routed)           0.024     1.740    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    Routing       SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.560     1.707    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.760ns  (logic 0.562ns (31.932%)  route 1.198ns (68.068%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.700ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.700ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.553ns (routing 0.463ns, distribution 1.090ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[8])
                                                                    0.382     0.382 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[8]
                                       net (fo=1, routed)           0.884     1.266    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac0_common_stat[8]
    Routing       SLICE_X114Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_19/I4
    Routing       SLICE_X114Y104       LUT5 (Prop_E6LUT_SLICEL_I4_O)
                                                                    0.059     1.325 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_19/O
                                       net (fo=1, routed)           0.135     1.460    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_19_n_0
    Routing       SLICE_X112Y103                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_8/I4
    Placement     SLICE_X112Y103       LUT6 (Prop_F6LUT_SLICEM_I4_O)
                                                                    0.059     1.519 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_8/O
                                       net (fo=1, routed)           0.047     1.566    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_8_n_0
    Placement     SLICE_X111Y103                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_2/I5
    Routing       SLICE_X111Y103       LUT6 (Prop_E6LUT_SLICEL_I5_O)
                                                                    0.022     1.588 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_2/O
                                       net (fo=1, routed)           0.115     1.703    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_2_n_0
    Routing       SLICE_X111Y94                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/I0
    Routing       SLICE_X111Y94        LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                                    0.040     1.743 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                                       net (fo=1, routed)           0.017     1.760    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    Routing       SLICE_X111Y94        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.553     1.700    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X111Y94        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[1].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[1].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.098ns  (logic 0.039ns (39.796%)  route 0.059ns (60.204%))
  Logic Levels:           0  
  Clock Path Skew:        -0.139ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.554ns
    Source Clock Delay      (SCD):    1.693ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.344ns (routing 0.607ns, distribution 0.737ns)
  Clock Net Delay (Destination): 1.407ns (routing 0.463ns, distribution 0.944ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        1.344     1.693    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[1].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
                  SLICE_X77Y81         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[1].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X77Y81         FDRE (Prop_CFF_SLICEL_C_Q)
                                                                    0.039     1.732 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[1].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/Q
                                       net (fo=1, routed)           0.059     1.791    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[1].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[3]
    Routing       SLICE_X77Y81         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[1].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.407     1.554    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[1].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
                  SLICE_X77Y81         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[1].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[1].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[1].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.099ns  (logic 0.039ns (39.394%)  route 0.060ns (60.606%))
  Logic Levels:           0  
  Clock Path Skew:        -0.128ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.565ns
    Source Clock Delay      (SCD):    1.693ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.344ns (routing 0.607ns, distribution 0.737ns)
  Clock Net Delay (Destination): 1.418ns (routing 0.463ns, distribution 0.955ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        1.344     1.693    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[1].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
                  SLICE_X77Y81         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[1].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X77Y81         FDRE (Prop_DFF_SLICEL_C_Q)
                                                                    0.039     1.732 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[1].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/Q
                                       net (fo=1, routed)           0.060     1.792    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[1].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[2]
    Routing       SLICE_X77Y79         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[1].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.418     1.565    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[1].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
                  SLICE_X77Y79         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[1].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[4].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[4].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.095ns  (logic 0.039ns (41.053%)  route 0.056ns (58.947%))
  Logic Levels:           0  
  Clock Path Skew:        -0.151ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.549ns
    Source Clock Delay      (SCD):    1.700ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.351ns (routing 0.607ns, distribution 0.744ns)
  Clock Net Delay (Destination): 1.402ns (routing 0.463ns, distribution 0.939ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        1.351     1.700    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[4].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
                  SLICE_X73Y71         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[4].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X73Y71         FDRE (Prop_DFF_SLICEL_C_Q)
                                                                    0.039     1.739 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[4].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/Q
                                       net (fo=1, routed)           0.056     1.795    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[4].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[0]
    Routing       SLICE_X73Y70         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[4].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.402     1.549    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[4].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
                  SLICE_X73Y70         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[4].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[4].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[4].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][7]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.097ns  (logic 0.039ns (40.206%)  route 0.058ns (59.794%))
  Logic Levels:           0  
  Clock Path Skew:        -0.137ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.562ns
    Source Clock Delay      (SCD):    1.699ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.350ns (routing 0.607ns, distribution 0.743ns)
  Clock Net Delay (Destination): 1.415ns (routing 0.463ns, distribution 0.952ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        1.350     1.699    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[4].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
                  SLICE_X73Y74         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[4].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[7]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X73Y74         FDRE (Prop_CFF_SLICEL_C_Q)
                                                                    0.039     1.738 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[4].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[7]/Q
                                       net (fo=1, routed)           0.058     1.796    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[4].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[7]
    Routing       SLICE_X73Y72         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[4].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][7]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.415     1.562    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[4].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
                  SLICE_X73Y72         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[4].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][7]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[4].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[4].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.096ns  (logic 0.039ns (40.625%)  route 0.057ns (59.375%))
  Logic Levels:           0  
  Clock Path Skew:        -0.147ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.555ns
    Source Clock Delay      (SCD):    1.702ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.353ns (routing 0.607ns, distribution 0.746ns)
  Clock Net Delay (Destination): 1.408ns (routing 0.463ns, distribution 0.945ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        1.353     1.702    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[4].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
                  SLICE_X73Y73         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[4].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X73Y73         FDRE (Prop_HFF_SLICEL_C_Q)
                                                                    0.039     1.741 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[4].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/Q
                                       net (fo=1, routed)           0.057     1.798    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[4].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[3]
    Routing       SLICE_X72Y73         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[4].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.408     1.555    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[4].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
                  SLICE_X72Y73         FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_PORT[4].trig_fifo_inst/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFDAC1_CLK
  To Clock:  clk_pl_0

Max Delay             8 Endpoints
Min Delay             8 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.478ns  (logic 1.509ns (33.698%)  route 2.969ns (66.302%))
  Logic Levels:           5  (LUT4=1 LUT6=4)
  Clock Path Skew:        2.423ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.423ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.241ns (routing 0.690ns, distribution 1.551ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC1_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[13])
                                                                    1.059     1.059 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[13]
                                       net (fo=1, routed)           2.236     3.295    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac1_common_stat[13]
    Routing       SLICE_X114Y103                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_34/I5
    Routing       SLICE_X114Y103       LUT6 (Prop_G6LUT_SLICEL_I5_O)
                                                                    0.089     3.384 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_34/O
                                       net (fo=1, routed)           0.200     3.584    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_34_n_0
    Routing       SLICE_X111Y103                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_21/I5
    Routing       SLICE_X111Y103       LUT6 (Prop_G6LUT_SLICEL_I5_O)
                                                                    0.089     3.673 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_21/O
                                       net (fo=1, routed)           0.044     3.717    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_21_n_0
    Routing       SLICE_X111Y103                                                    f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_7/I1
    Placement     SLICE_X111Y103       LUT6 (Prop_F6LUT_SLICEL_I1_O)
                                                                    0.097     3.814 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_7/O
                                       net (fo=1, routed)           0.086     3.900    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_7_n_0
    Placement     SLICE_X111Y103                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_2/I2
    Routing       SLICE_X111Y103       LUT4 (Prop_D6LUT_SLICEL_I2_O)
                                                                    0.050     3.950 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_2/O
                                       net (fo=1, routed)           0.345     4.295    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_2_n_0
    Routing       SLICE_X112Y91                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/I0
    Routing       SLICE_X112Y91        LUT6 (Prop_H6LUT_SLICEM_I0_O)
                                                                    0.125     4.420 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                                       net (fo=1, routed)           0.058     4.478    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    Routing       SLICE_X112Y91        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.241     2.423    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X112Y91        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.190ns  (logic 1.053ns (25.131%)  route 3.137ns (74.869%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        2.441ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.441ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.259ns (routing 0.690ns, distribution 1.569ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC1_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[11])
                                                                    0.753     0.753 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[11]
                                       net (fo=1, routed)           2.212     2.965    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac1_common_stat[11]
    Routing       SLICE_X114Y106                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_19/I4
    Routing       SLICE_X114Y106       LUT5 (Prop_G6LUT_SLICEL_I4_O)
                                                                    0.089     3.054 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_19/O
                                       net (fo=1, routed)           0.353     3.407    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_19_n_0
    Routing       SLICE_X111Y103                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_7/I0
    Routing       SLICE_X111Y103       LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                                    0.051     3.458 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_7/O
                                       net (fo=1, routed)           0.095     3.553    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_7_n_0
    Routing       SLICE_X112Y103                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_2/I4
    Routing       SLICE_X112Y103       LUT6 (Prop_C6LUT_SLICEM_I4_O)
                                                                    0.123     3.676 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_2/O
                                       net (fo=1, routed)           0.405     4.081    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_2_n_0
    Routing       SLICE_X113Y93                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/I0
    Routing       SLICE_X113Y93        LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                                    0.037     4.118 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                                       net (fo=1, routed)           0.072     4.190    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    Routing       SLICE_X113Y93        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.259     2.441    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X113Y93        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.104ns  (logic 1.357ns (33.065%)  route 2.747ns (66.935%))
  Logic Levels:           4  (LUT3=1 LUT6=3)
  Clock Path Skew:        2.435ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.435ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.253ns (routing 0.690ns, distribution 1.563ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC1_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[15])
                                                                    0.840     0.840 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[15]
                                       net (fo=1, routed)           2.141     2.981    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac1_common_stat[15]
    Routing       SLICE_X114Y101                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_24/I1
    Routing       SLICE_X114Y101       LUT6 (Prop_G6LUT_SLICEL_I1_O)
                                                                    0.123     3.104 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_24/O
                                       net (fo=1, routed)           0.046     3.150    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_24_n_0
    Routing       SLICE_X114Y101                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_8/I1
    Routing       SLICE_X114Y101       LUT3 (Prop_E6LUT_SLICEL_I1_O)
                                                                    0.099     3.249 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_8/O
                                       net (fo=1, routed)           0.108     3.357    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_8_n_0
    Routing       SLICE_X114Y101                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_2/I1
    Routing       SLICE_X114Y101       LUT6 (Prop_H6LUT_SLICEL_I1_O)
                                                                    0.150     3.507 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_2/O
                                       net (fo=1, routed)           0.386     3.893    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_2_n_0
    Routing       SLICE_X113Y95                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/I0
    Routing       SLICE_X113Y95        LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                                    0.145     4.038 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                                       net (fo=1, routed)           0.066     4.104    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    Routing       SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.253     2.435    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.010ns  (logic 1.261ns (31.446%)  route 2.749ns (68.554%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        2.432ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.432ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.250ns (routing 0.690ns, distribution 1.560ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC1_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[14])
                                                                    0.779     0.779 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[14]
                                       net (fo=1, routed)           2.245     3.024    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac1_common_stat[14]
    Routing       SLICE_X114Y100                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_26/I0
    Routing       SLICE_X114Y100       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                                    0.146     3.170 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_26/O
                                       net (fo=1, routed)           0.091     3.261    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_26_n_0
    Routing       SLICE_X113Y100                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_9/I3
    Routing       SLICE_X113Y100       LUT6 (Prop_F6LUT_SLICEM_I3_O)
                                                                    0.123     3.384 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_9/O
                                       net (fo=1, routed)           0.085     3.469    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_9_n_0
    Routing       SLICE_X113Y101                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_2/I3
    Routing       SLICE_X113Y101       LUT6 (Prop_H6LUT_SLICEM_I3_O)
                                                                    0.090     3.559 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_2/O
                                       net (fo=1, routed)           0.278     3.837    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_2_n_0
    Routing       SLICE_X114Y91                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/I0
    Routing       SLICE_X114Y91        LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                                    0.123     3.960 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                                       net (fo=1, routed)           0.050     4.010    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    Routing       SLICE_X114Y91        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.250     2.432    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X114Y91        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.997ns  (logic 1.163ns (29.097%)  route 2.834ns (70.903%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        2.445ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.445ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.263ns (routing 0.690ns, distribution 1.573ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC1_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[10])
                                                                    0.753     0.753 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[10]
                                       net (fo=1, routed)           2.189     2.942    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac1_common_stat[10]
    Routing       SLICE_X114Y106                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_20/I3
    Routing       SLICE_X114Y106       LUT5 (Prop_H6LUT_SLICEL_I3_O)
                                                                    0.150     3.092 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_20/O
                                       net (fo=1, routed)           0.252     3.344    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_20_n_0
    Routing       SLICE_X112Y104                                                    f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_7/I3
    Routing       SLICE_X112Y104       LUT5 (Prop_B6LUT_SLICEM_I3_O)
                                                                    0.037     3.381 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_7/O
                                       net (fo=1, routed)           0.106     3.487    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_7_n_0
    Routing       SLICE_X113Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_2/I2
    Routing       SLICE_X113Y104       LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                                    0.101     3.588 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_2/O
                                       net (fo=1, routed)           0.215     3.803    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_2_n_0
    Routing       SLICE_X113Y96                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/I0
    Routing       SLICE_X113Y96        LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                                    0.122     3.925 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                                       net (fo=1, routed)           0.072     3.997    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    Routing       SLICE_X113Y96        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.263     2.445    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X113Y96        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.885ns  (logic 1.048ns (26.976%)  route 2.837ns (73.024%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        2.429ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.429ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.247ns (routing 0.690ns, distribution 1.557ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC1_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[8])
                                                                    0.731     0.731 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[8]
                                       net (fo=1, routed)           2.192     2.923    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac1_common_stat[8]
    Routing       SLICE_X114Y106                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_16/I4
    Routing       SLICE_X114Y106       LUT5 (Prop_F6LUT_SLICEL_I4_O)
                                                                    0.089     3.012 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_16/O
                                       net (fo=1, routed)           0.235     3.247    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_16_n_0
    Routing       SLICE_X111Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_7/I1
    Routing       SLICE_X111Y104       LUT6 (Prop_G6LUT_SLICEL_I1_O)
                                                                    0.097     3.344 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_7/O
                                       net (fo=1, routed)           0.141     3.485    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_7_n_0
    Routing       SLICE_X111Y103                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_2/I4
    Routing       SLICE_X111Y103       LUT6 (Prop_E6LUT_SLICEL_I4_O)
                                                                    0.035     3.520 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_2/O
                                       net (fo=1, routed)           0.219     3.739    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_2_n_0
    Routing       SLICE_X111Y94                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/I0
    Routing       SLICE_X111Y94        LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                                    0.096     3.835 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                                       net (fo=1, routed)           0.050     3.885    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    Routing       SLICE_X111Y94        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.247     2.429    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X111Y94        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.884ns  (logic 1.096ns (28.218%)  route 2.788ns (71.782%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        2.435ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.435ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.253ns (routing 0.690ns, distribution 1.563ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC1_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[12])
                                                                    0.759     0.759 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[12]
                                       net (fo=1, routed)           2.177     2.936    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac1_common_stat[12]
    Routing       SLICE_X110Y102                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_22/I4
    Routing       SLICE_X110Y102       LUT5 (Prop_E6LUT_SLICEM_I4_O)
                                                                    0.148     3.084 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_22/O
                                       net (fo=1, routed)           0.155     3.239    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_22_n_0
    Routing       SLICE_X110Y101                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_9/I5
    Routing       SLICE_X110Y101       LUT6 (Prop_H6LUT_SLICEM_I5_O)
                                                                    0.053     3.292 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_9/O
                                       net (fo=1, routed)           0.171     3.463    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_9_n_0
    Routing       SLICE_X113Y103                                                    f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_2/I2
    Routing       SLICE_X113Y103       LUT6 (Prop_B6LUT_SLICEM_I2_O)
                                                                    0.037     3.500 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_2/O
                                       net (fo=1, routed)           0.213     3.713    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_2_n_0
    Routing       SLICE_X113Y95                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/I0
    Routing       SLICE_X113Y95        LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                                    0.099     3.812 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                                       net (fo=1, routed)           0.072     3.884    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    Routing       SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.253     2.435    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.691ns  (logic 0.990ns (26.822%)  route 2.701ns (73.178%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        2.429ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.429ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.247ns (routing 0.690ns, distribution 1.557ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC1_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[9])
                                                                    0.674     0.674 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[9]
                                       net (fo=1, routed)           2.165     2.839    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac1_common_stat[9]
    Routing       SLICE_X114Y106                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_27/I4
    Routing       SLICE_X114Y106       LUT5 (Prop_E6LUT_SLICEL_I4_O)
                                                                    0.035     2.874 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_27/O
                                       net (fo=1, routed)           0.215     3.089    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_27_n_0
    Routing       SLICE_X112Y102                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_12/I2
    Routing       SLICE_X112Y102       LUT6 (Prop_D6LUT_SLICEM_I2_O)
                                                                    0.099     3.188 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_12/O
                                       net (fo=1, routed)           0.052     3.240    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_12_n_0
    Routing       SLICE_X112Y102                                                    f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_2/I5
    Routing       SLICE_X112Y102       LUT6 (Prop_C6LUT_SLICEM_I5_O)
                                                                    0.145     3.385 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_2/O
                                       net (fo=1, routed)           0.203     3.588    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_2_n_0
    Routing       SLICE_X112Y95                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/I0
    Routing       SLICE_X112Y95        LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                                    0.037     3.625 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                                       net (fo=1, routed)           0.066     3.691    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    Routing       SLICE_X112Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.247     2.429    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X112Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.832ns  (logic 0.466ns (25.437%)  route 1.366ns (74.563%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.702ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.702ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.555ns (routing 0.463ns, distribution 1.092ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC1_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[9])
                                                                    0.338     0.338 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[9]
                                       net (fo=1, routed)           1.095     1.433    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac1_common_stat[9]
    Routing       SLICE_X114Y106                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_27/I4
    Routing       SLICE_X114Y106       LUT5 (Prop_E6LUT_SLICEL_I4_O)
                                                                    0.014     1.447 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_27/O
                                       net (fo=1, routed)           0.111     1.558    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_27_n_0
    Routing       SLICE_X112Y102                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_12/I2
    Routing       SLICE_X112Y102       LUT6 (Prop_D6LUT_SLICEM_I2_O)
                                                                    0.041     1.599 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_12/O
                                       net (fo=1, routed)           0.029     1.628    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_12_n_0
    Routing       SLICE_X112Y102                                                    f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_2/I5
    Routing       SLICE_X112Y102       LUT6 (Prop_C6LUT_SLICEM_I5_O)
                                                                    0.059     1.687 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_2/O
                                       net (fo=1, routed)           0.107     1.794    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_2_n_0
    Routing       SLICE_X112Y95                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/I0
    Routing       SLICE_X112Y95        LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                                    0.014     1.808 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                                       net (fo=1, routed)           0.024     1.832    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    Routing       SLICE_X112Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.555     1.702    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X112Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.927ns  (logic 0.523ns (27.141%)  route 1.404ns (72.859%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.707ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.707ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.560ns (routing 0.463ns, distribution 1.097ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC1_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[12])
                                                                    0.386     0.386 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[12]
                                       net (fo=1, routed)           1.099     1.485    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac1_common_stat[12]
    Routing       SLICE_X110Y102                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_22/I4
    Routing       SLICE_X110Y102       LUT5 (Prop_E6LUT_SLICEM_I4_O)
                                                                    0.059     1.544 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_22/O
                                       net (fo=1, routed)           0.078     1.622    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_22_n_0
    Routing       SLICE_X110Y101                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_9/I5
    Routing       SLICE_X110Y101       LUT6 (Prop_H6LUT_SLICEM_I5_O)
                                                                    0.023     1.645 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_9/O
                                       net (fo=1, routed)           0.091     1.736    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_9_n_0
    Routing       SLICE_X113Y103                                                    f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_2/I2
    Routing       SLICE_X113Y103       LUT6 (Prop_B6LUT_SLICEM_I2_O)
                                                                    0.014     1.750 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_2/O
                                       net (fo=1, routed)           0.110     1.860    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_2_n_0
    Routing       SLICE_X113Y95                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/I0
    Routing       SLICE_X113Y95        LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                                    0.041     1.901 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                                       net (fo=1, routed)           0.026     1.927    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    Routing       SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.560     1.707    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.947ns  (logic 0.511ns (26.246%)  route 1.436ns (73.755%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.700ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.700ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.553ns (routing 0.463ns, distribution 1.090ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC1_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[8])
                                                                    0.382     0.382 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[8]
                                       net (fo=1, routed)           1.109     1.491    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac1_common_stat[8]
    Routing       SLICE_X114Y106                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_16/I4
    Routing       SLICE_X114Y106       LUT5 (Prop_F6LUT_SLICEL_I4_O)
                                                                    0.035     1.526 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_16/O
                                       net (fo=1, routed)           0.123     1.649    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_16_n_0
    Routing       SLICE_X111Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_7/I1
    Routing       SLICE_X111Y104       LUT6 (Prop_G6LUT_SLICEL_I1_O)
                                                                    0.040     1.689 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_7/O
                                       net (fo=1, routed)           0.072     1.761    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_7_n_0
    Routing       SLICE_X111Y103                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_2/I4
    Routing       SLICE_X111Y103       LUT6 (Prop_E6LUT_SLICEL_I4_O)
                                                                    0.014     1.775 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_2/O
                                       net (fo=1, routed)           0.115     1.890    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_2_n_0
    Routing       SLICE_X111Y94                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/I0
    Routing       SLICE_X111Y94        LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                                    0.040     1.930 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                                       net (fo=1, routed)           0.017     1.947    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    Routing       SLICE_X111Y94        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.553     1.700    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X111Y94        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.968ns  (logic 0.540ns (27.439%)  route 1.428ns (72.561%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        1.717ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.717ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.570ns (routing 0.463ns, distribution 1.107ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC1_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[10])
                                                                    0.375     0.375 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[10]
                                       net (fo=1, routed)           1.104     1.479    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac1_common_stat[10]
    Routing       SLICE_X114Y106                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_20/I3
    Routing       SLICE_X114Y106       LUT5 (Prop_H6LUT_SLICEL_I3_O)
                                                                    0.060     1.539 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_20/O
                                       net (fo=1, routed)           0.127     1.666    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_20_n_0
    Routing       SLICE_X112Y104                                                    f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_7/I3
    Routing       SLICE_X112Y104       LUT5 (Prop_B6LUT_SLICEM_I3_O)
                                                                    0.014     1.680 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_7/O
                                       net (fo=1, routed)           0.057     1.737    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_7_n_0
    Routing       SLICE_X113Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_2/I2
    Routing       SLICE_X113Y104       LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                                    0.041     1.778 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_2/O
                                       net (fo=1, routed)           0.114     1.892    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_2_n_0
    Routing       SLICE_X113Y96                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/I0
    Routing       SLICE_X113Y96        LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                                    0.050     1.942 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                                       net (fo=1, routed)           0.026     1.968    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    Routing       SLICE_X113Y96        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.570     1.717    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X113Y96        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.984ns  (logic 0.592ns (29.839%)  route 1.392ns (70.161%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        1.705ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.705ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.558ns (routing 0.463ns, distribution 1.095ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC1_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[14])
                                                                    0.398     0.398 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[14]
                                       net (fo=1, routed)           1.137     1.535    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac1_common_stat[14]
    Routing       SLICE_X114Y100                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_26/I0
    Routing       SLICE_X114Y100       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                                    0.059     1.594 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_26/O
                                       net (fo=1, routed)           0.047     1.641    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_26_n_0
    Routing       SLICE_X113Y100                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_9/I3
    Routing       SLICE_X113Y100       LUT6 (Prop_F6LUT_SLICEM_I3_O)
                                                                    0.050     1.691 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_9/O
                                       net (fo=1, routed)           0.047     1.738    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_9_n_0
    Routing       SLICE_X113Y101                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_2/I3
    Routing       SLICE_X113Y101       LUT6 (Prop_H6LUT_SLICEM_I3_O)
                                                                    0.035     1.773 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_2/O
                                       net (fo=1, routed)           0.144     1.917    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_2_n_0
    Routing       SLICE_X114Y91                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/I0
    Routing       SLICE_X114Y91        LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                                    0.050     1.967 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                                       net (fo=1, routed)           0.017     1.984    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    Routing       SLICE_X114Y91        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.558     1.705    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X114Y91        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        2.002ns  (logic 0.623ns (31.119%)  route 1.379ns (68.881%))
  Logic Levels:           4  (LUT3=1 LUT6=3)
  Clock Path Skew:        1.707ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.707ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.560ns (routing 0.463ns, distribution 1.097ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC1_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[15])
                                                                    0.413     0.413 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[15]
                                       net (fo=1, routed)           1.084     1.497    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac1_common_stat[15]
    Routing       SLICE_X114Y101                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_24/I1
    Routing       SLICE_X114Y101       LUT6 (Prop_G6LUT_SLICEL_I1_O)
                                                                    0.050     1.547 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_24/O
                                       net (fo=1, routed)           0.025     1.572    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_24_n_0
    Routing       SLICE_X114Y101                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_8/I1
    Routing       SLICE_X114Y101       LUT3 (Prop_E6LUT_SLICEL_I1_O)
                                                                    0.041     1.613 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_8/O
                                       net (fo=1, routed)           0.053     1.666    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_8_n_0
    Routing       SLICE_X114Y101                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_2/I1
    Routing       SLICE_X114Y101       LUT6 (Prop_H6LUT_SLICEL_I1_O)
                                                                    0.060     1.726 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_2/O
                                       net (fo=1, routed)           0.193     1.919    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_2_n_0
    Routing       SLICE_X113Y95                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/I0
    Routing       SLICE_X113Y95        LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                                    0.059     1.978 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                                       net (fo=1, routed)           0.024     2.002    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    Routing       SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.560     1.707    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        2.074ns  (logic 0.489ns (23.578%)  route 1.585ns (76.422%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.715ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.715ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.568ns (routing 0.463ns, distribution 1.105ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC1_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[11])
                                                                    0.367     0.367 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[11]
                                       net (fo=1, routed)           1.118     1.485    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac1_common_stat[11]
    Routing       SLICE_X114Y106                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_19/I4
    Routing       SLICE_X114Y106       LUT5 (Prop_G6LUT_SLICEL_I4_O)
                                                                    0.035     1.520 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_19/O
                                       net (fo=1, routed)           0.184     1.704    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_19_n_0
    Routing       SLICE_X111Y103                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_7/I0
    Routing       SLICE_X111Y103       LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                                    0.023     1.727 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_7/O
                                       net (fo=1, routed)           0.052     1.779    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_7_n_0
    Routing       SLICE_X112Y103                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_2/I4
    Routing       SLICE_X112Y103       LUT6 (Prop_C6LUT_SLICEM_I4_O)
                                                                    0.050     1.829 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_2/O
                                       net (fo=1, routed)           0.205     2.034    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_2_n_0
    Routing       SLICE_X113Y93                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/I0
    Routing       SLICE_X113Y93        LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                                    0.014     2.048 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                                       net (fo=1, routed)           0.026     2.074    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    Routing       SLICE_X113Y93        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.568     1.715    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X113Y93        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        2.202ns  (logic 0.707ns (32.107%)  route 1.495ns (67.893%))
  Logic Levels:           5  (LUT4=1 LUT6=4)
  Clock Path Skew:        1.698ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.698ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.551ns (routing 0.463ns, distribution 1.088ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC1_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[13])
                                                                    0.524     0.524 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[13]
                                       net (fo=1, routed)           1.133     1.657    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac1_common_stat[13]
    Routing       SLICE_X114Y103                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_34/I5
    Routing       SLICE_X114Y103       LUT6 (Prop_G6LUT_SLICEL_I5_O)
                                                                    0.035     1.692 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_34/O
                                       net (fo=1, routed)           0.101     1.793    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_34_n_0
    Routing       SLICE_X111Y103                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_21/I5
    Routing       SLICE_X111Y103       LUT6 (Prop_G6LUT_SLICEL_I5_O)
                                                                    0.035     1.828 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_21/O
                                       net (fo=1, routed)           0.025     1.853    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_21_n_0
    Routing       SLICE_X111Y103                                                    f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_7/I1
    Placement     SLICE_X111Y103       LUT6 (Prop_F6LUT_SLICEL_I1_O)
                                                                    0.040     1.893 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_7/O
                                       net (fo=1, routed)           0.041     1.934    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_7_n_0
    Placement     SLICE_X111Y103                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_2/I2
    Routing       SLICE_X111Y103       LUT4 (Prop_D6LUT_SLICEL_I2_O)
                                                                    0.022     1.956 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_2/O
                                       net (fo=1, routed)           0.174     2.130    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_2_n_0
    Routing       SLICE_X112Y91                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/I0
    Routing       SLICE_X112Y91        LUT6 (Prop_H6LUT_SLICEM_I0_O)
                                                                    0.051     2.181 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                                       net (fo=1, routed)           0.021     2.202    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    Routing       SLICE_X112Y91        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.551     1.698    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X112Y91        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_out1_d_1_clk_adc0_x2_0
  To Clock:  clk_pl_0

Max Delay         12750 Endpoints
Min Delay         12750 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/FABRIC_CLK
                            (rising edge-triggered cell HSADC clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.609ns  (logic 0.655ns (40.709%)  route 0.954ns (59.292%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        -3.750ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.430ns
    Source Clock Delay      (SCD):    6.180ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      3.091ns (routing 1.754ns, distribution 1.337ns)
  Clock Net Delay (Destination): 2.248ns (routing 0.690ns, distribution 1.558ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.416     2.943    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                   -0.127     2.816 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.245     3.061    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.028     3.089 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        3.091     6.180    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/m1_axis_aclk
                  HSADC_X0Y1           HSADC                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/FABRIC_CLK
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y1           HSADC (Prop_HSADC_FABRIC_CLK_STATUS_COMMON[5])
                                                                    0.450     6.630 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[5]
                                       net (fo=1, routed)           0.543     7.173    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc1_common_stat[5]
    Routing       SLICE_X111Y87                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_20/I3
    Routing       SLICE_X111Y87        LUT6 (Prop_D6LUT_SLICEL_I3_O)
                                                                    0.036     7.209 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_20/O
                                       net (fo=1, routed)           0.043     7.252    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_20_n_0
    Routing       SLICE_X111Y87                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_14/I0
    Routing       SLICE_X111Y87        LUT6 (Prop_G6LUT_SLICEL_I0_O)
                                                                    0.097     7.349 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_14/O
                                       net (fo=1, routed)           0.162     7.511    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_14_n_0
    Routing       SLICE_X111Y91                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_5/I0
    Routing       SLICE_X111Y91        LUT5 (Prop_E6LUT_SLICEL_I0_O)
                                                                    0.035     7.546 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_5/O
                                       net (fo=1, routed)           0.140     7.686    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_5_n_0
    Routing       SLICE_X112Y92                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_1/I3
    Routing       SLICE_X112Y92        LUT6 (Prop_C6LUT_SLICEM_I3_O)
                                                                    0.037     7.723 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_1/O
                                       net (fo=1, routed)           0.066     7.789    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_79
    Routing       SLICE_X112Y92        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[5]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.248     2.430    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X112Y92        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[5]/C

Slack:                    inf
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/cdc_adc1_clk_valid_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.504ns  (logic 0.077ns (15.277%)  route 0.427ns (84.723%))
  Logic Levels:           0  
  Clock Path Skew:        -3.624ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.388ns
    Source Clock Delay      (SCD):    6.012ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      2.923ns (routing 1.754ns, distribution 1.169ns)
  Clock Net Delay (Destination): 2.206ns (routing 0.690ns, distribution 1.516ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.416     2.943    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                   -0.127     2.816 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.245     3.061    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.028     3.089 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.923     6.012    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
                  SLICE_X96Y102        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  ---------------------------------------------------------------------------------    -------------------
    Placement     SLICE_X96Y102        FDRE (Prop_AFF_SLICEM_C_Q)
                                                                    0.077     6.089 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                                       net (fo=3, routed)           0.427     6.516    d_1_i/usp_rf_data_converter_0/inst/cdc_adc1_clk_valid_i/src_in
    Placement     SLICE_X104Y102       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_adc1_clk_valid_i/syncstages_ff_reg[0]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.206     2.388    d_1_i/usp_rf_data_converter_0/inst/cdc_adc1_clk_valid_i/dest_clk
                  SLICE_X104Y102       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_adc1_clk_valid_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/dest_req_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.523ns  (logic 0.079ns (15.097%)  route 0.444ns (84.903%))
  Logic Levels:           0  
  Clock Path Skew:        -3.700ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.161ns
    Source Clock Delay      (SCD):    5.861ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      2.772ns (routing 1.754ns, distribution 1.018ns)
  Clock Net Delay (Destination): 1.979ns (routing 0.690ns, distribution 1.289ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.416     2.943    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                   -0.127     2.816 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.245     3.061    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.028     3.089 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.772     5.861    d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/dest_clk
                  SLICE_X65Y116        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/dest_req_ff_reg/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X65Y116        FDRE (Prop_EFF_SLICEL_C_Q)
                                                                    0.079     5.940 r  d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/dest_req_ff_reg/Q
                                       net (fo=2, routed)           0.444     6.384    d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/xpm_cdc_single_dest2src_inst/src_in
    Routing       SLICE_X64Y114        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.979     2.161    d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/xpm_cdc_single_dest2src_inst/dest_clk
                  SLICE_X64Y114        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_time_tagger_0/inst/CMD/xpm_cdc_handshake_core/dest_req_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/CMD/xpm_cdc_handshake_core/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.392ns  (logic 0.080ns (20.411%)  route 0.312ns (79.589%))
  Logic Levels:           0  
  Clock Path Skew:        -3.656ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.204ns
    Source Clock Delay      (SCD):    5.860ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      2.771ns (routing 1.754ns, distribution 1.017ns)
  Clock Net Delay (Destination): 2.022ns (routing 0.690ns, distribution 1.332ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.416     2.943    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                   -0.127     2.816 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.245     3.061    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.028     3.089 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.771     5.860    d_1_i/qick_time_tagger_0/inst/CMD/xpm_cdc_handshake_core/dest_clk
                  SLICE_X71Y115        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/CMD/xpm_cdc_handshake_core/dest_req_ff_reg/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X71Y115        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                                    0.080     5.940 r  d_1_i/qick_time_tagger_0/inst/CMD/xpm_cdc_handshake_core/dest_req_ff_reg/Q
                                       net (fo=2, routed)           0.312     6.252    d_1_i/qick_time_tagger_0/inst/CMD/xpm_cdc_handshake_core/xpm_cdc_single_dest2src_inst/src_in
    Routing       SLICE_X70Y115        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/CMD/xpm_cdc_handshake_core/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.022     2.204    d_1_i/qick_time_tagger_0/inst/CMD/xpm_cdc_handshake_core/xpm_cdc_single_dest2src_inst/dest_clk
                  SLICE_X70Y115        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/CMD/xpm_cdc_handshake_core/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_time_tagger_1/inst/CMD/qtt_rst_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[10]_rep__239/D
                            (rising edge-triggered cell FDCE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        8.149ns  (logic 0.501ns (6.148%)  route 7.648ns (93.852%))
  Logic Levels:           3  (CARRY8=2 LUT2=1)
  Clock Path Skew:        -3.574ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.254ns
    Source Clock Delay      (SCD):    5.828ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      2.739ns (routing 1.754ns, distribution 0.985ns)
  Clock Net Delay (Destination): 2.072ns (routing 0.690ns, distribution 1.382ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.416     2.943    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                   -0.127     2.816 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.245     3.061    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.028     3.089 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.739     5.828    d_1_i/qick_time_tagger_1/inst/CMD/adc_clk
                  SLICE_X65Y127        FDCE                                         r  d_1_i/qick_time_tagger_1/inst/CMD/qtt_rst_reg/C
  ---------------------------------------------------------------------------------    -------------------
    Placement     SLICE_X65Y127        FDCE (Prop_DFF2_SLICEL_C_Q)
                                                                    0.081     5.909 f  d_1_i/qick_time_tagger_1/inst/CMD/qtt_rst_reg/Q
                                       net (fo=139, routed)         2.236     8.145    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/qtt_rst_req
    Moved         SLICE_X85Y244                                                     f  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr[0]_i_11/I1
    Moved         SLICE_X85Y244        LUT2 (Prop_A6LUT_SLICEL_I1_O)
                                                                    0.149     8.294 r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr[0]_i_11/O
                                       net (fo=1, routed)           0.009     8.303    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr[0]_i_11_n_0
    Moved         SLICE_X85Y244                                                     r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[0]_i_2/S[0]
    Moved         SLICE_X85Y244        CARRY8 (Prop_CARRY8_SLICEL_S[0]_CO[7])
                                                                    0.190     8.493 r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[0]_i_2/CO[7]
                                       net (fo=1, routed)           0.026     8.519    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[0]_i_2_n_0
    Moved         SLICE_X85Y245                                                     r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[8]_i_1/CI
    Moved         SLICE_X85Y245        CARRY8 (Prop_CARRY8_SLICEL_CI_O[2])
                                                                    0.081     8.600 r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[8]_i_1/O[2]
                                       net (fo=242, routed)         5.377    13.977    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[8]_i_1_n_13
    New           SLICE_X33Y473        FDCE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[10]_rep__239/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.072     2.254    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/ps_clk
                  SLICE_X33Y473        FDCE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[10]_rep__239/C

Slack:                    inf
  Source:                 d_1_i/qick_time_tagger_1/inst/CMD/qtt_rst_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[10]_rep__238/D
                            (rising edge-triggered cell FDCE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        8.117ns  (logic 0.501ns (6.172%)  route 7.616ns (93.828%))
  Logic Levels:           3  (CARRY8=2 LUT2=1)
  Clock Path Skew:        -3.574ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.254ns
    Source Clock Delay      (SCD):    5.828ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      2.739ns (routing 1.754ns, distribution 0.985ns)
  Clock Net Delay (Destination): 2.072ns (routing 0.690ns, distribution 1.382ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.416     2.943    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                   -0.127     2.816 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.245     3.061    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.028     3.089 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.739     5.828    d_1_i/qick_time_tagger_1/inst/CMD/adc_clk
                  SLICE_X65Y127        FDCE                                         r  d_1_i/qick_time_tagger_1/inst/CMD/qtt_rst_reg/C
  ---------------------------------------------------------------------------------    -------------------
    Placement     SLICE_X65Y127        FDCE (Prop_DFF2_SLICEL_C_Q)
                                                                    0.081     5.909 f  d_1_i/qick_time_tagger_1/inst/CMD/qtt_rst_reg/Q
                                       net (fo=139, routed)         2.236     8.145    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/qtt_rst_req
    Moved         SLICE_X85Y244                                                     f  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr[0]_i_11/I1
    Moved         SLICE_X85Y244        LUT2 (Prop_A6LUT_SLICEL_I1_O)
                                                                    0.149     8.294 r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr[0]_i_11/O
                                       net (fo=1, routed)           0.009     8.303    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr[0]_i_11_n_0
    Moved         SLICE_X85Y244                                                     r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[0]_i_2/S[0]
    Moved         SLICE_X85Y244        CARRY8 (Prop_CARRY8_SLICEL_S[0]_CO[7])
                                                                    0.190     8.493 r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[0]_i_2/CO[7]
                                       net (fo=1, routed)           0.026     8.519    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[0]_i_2_n_0
    Moved         SLICE_X85Y245                                                     r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[8]_i_1/CI
    Moved         SLICE_X85Y245        CARRY8 (Prop_CARRY8_SLICEL_CI_O[2])
                                                                    0.081     8.600 r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[8]_i_1/O[2]
                                       net (fo=242, routed)         5.345    13.945    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[8]_i_1_n_13
    New           SLICE_X33Y473        FDCE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[10]_rep__238/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.072     2.254    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/ps_clk
                  SLICE_X33Y473        FDCE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[10]_rep__238/C

Slack:                    inf
  Source:                 d_1_i/qick_time_tagger_1/inst/CMD/qtt_rst_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[10]_rep__236/D
                            (rising edge-triggered cell FDCE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        8.018ns  (logic 0.501ns (6.249%)  route 7.517ns (93.751%))
  Logic Levels:           3  (CARRY8=2 LUT2=1)
  Clock Path Skew:        -3.579ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.249ns
    Source Clock Delay      (SCD):    5.828ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      2.739ns (routing 1.754ns, distribution 0.985ns)
  Clock Net Delay (Destination): 2.067ns (routing 0.690ns, distribution 1.377ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.416     2.943    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                   -0.127     2.816 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.245     3.061    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.028     3.089 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.739     5.828    d_1_i/qick_time_tagger_1/inst/CMD/adc_clk
                  SLICE_X65Y127        FDCE                                         r  d_1_i/qick_time_tagger_1/inst/CMD/qtt_rst_reg/C
  ---------------------------------------------------------------------------------    -------------------
    Placement     SLICE_X65Y127        FDCE (Prop_DFF2_SLICEL_C_Q)
                                                                    0.081     5.909 f  d_1_i/qick_time_tagger_1/inst/CMD/qtt_rst_reg/Q
                                       net (fo=139, routed)         2.236     8.145    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/qtt_rst_req
    Moved         SLICE_X85Y244                                                     f  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr[0]_i_11/I1
    Moved         SLICE_X85Y244        LUT2 (Prop_A6LUT_SLICEL_I1_O)
                                                                    0.149     8.294 r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr[0]_i_11/O
                                       net (fo=1, routed)           0.009     8.303    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr[0]_i_11_n_0
    Moved         SLICE_X85Y244                                                     r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[0]_i_2/S[0]
    Moved         SLICE_X85Y244        CARRY8 (Prop_CARRY8_SLICEL_S[0]_CO[7])
                                                                    0.190     8.493 r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[0]_i_2/CO[7]
                                       net (fo=1, routed)           0.026     8.519    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[0]_i_2_n_0
    Moved         SLICE_X85Y245                                                     r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[8]_i_1/CI
    Moved         SLICE_X85Y245        CARRY8 (Prop_CARRY8_SLICEL_CI_O[2])
                                                                    0.081     8.600 r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[8]_i_1/O[2]
                                       net (fo=242, routed)         5.246    13.846    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[8]_i_1_n_13
    New           SLICE_X33Y463        FDCE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[10]_rep__236/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.067     2.249    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/ps_clk
                  SLICE_X33Y463        FDCE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[10]_rep__236/C

Slack:                    inf
  Source:                 d_1_i/qick_time_tagger_1/inst/CMD/qtt_rst_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[10]_rep__237/D
                            (rising edge-triggered cell FDCE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        7.959ns  (logic 0.501ns (6.295%)  route 7.458ns (93.705%))
  Logic Levels:           3  (CARRY8=2 LUT2=1)
  Clock Path Skew:        -3.576ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.252ns
    Source Clock Delay      (SCD):    5.828ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      2.739ns (routing 1.754ns, distribution 0.985ns)
  Clock Net Delay (Destination): 2.070ns (routing 0.690ns, distribution 1.380ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.416     2.943    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                   -0.127     2.816 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.245     3.061    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.028     3.089 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.739     5.828    d_1_i/qick_time_tagger_1/inst/CMD/adc_clk
                  SLICE_X65Y127        FDCE                                         r  d_1_i/qick_time_tagger_1/inst/CMD/qtt_rst_reg/C
  ---------------------------------------------------------------------------------    -------------------
    Placement     SLICE_X65Y127        FDCE (Prop_DFF2_SLICEL_C_Q)
                                                                    0.081     5.909 f  d_1_i/qick_time_tagger_1/inst/CMD/qtt_rst_reg/Q
                                       net (fo=139, routed)         2.236     8.145    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/qtt_rst_req
    Moved         SLICE_X85Y244                                                     f  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr[0]_i_11/I1
    Moved         SLICE_X85Y244        LUT2 (Prop_A6LUT_SLICEL_I1_O)
                                                                    0.149     8.294 r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr[0]_i_11/O
                                       net (fo=1, routed)           0.009     8.303    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr[0]_i_11_n_0
    Moved         SLICE_X85Y244                                                     r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[0]_i_2/S[0]
    Moved         SLICE_X85Y244        CARRY8 (Prop_CARRY8_SLICEL_S[0]_CO[7])
                                                                    0.190     8.493 r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[0]_i_2/CO[7]
                                       net (fo=1, routed)           0.026     8.519    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[0]_i_2_n_0
    Moved         SLICE_X85Y245                                                     r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[8]_i_1/CI
    Moved         SLICE_X85Y245        CARRY8 (Prop_CARRY8_SLICEL_CI_O[2])
                                                                    0.081     8.600 r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[8]_i_1/O[2]
                                       net (fo=242, routed)         5.187    13.787    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[8]_i_1_n_13
    New           SLICE_X33Y468        FDCE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[10]_rep__237/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.070     2.252    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/ps_clk
                  SLICE_X33Y468        FDCE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[10]_rep__237/C

Slack:                    inf
  Source:                 d_1_i/qick_time_tagger_1/inst/CMD/qtt_rst_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[10]_rep__234/D
                            (rising edge-triggered cell FDCE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        7.950ns  (logic 0.501ns (6.302%)  route 7.449ns (93.698%))
  Logic Levels:           3  (CARRY8=2 LUT2=1)
  Clock Path Skew:        -3.591ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.237ns
    Source Clock Delay      (SCD):    5.828ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      2.739ns (routing 1.754ns, distribution 0.985ns)
  Clock Net Delay (Destination): 2.055ns (routing 0.690ns, distribution 1.365ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.416     2.943    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                   -0.127     2.816 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.245     3.061    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.028     3.089 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.739     5.828    d_1_i/qick_time_tagger_1/inst/CMD/adc_clk
                  SLICE_X65Y127        FDCE                                         r  d_1_i/qick_time_tagger_1/inst/CMD/qtt_rst_reg/C
  ---------------------------------------------------------------------------------    -------------------
    Placement     SLICE_X65Y127        FDCE (Prop_DFF2_SLICEL_C_Q)
                                                                    0.081     5.909 f  d_1_i/qick_time_tagger_1/inst/CMD/qtt_rst_reg/Q
                                       net (fo=139, routed)         2.236     8.145    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/qtt_rst_req
    Moved         SLICE_X85Y244                                                     f  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr[0]_i_11/I1
    Moved         SLICE_X85Y244        LUT2 (Prop_A6LUT_SLICEL_I1_O)
                                                                    0.149     8.294 r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr[0]_i_11/O
                                       net (fo=1, routed)           0.009     8.303    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr[0]_i_11_n_0
    Moved         SLICE_X85Y244                                                     r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[0]_i_2/S[0]
    Moved         SLICE_X85Y244        CARRY8 (Prop_CARRY8_SLICEL_S[0]_CO[7])
                                                                    0.190     8.493 r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[0]_i_2/CO[7]
                                       net (fo=1, routed)           0.026     8.519    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[0]_i_2_n_0
    Moved         SLICE_X85Y245                                                     r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[8]_i_1/CI
    Moved         SLICE_X85Y245        CARRY8 (Prop_CARRY8_SLICEL_CI_O[2])
                                                                    0.081     8.600 r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[8]_i_1/O[2]
                                       net (fo=242, routed)         5.178    13.778    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[8]_i_1_n_13
    New           SLICE_X33Y453        FDCE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[10]_rep__234/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.055     2.237    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/ps_clk
                  SLICE_X33Y453        FDCE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[10]_rep__234/C

Slack:                    inf
  Source:                 d_1_i/qick_time_tagger_1/inst/CMD/qtt_rst_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[10]_rep__235/D
                            (rising edge-triggered cell FDCE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        7.914ns  (logic 0.501ns (6.331%)  route 7.413ns (93.669%))
  Logic Levels:           3  (CARRY8=2 LUT2=1)
  Clock Path Skew:        -3.584ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.244ns
    Source Clock Delay      (SCD):    5.828ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      2.739ns (routing 1.754ns, distribution 0.985ns)
  Clock Net Delay (Destination): 2.062ns (routing 0.690ns, distribution 1.372ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.416     2.943    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                   -0.127     2.816 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.245     3.061    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.028     3.089 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.739     5.828    d_1_i/qick_time_tagger_1/inst/CMD/adc_clk
                  SLICE_X65Y127        FDCE                                         r  d_1_i/qick_time_tagger_1/inst/CMD/qtt_rst_reg/C
  ---------------------------------------------------------------------------------    -------------------
    Placement     SLICE_X65Y127        FDCE (Prop_DFF2_SLICEL_C_Q)
                                                                    0.081     5.909 f  d_1_i/qick_time_tagger_1/inst/CMD/qtt_rst_reg/Q
                                       net (fo=139, routed)         2.236     8.145    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/qtt_rst_req
    Moved         SLICE_X85Y244                                                     f  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr[0]_i_11/I1
    Moved         SLICE_X85Y244        LUT2 (Prop_A6LUT_SLICEL_I1_O)
                                                                    0.149     8.294 r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr[0]_i_11/O
                                       net (fo=1, routed)           0.009     8.303    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr[0]_i_11_n_0
    Moved         SLICE_X85Y244                                                     r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[0]_i_2/S[0]
    Moved         SLICE_X85Y244        CARRY8 (Prop_CARRY8_SLICEL_S[0]_CO[7])
                                                                    0.190     8.493 r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[0]_i_2/CO[7]
                                       net (fo=1, routed)           0.026     8.519    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[0]_i_2_n_0
    Moved         SLICE_X85Y245                                                     r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[8]_i_1/CI
    Moved         SLICE_X85Y245        CARRY8 (Prop_CARRY8_SLICEL_CI_O[2])
                                                                    0.081     8.600 r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[8]_i_1/O[2]
                                       net (fo=242, routed)         5.142    13.742    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[8]_i_1_n_13
    New           SLICE_X33Y458        FDCE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[10]_rep__235/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.062     2.244    d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/ps_clk
                  SLICE_X33Y458        FDCE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/wr_ptr_reg[10]_rep__235/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/qick_time_tagger_0/inst/CMD/xpm_cdc_handshake_core/dest_req_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/CMD/xpm_cdc_handshake_core/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.154ns  (logic 0.039ns (25.273%)  route 0.115ns (74.727%))
  Logic Levels:           0  
  Clock Path Skew:        -1.962ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.553ns
    Source Clock Delay      (SCD):    3.516ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      1.528ns (routing 0.960ns, distribution 0.568ns)
  Clock Net Delay (Destination): 1.406ns (routing 0.463ns, distribution 0.943ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           1.332     1.595    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                    0.230     1.825 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.146     1.971    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.017     1.988 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        1.528     3.516    d_1_i/qick_time_tagger_0/inst/CMD/xpm_cdc_handshake_core/dest_clk
                  SLICE_X71Y115        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/CMD/xpm_cdc_handshake_core/dest_req_ff_reg/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X71Y115        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                                    0.039     3.555 r  d_1_i/qick_time_tagger_0/inst/CMD/xpm_cdc_handshake_core/dest_req_ff_reg/Q
                                       net (fo=2, routed)           0.115     3.670    d_1_i/qick_time_tagger_0/inst/CMD/xpm_cdc_handshake_core/xpm_cdc_single_dest2src_inst/src_in
    Routing       SLICE_X70Y115        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/CMD/xpm_cdc_handshake_core/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.406     1.553    d_1_i/qick_time_tagger_0/inst/CMD/xpm_cdc_handshake_core/xpm_cdc_single_dest2src_inst/dest_clk
                  SLICE_X70Y115        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/CMD/xpm_cdc_handshake_core/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/dest_req_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.223ns  (logic 0.039ns (17.481%)  route 0.184ns (82.518%))
  Logic Levels:           0  
  Clock Path Skew:        -1.990ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.525ns
    Source Clock Delay      (SCD):    3.516ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      1.528ns (routing 0.960ns, distribution 0.568ns)
  Clock Net Delay (Destination): 1.378ns (routing 0.463ns, distribution 0.915ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           1.332     1.595    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                    0.230     1.825 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.146     1.971    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.017     1.988 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        1.528     3.516    d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/dest_clk
                  SLICE_X65Y116        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/dest_req_ff_reg/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X65Y116        FDRE (Prop_EFF_SLICEL_C_Q)
                                                                    0.039     3.555 r  d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/dest_req_ff_reg/Q
                                       net (fo=2, routed)           0.184     3.739    d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/xpm_cdc_single_dest2src_inst/src_in
    Routing       SLICE_X64Y114        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.378     1.525    d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/xpm_cdc_single_dest2src_inst/dest_clk
                  SLICE_X64Y114        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/CMD/xpm_cdc_handshake_core/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/cdc_adc1_clk_valid_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.231ns  (logic 0.038ns (16.473%)  route 0.193ns (83.527%))
  Logic Levels:           0  
  Clock Path Skew:        -1.920ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.676ns
    Source Clock Delay      (SCD):    3.596ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      1.608ns (routing 0.960ns, distribution 0.648ns)
  Clock Net Delay (Destination): 1.529ns (routing 0.463ns, distribution 1.066ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           1.332     1.595    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                    0.230     1.825 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.146     1.971    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.017     1.988 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        1.608     3.596    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
                  SLICE_X96Y102        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  ---------------------------------------------------------------------------------    -------------------
    Placement     SLICE_X96Y102        FDRE (Prop_AFF_SLICEM_C_Q)
                                                                    0.038     3.634 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                                       net (fo=3, routed)           0.193     3.826    d_1_i/usp_rf_data_converter_0/inst/cdc_adc1_clk_valid_i/src_in
    Placement     SLICE_X104Y102       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_adc1_clk_valid_i/syncstages_ff_reg[0]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.529     1.676    d_1_i/usp_rf_data_converter_0/inst/cdc_adc1_clk_valid_i/dest_clk
                  SLICE_X104Y102       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_adc1_clk_valid_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/FABRIC_CLK
                            (rising edge-triggered cell HSADC clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.770ns  (logic 0.310ns (40.260%)  route 0.460ns (59.740%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        -1.969ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.704ns
    Source Clock Delay      (SCD):    3.673ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      1.685ns (routing 0.960ns, distribution 0.725ns)
  Clock Net Delay (Destination): 1.557ns (routing 0.463ns, distribution 1.094ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           1.332     1.595    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                    0.230     1.825 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.146     1.971    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.017     1.988 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        1.685     3.673    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/m1_axis_aclk
                  HSADC_X0Y1           HSADC                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/FABRIC_CLK
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y1           HSADC (Prop_HSADC_FABRIC_CLK_STATUS_COMMON[5])
                                                                    0.228     3.901 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[5]
                                       net (fo=1, routed)           0.256     4.157    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc1_common_stat[5]
    Routing       SLICE_X111Y87                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_20/I3
    Routing       SLICE_X111Y87        LUT6 (Prop_D6LUT_SLICEL_I3_O)
                                                                    0.014     4.171 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_20/O
                                       net (fo=1, routed)           0.023     4.194    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_20_n_0
    Routing       SLICE_X111Y87                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_14/I0
    Routing       SLICE_X111Y87        LUT6 (Prop_G6LUT_SLICEL_I0_O)
                                                                    0.040     4.234 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_14/O
                                       net (fo=1, routed)           0.084     4.318    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_14_n_0
    Routing       SLICE_X111Y91                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_5/I0
    Routing       SLICE_X111Y91        LUT5 (Prop_E6LUT_SLICEL_I0_O)
                                                                    0.014     4.332 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_5/O
                                       net (fo=1, routed)           0.073     4.405    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_5_n_0
    Routing       SLICE_X112Y92                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_1/I3
    Routing       SLICE_X112Y92        LUT6 (Prop_C6LUT_SLICEM_I3_O)
                                                                    0.014     4.419 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_1/O
                                       net (fo=1, routed)           0.024     4.443    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_79
    Routing       SLICE_X112Y92        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[5]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.557     1.704    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X112Y92        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[5]/C

Slack:                    inf
  Source:                 d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_gray_2r_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/wr_gptr_rcd_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.097ns  (logic 0.039ns (40.206%)  route 0.058ns (59.794%))
  Logic Levels:           0  
  Clock Path Skew:        -1.966ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.531ns
    Source Clock Delay      (SCD):    3.498ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      1.510ns (routing 0.960ns, distribution 0.550ns)
  Clock Net Delay (Destination): 1.384ns (routing 0.463ns, distribution 0.921ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           1.332     1.595    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                    0.230     1.825 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.146     1.971    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.017     1.988 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        1.510     3.498    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/adc_clk
                  SLICE_X71Y134        FDCE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_gray_2r_reg[1]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X71Y134        FDCE (Prop_CFF_SLICEL_C_Q)
                                                                    0.039     3.537 r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_gray_2r_reg[1]/Q
                                       net (fo=1, routed)           0.058     3.595    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/count_gray_2r[1]
    Routing       SLICE_X71Y134        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/wr_gptr_rcd_reg[1]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.384     1.531    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/ps_clk
                  SLICE_X71Y134        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/wr_gptr_rcd_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_gray_2r_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/wr_gptr_rcd_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.099ns  (logic 0.039ns (39.394%)  route 0.060ns (60.606%))
  Logic Levels:           0  
  Clock Path Skew:        -1.966ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.531ns
    Source Clock Delay      (SCD):    3.498ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      1.510ns (routing 0.960ns, distribution 0.550ns)
  Clock Net Delay (Destination): 1.384ns (routing 0.463ns, distribution 0.921ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           1.332     1.595    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                    0.230     1.825 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.146     1.971    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.017     1.988 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        1.510     3.498    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/adc_clk
                  SLICE_X71Y134        FDCE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_gray_2r_reg[3]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X71Y134        FDCE (Prop_BFF_SLICEL_C_Q)
                                                                    0.039     3.537 r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_gray_2r_reg[3]/Q
                                       net (fo=1, routed)           0.060     3.597    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/count_gray_2r[3]
    Routing       SLICE_X71Y134        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/wr_gptr_rcd_reg[3]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.384     1.531    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/ps_clk
                  SLICE_X71Y134        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/wr_gptr_rcd_reg[3]/C

Slack:                    inf
  Source:                 d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/sync_p_i/gcc_wr_ptr/count_gray_2r_reg[6]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/sync_p_i/wr_gptr_cdc_reg[6]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.101ns  (logic 0.038ns (37.624%)  route 0.063ns (62.376%))
  Logic Levels:           0  
  Clock Path Skew:        -1.989ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.508ns
    Source Clock Delay      (SCD):    3.497ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      1.509ns (routing 0.960ns, distribution 0.549ns)
  Clock Net Delay (Destination): 1.361ns (routing 0.463ns, distribution 0.898ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           1.332     1.595    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                    0.230     1.825 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.146     1.971    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.017     1.988 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        1.509     3.497    d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/sync_p_i/gcc_wr_ptr/adc_clk
                  SLICE_X63Y172        FDCE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/sync_p_i/gcc_wr_ptr/count_gray_2r_reg[6]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X63Y172        FDCE (Prop_AFF_SLICEM_C_Q)
                                                                    0.038     3.535 r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/sync_p_i/gcc_wr_ptr/count_gray_2r_reg[6]/Q
                                       net (fo=1, routed)           0.063     3.598    d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/sync_p_i/gcc_wr_ptr_n_1
    Routing       SLICE_X63Y172        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/sync_p_i/wr_gptr_cdc_reg[6]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.361     1.508    d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/sync_p_i/ps_clk
                  SLICE_X63Y172        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/sync_p_i/wr_gptr_cdc_reg[6]/C

Slack:                    inf
  Source:                 d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/sync_p_i/gcc_wr_ptr/count_gray_2r_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/sync_p_i/wr_gptr_cdc_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.116ns  (logic 0.040ns (34.483%)  route 0.076ns (65.517%))
  Logic Levels:           0  
  Clock Path Skew:        -1.947ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.549ns
    Source Clock Delay      (SCD):    3.496ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      1.508ns (routing 0.960ns, distribution 0.548ns)
  Clock Net Delay (Destination): 1.402ns (routing 0.463ns, distribution 0.939ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           1.332     1.595    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                    0.230     1.825 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.146     1.971    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.017     1.988 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        1.508     3.496    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/sync_p_i/gcc_wr_ptr/adc_clk
                  SLICE_X71Y123        FDCE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/sync_p_i/gcc_wr_ptr/count_gray_2r_reg[0]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X71Y123        FDCE (Prop_AFF2_SLICEL_C_Q)
                                                                    0.040     3.536 r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/sync_p_i/gcc_wr_ptr/count_gray_2r_reg[0]/Q
                                       net (fo=1, routed)           0.076     3.612    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/sync_p_i/gcc_wr_ptr_n_7
    Routing       SLICE_X72Y123        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/sync_p_i/wr_gptr_cdc_reg[0]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.402     1.549    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/sync_p_i/ps_clk
                  SLICE_X72Y123        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/sync_p_i/wr_gptr_cdc_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/sync_p_i/gcc_wr_ptr/count_gray_2r_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/sync_p_i/wr_gptr_cdc_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.118ns  (logic 0.040ns (33.898%)  route 0.078ns (66.102%))
  Logic Levels:           0  
  Clock Path Skew:        -1.992ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.503ns
    Source Clock Delay      (SCD):    3.495ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      1.507ns (routing 0.960ns, distribution 0.547ns)
  Clock Net Delay (Destination): 1.356ns (routing 0.463ns, distribution 0.893ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           1.332     1.595    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                    0.230     1.825 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.146     1.971    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.017     1.988 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        1.507     3.495    d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/sync_p_i/gcc_wr_ptr/adc_clk
                  SLICE_X62Y173        FDCE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/sync_p_i/gcc_wr_ptr/count_gray_2r_reg[1]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X62Y173        FDCE (Prop_AFF2_SLICEL_C_Q)
                                                                    0.040     3.535 r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/sync_p_i/gcc_wr_ptr/count_gray_2r_reg[1]/Q
                                       net (fo=1, routed)           0.078     3.613    d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/sync_p_i/gcc_wr_ptr_n_6
    Routing       SLICE_X62Y173        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/sync_p_i/wr_gptr_cdc_reg[1]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.356     1.503    d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/sync_p_i/ps_clk
                  SLICE_X62Y173        FDRE                                         r  d_1_i/qick_time_tagger_1/inst/QTT/TAG_MEM/MEM0/sync_p_i/wr_gptr_cdc_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/sync_p_i/gcc_wr_ptr/count_gray_2r_reg[7]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/sync_p_i/wr_gptr_cdc_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.116ns  (logic 0.038ns (32.759%)  route 0.078ns (67.241%))
  Logic Levels:           0  
  Clock Path Skew:        -1.951ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.549ns
    Source Clock Delay      (SCD):    3.500ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      1.512ns (routing 0.960ns, distribution 0.552ns)
  Clock Net Delay (Destination): 1.402ns (routing 0.463ns, distribution 0.939ns)
  Timing Exception:       Asynchronous Clock Groups

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           1.332     1.595    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                    0.230     1.825 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.146     1.971    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.017     1.988 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        1.512     3.500    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/sync_p_i/gcc_wr_ptr/adc_clk
                  SLICE_X72Y124        FDCE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/sync_p_i/gcc_wr_ptr/count_gray_2r_reg[7]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X72Y124        FDCE (Prop_AFF_SLICEM_C_Q)
                                                                    0.038     3.538 r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/sync_p_i/gcc_wr_ptr/count_gray_2r_reg[7]/Q
                                       net (fo=1, routed)           0.078     3.616    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/sync_p_i/gcc_wr_ptr_n_0
    Routing       SLICE_X72Y123        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/sync_p_i/wr_gptr_cdc_reg[7]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.402     1.549    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/sync_p_i/ps_clk
                  SLICE_X72Y123        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/sync_p_i/wr_gptr_cdc_reg[7]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_pl_0
  To Clock:  clk_pl_0

Max Delay            90 Endpoints
Min Delay            90 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.408ns  (logic 0.233ns (6.837%)  route 3.175ns (93.163%))
  Logic Levels:           1  (LUT1=1)
  Clock Path Skew:        -0.469ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.133ns
    Source Clock Delay      (SCD):    2.602ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.376ns (routing 0.763ns, distribution 1.613ns)
  Clock Net Delay (Destination): 1.951ns (routing 0.690ns, distribution 1.261ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.376     2.602    d_1_i/rst_100/U0/slowest_sync_clk
                  SLICE_X85Y80         FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
  ---------------------------------------------------------------------------------    -------------------
    Placement     SLICE_X85Y80         FDRE (Prop_AFF2_SLICEL_C_Q)
                                                                    0.081     2.683 f  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/Q
                                       net (fo=5138, routed)        3.119     5.802    d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/peripheral_aresetn[0]_bufg_place_replica
    Placement     SLICE_X42Y40                                                      f  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1/I0
    Routing       SLICE_X42Y40         LUT1 (Prop_H6LUT_SLICEM_I0_O)
                                                                    0.152     5.954 r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1/O
                                       net (fo=1, routed)           0.056     6.010    d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/asr_d1
    Routing       SLICE_X42Y40         FDRE                                         r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.951     2.133    d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/aclk
                  SLICE_X42Y40         FDRE                                         r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C

Slack:                    inf
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        3.152ns  (logic 0.081ns (2.570%)  route 3.071ns (97.430%))
  Logic Levels:           0  
  Clock Path Skew:        -0.404ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.198ns
    Source Clock Delay      (SCD):    2.602ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.376ns (routing 0.763ns, distribution 1.613ns)
  Clock Net Delay (Destination): 2.016ns (routing 0.690ns, distribution 1.326ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.376     2.602    d_1_i/rst_100/U0/slowest_sync_clk
                  SLICE_X85Y80         FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
  ---------------------------------------------------------------------------------    -------------------
    Placement     SLICE_X85Y80         FDRE (Prop_AFF2_SLICEL_C_Q)
                                                                    0.081     2.683 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/Q
                                       net (fo=5138, routed)        3.071     5.754    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/src_arst
    Placement     SLICE_X24Y97         FDPE                                         f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE  (IS_INVERTED)
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.016     2.198    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/dest_clk
                  SLICE_X24Y97         FDPE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/PRE
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        3.152ns  (logic 0.081ns (2.570%)  route 3.071ns (97.430%))
  Logic Levels:           0  
  Clock Path Skew:        -0.404ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.198ns
    Source Clock Delay      (SCD):    2.602ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.376ns (routing 0.763ns, distribution 1.613ns)
  Clock Net Delay (Destination): 2.016ns (routing 0.690ns, distribution 1.326ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.376     2.602    d_1_i/rst_100/U0/slowest_sync_clk
                  SLICE_X85Y80         FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
  ---------------------------------------------------------------------------------    -------------------
    Placement     SLICE_X85Y80         FDRE (Prop_AFF2_SLICEL_C_Q)
                                                                    0.081     2.683 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/Q
                                       net (fo=5138, routed)        3.071     5.754    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/src_arst
    Placement     SLICE_X24Y97         FDPE                                         f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/PRE  (IS_INVERTED)
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.016     2.198    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/dest_clk
                  SLICE_X24Y97         FDPE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        3.148ns  (logic 0.081ns (2.573%)  route 3.067ns (97.427%))
  Logic Levels:           0  
  Clock Path Skew:        -0.401ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.201ns
    Source Clock Delay      (SCD):    2.602ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.376ns (routing 0.763ns, distribution 1.613ns)
  Clock Net Delay (Destination): 2.019ns (routing 0.690ns, distribution 1.329ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.376     2.602    d_1_i/rst_100/U0/slowest_sync_clk
                  SLICE_X85Y80         FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
  ---------------------------------------------------------------------------------    -------------------
    Placement     SLICE_X85Y80         FDRE (Prop_AFF2_SLICEL_C_Q)
                                                                    0.081     2.683 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/Q
                                       net (fo=5138, routed)        3.067     5.750    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/src_arst
    Placement     SLICE_X30Y70         FDPE                                         f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE  (IS_INVERTED)
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.019     2.201    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/dest_clk
                  SLICE_X30Y70         FDPE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/PRE
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        3.148ns  (logic 0.081ns (2.573%)  route 3.067ns (97.427%))
  Logic Levels:           0  
  Clock Path Skew:        -0.401ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.201ns
    Source Clock Delay      (SCD):    2.602ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.376ns (routing 0.763ns, distribution 1.613ns)
  Clock Net Delay (Destination): 2.019ns (routing 0.690ns, distribution 1.329ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.376     2.602    d_1_i/rst_100/U0/slowest_sync_clk
                  SLICE_X85Y80         FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
  ---------------------------------------------------------------------------------    -------------------
    Placement     SLICE_X85Y80         FDRE (Prop_AFF2_SLICEL_C_Q)
                                                                    0.081     2.683 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/Q
                                       net (fo=5138, routed)        3.067     5.750    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/src_arst
    Placement     SLICE_X30Y70         FDPE                                         f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/PRE  (IS_INVERTED)
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.019     2.201    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/dest_clk
                  SLICE_X30Y70         FDPE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        3.115ns  (logic 0.081ns (2.600%)  route 3.034ns (97.400%))
  Logic Levels:           0  
  Clock Path Skew:        -0.399ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.203ns
    Source Clock Delay      (SCD):    2.602ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.376ns (routing 0.763ns, distribution 1.613ns)
  Clock Net Delay (Destination): 2.021ns (routing 0.690ns, distribution 1.331ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.376     2.602    d_1_i/rst_100/U0/slowest_sync_clk
                  SLICE_X85Y80         FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
  ---------------------------------------------------------------------------------    -------------------
    Placement     SLICE_X85Y80         FDRE (Prop_AFF2_SLICEL_C_Q)
                                                                    0.081     2.683 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/Q
                                       net (fo=5138, routed)        3.034     5.717    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/src_arst
    Placement     SLICE_X30Y64         FDPE                                         f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE  (IS_INVERTED)
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.021     2.203    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/dest_clk
                  SLICE_X30Y64         FDPE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/PRE
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        3.115ns  (logic 0.081ns (2.600%)  route 3.034ns (97.400%))
  Logic Levels:           0  
  Clock Path Skew:        -0.399ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.203ns
    Source Clock Delay      (SCD):    2.602ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.376ns (routing 0.763ns, distribution 1.613ns)
  Clock Net Delay (Destination): 2.021ns (routing 0.690ns, distribution 1.331ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.376     2.602    d_1_i/rst_100/U0/slowest_sync_clk
                  SLICE_X85Y80         FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
  ---------------------------------------------------------------------------------    -------------------
    Placement     SLICE_X85Y80         FDRE (Prop_AFF2_SLICEL_C_Q)
                                                                    0.081     2.683 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/Q
                                       net (fo=5138, routed)        3.034     5.717    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/src_arst
    Placement     SLICE_X30Y64         FDPE                                         f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/PRE  (IS_INVERTED)
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.021     2.203    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/dest_clk
                  SLICE_X30Y64         FDPE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_dma_qtt/U0/I_RST_MODULE/REG_HRD_RST/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.812ns  (logic 0.081ns (2.880%)  route 2.731ns (97.120%))
  Logic Levels:           0  
  Clock Path Skew:        -0.471ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.131ns
    Source Clock Delay      (SCD):    2.602ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.376ns (routing 0.763ns, distribution 1.613ns)
  Clock Net Delay (Destination): 1.949ns (routing 0.690ns, distribution 1.259ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.376     2.602    d_1_i/rst_100/U0/slowest_sync_clk
                  SLICE_X85Y80         FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
  ---------------------------------------------------------------------------------    -------------------
    Placement     SLICE_X85Y80         FDRE (Prop_AFF2_SLICEL_C_Q)
                                                                    0.081     2.683 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/Q
                                       net (fo=5138, routed)        2.731     5.414    d_1_i/axi_dma_qtt/U0/I_RST_MODULE/REG_HRD_RST/peripheral_aresetn[0]_bufg_place_replica
    Placement     SLICE_X54Y54         FDRE                                         r  d_1_i/axi_dma_qtt/U0/I_RST_MODULE/REG_HRD_RST/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.949     2.131    d_1_i/axi_dma_qtt/U0/I_RST_MODULE/REG_HRD_RST/s_axi_lite_aclk
                  SLICE_X54Y54         FDRE                                         r  d_1_i/axi_dma_qtt/U0/I_RST_MODULE/REG_HRD_RST/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C

Slack:                    inf
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_dma_tproc/U0/I_RST_MODULE/REG_HRD_RST/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.624ns  (logic 0.081ns (3.087%)  route 2.543ns (96.913%))
  Logic Levels:           0  
  Clock Path Skew:        -0.472ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.130ns
    Source Clock Delay      (SCD):    2.602ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.376ns (routing 0.763ns, distribution 1.613ns)
  Clock Net Delay (Destination): 1.948ns (routing 0.690ns, distribution 1.258ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.376     2.602    d_1_i/rst_100/U0/slowest_sync_clk
                  SLICE_X85Y80         FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
  ---------------------------------------------------------------------------------    -------------------
    Placement     SLICE_X85Y80         FDRE (Prop_AFF2_SLICEL_C_Q)
                                                                    0.081     2.683 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/Q
                                       net (fo=5138, routed)        2.543     5.226    d_1_i/axi_dma_tproc/U0/I_RST_MODULE/REG_HRD_RST/peripheral_aresetn[0]_bufg_place_replica
    Placement     SLICE_X47Y50         FDRE                                         r  d_1_i/axi_dma_tproc/U0/I_RST_MODULE/REG_HRD_RST/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.948     2.130    d_1_i/axi_dma_tproc/U0/I_RST_MODULE/REG_HRD_RST/s_axi_lite_aclk
                  SLICE_X47Y50         FDRE                                         r  d_1_i/axi_dma_tproc/U0/I_RST_MODULE/REG_HRD_RST/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C

Slack:                    inf
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_dma_qtt/U0/I_RST_MODULE/REG_HRD_RST_OUT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.531ns  (logic 0.081ns (3.200%)  route 2.450ns (96.800%))
  Logic Levels:           0  
  Clock Path Skew:        -0.495ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.107ns
    Source Clock Delay      (SCD):    2.602ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.376ns (routing 0.763ns, distribution 1.613ns)
  Clock Net Delay (Destination): 1.925ns (routing 0.690ns, distribution 1.235ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.376     2.602    d_1_i/rst_100/U0/slowest_sync_clk
                  SLICE_X85Y80         FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
  ---------------------------------------------------------------------------------    -------------------
    Placement     SLICE_X85Y80         FDRE (Prop_AFF2_SLICEL_C_Q)
                                                                    0.081     2.683 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/Q
                                       net (fo=5138, routed)        2.450     5.133    d_1_i/axi_dma_qtt/U0/I_RST_MODULE/REG_HRD_RST_OUT/peripheral_aresetn[0]_bufg_place_replica
    Placement     SLICE_X48Y75         FDRE                                         r  d_1_i/axi_dma_qtt/U0/I_RST_MODULE/REG_HRD_RST_OUT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.925     2.107    d_1_i/axi_dma_qtt/U0/I_RST_MODULE/REG_HRD_RST_OUT/s_axi_lite_aclk
                  SLICE_X48Y75         FDRE                                         r  d_1_i/axi_dma_qtt/U0/I_RST_MODULE/REG_HRD_RST_OUT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/axis_switch_0/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_0/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.095ns  (logic 0.039ns (41.129%)  route 0.056ns (58.871%))
  Logic Levels:           0  
  Clock Path Skew:        0.184ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.493ns
    Source Clock Delay      (SCD):    1.309ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.189ns (routing 0.414ns, distribution 0.775ns)
  Clock Net Delay (Destination): 1.346ns (routing 0.463ns, distribution 0.883ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.189     1.309    d_1_i/axis_switch_0/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
                  SLICE_X47Y108        FDRE                                         r  d_1_i/axis_switch_0/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X47Y108        FDRE (Prop_AFF_SLICEL_C_Q)
                                                                    0.039     1.348 r  d_1_i/axis_switch_0/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/Q
                                       net (fo=2, routed)           0.056     1.404    d_1_i/axis_switch_0/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/src_in
    Routing       SLICE_X47Y108        FDRE                                         r  d_1_i/axis_switch_0/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.346     1.493    d_1_i/axis_switch_0/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/dest_clk
                  SLICE_X47Y108        FDRE                                         r  d_1_i/axis_switch_0/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_0/inst/gen_static_router.inst_static_router/inst_start_router_config/ctrl_soft_reset_r_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_0/inst/gen_static_router.gen_synch.inst_rst_synch/inst_xpm_cdc_single/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.130ns  (logic 0.038ns (29.231%)  route 0.092ns (70.769%))
  Logic Levels:           0  
  Clock Path Skew:        0.182ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.493ns
    Source Clock Delay      (SCD):    1.311ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.191ns (routing 0.414ns, distribution 0.777ns)
  Clock Net Delay (Destination): 1.346ns (routing 0.463ns, distribution 0.883ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.191     1.311    d_1_i/axis_switch_0/inst/gen_static_router.inst_static_router/inst_start_router_config/s_axi_ctrl_aclk
                  SLICE_X48Y111        FDRE                                         r  d_1_i/axis_switch_0/inst/gen_static_router.inst_static_router/inst_start_router_config/ctrl_soft_reset_r_reg/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X48Y111        FDRE (Prop_CFF_SLICEM_C_Q)
                                                                    0.038     1.349 r  d_1_i/axis_switch_0/inst/gen_static_router.inst_static_router/inst_start_router_config/ctrl_soft_reset_r_reg/Q
                                       net (fo=1, routed)           0.092     1.441    d_1_i/axis_switch_0/inst/gen_static_router.gen_synch.inst_rst_synch/inst_xpm_cdc_single/src_in
    Routing       SLICE_X48Y111        FDRE                                         r  d_1_i/axis_switch_0/inst/gen_static_router.gen_synch.inst_rst_synch/inst_xpm_cdc_single/syncstages_ff_reg[0]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.346     1.493    d_1_i/axis_switch_0/inst/gen_static_router.gen_synch.inst_rst_synch/inst_xpm_cdc_single/dest_clk
                  SLICE_X48Y111        FDRE                                         r  d_1_i/axis_switch_0/inst/gen_static_router.gen_synch.inst_rst_synch/inst_xpm_cdc_single/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_tt/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_tt/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.137ns  (logic 0.038ns (27.718%)  route 0.099ns (72.282%))
  Logic Levels:           0  
  Clock Path Skew:        0.177ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.482ns
    Source Clock Delay      (SCD):    1.305ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.185ns (routing 0.414ns, distribution 0.771ns)
  Clock Net Delay (Destination): 1.335ns (routing 0.463ns, distribution 0.872ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.185     1.305    d_1_i/axis_switch_tt/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
                  SLICE_X53Y115        FDRE                                         r  d_1_i/axis_switch_tt/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X53Y115        FDRE (Prop_EFF_SLICEM_C_Q)
                                                                    0.038     1.343 r  d_1_i/axis_switch_tt/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/Q
                                       net (fo=2, routed)           0.099     1.442    d_1_i/axis_switch_tt/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/src_in
    Routing       SLICE_X53Y114        FDRE                                         r  d_1_i/axis_switch_tt/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.335     1.482    d_1_i/axis_switch_tt/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/dest_clk
                  SLICE_X53Y114        FDRE                                         r  d_1_i/axis_switch_tt/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/s02_nodes/s02_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.145ns  (logic 0.039ns (26.963%)  route 0.106ns (73.037%))
  Logic Levels:           0  
  Clock Path Skew:        0.183ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.516ns
    Source Clock Delay      (SCD):    1.333ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.213ns (routing 0.414ns, distribution 0.799ns)
  Clock Net Delay (Destination): 1.369ns (routing 0.463ns, distribution 0.906ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.213     1.333    d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/aclk
                  SLICE_X42Y41         FDRE                                         r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X42Y41         FDRE (Prop_DFF_SLICEM_C_Q)
                                                                    0.039     1.372 r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                                       net (fo=72, routed)          0.106     1.478    d_1_i/axi_smc/inst/s02_nodes/s02_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    Routing       SLICE_X42Y40         FDCE                                         f  d_1_i/axi_smc/inst/s02_nodes/s02_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR  (IS_INVERTED)
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.369     1.516    d_1_i/axi_smc/inst/s02_nodes/s02_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
                  SLICE_X42Y40         FDCE                                         r  d_1_i/axi_smc/inst/s02_nodes/s02_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/s02_nodes/s02_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.145ns  (logic 0.039ns (26.963%)  route 0.106ns (73.037%))
  Logic Levels:           0  
  Clock Path Skew:        0.183ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.516ns
    Source Clock Delay      (SCD):    1.333ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.213ns (routing 0.414ns, distribution 0.799ns)
  Clock Net Delay (Destination): 1.369ns (routing 0.463ns, distribution 0.906ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.213     1.333    d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/aclk
                  SLICE_X42Y41         FDRE                                         r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X42Y41         FDRE (Prop_DFF_SLICEM_C_Q)
                                                                    0.039     1.372 r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                                       net (fo=72, routed)          0.106     1.478    d_1_i/axi_smc/inst/s02_nodes/s02_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    Routing       SLICE_X42Y40         FDCE                                         f  d_1_i/axi_smc/inst/s02_nodes/s02_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR  (IS_INVERTED)
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.369     1.516    d_1_i/axi_smc/inst/s02_nodes/s02_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
                  SLICE_X42Y40         FDCE                                         r  d_1_i/axi_smc/inst/s02_nodes/s02_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/s02_nodes/s02_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.145ns  (logic 0.039ns (26.963%)  route 0.106ns (73.037%))
  Logic Levels:           0  
  Clock Path Skew:        0.183ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.516ns
    Source Clock Delay      (SCD):    1.333ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.213ns (routing 0.414ns, distribution 0.799ns)
  Clock Net Delay (Destination): 1.369ns (routing 0.463ns, distribution 0.906ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.213     1.333    d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/aclk
                  SLICE_X42Y41         FDRE                                         r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X42Y41         FDRE (Prop_DFF_SLICEM_C_Q)
                                                                    0.039     1.372 r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                                       net (fo=72, routed)          0.106     1.478    d_1_i/axi_smc/inst/s02_nodes/s02_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    Routing       SLICE_X42Y40         FDCE                                         f  d_1_i/axi_smc/inst/s02_nodes/s02_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR  (IS_INVERTED)
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.369     1.516    d_1_i/axi_smc/inst/s02_nodes/s02_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
                  SLICE_X42Y40         FDCE                                         r  d_1_i/axi_smc/inst/s02_nodes/s02_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/s00_nodes/s00_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.175ns  (logic 0.039ns (22.326%)  route 0.136ns (77.674%))
  Logic Levels:           0  
  Clock Path Skew:        0.184ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.517ns
    Source Clock Delay      (SCD):    1.333ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.213ns (routing 0.414ns, distribution 0.799ns)
  Clock Net Delay (Destination): 1.370ns (routing 0.463ns, distribution 0.907ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.213     1.333    d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/aclk
                  SLICE_X42Y41         FDRE                                         r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X42Y41         FDRE (Prop_DFF_SLICEM_C_Q)
                                                                    0.039     1.372 r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                                       net (fo=72, routed)          0.136     1.508    d_1_i/axi_smc/inst/s00_nodes/s00_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    Routing       SLICE_X42Y36         FDCE                                         f  d_1_i/axi_smc/inst/s00_nodes/s00_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR  (IS_INVERTED)
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.370     1.517    d_1_i/axi_smc/inst/s00_nodes/s00_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
                  SLICE_X42Y36         FDCE                                         r  d_1_i/axi_smc/inst/s00_nodes/s00_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/s00_nodes/s00_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.175ns  (logic 0.039ns (22.326%)  route 0.136ns (77.674%))
  Logic Levels:           0  
  Clock Path Skew:        0.184ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.517ns
    Source Clock Delay      (SCD):    1.333ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.213ns (routing 0.414ns, distribution 0.799ns)
  Clock Net Delay (Destination): 1.370ns (routing 0.463ns, distribution 0.907ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.213     1.333    d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/aclk
                  SLICE_X42Y41         FDRE                                         r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X42Y41         FDRE (Prop_DFF_SLICEM_C_Q)
                                                                    0.039     1.372 r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                                       net (fo=72, routed)          0.136     1.508    d_1_i/axi_smc/inst/s00_nodes/s00_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    Routing       SLICE_X42Y36         FDCE                                         f  d_1_i/axi_smc/inst/s00_nodes/s00_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR  (IS_INVERTED)
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.370     1.517    d_1_i/axi_smc/inst/s00_nodes/s00_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
                  SLICE_X42Y36         FDCE                                         r  d_1_i/axi_smc/inst/s00_nodes/s00_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/s00_nodes/s00_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.175ns  (logic 0.039ns (22.326%)  route 0.136ns (77.674%))
  Logic Levels:           0  
  Clock Path Skew:        0.184ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.517ns
    Source Clock Delay      (SCD):    1.333ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.213ns (routing 0.414ns, distribution 0.799ns)
  Clock Net Delay (Destination): 1.370ns (routing 0.463ns, distribution 0.907ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.213     1.333    d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/aclk
                  SLICE_X42Y41         FDRE                                         r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X42Y41         FDRE (Prop_DFF_SLICEM_C_Q)
                                                                    0.039     1.372 r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                                       net (fo=72, routed)          0.136     1.508    d_1_i/axi_smc/inst/s00_nodes/s00_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    Routing       SLICE_X42Y36         FDCE                                         f  d_1_i/axi_smc/inst/s00_nodes/s00_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR  (IS_INVERTED)
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.370     1.517    d_1_i/axi_smc/inst/s00_nodes/s00_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
                  SLICE_X42Y36         FDCE                                         r  d_1_i/axi_smc/inst/s00_nodes/s00_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_tt/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_tt/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.229ns  (logic 0.039ns (17.002%)  route 0.190ns (82.998%))
  Logic Levels:           0  
  Clock Path Skew:        0.174ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.486ns
    Source Clock Delay      (SCD):    1.313ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.193ns (routing 0.414ns, distribution 0.779ns)
  Clock Net Delay (Destination): 1.339ns (routing 0.463ns, distribution 0.876ns)
  Timing Exception:       False Path

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.193     1.313    d_1_i/axis_switch_tt/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
                  SLICE_X51Y112        FDRE                                         r  d_1_i/axis_switch_tt/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X51Y112        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                                    0.039     1.352 r  d_1_i/axis_switch_tt/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/Q
                                       net (fo=2, routed)           0.190     1.542    d_1_i/axis_switch_tt/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/src_in
    Routing       SLICE_X53Y115        FDRE                                         r  d_1_i/axis_switch_tt/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.339     1.486    d_1_i/axis_switch_tt/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/dest_clk
                  SLICE_X53Y115        FDRE                                         r  d_1_i/axis_switch_tt/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFDAC0_CLK
  To Clock:  

Max Delay             8 Endpoints
Min Delay             8 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            PMOD0_0
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        4.549ns  (logic 1.012ns (22.256%)  route 3.537ns (77.744%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.449ns (routing 1.120ns, distribution 1.329ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.449     3.122    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
                  SLICE_X78Y80         FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[0]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X78Y80         FDCE (Prop_BFF_SLICEM_C_Q)
                                                                    0.078     3.200 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[0]/Q
                                       net (fo=3, routed)           3.537     6.737    PMOD0_0_OBUF
    Routing       C17                                                               r  PMOD0_0_OBUF_inst/I
    Routing       C17                  OBUF (Prop_OUTBUF_HPIOB_M_I_O)
                                                                    0.934     7.671 r  PMOD0_0_OBUF_inst/O
                                       net (fo=0)                   0.000     7.671    PMOD0_0
                  C17                                                               r  PMOD0_0 (OUT)
  ---------------------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            PMOD0_1
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        4.249ns  (logic 1.025ns (24.125%)  route 3.224ns (75.875%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.440ns (routing 1.120ns, distribution 1.320ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.440     3.113    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
                  SLICE_X79Y81         FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[1]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X79Y81         FDCE (Prop_HFF_SLICEM_C_Q)
                                                                    0.079     3.192 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[1]/Q
                                       net (fo=2, routed)           3.224     6.416    PMOD0_1_OBUF
    Routing       M18                                                               r  PMOD0_1_OBUF_inst/I
    Routing       M18                  OBUF (Prop_OUTBUF_HPIOB_SNGL_I_O)
                                                                    0.946     7.362 r  PMOD0_1_OBUF_inst/O
                                       net (fo=0)                   0.000     7.362    PMOD0_1
                  M18                                                               r  PMOD0_1 (OUT)
  ---------------------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            PMOD0_2
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        4.216ns  (logic 1.031ns (24.450%)  route 3.185ns (75.550%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.440ns (routing 1.120ns, distribution 1.320ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.440     3.113    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
                  SLICE_X79Y81         FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[2]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X79Y81         FDCE (Prop_GFF_SLICEM_C_Q)
                                                                    0.078     3.191 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[2]/Q
                                       net (fo=2, routed)           3.185     6.376    PMOD0_2_OBUF
    Routing       H16                                                               r  PMOD0_2_OBUF_inst/I
    Routing       H16                  OBUF (Prop_OUTBUF_HPIOB_S_I_O)
                                                                    0.953     7.329 r  PMOD0_2_OBUF_inst/O
                                       net (fo=0)                   0.000     7.329    PMOD0_2
                  H16                                                               r  PMOD0_2 (OUT)
  ---------------------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_dt_r_reg[0][1]_lopt_replica/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            PMOD0_5
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        4.184ns  (logic 1.035ns (24.735%)  route 3.149ns (75.265%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.424ns (routing 1.120ns, distribution 1.304ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.424     3.097    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
                  SLICE_X78Y93         FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_dt_r_reg[0][1]_lopt_replica/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X78Y93         FDCE (Prop_FFF2_SLICEM_C_Q)
                                                                    0.079     3.176 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_dt_r_reg[0][1]_lopt_replica/Q
                                       net (fo=1, routed)           3.149     6.325    lopt_1
    Routing       K16                                                               r  PMOD0_5_OBUF_inst/I
    Routing       K16                  OBUF (Prop_OUTBUF_HPIOB_M_I_O)
                                                                    0.956     7.281 r  PMOD0_5_OBUF_inst/O
                                       net (fo=0)                   0.000     7.281    PMOD0_5
                  K16                                                               r  PMOD0_5 (OUT)
  ---------------------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_dt_r_reg[0][0]_lopt_replica/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            PMOD0_4
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        4.124ns  (logic 1.036ns (25.113%)  route 3.088ns (74.887%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.424ns (routing 1.120ns, distribution 1.304ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.424     3.097    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
                  SLICE_X78Y93         FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_dt_r_reg[0][0]_lopt_replica/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X78Y93         FDCE (Prop_EFF2_SLICEM_C_Q)
                                                                    0.079     3.176 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_dt_r_reg[0][0]_lopt_replica/Q
                                       net (fo=1, routed)           3.088     6.264    lopt
    Routing       J16                                                               r  PMOD0_4_OBUF_inst/I
    Routing       J16                  OBUF (Prop_OUTBUF_HPIOB_S_I_O)
                                                                    0.957     7.221 r  PMOD0_4_OBUF_inst/O
                                       net (fo=0)                   0.000     7.221    PMOD0_4
                  J16                                                               r  PMOD0_4 (OUT)
  ---------------------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            PMOD0_3
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        4.040ns  (logic 1.031ns (25.518%)  route 3.009ns (74.482%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.425ns (routing 1.120ns, distribution 1.305ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.425     3.098    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
                  SLICE_X80Y80         FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[3]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X80Y80         FDCE (Prop_DFF_SLICEL_C_Q)
                                                                    0.079     3.177 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[3]/Q
                                       net (fo=2, routed)           3.009     6.186    PMOD0_3_OBUF
    Routing       H17                                                               r  PMOD0_3_OBUF_inst/I
    Routing       H17                  OBUF (Prop_OUTBUF_HPIOB_M_I_O)
                                                                    0.952     7.138 r  PMOD0_3_OBUF_inst/O
                                       net (fo=0)                   0.000     7.138    PMOD0_3
                  H17                                                               r  PMOD0_3 (OUT)
  ---------------------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_dt_r_reg[0][2]_lopt_replica/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            PMOD0_6
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        3.942ns  (logic 1.025ns (26.007%)  route 2.917ns (73.993%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.424ns (routing 1.120ns, distribution 1.304ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.424     3.097    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
                  SLICE_X78Y93         FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_dt_r_reg[0][2]_lopt_replica/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X78Y93         FDCE (Prop_GFF2_SLICEM_C_Q)
                                                                    0.079     3.176 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_dt_r_reg[0][2]_lopt_replica/Q
                                       net (fo=1, routed)           2.917     6.093    lopt_2
    Routing       H15                                                               r  PMOD0_6_OBUF_inst/I
    Routing       H15                  OBUF (Prop_OUTBUF_HPIOB_S_I_O)
                                                                    0.946     7.039 r  PMOD0_6_OBUF_inst/O
                                       net (fo=0)                   0.000     7.039    PMOD0_6
                  H15                                                               r  PMOD0_6 (OUT)
  ---------------------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_dt_r_reg[0][3]_lopt_replica/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            PMOD0_7
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        3.917ns  (logic 1.024ns (26.145%)  route 2.893ns (73.855%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.424ns (routing 1.120ns, distribution 1.304ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        2.424     3.097    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
                  SLICE_X78Y93         FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_dt_r_reg[0][3]_lopt_replica/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X78Y93         FDCE (Prop_HFF2_SLICEM_C_Q)
                                                                    0.078     3.175 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_dt_r_reg[0][3]_lopt_replica/Q
                                       net (fo=1, routed)           2.893     6.068    lopt_3
    Routing       J15                                                               r  PMOD0_7_OBUF_inst/I
    Routing       J15                  OBUF (Prop_OUTBUF_HPIOB_M_I_O)
                                                                    0.946     7.014 r  PMOD0_7_OBUF_inst/O
                                       net (fo=0)                   0.000     7.014    PMOD0_7
                  J15                                                               r  PMOD0_7 (OUT)
  ---------------------------------------------------------------------------------    -------------------





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_dt_r_reg[0][2]_lopt_replica/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            PMOD0_6
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.901ns  (logic 0.477ns (25.082%)  route 1.424ns (74.918%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.330ns (routing 0.607ns, distribution 0.723ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        1.330     1.679    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
                  SLICE_X78Y93         FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_dt_r_reg[0][2]_lopt_replica/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X78Y93         FDCE (Prop_GFF2_SLICEM_C_Q)
                                                                    0.039     1.718 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_dt_r_reg[0][2]_lopt_replica/Q
                                       net (fo=1, routed)           1.424     3.142    lopt_2
    Routing       H15                                                               r  PMOD0_6_OBUF_inst/I
    Routing       H15                  OBUF (Prop_OUTBUF_HPIOB_S_I_O)
                                                                    0.438     3.580 r  PMOD0_6_OBUF_inst/O
                                       net (fo=0)                   0.000     3.580    PMOD0_6
                  H15                                                               r  PMOD0_6 (OUT)
  ---------------------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_dt_r_reg[0][3]_lopt_replica/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            PMOD0_7
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.902ns  (logic 0.477ns (25.064%)  route 1.425ns (74.936%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.330ns (routing 0.607ns, distribution 0.723ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        1.330     1.679    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
                  SLICE_X78Y93         FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_dt_r_reg[0][3]_lopt_replica/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X78Y93         FDCE (Prop_HFF2_SLICEM_C_Q)
                                                                    0.039     1.718 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_dt_r_reg[0][3]_lopt_replica/Q
                                       net (fo=1, routed)           1.425     3.143    lopt_3
    Routing       J15                                                               r  PMOD0_7_OBUF_inst/I
    Routing       J15                  OBUF (Prop_OUTBUF_HPIOB_M_I_O)
                                                                    0.438     3.581 r  PMOD0_7_OBUF_inst/O
                                       net (fo=0)                   0.000     3.581    PMOD0_7
                  J15                                                               r  PMOD0_7 (OUT)
  ---------------------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            PMOD0_3
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.953ns  (logic 0.482ns (24.698%)  route 1.471ns (75.302%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.332ns (routing 0.607ns, distribution 0.725ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        1.332     1.681    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
                  SLICE_X80Y80         FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[3]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X80Y80         FDCE (Prop_DFF_SLICEL_C_Q)
                                                                    0.039     1.720 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[3]/Q
                                       net (fo=2, routed)           1.471     3.191    PMOD0_3_OBUF
    Routing       H17                                                               r  PMOD0_3_OBUF_inst/I
    Routing       H17                  OBUF (Prop_OUTBUF_HPIOB_M_I_O)
                                                                    0.443     3.634 r  PMOD0_3_OBUF_inst/O
                                       net (fo=0)                   0.000     3.634    PMOD0_3
                  H17                                                               r  PMOD0_3 (OUT)
  ---------------------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_dt_r_reg[0][0]_lopt_replica/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            PMOD0_4
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        2.002ns  (logic 0.487ns (24.323%)  route 1.515ns (75.677%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.330ns (routing 0.607ns, distribution 0.723ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        1.330     1.679    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
                  SLICE_X78Y93         FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_dt_r_reg[0][0]_lopt_replica/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X78Y93         FDCE (Prop_EFF2_SLICEM_C_Q)
                                                                    0.039     1.718 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_dt_r_reg[0][0]_lopt_replica/Q
                                       net (fo=1, routed)           1.515     3.233    lopt
    Routing       J16                                                               r  PMOD0_4_OBUF_inst/I
    Routing       J16                  OBUF (Prop_OUTBUF_HPIOB_S_I_O)
                                                                    0.448     3.681 r  PMOD0_4_OBUF_inst/O
                                       net (fo=0)                   0.000     3.681    PMOD0_4
                  J16                                                               r  PMOD0_4 (OUT)
  ---------------------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_dt_r_reg[0][1]_lopt_replica/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            PMOD0_5
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        2.025ns  (logic 0.487ns (24.060%)  route 1.538ns (75.940%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.330ns (routing 0.607ns, distribution 0.723ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        1.330     1.679    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
                  SLICE_X78Y93         FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_dt_r_reg[0][1]_lopt_replica/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X78Y93         FDCE (Prop_FFF2_SLICEM_C_Q)
                                                                    0.040     1.719 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_dt_r_reg[0][1]_lopt_replica/Q
                                       net (fo=1, routed)           1.538     3.257    lopt_1
    Routing       K16                                                               r  PMOD0_5_OBUF_inst/I
    Routing       K16                  OBUF (Prop_OUTBUF_HPIOB_M_I_O)
                                                                    0.447     3.704 r  PMOD0_5_OBUF_inst/O
                                       net (fo=0)                   0.000     3.704    PMOD0_5
                  K16                                                               r  PMOD0_5 (OUT)
  ---------------------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            PMOD0_2
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        2.049ns  (logic 0.483ns (23.582%)  route 1.566ns (76.418%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.337ns (routing 0.607ns, distribution 0.730ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        1.337     1.686    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
                  SLICE_X79Y81         FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[2]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X79Y81         FDCE (Prop_GFF_SLICEM_C_Q)
                                                                    0.039     1.725 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[2]/Q
                                       net (fo=2, routed)           1.566     3.291    PMOD0_2_OBUF
    Routing       H16                                                               r  PMOD0_2_OBUF_inst/I
    Routing       H16                  OBUF (Prop_OUTBUF_HPIOB_S_I_O)
                                                                    0.444     3.735 r  PMOD0_2_OBUF_inst/O
                                       net (fo=0)                   0.000     3.735    PMOD0_2
                  H16                                                               r  PMOD0_2 (OUT)
  ---------------------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            PMOD0_1
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        2.058ns  (logic 0.477ns (23.165%)  route 1.581ns (76.835%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.337ns (routing 0.607ns, distribution 0.730ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        1.337     1.686    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
                  SLICE_X79Y81         FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[1]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X79Y81         FDCE (Prop_HFF_SLICEM_C_Q)
                                                                    0.039     1.725 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[1]/Q
                                       net (fo=2, routed)           1.581     3.306    PMOD0_1_OBUF
    Routing       M18                                                               r  PMOD0_1_OBUF_inst/I
    Routing       M18                  OBUF (Prop_OUTBUF_HPIOB_SNGL_I_O)
                                                                    0.438     3.743 r  PMOD0_1_OBUF_inst/O
                                       net (fo=0)                   0.000     3.743    PMOD0_1
                  M18                                                               r  PMOD0_1 (OUT)
  ---------------------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            PMOD0_0
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        2.208ns  (logic 0.464ns (21.014%)  route 1.744ns (78.986%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.342ns (routing 0.607ns, distribution 0.735ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock RFDAC0_CLK rise edge)
                                                                    0.000     0.000 r  
                  HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                  HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                                    0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                                       net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
                  BUFG_GT_X1Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/I
                  BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                  X4Y2 (CLOCK_ROOT)    net (fo=6155, routed)        1.342     1.691    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
                  SLICE_X78Y80         FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[0]/C
  ---------------------------------------------------------------------------------    -------------------
    Routing       SLICE_X78Y80         FDCE (Prop_BFF_SLICEM_C_Q)
                                                                    0.038     1.729 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[0]/Q
                                       net (fo=3, routed)           1.744     3.473    PMOD0_0_OBUF
    Routing       C17                                                               r  PMOD0_0_OBUF_inst/I
    Routing       C17                  OBUF (Prop_OUTBUF_HPIOB_M_I_O)
                                                                    0.426     3.899 r  PMOD0_0_OBUF_inst/O
                                       net (fo=0)                   0.000     3.899    PMOD0_0
                  C17                                                               r  PMOD0_0 (OUT)
  ---------------------------------------------------------------------------------    -------------------





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_pl_0
  To Clock:  

Max Delay             6 Endpoints
Min Delay             6 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        2.829ns  (logic 0.028ns (0.990%)  route 2.801ns (99.010%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 fall edge)
                                                                    5.000     5.000 f  
    Routing       PS8_X0Y0             PS8                          0.000     5.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.198     5.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    Routing       BUFG_PS_X0Y61                                                     f  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
    Placement     BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.028     5.226 f  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                                       net (fo=36067, routed)       2.603     7.829    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    Placement     HSADC_X0Y1           HSADC                                        f  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/PLL_MONCLK
  ---------------------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        2.824ns  (logic 0.028ns (0.992%)  route 2.796ns (99.009%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 fall edge)
                                                                    5.000     5.000 f  
    Routing       PS8_X0Y0             PS8                          0.000     5.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.198     5.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    Routing       BUFG_PS_X0Y61                                                     f  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
    Placement     BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.028     5.226 f  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                                       net (fo=36067, routed)       2.598     7.824    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    Placement     HSDAC_X0Y1           HSDAC                                        f  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/PLL_MONCLK
  ---------------------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        2.816ns  (logic 0.028ns (0.994%)  route 2.788ns (99.006%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 fall edge)
                                                                    5.000     5.000 f  
    Routing       PS8_X0Y0             PS8                          0.000     5.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.198     5.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    Routing       BUFG_PS_X0Y61                                                     f  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
    Placement     BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.028     5.226 f  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                                       net (fo=36067, routed)       2.590     7.816    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    Placement     HSADC_X0Y0           HSADC                                        f  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/PLL_MONCLK
  ---------------------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        2.804ns  (logic 0.028ns (0.999%)  route 2.776ns (99.001%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 fall edge)
                                                                    5.000     5.000 f  
    Routing       PS8_X0Y0             PS8                          0.000     5.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.198     5.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    Routing       BUFG_PS_X0Y61                                                     f  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
    Placement     BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.028     5.226 f  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                                       net (fo=36067, routed)       2.578     7.804    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    Placement     HSDAC_X0Y0           HSDAC                                        f  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/PLL_MONCLK
  ---------------------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        2.771ns  (logic 0.028ns (1.010%)  route 2.743ns (98.990%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 fall edge)
                                                                    5.000     5.000 f  
    Routing       PS8_X0Y0             PS8                          0.000     5.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.198     5.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    Routing       BUFG_PS_X0Y61                                                     f  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
    Placement     BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.028     5.226 f  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                                       net (fo=36067, routed)       2.545     7.771    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    Placement     HSADC_X0Y2           HSADC                                        f  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/PLL_MONCLK
  ---------------------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        2.754ns  (logic 0.028ns (1.017%)  route 2.726ns (98.983%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 fall edge)
                                                                    5.000     5.000 f  
    Routing       PS8_X0Y0             PS8                          0.000     5.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.198     5.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    Routing       BUFG_PS_X0Y61                                                     f  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
    Placement     BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.028     5.226 f  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                                       net (fo=36067, routed)       2.528     7.754    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    Placement     HSADC_X0Y3           HSADC                                        f  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/PLL_MONCLK
  ---------------------------------------------------------------------------------    -------------------





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.488ns  (logic 0.017ns (1.142%)  route 1.471ns (98.858%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
    Routing       PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    Routing       BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
    Placement     BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                                       net (fo=36067, routed)       1.368     1.488    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    Placement     HSADC_X0Y3           HSADC                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/PLL_MONCLK
  ---------------------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.499ns  (logic 0.017ns (1.134%)  route 1.482ns (98.866%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
    Routing       PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    Routing       BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
    Placement     BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                                       net (fo=36067, routed)       1.379     1.499    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    Placement     HSADC_X0Y2           HSADC                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/PLL_MONCLK
  ---------------------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.514ns  (logic 0.017ns (1.123%)  route 1.497ns (98.877%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
    Routing       PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    Routing       BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
    Placement     BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                                       net (fo=36067, routed)       1.394     1.514    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    Placement     HSDAC_X0Y0           HSDAC                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/PLL_MONCLK
  ---------------------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.520ns  (logic 0.017ns (1.118%)  route 1.503ns (98.882%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
    Routing       PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    Routing       BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
    Placement     BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                                       net (fo=36067, routed)       1.400     1.520    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    Placement     HSADC_X0Y1           HSADC                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/PLL_MONCLK
  ---------------------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.527ns  (logic 0.017ns (1.113%)  route 1.510ns (98.887%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
    Routing       PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    Routing       BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
    Placement     BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                                       net (fo=36067, routed)       1.407     1.527    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    Placement     HSDAC_X0Y1           HSDAC                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/PLL_MONCLK
  ---------------------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.530ns  (logic 0.017ns (1.111%)  route 1.513ns (98.889%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
    Routing       PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    Routing       BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
    Placement     BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                                       net (fo=36067, routed)       1.410     1.530    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    Placement     HSADC_X0Y0           HSADC                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/PLL_MONCLK
  ---------------------------------------------------------------------------------    -------------------





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  
  To Clock:  clk_out1_d_1_clk_adc0_x2_0

Max Delay             1 Endpoint
Min Delay             1 Endpoint
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/LOCKED
                            (internal pin)
  Destination:            d_1_i/rst_adc0_x2/U0/EXT_LPF/lpf_int_reg/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.292ns  (logic 0.088ns (2.673%)  route 3.204ns (97.327%))
  Logic Levels:           1  (LUT4=1)
  Clock Uncertainty:      0.139ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.094ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Destination): 2.476ns (routing 1.589ns, distribution 0.887ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
    Routing       MMCM_X0Y7            MMCME4_ADV                   0.000     0.000 f  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/LOCKED
                                       net (fo=1, routed)           3.138     3.138    d_1_i/rst_adc0_x2/U0/EXT_LPF/dcm_locked
    Routing       SLICE_X79Y139                                                     f  d_1_i/rst_adc0_x2/U0/EXT_LPF/lpf_int0/I0
    Routing       SLICE_X79Y139        LUT4 (Prop_C6LUT_SLICEM_I0_O)
                                                                    0.088     3.226 r  d_1_i/rst_adc0_x2/U0/EXT_LPF/lpf_int0/O
                                       net (fo=1, routed)           0.066     3.292    d_1_i/rst_adc0_x2/U0/EXT_LPF/lpf_int0__0
    Routing       SLICE_X79Y139        FDRE                                         r  d_1_i/rst_adc0_x2/U0/EXT_LPF/lpf_int_reg/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           2.162     2.548    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                    0.630     3.178 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.216     3.394    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.024     3.418 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        2.476     5.894    d_1_i/rst_adc0_x2/U0/EXT_LPF/slowest_sync_clk
                  SLICE_X79Y139        FDRE                                         r  d_1_i/rst_adc0_x2/U0/EXT_LPF/lpf_int_reg/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/LOCKED
                            (internal pin)
  Destination:            d_1_i/rst_adc0_x2/U0/EXT_LPF/lpf_int_reg/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.679ns  (logic 0.035ns (2.085%)  route 1.644ns (97.915%))
  Logic Levels:           1  (LUT4=1)
  Clock Uncertainty:      0.139ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.094ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Destination): 1.721ns (routing 1.079ns, distribution 0.642ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
    Routing       MMCM_X0Y7            MMCME4_ADV                   0.000     0.000 f  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/LOCKED
                                       net (fo=1, routed)           1.620     1.620    d_1_i/rst_adc0_x2/U0/EXT_LPF/dcm_locked
    Routing       SLICE_X79Y139                                                     f  d_1_i/rst_adc0_x2/U0/EXT_LPF/lpf_int0/I0
    Routing       SLICE_X79Y139        LUT4 (Prop_C6LUT_SLICEM_I0_O)
                                                                    0.035     1.655 r  d_1_i/rst_adc0_x2/U0/EXT_LPF/lpf_int0/O
                                       net (fo=1, routed)           0.024     1.679    d_1_i/rst_adc0_x2/U0/EXT_LPF/lpf_int0__0
    Routing       SLICE_X79Y139        FDRE                                         r  d_1_i/rst_adc0_x2/U0/EXT_LPF/lpf_int_reg/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                                    0.000     0.000 r  
                  HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                  HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                                    0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/CLK_ADC
                                       net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt_0
                  BUFG_GT_X1Y27                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/I
                  BUFG_GT_X1Y27        BUFG_GT (Prop_BUFG_GT_I_O)
                                                                    0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc1_bufg_gt/O
                                       net (fo=1, routed)           1.507     1.859    d_1_i/clk_adc0_x2/inst/clk_in1
                  MMCM_X0Y7                                                         r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
                  MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                                   -0.295     1.564 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                                       net (fo=1, routed)           0.166     1.730    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
                  BUFGCE_X0Y179                                                     r  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
                  BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                                    0.019     1.749 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
                  X3Y2 (CLOCK_ROOT)    net (fo=2984, routed)        1.721     3.470    d_1_i/rst_adc0_x2/U0/EXT_LPF/slowest_sync_clk
                  SLICE_X79Y139        FDRE                                         r  d_1_i/rst_adc0_x2/U0/EXT_LPF/lpf_int_reg/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  
  To Clock:  clk_pl_0

Max Delay             7 Endpoints
Min Delay             7 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[7]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.508ns  (logic 0.477ns (13.597%)  route 3.031ns (86.403%))
  Logic Levels:           5  (LUT6=5)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.259ns (routing 0.690ns, distribution 1.569ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[7]
                                       net (fo=1, routed)           2.398     2.398    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac1_common_stat[7]
    Routing       SLICE_X112Y100                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_29/I5
    Routing       SLICE_X112Y100       LUT6 (Prop_D6LUT_SLICEM_I5_O)
                                                                    0.145     2.543 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_29/O
                                       net (fo=1, routed)           0.045     2.588    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_29_n_0
    Routing       SLICE_X112Y100                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_20/I5
    Routing       SLICE_X112Y100       LUT6 (Prop_F6LUT_SLICEM_I5_O)
                                                                    0.123     2.711 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_20/O
                                       net (fo=1, routed)           0.139     2.850    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_20_n_0
    Routing       SLICE_X111Y102                                                    f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_8/I1
    Placement     SLICE_X111Y102       LUT6 (Prop_F6LUT_SLICEL_I1_O)
                                                                    0.049     2.899 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_8/O
                                       net (fo=1, routed)           0.039     2.938    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_8_n_0
    Placement     SLICE_X111Y102                                                    f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_3/I0
    Routing       SLICE_X111Y102       LUT6 (Prop_G6LUT_SLICEL_I0_O)
                                                                    0.035     2.973 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_3/O
                                       net (fo=1, routed)           0.357     3.330    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_3_n_0
    Routing       SLICE_X113Y93                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_1/I2
    Routing       SLICE_X113Y93        LUT6 (Prop_A6LUT_SLICEM_I2_O)
                                                                    0.125     3.455 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_1/O
                                       net (fo=1, routed)           0.053     3.508    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_77
    Routing       SLICE_X113Y93        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[7]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.259     2.441    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X113Y93        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[7]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[2]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.417ns  (logic 0.305ns (8.926%)  route 3.112ns (91.074%))
  Logic Levels:           5  (LUT4=1 LUT6=4)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.251ns (routing 0.690ns, distribution 1.561ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[2]
                                       net (fo=1, routed)           2.067     2.067    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac1_common_stat[2]
    Routing       SLICE_X114Y106                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_68/I0
    Routing       SLICE_X114Y106       LUT4 (Prop_C6LUT_SLICEL_I0_O)
                                                                    0.050     2.117 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_68/O
                                       net (fo=1, routed)           0.279     2.396    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_68_n_0
    Routing       SLICE_X110Y100                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_34/I0
    Routing       SLICE_X110Y100       LUT6 (Prop_B6LUT_SLICEM_I0_O)
                                                                    0.037     2.433 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_34/O
                                       net (fo=1, routed)           0.186     2.619    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_34_n_0
    Routing       SLICE_X115Y100                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_10/I4
    Placement     SLICE_X115Y100       LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                                    0.090     2.709 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_10/O
                                       net (fo=1, routed)           0.095     2.804    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_10_n_0
    Placement     SLICE_X115Y102                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_2/I3
    Routing       SLICE_X115Y102       LUT6 (Prop_H6LUT_SLICEM_I3_O)
                                                                    0.039     2.843 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_2/O
                                       net (fo=1, routed)           0.436     3.279    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_2_n_0
    Routing       SLICE_X114Y92                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_1/I0
    Routing       SLICE_X114Y92        LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                                    0.089     3.368 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_1/O
                                       net (fo=1, routed)           0.049     3.417    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_82
    Routing       SLICE_X114Y92        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[2]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.251     2.433    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X114Y92        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[1]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.311ns  (logic 0.332ns (10.027%)  route 2.979ns (89.973%))
  Logic Levels:           5  (LUT4=1 LUT5=1 LUT6=3)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.258ns (routing 0.690ns, distribution 1.568ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[1]
                                       net (fo=2, routed)           2.341     2.341    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac1_common_stat[1]
    Routing       SLICE_X112Y101                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_61/I0
    Routing       SLICE_X112Y101       LUT4 (Prop_B6LUT_SLICEM_I0_O)
                                                                    0.052     2.393 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_61/O
                                       net (fo=1, routed)           0.085     2.478    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_61_n_0
    Routing       SLICE_X112Y100                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_33/I4
    Routing       SLICE_X112Y100       LUT5 (Prop_C6LUT_SLICEM_I4_O)
                                                                    0.051     2.529 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_33/O
                                       net (fo=1, routed)           0.085     2.614    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_33_n_0
    Routing       SLICE_X112Y101                                                    f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_10/I4
    Routing       SLICE_X112Y101       LUT6 (Prop_D6LUT_SLICEM_I4_O)
                                                                    0.088     2.702 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_10/O
                                       net (fo=1, routed)           0.194     2.896    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_10_n_0
    Routing       SLICE_X113Y99                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_2/I4
    Routing       SLICE_X113Y99        LUT6 (Prop_G6LUT_SLICEM_I4_O)
                                                                    0.090     2.986 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_2/O
                                       net (fo=1, routed)           0.202     3.188    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_2_n_0
    Routing       SLICE_X113Y92                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_1/I0
    Routing       SLICE_X113Y92        LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                                    0.051     3.239 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_1/O
                                       net (fo=1, routed)           0.072     3.311    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_83
    Routing       SLICE_X113Y92        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[1]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.258     2.440    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X113Y92        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[3]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.238ns  (logic 0.361ns (11.149%)  route 2.877ns (88.851%))
  Logic Levels:           5  (LUT6=5)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.255ns (routing 0.690ns, distribution 1.565ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[3]
                                       net (fo=1, routed)           2.154     2.154    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac1_common_stat[3]
    Routing       SLICE_X110Y102                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_62/I5
    Placement     SLICE_X110Y102       LUT6 (Prop_G6LUT_SLICEM_I5_O)
                                                                    0.037     2.191 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_62/O
                                       net (fo=1, routed)           0.048     2.239    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_62_n_0
    Placement     SLICE_X110Y102                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_32/I5
    Routing       SLICE_X110Y102       LUT6 (Prop_H6LUT_SLICEM_I5_O)
                                                                    0.053     2.292 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_32/O
                                       net (fo=1, routed)           0.267     2.559    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_32_n_0
    Routing       SLICE_X115Y102                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_10/I1
    Placement     SLICE_X115Y102       LUT6 (Prop_C6LUT_SLICEM_I1_O)
                                                                    0.145     2.704 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_10/O
                                       net (fo=1, routed)           0.039     2.743    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_10_n_0
    Placement     SLICE_X115Y102                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_2/I5
    Routing       SLICE_X115Y102       LUT6 (Prop_B6LUT_SLICEM_I5_O)
                                                                    0.089     2.832 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_2/O
                                       net (fo=1, routed)           0.303     3.135    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_2_n_0
    Routing       SLICE_X115Y91                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_1/I0
    Routing       SLICE_X115Y91        LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                                    0.037     3.172 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_1/O
                                       net (fo=1, routed)           0.066     3.238    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_81
    Routing       SLICE_X115Y91        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[3]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.255     2.437    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X115Y91        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[3]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[4]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.215ns  (logic 0.301ns (9.362%)  route 2.914ns (90.638%))
  Logic Levels:           5  (LUT6=5)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.259ns (routing 0.690ns, distribution 1.569ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[4]
                                       net (fo=1, routed)           2.233     2.233    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac1_common_stat[4]
    Routing       SLICE_X110Y102                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_37/I5
    Placement     SLICE_X110Y102       LUT6 (Prop_C6LUT_SLICEM_I5_O)
                                                                    0.088     2.321 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_37/O
                                       net (fo=1, routed)           0.040     2.361    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_37_n_0
    Placement     SLICE_X110Y102                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_22/I5
    Routing       SLICE_X110Y102       LUT6 (Prop_D6LUT_SLICEM_I5_O)
                                                                    0.037     2.398 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_22/O
                                       net (fo=1, routed)           0.152     2.550    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_22_n_0
    Routing       SLICE_X113Y102                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_11/I0
    Placement     SLICE_X113Y102       LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                                    0.051     2.601 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_11/O
                                       net (fo=1, routed)           0.093     2.694    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_11_n_0
    Placement     SLICE_X113Y104                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_3/I5
    Routing       SLICE_X113Y104       LUT6 (Prop_C6LUT_SLICEM_I5_O)
                                                                    0.037     2.731 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_3/O
                                       net (fo=1, routed)           0.330     3.061    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_3_n_0
    Routing       SLICE_X113Y93                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_1/I2
    Routing       SLICE_X113Y93        LUT6 (Prop_C6LUT_SLICEM_I2_O)
                                                                    0.088     3.149 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_1/O
                                       net (fo=1, routed)           0.066     3.215    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_80
    Routing       SLICE_X113Y93        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[4]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.259     2.441    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X113Y93        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[4]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[5]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.183ns  (logic 0.391ns (12.284%)  route 2.792ns (87.716%))
  Logic Levels:           5  (LUT4=1 LUT6=4)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.248ns (routing 0.690ns, distribution 1.558ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[5]
                                       net (fo=1, routed)           2.228     2.228    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac1_common_stat[5]
    Routing       SLICE_X109Y101                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_26/I5
    Routing       SLICE_X109Y101       LUT6 (Prop_H6LUT_SLICEM_I5_O)
                                                                    0.152     2.380 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_26/O
                                       net (fo=1, routed)           0.091     2.471    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_26_n_0
    Routing       SLICE_X109Y100                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_25/I5
    Routing       SLICE_X109Y100       LUT6 (Prop_H6LUT_SLICEM_I5_O)
                                                                    0.039     2.510 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_25/O
                                       net (fo=1, routed)           0.141     2.651    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_25_n_0
    Routing       SLICE_X111Y100                                                    f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_17/I1
    Routing       SLICE_X111Y100       LUT6 (Prop_G6LUT_SLICEL_I1_O)
                                                                    0.050     2.701 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_17/O
                                       net (fo=1, routed)           0.046     2.747    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_17_n_0
    Routing       SLICE_X111Y100                                                    f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_6/I3
    Routing       SLICE_X111Y100       LUT4 (Prop_E6LUT_SLICEL_I3_O)
                                                                    0.099     2.846 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_6/O
                                       net (fo=1, routed)           0.220     3.066    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_6_n_0
    Routing       SLICE_X112Y92                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_1/I5
    Routing       SLICE_X112Y92        LUT6 (Prop_C6LUT_SLICEM_I5_O)
                                                                    0.051     3.117 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_1/O
                                       net (fo=1, routed)           0.066     3.183    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_79
    Routing       SLICE_X112Y92        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[5]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.248     2.430    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X112Y92        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[5]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[0]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.997ns  (logic 0.265ns (8.842%)  route 2.732ns (91.158%))
  Logic Levels:           4  (LUT6=4)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.259ns (routing 0.690ns, distribution 1.569ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[0]
                                       net (fo=1, routed)           2.146     2.146    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac1_common_stat[0]
    Routing       SLICE_X111Y100                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_47/I3
    Routing       SLICE_X111Y100       LUT6 (Prop_H6LUT_SLICEL_I3_O)
                                                                    0.124     2.270 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_47/O
                                       net (fo=1, routed)           0.206     2.476    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_47_n_0
    Routing       SLICE_X113Y100                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_24/I0
    Placement     SLICE_X113Y100       LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                                    0.051     2.527 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_24/O
                                       net (fo=1, routed)           0.091     2.618    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_24_n_0
    Placement     SLICE_X113Y99                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_6/I4
    Routing       SLICE_X113Y99        LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                                    0.053     2.671 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_6/O
                                       net (fo=1, routed)           0.217     2.888    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_6_n_0
    Routing       SLICE_X115Y94                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_1/I5
    Routing       SLICE_X115Y94        LUT6 (Prop_D6LUT_SLICEM_I5_O)
                                                                    0.037     2.925 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_1/O
                                       net (fo=1, routed)           0.072     2.997    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_84
    Routing       SLICE_X115Y94        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[0]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       2.259     2.441    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X115Y94        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[0]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[2]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.599ns  (logic 0.101ns (16.868%)  route 0.498ns (83.132%))
  Logic Levels:           4  (LUT6=4)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.559ns (routing 0.463ns, distribution 1.096ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[2]
                                       net (fo=2, routed)           0.243     0.243    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc1_common_stat[2]
    Routing       SLICE_X112Y87                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_49/I3
    Routing       SLICE_X112Y87        LUT6 (Prop_C6LUT_SLICEM_I3_O)
                                                                    0.022     0.265 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_49/O
                                       net (fo=1, routed)           0.045     0.310    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_49_n_0
    Routing       SLICE_X112Y87                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_21/I2
    Placement     SLICE_X112Y87        LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                                    0.035     0.345 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_21/O
                                       net (fo=1, routed)           0.024     0.369    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_21_n_0
    Placement     SLICE_X112Y87                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_6/I1
    Routing       SLICE_X112Y87        LUT6 (Prop_G6LUT_SLICEM_I1_O)
                                                                    0.022     0.391 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_6/O
                                       net (fo=1, routed)           0.170     0.561    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_6_n_0
    Routing       SLICE_X114Y92                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_1/I4
    Routing       SLICE_X114Y92        LUT6 (Prop_D6LUT_SLICEL_I4_O)
                                                                    0.022     0.583 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_1/O
                                       net (fo=1, routed)           0.016     0.599    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_82
    Routing       SLICE_X114Y92        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[2]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.559     1.706    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X114Y92        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[1]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.642ns  (logic 0.110ns (17.143%)  route 0.532ns (82.857%))
  Logic Levels:           3  (LUT6=3)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.567ns (routing 0.463ns, distribution 1.104ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[1]
                                       net (fo=2, routed)           0.277     0.277    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc1_common_stat[1]
    Routing       SLICE_X110Y85                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_15/I1
    Routing       SLICE_X110Y85        LUT6 (Prop_G6LUT_SLICEM_I1_O)
                                                                    0.035     0.312 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_15/O
                                       net (fo=1, routed)           0.104     0.416    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_15_n_0
    Routing       SLICE_X110Y90                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_4/I0
    Routing       SLICE_X110Y90        LUT6 (Prop_G6LUT_SLICEM_I0_O)
                                                                    0.040     0.456 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_4/O
                                       net (fo=1, routed)           0.125     0.581    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_4_n_0
    Routing       SLICE_X113Y92                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_1/I2
    Routing       SLICE_X113Y92        LUT6 (Prop_D6LUT_SLICEM_I2_O)
                                                                    0.035     0.616 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_1/O
                                       net (fo=1, routed)           0.026     0.642    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_83
    Routing       SLICE_X113Y92        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[1]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.567     1.714    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X113Y92        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[0]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.653ns  (logic 0.115ns (17.611%)  route 0.538ns (82.389%))
  Logic Levels:           4  (LUT6=4)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.567ns (routing 0.463ns, distribution 1.104ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[0]
                                       net (fo=1, routed)           0.385     0.385    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc2_common_stat[0]
    Routing       SLICE_X115Y90                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_38/I0
    Placement     SLICE_X115Y90        LUT6 (Prop_G6LUT_SLICEM_I0_O)
                                                                    0.035     0.420 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_38/O
                                       net (fo=1, routed)           0.027     0.447    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_38_n_0
    Placement     SLICE_X115Y90                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_20/I2
    Placement     SLICE_X115Y90        LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                                    0.023     0.470 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_20/O
                                       net (fo=1, routed)           0.051     0.521    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_20_n_0
    Placement     SLICE_X115Y92                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_5/I2
    Routing       SLICE_X115Y92        LUT6 (Prop_G6LUT_SLICEM_I2_O)
                                                                    0.022     0.543 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_5/O
                                       net (fo=1, routed)           0.049     0.592    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_5_n_0
    Routing       SLICE_X115Y94                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_1/I4
    Routing       SLICE_X115Y94        LUT6 (Prop_D6LUT_SLICEM_I4_O)
                                                                    0.035     0.627 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_1/O
                                       net (fo=1, routed)           0.026     0.653    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_84
    Routing       SLICE_X115Y94        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[0]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.567     1.714    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X115Y94        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[7]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.725ns  (logic 0.204ns (28.138%)  route 0.521ns (71.862%))
  Logic Levels:           4  (LUT6=4)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.568ns (routing 0.463ns, distribution 1.105ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[7]
                                       net (fo=1, routed)           0.196     0.196    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc1_common_stat[7]
    Routing       SLICE_X114Y85                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_28/I3
    Routing       SLICE_X114Y85        LUT6 (Prop_B6LUT_SLICEL_I3_O)
                                                                    0.060     0.256 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_28/O
                                       net (fo=1, routed)           0.158     0.414    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_28_n_0
    Routing       SLICE_X110Y91                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_15/I4
    Routing       SLICE_X110Y91        LUT6 (Prop_F6LUT_SLICEM_I4_O)
                                                                    0.059     0.473 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_15/O
                                       net (fo=1, routed)           0.101     0.574    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_15_n_0
    Routing       SLICE_X113Y91                                                     f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_5/I4
    Routing       SLICE_X113Y91        LUT6 (Prop_C6LUT_SLICEM_I4_O)
                                                                    0.050     0.624 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_5/O
                                       net (fo=1, routed)           0.048     0.672    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_5_n_0
    Routing       SLICE_X113Y93                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_1/I4
    Routing       SLICE_X113Y93        LUT6 (Prop_A6LUT_SLICEM_I4_O)
                                                                    0.035     0.707 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_1/O
                                       net (fo=1, routed)           0.018     0.725    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_77
    Routing       SLICE_X113Y93        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[7]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.568     1.715    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X113Y93        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[7]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[3]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.798ns  (logic 0.160ns (20.050%)  route 0.638ns (79.950%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.565ns (routing 0.463ns, distribution 1.102ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[3]
                                       net (fo=1, routed)           0.393     0.393    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc2_common_stat[3]
    Routing       SLICE_X116Y89                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_46/I4
    Routing       SLICE_X116Y89        LUT5 (Prop_D6LUT_SLICEL_I4_O)
                                                                    0.050     0.443 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_46/O
                                       net (fo=1, routed)           0.094     0.537    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_46_n_0
    Routing       SLICE_X115Y88                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_18/I4
    Routing       SLICE_X115Y88        LUT6 (Prop_B6LUT_SLICEM_I4_O)
                                                                    0.035     0.572 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_18/O
                                       net (fo=1, routed)           0.082     0.654    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_18_n_0
    Routing       SLICE_X115Y91                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_4/I3
    Routing       SLICE_X115Y91        LUT6 (Prop_G6LUT_SLICEM_I3_O)
                                                                    0.040     0.694 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_4/O
                                       net (fo=1, routed)           0.045     0.739    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_4_n_0
    Routing       SLICE_X115Y91                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_1/I2
    Routing       SLICE_X115Y91        LUT6 (Prop_C6LUT_SLICEM_I2_O)
                                                                    0.035     0.774 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_1/O
                                       net (fo=1, routed)           0.024     0.798    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_81
    Routing       SLICE_X115Y91        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[3]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.565     1.712    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X115Y91        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[3]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[4]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.827ns  (logic 0.144ns (17.412%)  route 0.683ns (82.588%))
  Logic Levels:           4  (LUT6=4)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.568ns (routing 0.463ns, distribution 1.105ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[4]
                                       net (fo=1, routed)           0.236     0.236    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc1_common_stat[4]
    Routing       SLICE_X114Y85                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_29/I3
    Routing       SLICE_X114Y85        LUT6 (Prop_C6LUT_SLICEL_I3_O)
                                                                    0.022     0.258 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_29/O
                                       net (fo=1, routed)           0.158     0.416    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_29_n_0
    Routing       SLICE_X110Y86                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_14/I3
    Routing       SLICE_X110Y86        LUT6 (Prop_F6LUT_SLICEM_I3_O)
                                                                    0.040     0.456 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_14/O
                                       net (fo=1, routed)           0.196     0.652    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_14_n_0
    Routing       SLICE_X114Y93                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_5/I0
    Routing       SLICE_X114Y93        LUT6 (Prop_G6LUT_SLICEL_I0_O)
                                                                    0.060     0.712 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_5/O
                                       net (fo=1, routed)           0.069     0.781    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_5_n_0
    Routing       SLICE_X113Y93                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_1/I4
    Routing       SLICE_X113Y93        LUT6 (Prop_C6LUT_SLICEM_I4_O)
                                                                    0.022     0.803 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_1/O
                                       net (fo=1, routed)           0.024     0.827    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_80
    Routing       SLICE_X113Y93        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[4]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.568     1.715    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X113Y93        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[4]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[5]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.382ns  (logic 0.127ns (9.190%)  route 1.255ns (90.810%))
  Logic Levels:           4  (LUT4=1 LUT5=2 LUT6=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.557ns (routing 0.463ns, distribution 1.094ns)

    Pin Reuse     Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  ---------------------------------------------------------------------------------    -------------------
    Routing       HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[5]
                                       net (fo=1, routed)           0.934     0.934    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac0_common_stat[5]
    Routing       SLICE_X114Y105                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_23/I4
    Routing       SLICE_X114Y105       LUT5 (Prop_A6LUT_SLICEL_I4_O)
                                                                    0.041     0.975 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_23/O
                                       net (fo=1, routed)           0.112     1.087    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_23_n_0
    Routing       SLICE_X111Y102                                                    f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_16/I1
    Routing       SLICE_X111Y102       LUT5 (Prop_D6LUT_SLICEL_I1_O)
                                                                    0.050     1.137 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_16/O
                                       net (fo=1, routed)           0.070     1.207    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_16_n_0
    Routing       SLICE_X111Y100                                                    r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_6/I2
    Routing       SLICE_X111Y100       LUT4 (Prop_E6LUT_SLICEL_I2_O)
                                                                    0.014     1.221 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_6/O
                                       net (fo=1, routed)           0.115     1.336    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_6_n_0
    Routing       SLICE_X112Y92                                                     r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_1/I5
    Routing       SLICE_X112Y92        LUT6 (Prop_C6LUT_SLICEM_I5_O)
                                                                    0.022     1.358 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_1/O
                                       net (fo=1, routed)           0.024     1.382    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_79
    Routing       SLICE_X112Y92        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[5]/D
  ---------------------------------------------------------------------------------    -------------------

                                       (clock clk_pl_0 rise edge)
                                                                    0.000     0.000 r  
                  PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                                       net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
                  BUFG_PS_X0Y61                                                     r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/I
                  BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                                    0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                  X2Y3 (CLOCK_ROOT)    net (fo=36067, routed)       1.557     1.704    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
                  SLICE_X112Y92        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[5]/C





