Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version      : Vivado v.2023.1 (lin64) Build 3865809 Sun May  7 15:04:56 MDT 2023
| Date              : Thu Jun  5 19:25:58 2025
| Host              : linux-139028 running 64-bit Debian GNU/Linux 12 (bookworm)
| Command           : report_timing_summary -max_paths 10 -report_unconstrained -file d_1_wrapper_timing_summary_routed.rpt -pb d_1_wrapper_timing_summary_routed.pb -rpx d_1_wrapper_timing_summary_routed.rpx -warn_on_violation
| Design            : d_1_wrapper
| Device            : xczu28dr-ffvg1517
| Speed File        : -2  PRODUCTION 1.30 05-03-2022
| Design State      : Routed
| Temperature Grade : E
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

Timing Summary Report

------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------

  Enable Multi Corner Analysis               :  Yes
  Enable Pessimism Removal                   :  Yes
  Pessimism Removal Resolution               :  Nearest Common Node
  Enable Input Delay Default Clock           :  No
  Enable Preset / Clear Arcs                 :  No
  Disable Flight Delays                      :  No
  Ignore I/O Paths                           :  No
  Timing Early Launch at Borrowing Latches   :  No
  Borrow Time for Max Delay Exceptions       :  Yes
  Merge Timing Exceptions                    :  Yes

  Corner  Analyze    Analyze    
  Name    Max Paths  Min Paths  
  ------  ---------  ---------  
  Slow    Yes        Yes        
  Fast    Yes        Yes        


------------------------------------------------------------------------------------------------
| Report Methodology
| ------------------
------------------------------------------------------------------------------------------------

Rule       Severity  Description                                                                                            Violations  
---------  --------  -----------------------------------------------------------------------------------------------------  ----------  
LUTAR-1    Warning   LUT drives async reset alert                                                                           24          
TIMING-9   Warning   Unknown CDC Logic                                                                                      1           
TIMING-10  Warning   Missing property on synchronizer                                                                       1           
TIMING-18  Warning   Missing input or output delay                                                                          8           
TIMING-24  Warning   Overridden Max delay datapath only                                                                     12          
TIMING-47  Warning   False path, asynchronous clock group or max delay datapath only constraint between synchronous clocks  2           
CLKC-11    Advisory  MMCME4 divide could be done by BUFG_GT                                                                 1           
CLKC-56    Advisory  MMCME4 with global clock driver has no LOC                                                             2           
XDCB-6     Advisory  Timing constraint pointing to hierarchical pins                                                        1           

Note: This report is based on the most recent report_methodology run and may not be up-to-date. Run report_methodology on the current design for the latest report.



check_timing report

Table of Contents
-----------------
1. checking no_clock (0)
2. checking constant_clock (0)
3. checking pulse_width_clock (0)
4. checking unconstrained_internal_endpoints (0)
5. checking no_input_delay (1)
6. checking no_output_delay (9)
7. checking multiple_clock (0)
8. checking generated_clocks (0)
9. checking loops (0)
10. checking partial_input_delay (0)
11. checking partial_output_delay (0)
12. checking latch_loops (0)

1. checking no_clock (0)
------------------------
 There are 0 register/latch pins with no clock.


2. checking constant_clock (0)
------------------------------
 There are 0 register/latch pins with constant_clock.


3. checking pulse_width_clock (0)
---------------------------------
 There are 0 register/latch pins which need pulse_width check


4. checking unconstrained_internal_endpoints (0)
------------------------------------------------
 There are 0 pins that are not constrained for maximum delay.

 There are 0 pins that are not constrained for maximum delay due to constant clock.


5. checking no_input_delay (1)
------------------------------
 There is 1 input port with no input delay specified. (HIGH)

 There are 0 input ports with no input delay but user has a false path constraint.


6. checking no_output_delay (9)
-------------------------------
 There are 9 ports with no output delay specified. (HIGH)

 There are 0 ports with no output delay but user has a false path constraint

 There are 0 ports with no output delay but with a timing clock defined on it or propagating through it


7. checking multiple_clock (0)
------------------------------
 There are 0 register/latch pins with multiple clocks.


8. checking generated_clocks (0)
--------------------------------
 There are 0 generated clocks that are not connected to a clock source.


9. checking loops (0)
---------------------
 There are 0 combinational loops in the design.


10. checking partial_input_delay (0)
------------------------------------
 There are 0 input ports with partial input delay specified.


11. checking partial_output_delay (0)
-------------------------------------
 There are 0 ports with partial output delay specified.


12. checking latch_loops (0)
----------------------------
 There are 0 combinational latch loops in the design through latch input



------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------

    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
      0.008        0.000                      0               790988        0.008        0.000                      0               790286        0.000        0.000                       0                275005  


All user specified timing constraints are met.


------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------

Clock                                                                                                Waveform(ns)           Period(ns)      Frequency(MHz)
-----                                                                                                ------------           ----------      --------------
RFADC0_CLK                                                                                           {0.000 1.953}          3.906           256.016         
  clk_out1_d_1_clk_adc0_x2_0                                                                         {0.000 0.976}          1.953           512.033         
RFADC0_CLK_dummy                                                                                     {0.000 1.953}          3.906           256.016         
RFADC1_CLK                                                                                           {0.000 5.000}          10.000          100.000         
RFADC1_CLK_dummy                                                                                     {0.000 5.000}          10.000          100.000         
RFADC1_FABCLK0                                                                                       {0.000 5.000}          10.000          100.000         
RFADC1_FABCLK1                                                                                       {0.000 5.000}          10.000          100.000         
RFADC1_FABCLK2                                                                                       {0.000 5.000}          10.000          100.000         
RFADC1_FABCLK3                                                                                       {0.000 5.000}          10.000          100.000         
RFADC2_CLK                                                                                           {0.000 1.953}          3.906           256.016         
RFADC2_CLK_dummy                                                                                     {0.000 1.953}          3.906           256.016         
RFADC3_CLK                                                                                           {0.000 5.000}          10.000          100.000         
RFADC3_CLK_dummy                                                                                     {0.000 5.000}          10.000          100.000         
RFADC3_FABCLK0                                                                                       {0.000 5.000}          10.000          100.000         
RFADC3_FABCLK1                                                                                       {0.000 5.000}          10.000          100.000         
RFADC3_FABCLK2                                                                                       {0.000 5.000}          10.000          100.000         
RFADC3_FABCLK3                                                                                       {0.000 5.000}          10.000          100.000         
RFDAC0_CLK                                                                                           {0.000 1.302}          2.604           384.025         
  clk_out1_d_1_clk_core_0                                                                            {0.000 2.604}          5.208           192.012         
RFDAC1_CLK                                                                                           {0.000 1.302}          2.604           384.025         
clk_pl_0                                                                                             {0.000 5.000}          10.000          100.000         
dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {0.000 25.000}         50.000          20.000          
sys_clk_ddr4_clk_p                                                                                   {0.000 1.667}          3.334           299.940         
  mmcm_clkout0                                                                                       {0.000 1.500}          3.001           333.267         
    pll_clk[0]                                                                                       {0.000 0.188}          0.375           2666.133        
      pll_clk[0]_DIV                                                                                 {0.000 1.500}          3.001           333.267         
    pll_clk[1]                                                                                       {0.000 0.188}          0.375           2666.133        
      pll_clk[1]_DIV                                                                                 {0.000 1.500}          3.001           333.267         
    pll_clk[2]                                                                                       {0.000 0.188}          0.375           2666.133        
      pll_clk[2]_DIV                                                                                 {0.000 1.500}          3.001           333.267         
  mmcm_clkout5                                                                                       {0.000 6.001}          12.002          83.317          
  mmcm_clkout6                                                                                       {0.000 3.001}          6.001           166.633         


------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------

Clock                                                                                                    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
-----                                                                                                    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
RFADC0_CLK                                                                                                 2.841        0.000                      0                   46        0.037        0.000                      0                   46        0.586        0.000                       0                    37  
  clk_out1_d_1_clk_adc0_x2_0                                                                               0.008        0.000                      0               256832        0.008        0.000                      0               256832        0.030        0.000                       0                 82754  
RFDAC0_CLK                                                                                                 0.027        0.000                      0               229712        0.010        0.000                      0               229712        0.391        0.000                       0                 88054  
  clk_out1_d_1_clk_core_0                                                                                  0.209        0.000                      0                13991        0.010        0.000                      0                13991        2.062        0.000                       0                  4501  
clk_pl_0                                                                                                   0.935        0.000                      0               168966        0.011        0.000                      0               168966        3.400        0.000                       0                 55323  
dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK       10.588        0.000                      0                  992        0.030        0.000                      0                  992       24.468        0.000                       0                   479  
sys_clk_ddr4_clk_p                                                                                         1.762        0.000                      0                   23        0.052        0.000                      0                   23        0.500        0.000                       0                    19  
  mmcm_clkout0                                                                                             0.062        0.000                      0               109918        0.010        0.000                      0               109918        0.000        0.000                       0                 41416  
    pll_clk[0]                                                                                                                                                                                                                                         0.000        0.000                       0                     9  
      pll_clk[0]_DIV                                                                                                                                                                                                                                   0.300        0.000                       0                    40  
    pll_clk[1]                                                                                                                                                                                                                                         0.000        0.000                       0                     9  
      pll_clk[1]_DIV                                                                                                                                                                                                                                   0.300        0.000                       0                    40  
    pll_clk[2]                                                                                                                                                                                                                                         0.000        0.000                       0                     7  
      pll_clk[2]_DIV                                                                                                                                                                                                                                   0.300        0.000                       0                    25  
  mmcm_clkout5                                                                                             9.638        0.000                      0                  827        0.017        0.000                      0                  827        5.469        0.000                       0                   570  
  mmcm_clkout6                                                                                             0.924        0.000                      0                 5636        0.024        0.000                      0                 5152        0.975        0.000                       0                  1722  


------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------

From Clock                                                                                           To Clock                                                                                                 WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------                                                                                           --------                                                                                                 -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  
mmcm_clkout5                                                                                         dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK       11.619        0.000                      0                    8                                                                        
mmcm_clkout5                                                                                         mmcm_clkout0                                                                                               2.357        0.000                      0                   28                                                                        
mmcm_clkout6                                                                                         mmcm_clkout0                                                                                               1.242        0.000                      0                  129                                                                        
mmcm_clkout0                                                                                         pll_clk[0]_DIV                                                                                             0.182        0.000                      0                  352        0.622        0.000                      0                  352  
mmcm_clkout0                                                                                         pll_clk[1]_DIV                                                                                             0.676        0.000                      0                  352        0.536        0.000                      0                  352  
mmcm_clkout0                                                                                         pll_clk[2]_DIV                                                                                             0.688        0.000                      0                  216        0.569        0.000                      0                  216  
dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  mmcm_clkout5                                                                                              49.663        0.000                      0                    8                                                                        
mmcm_clkout0                                                                                         mmcm_clkout5                                                                                              11.320        0.000                      0                   10                                                                        
mmcm_clkout0                                                                                         mmcm_clkout6                                                                                               0.820        0.000                      0                   36        0.456        0.000                      0                    1  


------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------

Path Group                                                                                           From Clock                                                                                           To Clock                                                                                                 WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------                                                                                           ----------                                                                                           --------                                                                                                 -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  
**async_default**                                                                                    clk_out1_d_1_clk_adc0_x2_0                                                                           clk_out1_d_1_clk_adc0_x2_0                                                                                 0.858        0.000                      0                    4        0.126        0.000                      0                    4  
**async_default**                                                                                    clk_out1_d_1_clk_core_0                                                                              clk_out1_d_1_clk_core_0                                                                                    2.764        0.000                      0                 2055        0.115        0.000                      0                 2055  
**async_default**                                                                                    clk_pl_0                                                                                             clk_pl_0                                                                                                   6.406        0.000                      0                  642        0.154        0.000                      0                  642  
**async_default**                                                                                    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK       46.371        0.000                      0                  100        0.130        0.000                      0                  100  
**async_default**                                                                                    mmcm_clkout5                                                                                         mmcm_clkout5                                                                                              10.598        0.000                      0                  105        0.137        0.000                      0                  105  


------------------------------------------------------------------------------------------------
| User Ignored Path Table
| -----------------------
------------------------------------------------------------------------------------------------

Path Group                                                                                           From Clock                                                                                           To Clock                                                                                           
----------                                                                                           ----------                                                                                           --------                                                                                           
(none)                                                                                               RFDAC0_CLK                                                                                                                                                                                                
(none)                                                                                                                                                                                                    RFADC0_CLK                                                                                           
(none)                                                                                                                                                                                                    RFDAC0_CLK                                                                                           
(none)                                                                                               RFDAC0_CLK                                                                                           RFDAC0_CLK                                                                                           
(none)                                                                                               clk_out1_d_1_clk_adc0_x2_0                                                                           RFDAC0_CLK                                                                                           
(none)                                                                                               clk_out1_d_1_clk_core_0                                                                              RFDAC0_CLK                                                                                           
(none)                                                                                               clk_pl_0                                                                                             RFDAC0_CLK                                                                                           
(none)                                                                                                                                                                                                    clk_out1_d_1_clk_adc0_x2_0                                                                           
(none)                                                                                               RFDAC0_CLK                                                                                           clk_out1_d_1_clk_adc0_x2_0                                                                           
(none)                                                                                               clk_pl_0                                                                                             clk_out1_d_1_clk_adc0_x2_0                                                                           
(none)                                                                                               mmcm_clkout0                                                                                         clk_out1_d_1_clk_adc0_x2_0                                                                           
(none)                                                                                                                                                                                                    clk_out1_d_1_clk_core_0                                                                              
(none)                                                                                               RFDAC0_CLK                                                                                           clk_out1_d_1_clk_core_0                                                                              
(none)                                                                                               clk_pl_0                                                                                             clk_out1_d_1_clk_core_0                                                                              
(none)                                                                                                                                                                                                    clk_pl_0                                                                                             
(none)                                                                                               RFADC0_CLK                                                                                           clk_pl_0                                                                                             
(none)                                                                                               RFADC1_CLK                                                                                           clk_pl_0                                                                                             
(none)                                                                                               RFADC2_CLK                                                                                           clk_pl_0                                                                                             
(none)                                                                                               RFADC3_CLK                                                                                           clk_pl_0                                                                                             
(none)                                                                                               RFDAC0_CLK                                                                                           clk_pl_0                                                                                             
(none)                                                                                               RFDAC1_CLK                                                                                           clk_pl_0                                                                                             
(none)                                                                                               clk_out1_d_1_clk_adc0_x2_0                                                                           clk_pl_0                                                                                             
(none)                                                                                               clk_out1_d_1_clk_core_0                                                                              clk_pl_0                                                                                             
(none)                                                                                               clk_pl_0                                                                                             clk_pl_0                                                                                             
(none)                                                                                               mmcm_clkout5                                                                                         dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  
(none)                                                                                               RFDAC0_CLK                                                                                           mmcm_clkout0                                                                                         
(none)                                                                                               clk_out1_d_1_clk_adc0_x2_0                                                                           mmcm_clkout0                                                                                         
(none)                                                                                               clk_pl_0                                                                                             mmcm_clkout0                                                                                         
(none)                                                                                               mmcm_clkout0                                                                                         mmcm_clkout0                                                                                         
(none)                                                                                               mmcm_clkout5                                                                                         mmcm_clkout0                                                                                         
(none)                                                                                               mmcm_clkout6                                                                                         mmcm_clkout0                                                                                         
(none)                                                                                               sys_clk_ddr4_clk_p                                                                                   mmcm_clkout0                                                                                         
(none)                                                                                               dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  mmcm_clkout5                                                                                         
(none)                                                                                               mmcm_clkout0                                                                                         mmcm_clkout5                                                                                         
(none)                                                                                               mmcm_clkout0                                                                                         mmcm_clkout6                                                                                         
(none)                                                                                               mmcm_clkout6                                                                                         mmcm_clkout6                                                                                         
(none)                                                                                               sys_clk_ddr4_clk_p                                                                                   mmcm_clkout6                                                                                         
(none)                                                                                               clk_pl_0                                                                                             sys_clk_ddr4_clk_p                                                                                   


------------------------------------------------------------------------------------------------
| Unconstrained Path Table
| ------------------------
------------------------------------------------------------------------------------------------

Path Group                                                                                           From Clock                                                                                           To Clock                                                                                           
----------                                                                                           ----------                                                                                           --------                                                                                           
(none)                                                                                               clk_pl_0                                                                                                                                                                                                  
(none)                                                                                               mmcm_clkout0                                                                                                                                                                                              
(none)                                                                                                                                                                                                    clk_out1_d_1_clk_adc0_x2_0                                                                           
(none)                                                                                                                                                                                                    clk_out1_d_1_clk_core_0                                                                              
(none)                                                                                                                                                                                                    clk_pl_0                                                                                             
(none)                                                                                                                                                                                                    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  
(none)                                                                                                                                                                                                    sys_clk_ddr4_clk_p                                                                                   


------------------------------------------------------------------------------------------------
| Timing Details
| --------------
------------------------------------------------------------------------------------------------


---------------------------------------------------------------------------------------------------
From Clock:  RFADC0_CLK
  To Clock:  RFADC0_CLK

Setup :            0  Failing Endpoints,  Worst Slack        2.841ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.037ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        0.586ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             2.841ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc0/U0/EXT_LPF/lpf_int_reg/C
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/SEQ/Core_reg/S
                            (rising edge-triggered cell FDSE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.906ns  (RFADC0_CLK rise@3.906ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.817ns  (logic 0.080ns (9.792%)  route 0.737ns (90.208%))
  Logic Levels:           0  
  Clock Path Skew:        -0.138ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.697ns = ( 6.603 - 3.906 ) 
    Source Clock Delay      (SCD):    3.172ns
    Clock Pessimism Removal (CPR):    0.337ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.645ns (routing 1.519ns, distribution 1.126ns)
  Clock Net Delay (Destination): 2.311ns (routing 1.383ns, distribution 0.928ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=35, routed)          2.645     3.172    d_1_i/rst_adc0/U0/EXT_LPF/slowest_sync_clk
    SLICE_X36Y297        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/lpf_int_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X36Y297        FDRE (Prop_BFF2_SLICEL_C_Q)
                                                      0.080     3.252 r  d_1_i/rst_adc0/U0/EXT_LPF/lpf_int_reg/Q
                         net (fo=4, routed)           0.737     3.989    d_1_i/rst_adc0/U0/SEQ/lpf_int
    SLICE_X43Y295        FDSE                                         r  d_1_i/rst_adc0/U0/SEQ/Core_reg/S
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      3.906     3.906 r  
    HSADC_X0Y0           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=35, routed)          2.311     6.603    d_1_i/rst_adc0/U0/SEQ/slowest_sync_clk
    SLICE_X43Y295        FDSE                                         r  d_1_i/rst_adc0/U0/SEQ/Core_reg/C
                         clock pessimism              0.337     6.940    
                         clock uncertainty           -0.035     6.904    
    SLICE_X43Y295        FDSE (Setup_HFF_SLICEL_C_S)
                                                     -0.074     6.830    d_1_i/rst_adc0/U0/SEQ/Core_reg
  -------------------------------------------------------------------
                         required time                          6.830    
                         arrival time                          -3.989    
  -------------------------------------------------------------------
                         slack                                  2.841    

Slack (MET) :             2.841ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc0/U0/EXT_LPF/lpf_int_reg/C
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/SEQ/from_sys_reg/S
                            (rising edge-triggered cell FDSE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.906ns  (RFADC0_CLK rise@3.906ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.817ns  (logic 0.080ns (9.792%)  route 0.737ns (90.208%))
  Logic Levels:           0  
  Clock Path Skew:        -0.138ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.697ns = ( 6.603 - 3.906 ) 
    Source Clock Delay      (SCD):    3.172ns
    Clock Pessimism Removal (CPR):    0.337ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.645ns (routing 1.519ns, distribution 1.126ns)
  Clock Net Delay (Destination): 2.311ns (routing 1.383ns, distribution 0.928ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=35, routed)          2.645     3.172    d_1_i/rst_adc0/U0/EXT_LPF/slowest_sync_clk
    SLICE_X36Y297        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/lpf_int_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X36Y297        FDRE (Prop_BFF2_SLICEL_C_Q)
                                                      0.080     3.252 r  d_1_i/rst_adc0/U0/EXT_LPF/lpf_int_reg/Q
                         net (fo=4, routed)           0.737     3.989    d_1_i/rst_adc0/U0/SEQ/lpf_int
    SLICE_X43Y295        FDSE                                         r  d_1_i/rst_adc0/U0/SEQ/from_sys_reg/S
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      3.906     3.906 r  
    HSADC_X0Y0           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=35, routed)          2.311     6.603    d_1_i/rst_adc0/U0/SEQ/slowest_sync_clk
    SLICE_X43Y295        FDSE                                         r  d_1_i/rst_adc0/U0/SEQ/from_sys_reg/C
                         clock pessimism              0.337     6.940    
                         clock uncertainty           -0.035     6.904    
    SLICE_X43Y295        FDSE (Setup_HFF2_SLICEL_C_S)
                                                     -0.074     6.830    d_1_i/rst_adc0/U0/SEQ/from_sys_reg
  -------------------------------------------------------------------
                         required time                          6.830    
                         arrival time                          -3.989    
  -------------------------------------------------------------------
                         slack                                  2.841    

Slack (MET) :             2.841ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc0/U0/EXT_LPF/lpf_int_reg/C
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/SEQ/pr_reg/S
                            (rising edge-triggered cell FDSE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.906ns  (RFADC0_CLK rise@3.906ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.817ns  (logic 0.080ns (9.792%)  route 0.737ns (90.208%))
  Logic Levels:           0  
  Clock Path Skew:        -0.138ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.697ns = ( 6.603 - 3.906 ) 
    Source Clock Delay      (SCD):    3.172ns
    Clock Pessimism Removal (CPR):    0.337ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.645ns (routing 1.519ns, distribution 1.126ns)
  Clock Net Delay (Destination): 2.311ns (routing 1.383ns, distribution 0.928ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=35, routed)          2.645     3.172    d_1_i/rst_adc0/U0/EXT_LPF/slowest_sync_clk
    SLICE_X36Y297        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/lpf_int_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X36Y297        FDRE (Prop_BFF2_SLICEL_C_Q)
                                                      0.080     3.252 r  d_1_i/rst_adc0/U0/EXT_LPF/lpf_int_reg/Q
                         net (fo=4, routed)           0.737     3.989    d_1_i/rst_adc0/U0/SEQ/lpf_int
    SLICE_X43Y295        FDSE                                         r  d_1_i/rst_adc0/U0/SEQ/pr_reg/S
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      3.906     3.906 r  
    HSADC_X0Y0           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=35, routed)          2.311     6.603    d_1_i/rst_adc0/U0/SEQ/slowest_sync_clk
    SLICE_X43Y295        FDSE                                         r  d_1_i/rst_adc0/U0/SEQ/pr_reg/C
                         clock pessimism              0.337     6.940    
                         clock uncertainty           -0.035     6.904    
    SLICE_X43Y295        FDSE (Setup_GFF2_SLICEL_C_S)
                                                     -0.074     6.830    d_1_i/rst_adc0/U0/SEQ/pr_reg
  -------------------------------------------------------------------
                         required time                          6.830    
                         arrival time                          -3.989    
  -------------------------------------------------------------------
                         slack                                  2.841    

Slack (MET) :             2.841ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc0/U0/EXT_LPF/lpf_int_reg/C
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/SEQ/seq_clr_reg/R
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.906ns  (RFADC0_CLK rise@3.906ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.817ns  (logic 0.080ns (9.792%)  route 0.737ns (90.208%))
  Logic Levels:           0  
  Clock Path Skew:        -0.138ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.697ns = ( 6.603 - 3.906 ) 
    Source Clock Delay      (SCD):    3.172ns
    Clock Pessimism Removal (CPR):    0.337ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.645ns (routing 1.519ns, distribution 1.126ns)
  Clock Net Delay (Destination): 2.311ns (routing 1.383ns, distribution 0.928ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=35, routed)          2.645     3.172    d_1_i/rst_adc0/U0/EXT_LPF/slowest_sync_clk
    SLICE_X36Y297        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/lpf_int_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X36Y297        FDRE (Prop_BFF2_SLICEL_C_Q)
                                                      0.080     3.252 r  d_1_i/rst_adc0/U0/EXT_LPF/lpf_int_reg/Q
                         net (fo=4, routed)           0.737     3.989    d_1_i/rst_adc0/U0/SEQ/lpf_int
    SLICE_X43Y295        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/seq_clr_reg/R
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      3.906     3.906 r  
    HSADC_X0Y0           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=35, routed)          2.311     6.603    d_1_i/rst_adc0/U0/SEQ/slowest_sync_clk
    SLICE_X43Y295        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/seq_clr_reg/C
                         clock pessimism              0.337     6.940    
                         clock uncertainty           -0.035     6.904    
    SLICE_X43Y295        FDRE (Setup_EFF_SLICEL_C_R)
                                                     -0.074     6.830    d_1_i/rst_adc0/U0/SEQ/seq_clr_reg
  -------------------------------------------------------------------
                         required time                          6.830    
                         arrival time                          -3.989    
  -------------------------------------------------------------------
                         slack                                  2.841    

Slack (MET) :             3.107ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc0/U0/EXT_LPF/POR_SRL_I/CLK
                            (rising edge-triggered cell SRL16E clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/EXT_LPF/lpf_int_reg/D
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.906ns  (RFADC0_CLK rise@3.906ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.724ns  (logic 0.557ns (76.934%)  route 0.167ns (23.066%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        -0.065ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.750ns = ( 6.656 - 3.906 ) 
    Source Clock Delay      (SCD):    3.203ns
    Clock Pessimism Removal (CPR):    0.389ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.676ns (routing 1.519ns, distribution 1.157ns)
  Clock Net Delay (Destination): 2.364ns (routing 1.383ns, distribution 0.981ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=35, routed)          2.676     3.203    d_1_i/rst_adc0/U0/EXT_LPF/slowest_sync_clk
    SLICE_X35Y298        SRL16E                                       r  d_1_i/rst_adc0/U0/EXT_LPF/POR_SRL_I/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X35Y298        SRL16E (Prop_H6LUT_SLICEM_CLK_Q)
                                                      0.392     3.595 r  d_1_i/rst_adc0/U0/EXT_LPF/POR_SRL_I/Q
                         net (fo=1, routed)           0.149     3.744    d_1_i/rst_adc0/U0/EXT_LPF/Q
    SLICE_X36Y297        LUT3 (Prop_B5LUT_SLICEL_I2_O)
                                                      0.165     3.909 r  d_1_i/rst_adc0/U0/EXT_LPF/lpf_int0/O
                         net (fo=1, routed)           0.018     3.927    d_1_i/rst_adc0/U0/EXT_LPF/lpf_int0__0
    SLICE_X36Y297        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/lpf_int_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      3.906     3.906 r  
    HSADC_X0Y0           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=35, routed)          2.364     6.656    d_1_i/rst_adc0/U0/EXT_LPF/slowest_sync_clk
    SLICE_X36Y297        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/lpf_int_reg/C
                         clock pessimism              0.389     7.044    
                         clock uncertainty           -0.035     7.009    
    SLICE_X36Y297        FDRE (Setup_BFF2_SLICEL_C_D)
                                                      0.025     7.034    d_1_i/rst_adc0/U0/EXT_LPF/lpf_int_reg
  -------------------------------------------------------------------
                         required time                          7.034    
                         arrival time                          -3.927    
  -------------------------------------------------------------------
                         slack                                  3.107    

Slack (MET) :             3.341ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4/C
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/EXT_LPF/EXT_LPF[1].exr_lpf_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.906ns  (RFADC0_CLK rise@3.906ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.475ns  (logic 0.077ns (16.208%)  route 0.398ns (83.792%))
  Logic Levels:           0  
  Clock Path Skew:        -0.080ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.752ns = ( 6.658 - 3.906 ) 
    Source Clock Delay      (SCD):    3.173ns
    Clock Pessimism Removal (CPR):    0.342ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.646ns (routing 1.519ns, distribution 1.127ns)
  Clock Net Delay (Destination): 2.366ns (routing 1.383ns, distribution 0.983ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=35, routed)          2.646     3.173    d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/slowest_sync_clk
    SLICE_X34Y299        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4/C
  -------------------------------------------------------------------    -------------------
    SLICE_X34Y299        FDRE (Prop_CFF2_SLICEM_C_Q)
                                                      0.077     3.250 r  d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4/Q
                         net (fo=2, routed)           0.398     3.648    d_1_i/rst_adc0/U0/EXT_LPF/p_3_in6_in
    SLICE_X36Y297        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/EXT_LPF[1].exr_lpf_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      3.906     3.906 r  
    HSADC_X0Y0           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=35, routed)          2.366     6.658    d_1_i/rst_adc0/U0/EXT_LPF/slowest_sync_clk
    SLICE_X36Y297        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/EXT_LPF[1].exr_lpf_reg[1]/C
                         clock pessimism              0.342     6.999    
                         clock uncertainty           -0.035     6.964    
    SLICE_X36Y297        FDRE (Setup_FFF2_SLICEL_C_D)
                                                      0.025     6.989    d_1_i/rst_adc0/U0/EXT_LPF/EXT_LPF[1].exr_lpf_reg[1]
  -------------------------------------------------------------------
                         required time                          6.989    
                         arrival time                          -3.648    
  -------------------------------------------------------------------
                         slack                                  3.341    

Slack (MET) :             3.342ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/SEQ/core_dec_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.906ns  (RFADC0_CLK rise@3.906ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.527ns  (logic 0.227ns (43.048%)  route 0.300ns (56.952%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        -0.027ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.695ns = ( 6.601 - 3.906 ) 
    Source Clock Delay      (SCD):    3.116ns
    Clock Pessimism Removal (CPR):    0.395ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.589ns (routing 1.519ns, distribution 1.070ns)
  Clock Net Delay (Destination): 2.309ns (routing 1.383ns, distribution 0.926ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=35, routed)          2.589     3.116    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/slowest_sync_clk
    SLICE_X43Y296        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X43Y296        FDRE (Prop_FFF2_SLICEL_C_Q)
                                                      0.081     3.197 r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[0]/Q
                         net (fo=7, routed)           0.251     3.448    d_1_i/rst_adc0/U0/SEQ/seq_cnt[0]
    SLICE_X43Y296        LUT4 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.146     3.594 r  d_1_i/rst_adc0/U0/SEQ/pr_dec0/O
                         net (fo=1, routed)           0.049     3.643    d_1_i/rst_adc0/U0/SEQ/pr_dec0__0
    SLICE_X43Y296        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/core_dec_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      3.906     3.906 r  
    HSADC_X0Y0           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=35, routed)          2.309     6.601    d_1_i/rst_adc0/U0/SEQ/slowest_sync_clk
    SLICE_X43Y296        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/core_dec_reg[1]/C
                         clock pessimism              0.395     6.995    
                         clock uncertainty           -0.035     6.960    
    SLICE_X43Y296        FDRE (Setup_DFF_SLICEL_C_D)
                                                      0.025     6.985    d_1_i/rst_adc0/U0/SEQ/core_dec_reg[1]
  -------------------------------------------------------------------
                         required time                          6.985    
                         arrival time                          -3.643    
  -------------------------------------------------------------------
                         slack                                  3.342    

Slack (MET) :             3.343ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc0/U0/SEQ/seq_clr_reg/C
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[0]/R
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.906ns  (RFADC0_CLK rise@3.906ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.418ns  (logic 0.079ns (18.900%)  route 0.339ns (81.101%))
  Logic Levels:           0  
  Clock Path Skew:        -0.036ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.697ns = ( 6.603 - 3.906 ) 
    Source Clock Delay      (SCD):    3.115ns
    Clock Pessimism Removal (CPR):    0.383ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.588ns (routing 1.519ns, distribution 1.069ns)
  Clock Net Delay (Destination): 2.311ns (routing 1.383ns, distribution 0.928ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=35, routed)          2.588     3.115    d_1_i/rst_adc0/U0/SEQ/slowest_sync_clk
    SLICE_X43Y295        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/seq_clr_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X43Y295        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     3.194 f  d_1_i/rst_adc0/U0/SEQ/seq_clr_reg/Q
                         net (fo=6, routed)           0.339     3.533    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/seq_clr
    SLICE_X43Y296        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[0]/R  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      3.906     3.906 r  
    HSADC_X0Y0           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=35, routed)          2.311     6.603    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/slowest_sync_clk
    SLICE_X43Y296        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[0]/C
                         clock pessimism              0.383     6.985    
                         clock uncertainty           -0.035     6.950    
    SLICE_X43Y296        FDRE (Setup_FFF2_SLICEL_C_R)
                                                     -0.074     6.876    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[0]
  -------------------------------------------------------------------
                         required time                          6.876    
                         arrival time                          -3.533    
  -------------------------------------------------------------------
                         slack                                  3.343    

Slack (MET) :             3.343ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc0/U0/SEQ/seq_clr_reg/C
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[1]/R
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.906ns  (RFADC0_CLK rise@3.906ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.418ns  (logic 0.079ns (18.900%)  route 0.339ns (81.101%))
  Logic Levels:           0  
  Clock Path Skew:        -0.036ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.697ns = ( 6.603 - 3.906 ) 
    Source Clock Delay      (SCD):    3.115ns
    Clock Pessimism Removal (CPR):    0.383ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.588ns (routing 1.519ns, distribution 1.069ns)
  Clock Net Delay (Destination): 2.311ns (routing 1.383ns, distribution 0.928ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=35, routed)          2.588     3.115    d_1_i/rst_adc0/U0/SEQ/slowest_sync_clk
    SLICE_X43Y295        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/seq_clr_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X43Y295        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     3.194 f  d_1_i/rst_adc0/U0/SEQ/seq_clr_reg/Q
                         net (fo=6, routed)           0.339     3.533    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/seq_clr
    SLICE_X43Y296        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[1]/R  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      3.906     3.906 r  
    HSADC_X0Y0           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=35, routed)          2.311     6.603    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/slowest_sync_clk
    SLICE_X43Y296        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[1]/C
                         clock pessimism              0.383     6.985    
                         clock uncertainty           -0.035     6.950    
    SLICE_X43Y296        FDRE (Setup_HFF_SLICEL_C_R)
                                                     -0.074     6.876    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[1]
  -------------------------------------------------------------------
                         required time                          6.876    
                         arrival time                          -3.533    
  -------------------------------------------------------------------
                         slack                                  3.343    

Slack (MET) :             3.343ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc0/U0/SEQ/seq_clr_reg/C
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[2]/R
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.906ns  (RFADC0_CLK rise@3.906ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.418ns  (logic 0.079ns (18.900%)  route 0.339ns (81.101%))
  Logic Levels:           0  
  Clock Path Skew:        -0.036ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.697ns = ( 6.603 - 3.906 ) 
    Source Clock Delay      (SCD):    3.115ns
    Clock Pessimism Removal (CPR):    0.383ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.588ns (routing 1.519ns, distribution 1.069ns)
  Clock Net Delay (Destination): 2.311ns (routing 1.383ns, distribution 0.928ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=35, routed)          2.588     3.115    d_1_i/rst_adc0/U0/SEQ/slowest_sync_clk
    SLICE_X43Y295        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/seq_clr_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X43Y295        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     3.194 f  d_1_i/rst_adc0/U0/SEQ/seq_clr_reg/Q
                         net (fo=6, routed)           0.339     3.533    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/seq_clr
    SLICE_X43Y296        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[2]/R  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      3.906     3.906 r  
    HSADC_X0Y0           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=35, routed)          2.311     6.603    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/slowest_sync_clk
    SLICE_X43Y296        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[2]/C
                         clock pessimism              0.383     6.985    
                         clock uncertainty           -0.035     6.950    
    SLICE_X43Y296        FDRE (Setup_HFF2_SLICEL_C_R)
                                                     -0.074     6.876    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[2]
  -------------------------------------------------------------------
                         required time                          6.876    
                         arrival time                          -3.533    
  -------------------------------------------------------------------
                         slack                                  3.343    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.037ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (RFADC0_CLK rise@0.000ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.090ns  (logic 0.059ns (65.666%)  route 0.031ns (34.334%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.946ns
    Source Clock Delay      (SCD):    1.676ns
    Clock Pessimism Removal (CPR):    0.265ns
  Clock Net Delay (Source):      1.413ns (routing 0.818ns, distribution 0.595ns)
  Clock Net Delay (Destination): 1.594ns (routing 0.914ns, distribution 0.680ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=35, routed)          1.413     1.676    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/slowest_sync_clk
    SLICE_X43Y296        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X43Y296        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     1.715 r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[1]/Q
                         net (fo=6, routed)           0.025     1.739    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/Q[1]
    SLICE_X43Y296        LUT3 (Prop_H5LUT_SLICEL_I1_O)
                                                      0.020     1.759 r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int[2]_i_1/O
                         net (fo=1, routed)           0.006     1.765    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int0[2]
    SLICE_X43Y296        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=35, routed)          1.594     1.946    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/slowest_sync_clk
    SLICE_X43Y296        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[2]/C
                         clock pessimism             -0.265     1.682    
    SLICE_X43Y296        FDRE (Hold_HFF2_SLICEL_C_D)
                                                      0.047     1.729    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[2]
  -------------------------------------------------------------------
                         required time                         -1.729    
                         arrival time                           1.765    
  -------------------------------------------------------------------
                         slack                                  0.037    

Slack (MET) :             0.039ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc0/U0/EXT_LPF/lpf_exr_reg/C
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/EXT_LPF/lpf_int_reg/D
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (RFADC0_CLK rise@0.000ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.092ns  (logic 0.060ns (65.152%)  route 0.032ns (34.848%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.981ns
    Source Clock Delay      (SCD):    1.707ns
    Clock Pessimism Removal (CPR):    0.269ns
  Clock Net Delay (Source):      1.444ns (routing 0.818ns, distribution 0.626ns)
  Clock Net Delay (Destination): 1.629ns (routing 0.914ns, distribution 0.715ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=35, routed)          1.444     1.707    d_1_i/rst_adc0/U0/EXT_LPF/slowest_sync_clk
    SLICE_X36Y297        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/lpf_exr_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X36Y297        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     1.746 r  d_1_i/rst_adc0/U0/EXT_LPF/lpf_exr_reg/Q
                         net (fo=2, routed)           0.025     1.771    d_1_i/rst_adc0/U0/EXT_LPF/lpf_exr
    SLICE_X36Y297        LUT3 (Prop_B5LUT_SLICEL_I0_O)
                                                      0.021     1.792 r  d_1_i/rst_adc0/U0/EXT_LPF/lpf_int0/O
                         net (fo=1, routed)           0.007     1.799    d_1_i/rst_adc0/U0/EXT_LPF/lpf_int0__0
    SLICE_X36Y297        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/lpf_int_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=35, routed)          1.629     1.981    d_1_i/rst_adc0/U0/EXT_LPF/slowest_sync_clk
    SLICE_X36Y297        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/lpf_int_reg/C
                         clock pessimism             -0.269     1.713    
    SLICE_X36Y297        FDRE (Hold_BFF2_SLICEL_C_D)
                                                      0.047     1.760    d_1_i/rst_adc0/U0/EXT_LPF/lpf_int_reg
  -------------------------------------------------------------------
                         required time                         -1.760    
                         arrival time                           1.799    
  -------------------------------------------------------------------
                         slack                                  0.039    

Slack (MET) :             0.042ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (RFADC0_CLK rise@0.000ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.095ns  (logic 0.059ns (62.413%)  route 0.036ns (37.587%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.946ns
    Source Clock Delay      (SCD):    1.676ns
    Clock Pessimism Removal (CPR):    0.265ns
  Clock Net Delay (Source):      1.413ns (routing 0.818ns, distribution 0.595ns)
  Clock Net Delay (Destination): 1.594ns (routing 0.914ns, distribution 0.680ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=35, routed)          1.413     1.676    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/slowest_sync_clk
    SLICE_X43Y296        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X43Y296        FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.039     1.715 r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[3]/Q
                         net (fo=5, routed)           0.030     1.744    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/Q[3]
    SLICE_X43Y296        LUT5 (Prop_G5LUT_SLICEL_I3_O)
                                                      0.020     1.764 r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int[4]_i_1/O
                         net (fo=1, routed)           0.006     1.770    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int0[4]
    SLICE_X43Y296        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=35, routed)          1.594     1.946    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/slowest_sync_clk
    SLICE_X43Y296        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[4]/C
                         clock pessimism             -0.265     1.682    
    SLICE_X43Y296        FDRE (Hold_GFF2_SLICEL_C_D)
                                                      0.047     1.729    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[4]
  -------------------------------------------------------------------
                         required time                         -1.729    
                         arrival time                           1.770    
  -------------------------------------------------------------------
                         slack                                  0.042    

Slack (MET) :             0.048ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc0/U0/SEQ/core_dec_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/SEQ/core_dec_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (RFADC0_CLK rise@0.000ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.113ns  (logic 0.059ns (52.212%)  route 0.054ns (47.788%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        0.018ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.942ns
    Source Clock Delay      (SCD):    1.673ns
    Clock Pessimism Removal (CPR):    0.252ns
  Clock Net Delay (Source):      1.410ns (routing 0.818ns, distribution 0.592ns)
  Clock Net Delay (Destination): 1.590ns (routing 0.914ns, distribution 0.676ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=35, routed)          1.410     1.673    d_1_i/rst_adc0/U0/SEQ/slowest_sync_clk
    SLICE_X43Y296        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/core_dec_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X43Y296        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     1.712 r  d_1_i/rst_adc0/U0/SEQ/core_dec_reg[1]/Q
                         net (fo=2, routed)           0.048     1.760    d_1_i/rst_adc0/U0/SEQ/core_dec_reg_n_0_[1]
    SLICE_X43Y295        LUT2 (Prop_C5LUT_SLICEL_I0_O)
                                                      0.020     1.780 r  d_1_i/rst_adc0/U0/SEQ/core_dec[2]_i_1/O
                         net (fo=1, routed)           0.006     1.786    d_1_i/rst_adc0/U0/SEQ/core_dec[2]_i_1_n_0
    SLICE_X43Y295        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/core_dec_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=35, routed)          1.590     1.942    d_1_i/rst_adc0/U0/SEQ/slowest_sync_clk
    SLICE_X43Y295        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/core_dec_reg[2]/C
                         clock pessimism             -0.252     1.690    
    SLICE_X43Y295        FDRE (Hold_CFF2_SLICEL_C_D)
                                                      0.047     1.737    d_1_i/rst_adc0/U0/SEQ/core_dec_reg[2]
  -------------------------------------------------------------------
                         required time                         -1.737    
                         arrival time                           1.786    
  -------------------------------------------------------------------
                         slack                                  0.048    

Slack (MET) :             0.051ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3/C
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4/D
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (RFADC0_CLK rise@0.000ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.103ns  (logic 0.039ns (37.864%)  route 0.064ns (62.136%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.981ns
    Source Clock Delay      (SCD):    1.707ns
    Clock Pessimism Removal (CPR):    0.269ns
  Clock Net Delay (Source):      1.444ns (routing 0.818ns, distribution 0.626ns)
  Clock Net Delay (Destination): 1.629ns (routing 0.914ns, distribution 0.715ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=35, routed)          1.444     1.707    d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/slowest_sync_clk
    SLICE_X36Y297        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3/C
  -------------------------------------------------------------------    -------------------
    SLICE_X36Y297        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.039     1.746 r  d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3/Q
                         net (fo=1, routed)           0.064     1.810    d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3
    SLICE_X36Y297        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=35, routed)          1.629     1.981    d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/slowest_sync_clk
    SLICE_X36Y297        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4/C
                         clock pessimism             -0.269     1.713    
    SLICE_X36Y297        FDRE (Hold_BFF_SLICEL_C_D)
                                                      0.046     1.759    d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4
  -------------------------------------------------------------------
                         required time                         -1.759    
                         arrival time                           1.810    
  -------------------------------------------------------------------
                         slack                                  0.051    

Slack (MET) :             0.052ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (RFADC0_CLK rise@0.000ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.104ns  (logic 0.062ns (59.703%)  route 0.042ns (40.297%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.946ns
    Source Clock Delay      (SCD):    1.676ns
    Clock Pessimism Removal (CPR):    0.265ns
  Clock Net Delay (Source):      1.413ns (routing 0.818ns, distribution 0.595ns)
  Clock Net Delay (Destination): 1.594ns (routing 0.914ns, distribution 0.680ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=35, routed)          1.413     1.676    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/slowest_sync_clk
    SLICE_X43Y296        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X43Y296        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     1.715 r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[1]/Q
                         net (fo=6, routed)           0.025     1.739    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/Q[1]
    SLICE_X43Y296        LUT2 (Prop_H6LUT_SLICEL_I1_O)
                                                      0.023     1.762 r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int[1]_i_1/O
                         net (fo=1, routed)           0.017     1.779    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int0[1]
    SLICE_X43Y296        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=35, routed)          1.594     1.946    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/slowest_sync_clk
    SLICE_X43Y296        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[1]/C
                         clock pessimism             -0.265     1.682    
    SLICE_X43Y296        FDRE (Hold_HFF_SLICEL_C_D)
                                                      0.046     1.728    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[1]
  -------------------------------------------------------------------
                         required time                         -1.728    
                         arrival time                           1.779    
  -------------------------------------------------------------------
                         slack                                  0.052    

Slack (MET) :             0.052ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/SEQ/core_dec_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (RFADC0_CLK rise@0.000ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.114ns  (logic 0.059ns (51.712%)  route 0.055ns (48.288%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        0.015ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.942ns
    Source Clock Delay      (SCD):    1.676ns
    Clock Pessimism Removal (CPR):    0.252ns
  Clock Net Delay (Source):      1.413ns (routing 0.818ns, distribution 0.595ns)
  Clock Net Delay (Destination): 1.590ns (routing 0.914ns, distribution 0.676ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=35, routed)          1.413     1.676    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/slowest_sync_clk
    SLICE_X43Y296        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X43Y296        FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.039     1.715 r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[3]/Q
                         net (fo=5, routed)           0.049     1.764    d_1_i/rst_adc0/U0/SEQ/seq_cnt[3]
    SLICE_X43Y295        LUT4 (Prop_D5LUT_SLICEL_I2_O)
                                                      0.020     1.784 r  d_1_i/rst_adc0/U0/SEQ/core_dec[0]_i_1/O
                         net (fo=1, routed)           0.006     1.790    d_1_i/rst_adc0/U0/SEQ/core_dec[0]_i_1_n_0
    SLICE_X43Y295        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/core_dec_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=35, routed)          1.590     1.942    d_1_i/rst_adc0/U0/SEQ/slowest_sync_clk
    SLICE_X43Y295        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/core_dec_reg[0]/C
                         clock pessimism             -0.252     1.690    
    SLICE_X43Y295        FDRE (Hold_DFF2_SLICEL_C_D)
                                                      0.047     1.737    d_1_i/rst_adc0/U0/SEQ/core_dec_reg[0]
  -------------------------------------------------------------------
                         required time                         -1.737    
                         arrival time                           1.790    
  -------------------------------------------------------------------
                         slack                                  0.052    

Slack (MET) :             0.055ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (RFADC0_CLK rise@0.000ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.107ns  (logic 0.061ns (57.260%)  route 0.046ns (42.740%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.946ns
    Source Clock Delay      (SCD):    1.676ns
    Clock Pessimism Removal (CPR):    0.265ns
  Clock Net Delay (Source):      1.413ns (routing 0.818ns, distribution 0.595ns)
  Clock Net Delay (Destination): 1.594ns (routing 0.914ns, distribution 0.680ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=35, routed)          1.413     1.676    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/slowest_sync_clk
    SLICE_X43Y296        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X43Y296        FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.039     1.715 r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[3]/Q
                         net (fo=5, routed)           0.030     1.744    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/Q[3]
    SLICE_X43Y296        LUT4 (Prop_G6LUT_SLICEL_I3_O)
                                                      0.022     1.766 r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int[3]_i_1/O
                         net (fo=1, routed)           0.016     1.782    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int0[3]
    SLICE_X43Y296        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=35, routed)          1.594     1.946    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/slowest_sync_clk
    SLICE_X43Y296        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[3]/C
                         clock pessimism             -0.265     1.682    
    SLICE_X43Y296        FDRE (Hold_GFF_SLICEL_C_D)
                                                      0.046     1.728    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[3]
  -------------------------------------------------------------------
                         required time                         -1.728    
                         arrival time                           1.782    
  -------------------------------------------------------------------
                         slack                                  0.055    

Slack (MET) :             0.062ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc0/U0/SEQ/core_dec_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/SEQ/pr_dec_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (RFADC0_CLK rise@0.000ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.126ns  (logic 0.061ns (48.413%)  route 0.065ns (51.587%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        0.018ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.942ns
    Source Clock Delay      (SCD):    1.673ns
    Clock Pessimism Removal (CPR):    0.252ns
  Clock Net Delay (Source):      1.410ns (routing 0.818ns, distribution 0.592ns)
  Clock Net Delay (Destination): 1.590ns (routing 0.914ns, distribution 0.676ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=35, routed)          1.410     1.673    d_1_i/rst_adc0/U0/SEQ/slowest_sync_clk
    SLICE_X43Y296        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/core_dec_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X43Y296        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     1.712 r  d_1_i/rst_adc0/U0/SEQ/core_dec_reg[1]/Q
                         net (fo=2, routed)           0.048     1.760    d_1_i/rst_adc0/U0/SEQ/core_dec_reg_n_0_[1]
    SLICE_X43Y295        LUT2 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.022     1.782 r  d_1_i/rst_adc0/U0/SEQ/pr_dec[2]_i_1/O
                         net (fo=1, routed)           0.017     1.799    d_1_i/rst_adc0/U0/SEQ/p_3_out[2]
    SLICE_X43Y295        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/pr_dec_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=35, routed)          1.590     1.942    d_1_i/rst_adc0/U0/SEQ/slowest_sync_clk
    SLICE_X43Y295        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/pr_dec_reg[2]/C
                         clock pessimism             -0.252     1.690    
    SLICE_X43Y295        FDRE (Hold_CFF_SLICEL_C_D)
                                                      0.046     1.736    d_1_i/rst_adc0/U0/SEQ/pr_dec_reg[2]
  -------------------------------------------------------------------
                         required time                         -1.736    
                         arrival time                           1.799    
  -------------------------------------------------------------------
                         slack                                  0.062    

Slack (MET) :             0.062ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (RFADC0_CLK rise@0.000ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.114ns  (logic 0.053ns (46.351%)  route 0.061ns (53.649%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.946ns
    Source Clock Delay      (SCD):    1.676ns
    Clock Pessimism Removal (CPR):    0.265ns
  Clock Net Delay (Source):      1.413ns (routing 0.818ns, distribution 0.595ns)
  Clock Net Delay (Destination): 1.594ns (routing 0.914ns, distribution 0.680ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=35, routed)          1.413     1.676    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/slowest_sync_clk
    SLICE_X43Y296        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X43Y296        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     1.715 r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[1]/Q
                         net (fo=6, routed)           0.046     1.761    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/Q[1]
    SLICE_X43Y296        LUT6 (Prop_E6LUT_SLICEL_I1_O)
                                                      0.014     1.775 r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int[5]_i_2/O
                         net (fo=1, routed)           0.015     1.790    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int0[5]
    SLICE_X43Y296        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=35, routed)          1.594     1.946    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/slowest_sync_clk
    SLICE_X43Y296        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[5]/C
                         clock pessimism             -0.265     1.682    
    SLICE_X43Y296        FDRE (Hold_EFF_SLICEL_C_D)
                                                      0.046     1.728    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[5]
  -------------------------------------------------------------------
                         required time                         -1.728    
                         arrival time                           1.790    
  -------------------------------------------------------------------
                         slack                                  0.062    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         RFADC0_CLK
Waveform(ns):       { 0.000 1.953 }
Period(ns):         3.906
Sources:            { d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX }

Check Type        Corner  Lib Pin            Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location       Pin
Min Period        n/a     HSADC/CLK_ADC      n/a            1.923         3.906       1.983      HSADC_X0Y0     d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
Min Period        n/a     BUFG_GT/I          n/a            1.290         3.906       2.616      BUFG_GT_X1Y3   d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/I
Min Period        n/a     MMCME4_ADV/CLKIN1  n/a            1.071         3.906       2.835      MMCM_X0Y1      d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
Min Period        n/a     SRL16E/CLK         n/a            1.064         3.906       2.842      SLICE_X35Y298  d_1_i/rst_adc0/U0/EXT_LPF/POR_SRL_I/CLK
Min Period        n/a     FDRE/C             n/a            0.550         3.906       3.356      SLICE_X43Y295  d_1_i/rst_adc0/U0/PR_OUT_DFF[0].FDRE_PER/C
Min Period        n/a     FDRE/C             n/a            0.550         3.906       3.356      SLICE_X36Y297  d_1_i/rst_adc0/U0/EXT_LPF/AUX_LPF[1].asr_lpf_reg[1]/C
Min Period        n/a     FDRE/C             n/a            0.550         3.906       3.356      SLICE_X36Y297  d_1_i/rst_adc0/U0/EXT_LPF/AUX_LPF[2].asr_lpf_reg[2]/C
Min Period        n/a     FDRE/C             n/a            0.550         3.906       3.356      SLICE_X36Y297  d_1_i/rst_adc0/U0/EXT_LPF/AUX_LPF[3].asr_lpf_reg[3]/C
Min Period        n/a     FDRE/C             n/a            0.550         3.906       3.356      SLICE_X36Y297  d_1_i/rst_adc0/U0/EXT_LPF/EXT_LPF[1].exr_lpf_reg[1]/C
Min Period        n/a     FDRE/C             n/a            0.550         3.906       3.356      SLICE_X36Y297  d_1_i/rst_adc0/U0/EXT_LPF/EXT_LPF[2].exr_lpf_reg[2]/C
Max Period        n/a     MMCME4_ADV/CLKIN1  n/a            100.000       3.906       96.094     MMCM_X0Y1      d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
Low Pulse Width   Slow    MMCME4_ADV/CLKIN1  n/a            1.367         1.953       0.586      MMCM_X0Y1      d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
Low Pulse Width   Fast    MMCME4_ADV/CLKIN1  n/a            1.367         1.953       0.586      MMCM_X0Y1      d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
Low Pulse Width   Slow    HSADC/CLK_ADC      n/a            0.800         1.953       1.153      HSADC_X0Y0     d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
Low Pulse Width   Fast    HSADC/CLK_ADC      n/a            0.800         1.953       1.153      HSADC_X0Y0     d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
Low Pulse Width   Slow    SRL16E/CLK         n/a            0.532         1.953       1.421      SLICE_X35Y298  d_1_i/rst_adc0/U0/EXT_LPF/POR_SRL_I/CLK
Low Pulse Width   Fast    SRL16E/CLK         n/a            0.532         1.953       1.421      SLICE_X35Y298  d_1_i/rst_adc0/U0/EXT_LPF/POR_SRL_I/CLK
Low Pulse Width   Slow    FDRE/C             n/a            0.275         1.953       1.678      SLICE_X43Y295  d_1_i/rst_adc0/U0/PR_OUT_DFF[0].FDRE_PER/C
Low Pulse Width   Fast    FDRE/C             n/a            0.275         1.953       1.678      SLICE_X43Y295  d_1_i/rst_adc0/U0/PR_OUT_DFF[0].FDRE_PER/C
Low Pulse Width   Slow    FDRE/C             n/a            0.275         1.953       1.678      SLICE_X36Y297  d_1_i/rst_adc0/U0/EXT_LPF/AUX_LPF[1].asr_lpf_reg[1]/C
Low Pulse Width   Fast    FDRE/C             n/a            0.275         1.953       1.678      SLICE_X36Y297  d_1_i/rst_adc0/U0/EXT_LPF/AUX_LPF[1].asr_lpf_reg[1]/C
High Pulse Width  Slow    MMCME4_ADV/CLKIN1  n/a            1.367         1.953       0.586      MMCM_X0Y1      d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
High Pulse Width  Fast    MMCME4_ADV/CLKIN1  n/a            1.367         1.953       0.586      MMCM_X0Y1      d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
High Pulse Width  Slow    HSADC/CLK_ADC      n/a            0.800         1.953       1.153      HSADC_X0Y0     d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
High Pulse Width  Fast    HSADC/CLK_ADC      n/a            0.800         1.953       1.153      HSADC_X0Y0     d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
High Pulse Width  Slow    SRL16E/CLK         n/a            0.532         1.953       1.421      SLICE_X35Y298  d_1_i/rst_adc0/U0/EXT_LPF/POR_SRL_I/CLK
High Pulse Width  Fast    SRL16E/CLK         n/a            0.532         1.953       1.421      SLICE_X35Y298  d_1_i/rst_adc0/U0/EXT_LPF/POR_SRL_I/CLK
High Pulse Width  Slow    FDRE/C             n/a            0.275         1.953       1.678      SLICE_X43Y295  d_1_i/rst_adc0/U0/PR_OUT_DFF[0].FDRE_PER/C
High Pulse Width  Fast    FDRE/C             n/a            0.275         1.953       1.678      SLICE_X43Y295  d_1_i/rst_adc0/U0/PR_OUT_DFF[0].FDRE_PER/C
High Pulse Width  Slow    FDRE/C             n/a            0.275         1.953       1.678      SLICE_X36Y297  d_1_i/rst_adc0/U0/EXT_LPF/AUX_LPF[1].asr_lpf_reg[1]/C
High Pulse Width  Fast    FDRE/C             n/a            0.275         1.953       1.678      SLICE_X36Y297  d_1_i/rst_adc0/U0/EXT_LPF/AUX_LPF[1].asr_lpf_reg[1]/C



---------------------------------------------------------------------------------------------------
From Clock:  clk_out1_d_1_clk_adc0_x2_0
  To Clock:  clk_out1_d_1_clk_adc0_x2_0

Setup :            0  Failing Endpoints,  Worst Slack        0.008ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.008ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        0.030ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.008ns  (required time - arrival time)
  Source:                 d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[6].dout_mux_r_reg[6][19]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.i_data_in/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][211]_srl1/D
                            (rising edge-triggered cell SRL16E clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            1.953ns  (clk_out1_d_1_clk_adc0_x2_0 rise@1.953ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        1.561ns  (logic 0.077ns (4.933%)  route 1.484ns (95.067%))
  Logic Levels:           0  
  Clock Path Skew:        -0.273ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.478ns = ( 7.431 - 1.953 ) 
    Source Clock Delay      (SCD):    5.563ns
    Clock Pessimism Removal (CPR):    -0.188ns
  Clock Uncertainty:      0.051ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.074ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.295ns (routing 0.858ns, distribution 1.437ns)
  Clock Net Delay (Destination): 1.882ns (routing 0.782ns, distribution 1.100ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.595     3.122    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.995 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.240    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.268 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       2.295     5.563    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/aclk
    SLICE_X86Y133        FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[6].dout_mux_r_reg[6][19]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X86Y133        FDRE (Prop_CFF2_SLICEM_C_Q)
                                                      0.077     5.640 r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[6].dout_mux_r_reg[6][19]/Q
                         net (fo=2, routed)           1.484     7.124    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.i_data_in/s_axis_data_tdata[211]
    SLICE_X56Y166        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.i_data_in/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][211]_srl1/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      1.953     1.953 r  
    HSADC_X0Y0           HSADC                        0.000     1.953 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     2.075 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     2.225    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.339 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.341     4.680    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.310 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.525    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.549 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.882     7.431    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.i_data_in/aclk
    SLICE_X56Y166        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.i_data_in/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][211]_srl1/CLK
                         clock pessimism             -0.188     7.243    
                         clock uncertainty           -0.051     7.191    
    SLICE_X56Y166        SRL16E (Setup_D6LUT_SLICEM_CLK_D)
                                                     -0.060     7.131    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.i_data_in/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][211]_srl1
  -------------------------------------------------------------------
                         required time                          7.131    
                         arrival time                          -7.124    
  -------------------------------------------------------------------
                         slack                                  0.008    

Slack (MET) :             0.008ns  (required time - arrival time)
  Source:                 d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/pinc_Nm_r3_reg/DSP_OUTPUT_INST/CLK
                            (rising edge-triggered cell DSP_OUTPUT clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/phase_0_r1_reg[27]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            1.953ns  (clk_out1_d_1_clk_adc0_x2_0 rise@1.953ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        1.546ns  (logic 0.486ns (31.438%)  route 1.060ns (68.562%))
  Logic Levels:           3  (CARRY8=2 LUT2=1)
  Clock Path Skew:        -0.373ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.472ns = ( 7.425 - 1.953 ) 
    Source Clock Delay      (SCD):    5.597ns
    Clock Pessimism Removal (CPR):    -0.248ns
  Clock Uncertainty:      0.051ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.074ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.329ns (routing 0.858ns, distribution 1.471ns)
  Clock Net Delay (Destination): 1.876ns (routing 0.782ns, distribution 1.094ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.595     3.122    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.995 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.240    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.268 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       2.329     5.597    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/pinc_Nm_r3_reg/CLK
    DSP48E2_X15Y44       DSP_OUTPUT                                   r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/pinc_Nm_r3_reg/DSP_OUTPUT_INST/CLK
  -------------------------------------------------------------------    -------------------
    DSP48E2_X15Y44       DSP_OUTPUT (Prop_DSP_OUTPUT_DSP48E2_CLK_P[1])
                                                      0.214     5.811 r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/pinc_Nm_r3_reg/DSP_OUTPUT_INST/P[1]
                         net (fo=2, routed)           0.998     6.809    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/aclk_0[18]
    SLICE_X65Y137        LUT2 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.035     6.844 r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/phase_0_r1[23]_i_7/O
                         net (fo=1, routed)           0.010     6.854    d_1_i/axis_dyn_readout_v1_3/inst_n_335
    SLICE_X65Y137        CARRY8 (Prop_CARRY8_SLICEL_S[2]_CO[7])
                                                      0.155     7.009 r  d_1_i/axis_dyn_readout_v1_3/ctrl_i/phase_0_r1_reg[23]_i_1/CO[7]
                         net (fo=1, routed)           0.026     7.035    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/CO[0]
    SLICE_X65Y138        CARRY8 (Prop_CARRY8_SLICEL_CI_O[3])
                                                      0.082     7.117 r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/phase_0_r1_reg[31]_i_1/O[3]
                         net (fo=1, routed)           0.026     7.143    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/phase_0[27]
    SLICE_X65Y138        FDRE                                         r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/phase_0_r1_reg[27]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      1.953     1.953 r  
    HSADC_X0Y0           HSADC                        0.000     1.953 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     2.075 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     2.225    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.339 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.341     4.680    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.310 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.525    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.549 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.876     7.425    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/aclk
    SLICE_X65Y138        FDRE                                         r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/phase_0_r1_reg[27]/C
                         clock pessimism             -0.248     7.177    
                         clock uncertainty           -0.051     7.126    
    SLICE_X65Y138        FDRE (Setup_DFF_SLICEL_C_D)
                                                      0.025     7.151    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/phase_0_r1_reg[27]
  -------------------------------------------------------------------
                         required time                          7.151    
                         arrival time                          -7.143    
  -------------------------------------------------------------------
                         slack                                  0.008    

Slack (MET) :             0.015ns  (required time - arrival time)
  Source:                 d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/pinc_Nm_r3_reg/DSP_OUTPUT_INST/CLK
                            (rising edge-triggered cell DSP_OUTPUT clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/phase_0_r1_reg[25]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            1.953ns  (clk_out1_d_1_clk_adc0_x2_0 rise@1.953ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        1.539ns  (logic 0.480ns (31.191%)  route 1.059ns (68.809%))
  Logic Levels:           3  (CARRY8=2 LUT2=1)
  Clock Path Skew:        -0.373ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.472ns = ( 7.425 - 1.953 ) 
    Source Clock Delay      (SCD):    5.597ns
    Clock Pessimism Removal (CPR):    -0.248ns
  Clock Uncertainty:      0.051ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.074ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.329ns (routing 0.858ns, distribution 1.471ns)
  Clock Net Delay (Destination): 1.876ns (routing 0.782ns, distribution 1.094ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.595     3.122    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.995 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.240    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.268 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       2.329     5.597    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/pinc_Nm_r3_reg/CLK
    DSP48E2_X15Y44       DSP_OUTPUT                                   r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/pinc_Nm_r3_reg/DSP_OUTPUT_INST/CLK
  -------------------------------------------------------------------    -------------------
    DSP48E2_X15Y44       DSP_OUTPUT (Prop_DSP_OUTPUT_DSP48E2_CLK_P[1])
                                                      0.214     5.811 r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/pinc_Nm_r3_reg/DSP_OUTPUT_INST/P[1]
                         net (fo=2, routed)           0.998     6.809    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/aclk_0[18]
    SLICE_X65Y137        LUT2 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.035     6.844 r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/phase_0_r1[23]_i_7/O
                         net (fo=1, routed)           0.010     6.854    d_1_i/axis_dyn_readout_v1_3/inst_n_335
    SLICE_X65Y137        CARRY8 (Prop_CARRY8_SLICEL_S[2]_CO[7])
                                                      0.155     7.009 r  d_1_i/axis_dyn_readout_v1_3/ctrl_i/phase_0_r1_reg[23]_i_1/CO[7]
                         net (fo=1, routed)           0.026     7.035    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/CO[0]
    SLICE_X65Y138        CARRY8 (Prop_CARRY8_SLICEL_CI_O[1])
                                                      0.076     7.111 r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/phase_0_r1_reg[31]_i_1/O[1]
                         net (fo=1, routed)           0.025     7.136    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/phase_0[25]
    SLICE_X65Y138        FDRE                                         r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/phase_0_r1_reg[25]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      1.953     1.953 r  
    HSADC_X0Y0           HSADC                        0.000     1.953 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     2.075 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     2.225    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.339 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.341     4.680    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.310 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.525    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.549 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.876     7.425    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/aclk
    SLICE_X65Y138        FDRE                                         r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/phase_0_r1_reg[25]/C
                         clock pessimism             -0.248     7.177    
                         clock uncertainty           -0.051     7.126    
    SLICE_X65Y138        FDRE (Setup_BFF_SLICEL_C_D)
                                                      0.025     7.151    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/phase_0_r1_reg[25]
  -------------------------------------------------------------------
                         required time                          7.151    
                         arrival time                          -7.136    
  -------------------------------------------------------------------
                         slack                                  0.015    

Slack (MET) :             0.022ns  (required time - arrival time)
  Source:                 d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dout_mux_r_reg[0][15]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.i_data_in/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][15]_srl1/D
                            (rising edge-triggered cell SRL16E clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            1.953ns  (clk_out1_d_1_clk_adc0_x2_0 rise@1.953ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        1.546ns  (logic 0.079ns (5.111%)  route 1.467ns (94.889%))
  Logic Levels:           0  
  Clock Path Skew:        -0.317ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.448ns = ( 7.401 - 1.953 ) 
    Source Clock Delay      (SCD):    5.576ns
    Clock Pessimism Removal (CPR):    -0.188ns
  Clock Uncertainty:      0.051ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.074ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.308ns (routing 0.858ns, distribution 1.450ns)
  Clock Net Delay (Destination): 1.852ns (routing 0.782ns, distribution 1.070ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.595     3.122    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.995 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.240    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.268 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       2.308     5.576    d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/aclk
    SLICE_X91Y144        FDRE                                         r  d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dout_mux_r_reg[0][15]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y144        FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.079     5.655 r  d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dout_mux_r_reg[0][15]/Q
                         net (fo=2, routed)           1.467     7.122    d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.i_data_in/s_axis_data_tdata[15]
    SLICE_X46Y172        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.i_data_in/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][15]_srl1/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      1.953     1.953 r  
    HSADC_X0Y0           HSADC                        0.000     1.953 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     2.075 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     2.225    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.339 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.341     4.680    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.310 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.525    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.549 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.852     7.401    d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.i_data_in/aclk
    SLICE_X46Y172        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.i_data_in/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][15]_srl1/CLK
                         clock pessimism             -0.188     7.212    
                         clock uncertainty           -0.051     7.161    
    SLICE_X46Y172        SRL16E (Setup_H5LUT_SLICEM_CLK_D)
                                                     -0.017     7.144    d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.i_data_in/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][15]_srl1
  -------------------------------------------------------------------
                         required time                          7.144    
                         arrival time                          -7.122    
  -------------------------------------------------------------------
                         slack                                  0.022    

Slack (MET) :             0.023ns  (required time - arrival time)
  Source:                 d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/pinc_Nm_r3_reg/DSP_OUTPUT_INST/CLK
                            (rising edge-triggered cell DSP_OUTPUT clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/phase_0_r1_reg[26]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            1.953ns  (clk_out1_d_1_clk_adc0_x2_0 rise@1.953ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        1.531ns  (logic 0.471ns (30.766%)  route 1.060ns (69.234%))
  Logic Levels:           3  (CARRY8=2 LUT2=1)
  Clock Path Skew:        -0.373ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.472ns = ( 7.425 - 1.953 ) 
    Source Clock Delay      (SCD):    5.597ns
    Clock Pessimism Removal (CPR):    -0.248ns
  Clock Uncertainty:      0.051ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.074ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.329ns (routing 0.858ns, distribution 1.471ns)
  Clock Net Delay (Destination): 1.876ns (routing 0.782ns, distribution 1.094ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.595     3.122    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.995 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.240    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.268 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       2.329     5.597    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/pinc_Nm_r3_reg/CLK
    DSP48E2_X15Y44       DSP_OUTPUT                                   r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/pinc_Nm_r3_reg/DSP_OUTPUT_INST/CLK
  -------------------------------------------------------------------    -------------------
    DSP48E2_X15Y44       DSP_OUTPUT (Prop_DSP_OUTPUT_DSP48E2_CLK_P[1])
                                                      0.214     5.811 r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/pinc_Nm_r3_reg/DSP_OUTPUT_INST/P[1]
                         net (fo=2, routed)           0.998     6.809    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/aclk_0[18]
    SLICE_X65Y137        LUT2 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.035     6.844 r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/phase_0_r1[23]_i_7/O
                         net (fo=1, routed)           0.010     6.854    d_1_i/axis_dyn_readout_v1_3/inst_n_335
    SLICE_X65Y137        CARRY8 (Prop_CARRY8_SLICEL_S[2]_CO[7])
                                                      0.155     7.009 r  d_1_i/axis_dyn_readout_v1_3/ctrl_i/phase_0_r1_reg[23]_i_1/CO[7]
                         net (fo=1, routed)           0.026     7.035    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/CO[0]
    SLICE_X65Y138        CARRY8 (Prop_CARRY8_SLICEL_CI_O[2])
                                                      0.067     7.102 r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/phase_0_r1_reg[31]_i_1/O[2]
                         net (fo=1, routed)           0.026     7.128    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/phase_0[26]
    SLICE_X65Y138        FDRE                                         r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/phase_0_r1_reg[26]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      1.953     1.953 r  
    HSADC_X0Y0           HSADC                        0.000     1.953 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     2.075 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     2.225    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.339 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.341     4.680    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.310 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.525    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.549 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.876     7.425    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/aclk
    SLICE_X65Y138        FDRE                                         r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/phase_0_r1_reg[26]/C
                         clock pessimism             -0.248     7.177    
                         clock uncertainty           -0.051     7.126    
    SLICE_X65Y138        FDRE (Setup_CFF_SLICEL_C_D)
                                                      0.025     7.151    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/phase_0_r1_reg[26]
  -------------------------------------------------------------------
                         required time                          7.151    
                         arrival time                          -7.128    
  -------------------------------------------------------------------
                         slack                                  0.023    

Slack (MET) :             0.025ns  (required time - arrival time)
  Source:                 d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/pinc_Nm_r3_reg/DSP_OUTPUT_INST/CLK
                            (rising edge-triggered cell DSP_OUTPUT clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/phase_0_r1_reg[31]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            1.953ns  (clk_out1_d_1_clk_adc0_x2_0 rise@1.953ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        1.580ns  (logic 0.520ns (32.913%)  route 1.060ns (67.087%))
  Logic Levels:           3  (CARRY8=2 LUT2=1)
  Clock Path Skew:        -0.322ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.523ns = ( 7.476 - 1.953 ) 
    Source Clock Delay      (SCD):    5.597ns
    Clock Pessimism Removal (CPR):    -0.248ns
  Clock Uncertainty:      0.051ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.074ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.329ns (routing 0.858ns, distribution 1.471ns)
  Clock Net Delay (Destination): 1.927ns (routing 0.782ns, distribution 1.145ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.595     3.122    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.995 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.240    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.268 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       2.329     5.597    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/pinc_Nm_r3_reg/CLK
    DSP48E2_X15Y44       DSP_OUTPUT                                   r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/pinc_Nm_r3_reg/DSP_OUTPUT_INST/CLK
  -------------------------------------------------------------------    -------------------
    DSP48E2_X15Y44       DSP_OUTPUT (Prop_DSP_OUTPUT_DSP48E2_CLK_P[1])
                                                      0.214     5.811 r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/pinc_Nm_r3_reg/DSP_OUTPUT_INST/P[1]
                         net (fo=2, routed)           0.998     6.809    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/aclk_0[18]
    SLICE_X65Y137        LUT2 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.035     6.844 r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/phase_0_r1[23]_i_7/O
                         net (fo=1, routed)           0.010     6.854    d_1_i/axis_dyn_readout_v1_3/inst_n_335
    SLICE_X65Y137        CARRY8 (Prop_CARRY8_SLICEL_S[2]_CO[7])
                                                      0.155     7.009 r  d_1_i/axis_dyn_readout_v1_3/ctrl_i/phase_0_r1_reg[23]_i_1/CO[7]
                         net (fo=1, routed)           0.026     7.035    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/CO[0]
    SLICE_X65Y138        CARRY8 (Prop_CARRY8_SLICEL_CI_O[7])
                                                      0.116     7.151 r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/phase_0_r1_reg[31]_i_1/O[7]
                         net (fo=1, routed)           0.026     7.177    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/phase_0[31]
    SLICE_X65Y138        FDRE                                         r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/phase_0_r1_reg[31]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      1.953     1.953 r  
    HSADC_X0Y0           HSADC                        0.000     1.953 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     2.075 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     2.225    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.339 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.341     4.680    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.310 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.525    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.549 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.927     7.476    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/aclk
    SLICE_X65Y138        FDRE                                         r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/phase_0_r1_reg[31]/C
                         clock pessimism             -0.248     7.228    
                         clock uncertainty           -0.051     7.177    
    SLICE_X65Y138        FDRE (Setup_HFF_SLICEL_C_D)
                                                      0.025     7.202    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/phase_0_r1_reg[31]
  -------------------------------------------------------------------
                         required time                          7.202    
                         arrival time                          -7.177    
  -------------------------------------------------------------------
                         slack                                  0.025    

Slack (MET) :             0.026ns  (required time - arrival time)
  Source:                 d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/dds_ctrl_int_r_reg[509]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[2].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/DSP_OUTPUT_INST/ALU_OUT[10]
                            (rising edge-triggered cell DSP_OUTPUT clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            1.953ns  (clk_out1_d_1_clk_adc0_x2_0 rise@1.953ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        1.670ns  (logic 0.860ns (51.509%)  route 0.810ns (48.491%))
  Logic Levels:           3  (DSP_ALU=1 DSP_C_DATA=1 LUT3=1)
  Clock Path Skew:        -0.221ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.560ns = ( 7.513 - 1.953 ) 
    Source Clock Delay      (SCD):    5.550ns
    Clock Pessimism Removal (CPR):    -0.231ns
  Clock Uncertainty:      0.051ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.074ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.282ns (routing 0.858ns, distribution 1.424ns)
  Clock Net Delay (Destination): 1.964ns (routing 0.782ns, distribution 1.182ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.595     3.122    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.995 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.240    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.268 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       2.282     5.550    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/aclk
    SLICE_X81Y56         FDRE                                         r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/dds_ctrl_int_r_reg[509]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y56         FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     5.631 r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/dds_ctrl_int_r_reg[509]/Q
                         net (fo=16, routed)          0.613     6.244    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[2].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/s_axis_phase_tdata[2]
    SLICE_X79Y65         LUT3 (Prop_B6LUT_SLICEM_I0_O)
                                                      0.089     6.333 r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[2].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP_i_27/O
                         net (fo=1, routed)           0.197     6.530    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[2].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/C[5]
    DSP48E2_X13Y26       DSP_C_DATA (Prop_DSP_C_DATA_DSP48E2_C[5]_C_DATA[5])
                                                      0.105     6.635 r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[2].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/DSP_C_DATA_INST/C_DATA[5]
                         net (fo=2, routed)           0.000     6.635    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[2].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/DSP_C_DATA.C_DATA<5>
    DSP48E2_X13Y26       DSP_ALU (Prop_DSP_ALU_DSP48E2_C_DATA[5]_ALU_OUT[10])
                                                      0.585     7.220 r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[2].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/DSP_ALU_INST/ALU_OUT[10]
                         net (fo=1, routed)           0.000     7.220    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[2].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/DSP_ALU.ALU_OUT<10>
    DSP48E2_X13Y26       DSP_OUTPUT                                   r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[2].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/DSP_OUTPUT_INST/ALU_OUT[10]
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      1.953     1.953 r  
    HSADC_X0Y0           HSADC                        0.000     1.953 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     2.075 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     2.225    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.339 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.341     4.680    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.310 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.525    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.549 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.964     7.513    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[2].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/CLK
    DSP48E2_X13Y26       DSP_OUTPUT                                   r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[2].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/DSP_OUTPUT_INST/CLK
                         clock pessimism             -0.231     7.282    
                         clock uncertainty           -0.051     7.230    
    DSP48E2_X13Y26       DSP_OUTPUT (Setup_DSP_OUTPUT_DSP48E2_CLK_ALU_OUT[10])
                                                      0.015     7.245    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[2].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/DSP_OUTPUT_INST
  -------------------------------------------------------------------
                         required time                          7.245    
                         arrival time                          -7.220    
  -------------------------------------------------------------------
                         slack                                  0.026    

Slack (MET) :             0.026ns  (required time - arrival time)
  Source:                 d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/dds_ctrl_int_r_reg[509]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[2].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/DSP_OUTPUT_INST/ALU_OUT[11]
                            (rising edge-triggered cell DSP_OUTPUT clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            1.953ns  (clk_out1_d_1_clk_adc0_x2_0 rise@1.953ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        1.670ns  (logic 0.860ns (51.509%)  route 0.810ns (48.491%))
  Logic Levels:           3  (DSP_ALU=1 DSP_C_DATA=1 LUT3=1)
  Clock Path Skew:        -0.221ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.560ns = ( 7.513 - 1.953 ) 
    Source Clock Delay      (SCD):    5.550ns
    Clock Pessimism Removal (CPR):    -0.231ns
  Clock Uncertainty:      0.051ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.074ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.282ns (routing 0.858ns, distribution 1.424ns)
  Clock Net Delay (Destination): 1.964ns (routing 0.782ns, distribution 1.182ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.595     3.122    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.995 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.240    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.268 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       2.282     5.550    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/aclk
    SLICE_X81Y56         FDRE                                         r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/dds_ctrl_int_r_reg[509]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y56         FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     5.631 r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/dds_ctrl_int_r_reg[509]/Q
                         net (fo=16, routed)          0.613     6.244    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[2].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/s_axis_phase_tdata[2]
    SLICE_X79Y65         LUT3 (Prop_B6LUT_SLICEM_I0_O)
                                                      0.089     6.333 r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[2].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP_i_27/O
                         net (fo=1, routed)           0.197     6.530    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[2].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/C[5]
    DSP48E2_X13Y26       DSP_C_DATA (Prop_DSP_C_DATA_DSP48E2_C[5]_C_DATA[5])
                                                      0.105     6.635 r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[2].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/DSP_C_DATA_INST/C_DATA[5]
                         net (fo=2, routed)           0.000     6.635    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[2].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/DSP_C_DATA.C_DATA<5>
    DSP48E2_X13Y26       DSP_ALU (Prop_DSP_ALU_DSP48E2_C_DATA[5]_ALU_OUT[11])
                                                      0.585     7.220 r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[2].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/DSP_ALU_INST/ALU_OUT[11]
                         net (fo=1, routed)           0.000     7.220    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[2].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/DSP_ALU.ALU_OUT<11>
    DSP48E2_X13Y26       DSP_OUTPUT                                   r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[2].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/DSP_OUTPUT_INST/ALU_OUT[11]
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      1.953     1.953 r  
    HSADC_X0Y0           HSADC                        0.000     1.953 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     2.075 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     2.225    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.339 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.341     4.680    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.310 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.525    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.549 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.964     7.513    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[2].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/CLK
    DSP48E2_X13Y26       DSP_OUTPUT                                   r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[2].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/DSP_OUTPUT_INST/CLK
                         clock pessimism             -0.231     7.282    
                         clock uncertainty           -0.051     7.230    
    DSP48E2_X13Y26       DSP_OUTPUT (Setup_DSP_OUTPUT_DSP48E2_CLK_ALU_OUT[11])
                                                      0.015     7.245    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[2].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/DSP_OUTPUT_INST
  -------------------------------------------------------------------
                         required time                          7.245    
                         arrival time                          -7.220    
  -------------------------------------------------------------------
                         slack                                  0.026    

Slack (MET) :             0.026ns  (required time - arrival time)
  Source:                 d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/dds_ctrl_int_r_reg[509]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[2].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/DSP_OUTPUT_INST/ALU_OUT[12]
                            (rising edge-triggered cell DSP_OUTPUT clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            1.953ns  (clk_out1_d_1_clk_adc0_x2_0 rise@1.953ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        1.670ns  (logic 0.860ns (51.509%)  route 0.810ns (48.491%))
  Logic Levels:           3  (DSP_ALU=1 DSP_C_DATA=1 LUT3=1)
  Clock Path Skew:        -0.221ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.560ns = ( 7.513 - 1.953 ) 
    Source Clock Delay      (SCD):    5.550ns
    Clock Pessimism Removal (CPR):    -0.231ns
  Clock Uncertainty:      0.051ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.074ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.282ns (routing 0.858ns, distribution 1.424ns)
  Clock Net Delay (Destination): 1.964ns (routing 0.782ns, distribution 1.182ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.595     3.122    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.995 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.240    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.268 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       2.282     5.550    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/aclk
    SLICE_X81Y56         FDRE                                         r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/dds_ctrl_int_r_reg[509]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y56         FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     5.631 r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/dds_ctrl_int_r_reg[509]/Q
                         net (fo=16, routed)          0.613     6.244    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[2].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/s_axis_phase_tdata[2]
    SLICE_X79Y65         LUT3 (Prop_B6LUT_SLICEM_I0_O)
                                                      0.089     6.333 r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[2].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP_i_27/O
                         net (fo=1, routed)           0.197     6.530    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[2].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/C[5]
    DSP48E2_X13Y26       DSP_C_DATA (Prop_DSP_C_DATA_DSP48E2_C[5]_C_DATA[5])
                                                      0.105     6.635 r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[2].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/DSP_C_DATA_INST/C_DATA[5]
                         net (fo=2, routed)           0.000     6.635    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[2].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/DSP_C_DATA.C_DATA<5>
    DSP48E2_X13Y26       DSP_ALU (Prop_DSP_ALU_DSP48E2_C_DATA[5]_ALU_OUT[12])
                                                      0.585     7.220 r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[2].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/DSP_ALU_INST/ALU_OUT[12]
                         net (fo=1, routed)           0.000     7.220    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[2].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/DSP_ALU.ALU_OUT<12>
    DSP48E2_X13Y26       DSP_OUTPUT                                   r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[2].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/DSP_OUTPUT_INST/ALU_OUT[12]
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      1.953     1.953 r  
    HSADC_X0Y0           HSADC                        0.000     1.953 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     2.075 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     2.225    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.339 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.341     4.680    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.310 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.525    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.549 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.964     7.513    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[2].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/CLK
    DSP48E2_X13Y26       DSP_OUTPUT                                   r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[2].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/DSP_OUTPUT_INST/CLK
                         clock pessimism             -0.231     7.282    
                         clock uncertainty           -0.051     7.230    
    DSP48E2_X13Y26       DSP_OUTPUT (Setup_DSP_OUTPUT_DSP48E2_CLK_ALU_OUT[12])
                                                      0.015     7.245    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[2].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/DSP_OUTPUT_INST
  -------------------------------------------------------------------
                         required time                          7.245    
                         arrival time                          -7.220    
  -------------------------------------------------------------------
                         slack                                  0.026    

Slack (MET) :             0.026ns  (required time - arrival time)
  Source:                 d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/dds_ctrl_int_r_reg[509]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[2].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/DSP_OUTPUT_INST/ALU_OUT[13]
                            (rising edge-triggered cell DSP_OUTPUT clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            1.953ns  (clk_out1_d_1_clk_adc0_x2_0 rise@1.953ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        1.670ns  (logic 0.860ns (51.509%)  route 0.810ns (48.491%))
  Logic Levels:           3  (DSP_ALU=1 DSP_C_DATA=1 LUT3=1)
  Clock Path Skew:        -0.221ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.560ns = ( 7.513 - 1.953 ) 
    Source Clock Delay      (SCD):    5.550ns
    Clock Pessimism Removal (CPR):    -0.231ns
  Clock Uncertainty:      0.051ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.074ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.282ns (routing 0.858ns, distribution 1.424ns)
  Clock Net Delay (Destination): 1.964ns (routing 0.782ns, distribution 1.182ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.595     3.122    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.995 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.240    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.268 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       2.282     5.550    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/aclk
    SLICE_X81Y56         FDRE                                         r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/dds_ctrl_int_r_reg[509]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y56         FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     5.631 r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/dds_ctrl_int_r_reg[509]/Q
                         net (fo=16, routed)          0.613     6.244    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[2].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/s_axis_phase_tdata[2]
    SLICE_X79Y65         LUT3 (Prop_B6LUT_SLICEM_I0_O)
                                                      0.089     6.333 r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[2].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP_i_27/O
                         net (fo=1, routed)           0.197     6.530    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[2].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/C[5]
    DSP48E2_X13Y26       DSP_C_DATA (Prop_DSP_C_DATA_DSP48E2_C[5]_C_DATA[5])
                                                      0.105     6.635 r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[2].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/DSP_C_DATA_INST/C_DATA[5]
                         net (fo=2, routed)           0.000     6.635    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[2].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/DSP_C_DATA.C_DATA<5>
    DSP48E2_X13Y26       DSP_ALU (Prop_DSP_ALU_DSP48E2_C_DATA[5]_ALU_OUT[13])
                                                      0.585     7.220 r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[2].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/DSP_ALU_INST/ALU_OUT[13]
                         net (fo=1, routed)           0.000     7.220    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[2].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/DSP_ALU.ALU_OUT<13>
    DSP48E2_X13Y26       DSP_OUTPUT                                   r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[2].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/DSP_OUTPUT_INST/ALU_OUT[13]
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      1.953     1.953 r  
    HSADC_X0Y0           HSADC                        0.000     1.953 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     2.075 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     2.225    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.339 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.341     4.680    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.310 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.525    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.549 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.964     7.513    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[2].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/CLK
    DSP48E2_X13Y26       DSP_OUTPUT                                   r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[2].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/DSP_OUTPUT_INST/CLK
                         clock pessimism             -0.231     7.282    
                         clock uncertainty           -0.051     7.230    
    DSP48E2_X13Y26       DSP_OUTPUT (Setup_DSP_OUTPUT_DSP48E2_CLK_ALU_OUT[13])
                                                      0.015     7.245    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[2].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/DSP_OUTPUT_INST
  -------------------------------------------------------------------
                         required time                          7.245    
                         arrival time                          -7.220    
  -------------------------------------------------------------------
                         slack                                  0.026    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.008ns  (arrival time - required time)
  Source:                 d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_sym_array.g_data_sym[55].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][5]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_sym_array.g_data_sym[49].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[5]_srl6/D
                            (rising edge-triggered cell SRL16E clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.138ns  (logic 0.057ns (41.304%)  route 0.081ns (58.696%))
  Logic Levels:           0  
  Clock Path Skew:        0.101ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.370ns
    Source Clock Delay      (SCD):    5.414ns
    Clock Pessimism Removal (CPR):    -0.144ns
  Clock Net Delay (Source):      1.818ns (routing 0.782ns, distribution 1.036ns)
  Clock Net Delay (Destination): 2.102ns (routing 0.858ns, distribution 1.244ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.341     2.727    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.357 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.572    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.596 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.818     5.414    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_sym_array.g_data_sym[55].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/aclk
    SLICE_X56Y168        FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_sym_array.g_data_sym[55].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X56Y168        FDRE (Prop_FFF_SLICEM_C_Q)
                                                      0.057     5.471 r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_sym_array.g_data_sym[55].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][5]/Q
                         net (fo=1, routed)           0.081     5.552    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_sym_array.g_data_sym[49].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[5]
    SLICE_X56Y170        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_sym_array.g_data_sym[49].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[5]_srl6/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.595     3.122    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.995 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.240    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.268 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       2.102     5.370    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_sym_array.g_data_sym[49].g_data_sym_casc_dly.i_data_sym_casc_dly/aclk
    SLICE_X56Y170        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_sym_array.g_data_sym[49].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[5]_srl6/CLK
                         clock pessimism              0.144     5.515    
    SLICE_X56Y170        SRL16E (Hold_F6LUT_SLICEM_CLK_D)
                                                      0.029     5.544    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_sym_array.g_data_sym[49].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[5]_srl6
  -------------------------------------------------------------------
                         required time                         -5.544    
                         arrival time                           5.552    
  -------------------------------------------------------------------
                         slack                                  0.008    

Slack (MET) :             0.010ns  (arrival time - required time)
  Source:                 d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_sym_array.g_data_sym[55].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][3]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_sym_array.g_data_sym[49].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[3]_srl6/D
                            (rising edge-triggered cell SRL16E clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.138ns  (logic 0.058ns (42.029%)  route 0.080ns (57.971%))
  Logic Levels:           0  
  Clock Path Skew:        0.100ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.370ns
    Source Clock Delay      (SCD):    5.415ns
    Clock Pessimism Removal (CPR):    -0.144ns
  Clock Net Delay (Source):      1.819ns (routing 0.782ns, distribution 1.037ns)
  Clock Net Delay (Destination): 2.102ns (routing 0.858ns, distribution 1.244ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.341     2.727    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.357 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.572    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.596 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.819     5.415    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_sym_array.g_data_sym[55].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/aclk
    SLICE_X56Y168        FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_sym_array.g_data_sym[55].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X56Y168        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.058     5.473 r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_sym_array.g_data_sym[55].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][3]/Q
                         net (fo=1, routed)           0.080     5.553    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_sym_array.g_data_sym[49].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[3]
    SLICE_X56Y170        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_sym_array.g_data_sym[49].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[3]_srl6/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.595     3.122    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.995 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.240    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.268 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       2.102     5.370    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_sym_array.g_data_sym[49].g_data_sym_casc_dly.i_data_sym_casc_dly/aclk
    SLICE_X56Y170        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_sym_array.g_data_sym[49].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[3]_srl6/CLK
                         clock pessimism              0.144     5.515    
    SLICE_X56Y170        SRL16E (Hold_D6LUT_SLICEM_CLK_D)
                                                      0.028     5.543    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_sym_array.g_data_sym[49].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[3]_srl6
  -------------------------------------------------------------------
                         required time                         -5.543    
                         arrival time                           5.553    
  -------------------------------------------------------------------
                         slack                                  0.010    

Slack (MET) :             0.010ns  (arrival time - required time)
  Source:                 d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[10].g_symmetric.g_data_array.g_data[58].g_data_buff.i_data_buf/g_buff.i_buff/gen_reg.d_reg_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[10].g_symmetric.g_data_sym_array.g_data_sym[54].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[1]_srl5/D
                            (rising edge-triggered cell SRL16E clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.157ns  (logic 0.059ns (37.580%)  route 0.098ns (62.420%))
  Logic Levels:           0  
  Clock Path Skew:        0.118ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.418ns
    Source Clock Delay      (SCD):    5.484ns
    Clock Pessimism Removal (CPR):    -0.184ns
  Clock Net Delay (Source):      1.888ns (routing 0.782ns, distribution 1.106ns)
  Clock Net Delay (Destination): 2.150ns (routing 0.858ns, distribution 1.292ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.341     2.727    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.357 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.572    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.596 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.888     5.484    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[10].g_symmetric.g_data_array.g_data[58].g_data_buff.i_data_buf/g_buff.i_buff/aclk
    SLICE_X65Y127        FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[10].g_symmetric.g_data_array.g_data[58].g_data_buff.i_data_buf/g_buff.i_buff/gen_reg.d_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y127        FDRE (Prop_CFF2_SLICEL_C_Q)
                                                      0.059     5.543 r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[10].g_symmetric.g_data_array.g_data[58].g_data_buff.i_data_buf/g_buff.i_buff/gen_reg.d_reg_reg[1]/Q
                         net (fo=1, routed)           0.098     5.641    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[10].g_symmetric.g_data_sym_array.g_data_sym[54].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[1]_0
    SLICE_X66Y128        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[10].g_symmetric.g_data_sym_array.g_data_sym[54].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[1]_srl5/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.595     3.122    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.995 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.240    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.268 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       2.150     5.418    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[10].g_symmetric.g_data_sym_array.g_data_sym[54].g_data_sym_casc_dly.i_data_sym_casc_dly/aclk
    SLICE_X66Y128        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[10].g_symmetric.g_data_sym_array.g_data_sym[54].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[1]_srl5/CLK
                         clock pessimism              0.184     5.602    
    SLICE_X66Y128        SRL16E (Hold_B6LUT_SLICEM_CLK_D)
                                                      0.029     5.631    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[10].g_symmetric.g_data_sym_array.g_data_sym[54].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[1]_srl5
  -------------------------------------------------------------------
                         required time                         -5.631    
                         arrival time                           5.641    
  -------------------------------------------------------------------
                         slack                                  0.010    

Slack (MET) :             0.011ns  (arrival time - required time)
  Source:                 d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[9].g_symmetric.g_data_array.g_data[59].g_data_buff.i_data_buf/g_buff.i_buff/gen_reg.d_reg_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[9].g_symmetric.g_data_sym_array.g_data_sym[53].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6/D
                            (rising edge-triggered cell SRL16E clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.214ns  (logic 0.058ns (27.103%)  route 0.156ns (72.897%))
  Logic Levels:           0  
  Clock Path Skew:        0.171ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.431ns
    Source Clock Delay      (SCD):    5.440ns
    Clock Pessimism Removal (CPR):    -0.180ns
  Clock Net Delay (Source):      1.844ns (routing 0.782ns, distribution 1.062ns)
  Clock Net Delay (Destination): 2.163ns (routing 0.858ns, distribution 1.305ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.341     2.727    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.357 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.572    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.596 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.844     5.440    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[9].g_symmetric.g_data_array.g_data[59].g_data_buff.i_data_buf/g_buff.i_buff/aclk
    SLICE_X59Y13         FDRE                                         r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[9].g_symmetric.g_data_array.g_data[59].g_data_buff.i_data_buf/g_buff.i_buff/gen_reg.d_reg_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X59Y13         FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.058     5.498 r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[9].g_symmetric.g_data_array.g_data[59].g_data_buff.i_data_buf/g_buff.i_buff/gen_reg.d_reg_reg[7]/Q
                         net (fo=1, routed)           0.156     5.654    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[9].g_symmetric.g_data_sym_array.g_data_sym[53].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_0
    SLICE_X61Y14         SRL16E                                       r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[9].g_symmetric.g_data_sym_array.g_data_sym[53].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.595     3.122    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.995 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.240    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.268 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       2.163     5.431    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[9].g_symmetric.g_data_sym_array.g_data_sym[53].g_data_sym_casc_dly.i_data_sym_casc_dly/aclk
    SLICE_X61Y14         SRL16E                                       r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[9].g_symmetric.g_data_sym_array.g_data_sym[53].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6/CLK
                         clock pessimism              0.180     5.611    
    SLICE_X61Y14         SRL16E (Hold_H6LUT_SLICEM_CLK_D)
                                                      0.032     5.643    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[9].g_symmetric.g_data_sym_array.g_data_sym[53].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6
  -------------------------------------------------------------------
                         required time                         -5.643    
                         arrival time                           5.654    
  -------------------------------------------------------------------
                         slack                                  0.011    

Slack (MET) :             0.011ns  (arrival time - required time)
  Source:                 d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_phase[6].phase_v1_r1_reg[6][23]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/dds_ctrl_int_r_reg[487]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.187ns  (logic 0.059ns (31.551%)  route 0.128ns (68.449%))
  Logic Levels:           0  
  Clock Path Skew:        0.114ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.413ns
    Source Clock Delay      (SCD):    5.483ns
    Clock Pessimism Removal (CPR):    -0.184ns
  Clock Net Delay (Source):      1.887ns (routing 0.782ns, distribution 1.105ns)
  Clock Net Delay (Destination): 2.145ns (routing 0.858ns, distribution 1.287ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.341     2.727    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.357 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.572    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.596 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.887     5.483    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/aclk
    SLICE_X68Y150        FDRE                                         r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_phase[6].phase_v1_r1_reg[6][23]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X68Y150        FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.059     5.542 r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_phase[6].phase_v1_r1_reg[6][23]/Q
                         net (fo=1, routed)           0.128     5.670    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_phase[6].phase_v1_r1_reg[6]_17[23]
    SLICE_X68Y145        FDRE                                         r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/dds_ctrl_int_r_reg[487]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.595     3.122    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.995 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.240    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.268 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       2.145     5.413    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/aclk
    SLICE_X68Y145        FDRE                                         r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/dds_ctrl_int_r_reg[487]/C
                         clock pessimism              0.184     5.597    
    SLICE_X68Y145        FDRE (Hold_DFF2_SLICEL_C_D)
                                                      0.062     5.659    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/dds_ctrl_int_r_reg[487]
  -------------------------------------------------------------------
                         required time                         -5.659    
                         arrival time                           5.670    
  -------------------------------------------------------------------
                         slack                                  0.011    

Slack (MET) :             0.011ns  (arrival time - required time)
  Source:                 d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/dds_ctrl_int_r_reg[321]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_common.i_stream_poff_gen.poff_channel_in/opt_has_pipe.first_q_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.288ns  (logic 0.059ns (20.478%)  route 0.229ns (79.522%))
  Logic Levels:           0  
  Clock Path Skew:        0.217ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.456ns
    Source Clock Delay      (SCD):    5.487ns
    Clock Pessimism Removal (CPR):    -0.248ns
  Clock Net Delay (Source):      1.891ns (routing 0.782ns, distribution 1.109ns)
  Clock Net Delay (Destination): 2.188ns (routing 0.858ns, distribution 1.330ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.341     2.727    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.357 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.572    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.596 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.891     5.487    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/aclk
    SLICE_X65Y120        FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/dds_ctrl_int_r_reg[321]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y120        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.059     5.546 r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/dds_ctrl_int_r_reg[321]/Q
                         net (fo=2, routed)           0.229     5.775    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_common.i_stream_poff_gen.poff_channel_in/s_axis_phase_tdata[1]
    SLICE_X74Y116        FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_common.i_stream_poff_gen.poff_channel_in/opt_has_pipe.first_q_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.595     3.122    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.995 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.240    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.268 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       2.188     5.456    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_common.i_stream_poff_gen.poff_channel_in/aclk
    SLICE_X74Y116        FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_common.i_stream_poff_gen.poff_channel_in/opt_has_pipe.first_q_reg[1]/C
                         clock pessimism              0.248     5.704    
    SLICE_X74Y116        FDRE (Hold_EFF_SLICEL_C_D)
                                                      0.060     5.764    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_common.i_stream_poff_gen.poff_channel_in/opt_has_pipe.first_q_reg[1]
  -------------------------------------------------------------------
                         required time                         -5.764    
                         arrival time                           5.775    
  -------------------------------------------------------------------
                         slack                                  0.011    

Slack (MET) :             0.011ns  (arrival time - required time)
  Source:                 d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[0].g_symmetric.g_data_array.g_data[55].g_data_buff.i_data_buf/g_buff.i_buff/gen_reg.d_reg_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[0].g_symmetric.g_data_sym_array.g_data_sym[57].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl2/D
                            (rising edge-triggered cell SRL16E clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.126ns  (logic 0.059ns (46.825%)  route 0.067ns (53.175%))
  Logic Levels:           0  
  Clock Path Skew:        0.083ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.458ns
    Source Clock Delay      (SCD):    5.501ns
    Clock Pessimism Removal (CPR):    -0.125ns
  Clock Net Delay (Source):      1.905ns (routing 0.782ns, distribution 1.123ns)
  Clock Net Delay (Destination): 2.190ns (routing 0.858ns, distribution 1.332ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.341     2.727    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.357 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.572    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.596 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.905     5.501    d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[0].g_symmetric.g_data_array.g_data[55].g_data_buff.i_data_buf/g_buff.i_buff/aclk
    SLICE_X36Y142        FDRE                                         r  d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[0].g_symmetric.g_data_array.g_data[55].g_data_buff.i_data_buf/g_buff.i_buff/gen_reg.d_reg_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X36Y142        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.059     5.560 r  d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[0].g_symmetric.g_data_array.g_data[55].g_data_buff.i_data_buf/g_buff.i_buff/gen_reg.d_reg_reg[7]/Q
                         net (fo=1, routed)           0.067     5.627    d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[0].g_symmetric.g_data_sym_array.g_data_sym[57].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_0
    SLICE_X35Y142        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[0].g_symmetric.g_data_sym_array.g_data_sym[57].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl2/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.595     3.122    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.995 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.240    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.268 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       2.190     5.458    d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[0].g_symmetric.g_data_sym_array.g_data_sym[57].g_data_sym_casc_dly.i_data_sym_casc_dly/aclk
    SLICE_X35Y142        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[0].g_symmetric.g_data_sym_array.g_data_sym[57].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl2/CLK
                         clock pessimism              0.125     5.584    
    SLICE_X35Y142        SRL16E (Hold_H6LUT_SLICEM_CLK_D)
                                                      0.032     5.616    d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[0].g_symmetric.g_data_sym_array.g_data_sym[57].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl2
  -------------------------------------------------------------------
                         required time                         -5.616    
                         arrival time                           5.627    
  -------------------------------------------------------------------
                         slack                                  0.011    

Slack (MET) :             0.012ns  (arrival time - required time)
  Source:                 d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[8].g_symmetric.g_data_sym_array.g_data_sym[51].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][7]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[8].g_symmetric.g_data_sym_array.g_data_sym[45].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6/D
                            (rising edge-triggered cell SRL16E clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.130ns  (logic 0.058ns (44.615%)  route 0.072ns (55.385%))
  Logic Levels:           0  
  Clock Path Skew:        0.086ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.455ns
    Source Clock Delay      (SCD):    5.502ns
    Clock Pessimism Removal (CPR):    -0.133ns
  Clock Net Delay (Source):      1.906ns (routing 0.782ns, distribution 1.124ns)
  Clock Net Delay (Destination): 2.187ns (routing 0.858ns, distribution 1.329ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.341     2.727    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.357 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.572    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.596 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.906     5.502    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[8].g_symmetric.g_data_sym_array.g_data_sym[51].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/aclk
    SLICE_X67Y144        FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[8].g_symmetric.g_data_sym_array.g_data_sym[51].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X67Y144        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.058     5.560 r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[8].g_symmetric.g_data_sym_array.g_data_sym[51].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][7]/Q
                         net (fo=1, routed)           0.072     5.632    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[8].g_symmetric.g_data_sym_array.g_data_sym[45].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]
    SLICE_X67Y145        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[8].g_symmetric.g_data_sym_array.g_data_sym[45].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.595     3.122    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.995 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.240    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.268 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       2.187     5.455    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[8].g_symmetric.g_data_sym_array.g_data_sym[45].g_data_sym_casc_dly.i_data_sym_casc_dly/aclk
    SLICE_X67Y145        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[8].g_symmetric.g_data_sym_array.g_data_sym[45].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6/CLK
                         clock pessimism              0.133     5.588    
    SLICE_X67Y145        SRL16E (Hold_H6LUT_SLICEM_CLK_D)
                                                      0.032     5.620    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[8].g_symmetric.g_data_sym_array.g_data_sym[45].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6
  -------------------------------------------------------------------
                         required time                         -5.620    
                         arrival time                           5.632    
  -------------------------------------------------------------------
                         slack                                  0.012    

Slack (MET) :             0.012ns  (arrival time - required time)
  Source:                 d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[3].g_symmetric.g_data_array.g_data[6].g_data_buff.i_data_buf/g_buff.i_buff/gen_reg.d_reg_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[3].g_symmetric.g_data_array.g_data[14].i_data_casc_dly/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[31][7]_srl32/D
                            (rising edge-triggered cell SRLC32E clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.114ns  (logic 0.039ns (34.116%)  route 0.075ns (65.884%))
  Logic Levels:           0  
  Clock Path Skew:        0.040ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.140ns
    Source Clock Delay      (SCD):    3.220ns
    Clock Pessimism Removal (CPR):    -0.120ns
  Clock Net Delay (Source):      1.149ns (routing 0.470ns, distribution 0.679ns)
  Clock Net Delay (Destination): 1.315ns (routing 0.521ns, distribution 0.794ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.415     1.678    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.908 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.054    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.071 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.149     3.220    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[3].g_symmetric.g_data_array.g_data[6].g_data_buff.i_data_buf/g_buff.i_buff/aclk
    SLICE_X55Y267        FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[3].g_symmetric.g_data_array.g_data[6].g_data_buff.i_data_buf/g_buff.i_buff/gen_reg.d_reg_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X55Y267        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.039     3.259 r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[3].g_symmetric.g_data_array.g_data[6].g_data_buff.i_data_buf/g_buff.i_buff/gen_reg.d_reg_reg[7]/Q
                         net (fo=2, routed)           0.075     3.334    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[3].g_symmetric.g_data_array.g_data[14].i_data_casc_dly/g_parallel.g_paths[3].data_casc[7]_150[7]
    SLICE_X54Y267        SRLC32E                                      r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[3].g_symmetric.g_data_array.g_data[14].i_data_casc_dly/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[31][7]_srl32/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.583     1.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.640 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.806    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.825 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.315     3.140    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[3].g_symmetric.g_data_array.g_data[14].i_data_casc_dly/aclk
    SLICE_X54Y267        SRLC32E                                      r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[3].g_symmetric.g_data_array.g_data[14].i_data_casc_dly/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[31][7]_srl32/CLK
                         clock pessimism              0.120     3.260    
    SLICE_X54Y267        SRLC32E (Hold_H6LUT_SLICEM_CLK_D)
                                                      0.062     3.322    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[3].g_symmetric.g_data_array.g_data[14].i_data_casc_dly/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[31][7]_srl32
  -------------------------------------------------------------------
                         required time                         -3.322    
                         arrival time                           3.334    
  -------------------------------------------------------------------
                         slack                                  0.012    

Slack (MET) :             0.012ns  (arrival time - required time)
  Source:                 d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[11].g_symmetric.g_data_sym_array.g_data_sym[44].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][7]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[11].g_symmetric.g_data_sym_array.g_data_sym[38].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6/D
                            (rising edge-triggered cell SRL16E clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.130ns  (logic 0.058ns (44.615%)  route 0.072ns (55.385%))
  Logic Levels:           0  
  Clock Path Skew:        0.086ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.406ns
    Source Clock Delay      (SCD):    5.459ns
    Clock Pessimism Removal (CPR):    -0.138ns
  Clock Net Delay (Source):      1.863ns (routing 0.782ns, distribution 1.081ns)
  Clock Net Delay (Destination): 2.138ns (routing 0.858ns, distribution 1.280ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.341     2.727    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.357 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.572    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.596 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.863     5.459    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[11].g_symmetric.g_data_sym_array.g_data_sym[44].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/aclk
    SLICE_X53Y192        FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[11].g_symmetric.g_data_sym_array.g_data_sym[44].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X53Y192        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.058     5.517 r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[11].g_symmetric.g_data_sym_array.g_data_sym[44].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][7]/Q
                         net (fo=1, routed)           0.072     5.589    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[11].g_symmetric.g_data_sym_array.g_data_sym[38].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]
    SLICE_X53Y193        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[11].g_symmetric.g_data_sym_array.g_data_sym[38].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.595     3.122    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.995 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.240    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.268 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       2.138     5.406    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[11].g_symmetric.g_data_sym_array.g_data_sym[38].g_data_sym_casc_dly.i_data_sym_casc_dly/aclk
    SLICE_X53Y193        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[11].g_symmetric.g_data_sym_array.g_data_sym[38].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6/CLK
                         clock pessimism              0.138     5.544    
    SLICE_X53Y193        SRL16E (Hold_H6LUT_SLICEM_CLK_D)
                                                      0.032     5.576    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[11].g_symmetric.g_data_sym_array.g_data_sym[38].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6
  -------------------------------------------------------------------
                         required time                         -5.576    
                         arrival time                           5.589    
  -------------------------------------------------------------------
                         slack                                  0.012    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         clk_out1_d_1_clk_adc0_x2_0
Waveform(ns):       { 0.000 0.976 }
Period(ns):         1.953
Sources:            { d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0 }

Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location      Pin
Min Period        n/a     HSADC/FABRIC_CLK    n/a            1.923         1.953       0.030      HSADC_X0Y0    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/FABRIC_CLK
Min Period        n/a     HSADC/FABRIC_CLK    n/a            1.923         1.953       0.030      HSADC_X0Y2    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/FABRIC_CLK
Min Period        n/a     RAMB36E2/CLKARDCLK  n/a            1.355         1.953       0.598      RAMB36_X7Y38  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_0/CLKARDCLK
Min Period        n/a     RAMB36E2/CLKARDCLK  n/a            1.355         1.953       0.598      RAMB36_X7Y39  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_1/CLKARDCLK
Min Period        n/a     RAMB36E2/CLKARDCLK  n/a            1.355         1.953       0.598      RAMB36_X7Y32  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_10/CLKARDCLK
Min Period        n/a     RAMB36E2/CLKARDCLK  n/a            1.355         1.953       0.598      RAMB36_X7Y33  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_11/CLKARDCLK
Min Period        n/a     RAMB36E2/CLKARDCLK  n/a            1.355         1.953       0.598      RAMB36_X7Y34  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_12/CLKARDCLK
Min Period        n/a     RAMB36E2/CLKARDCLK  n/a            1.355         1.953       0.598      RAMB36_X7Y35  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_13/CLKARDCLK
Min Period        n/a     RAMB36E2/CLKARDCLK  n/a            1.355         1.953       0.598      RAMB36_X7Y36  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_14/CLKARDCLK
Min Period        n/a     RAMB36E2/CLKARDCLK  n/a            1.355         1.953       0.598      RAMB36_X7Y37  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_15/CLKARDCLK
Low Pulse Width   Slow    HSADC/FABRIC_CLK    n/a            0.800         0.976       0.176      HSADC_X0Y0    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/FABRIC_CLK
Low Pulse Width   Fast    HSADC/FABRIC_CLK    n/a            0.800         0.977       0.177      HSADC_X0Y0    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/FABRIC_CLK
Low Pulse Width   Slow    HSADC/FABRIC_CLK    n/a            0.800         0.977       0.177      HSADC_X0Y2    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/FABRIC_CLK
Low Pulse Width   Fast    HSADC/FABRIC_CLK    n/a            0.800         0.976       0.176      HSADC_X0Y2    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/FABRIC_CLK
Low Pulse Width   Slow    RAMB36E2/CLKARDCLK  n/a            0.542         0.977       0.435      RAMB36_X7Y38  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_0/CLKARDCLK
Low Pulse Width   Fast    RAMB36E2/CLKARDCLK  n/a            0.542         0.977       0.435      RAMB36_X7Y38  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_0/CLKARDCLK
Low Pulse Width   Slow    RAMB36E2/CLKARDCLK  n/a            0.542         0.977       0.435      RAMB36_X7Y39  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_1/CLKARDCLK
Low Pulse Width   Fast    RAMB36E2/CLKARDCLK  n/a            0.542         0.976       0.434      RAMB36_X7Y39  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_1/CLKARDCLK
Low Pulse Width   Slow    RAMB36E2/CLKARDCLK  n/a            0.542         0.976       0.434      RAMB36_X7Y32  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_10/CLKARDCLK
Low Pulse Width   Fast    RAMB36E2/CLKARDCLK  n/a            0.542         0.976       0.434      RAMB36_X7Y32  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_10/CLKARDCLK
High Pulse Width  Slow    HSADC/FABRIC_CLK    n/a            0.800         0.976       0.176      HSADC_X0Y0    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/FABRIC_CLK
High Pulse Width  Fast    HSADC/FABRIC_CLK    n/a            0.800         0.976       0.176      HSADC_X0Y0    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/FABRIC_CLK
High Pulse Width  Slow    HSADC/FABRIC_CLK    n/a            0.800         0.976       0.176      HSADC_X0Y2    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/FABRIC_CLK
High Pulse Width  Fast    HSADC/FABRIC_CLK    n/a            0.800         0.976       0.176      HSADC_X0Y2    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/FABRIC_CLK
High Pulse Width  Slow    RAMB36E2/CLKARDCLK  n/a            0.542         0.976       0.434      RAMB36_X7Y38  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_0/CLKARDCLK
High Pulse Width  Fast    RAMB36E2/CLKARDCLK  n/a            0.542         0.976       0.434      RAMB36_X7Y38  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_0/CLKARDCLK
High Pulse Width  Slow    RAMB36E2/CLKARDCLK  n/a            0.542         0.976       0.434      RAMB36_X7Y39  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_1/CLKARDCLK
High Pulse Width  Fast    RAMB36E2/CLKARDCLK  n/a            0.542         0.976       0.434      RAMB36_X7Y39  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_1/CLKARDCLK
High Pulse Width  Slow    RAMB36E2/CLKARDCLK  n/a            0.542         0.976       0.434      RAMB36_X7Y32  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_10/CLKARDCLK
High Pulse Width  Fast    RAMB36E2/CLKARDCLK  n/a            0.542         0.976       0.434      RAMB36_X7Y32  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_10/CLKARDCLK



---------------------------------------------------------------------------------------------------
From Clock:  RFDAC0_CLK
  To Clock:  RFDAC0_CLK

Setup :            0  Failing Endpoints,  Worst Slack        0.027ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.010ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        0.391ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.027ns  (required time - arrival time)
  Source:                 d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_r2_reg[26]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[11].phase_v0_r2_reg[11][28]_srl2___inst_signal_gen_top_i_signal_gen_i_ctrl_i_en_reg_r2_reg_r/D
                            (rising edge-triggered cell SRL16E clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.604ns  (RFDAC0_CLK rise@2.604ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        2.345ns  (logic 0.480ns (20.466%)  route 1.865ns (79.534%))
  Logic Levels:           3  (CARRY8=1 LUT3=1 LUT4=1)
  Clock Path Skew:        -0.121ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.349ns = ( 5.953 - 2.604 ) 
    Source Clock Delay      (SCD):    3.751ns
    Clock Pessimism Removal (CPR):    0.281ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.078ns (routing 1.381ns, distribution 1.697ns)
  Clock Net Delay (Destination): 2.828ns (routing 1.256ns, distribution 1.572ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       3.078     3.751    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X105Y231       FDRE                                         r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_r2_reg[26]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X105Y231       FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.079     3.830 f  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_r2_reg[26]/Q
                         net (fo=42, routed)          1.271     5.101    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_N[30]
    SLICE_X108Y165       LUT3 (Prop_C5LUT_SLICEL_I2_O)
                                                      0.158     5.259 r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v0[11]_carry__2_i_4/O
                         net (fo=2, routed)           0.166     5.425    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v0[11]_carry__2_i_4_n_0
    SLICE_X108Y165       LUT4 (Prop_D6LUT_SLICEL_I3_O)
                                                      0.099     5.524 r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v0[11]_carry__2_i_12/O
                         net (fo=1, routed)           0.009     5.533    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v0[11]_carry__2_i_12_n_0
    SLICE_X108Y165       CARRY8 (Prop_CARRY8_SLICEL_S[3]_O[4])
                                                      0.144     5.677 r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v0[11]_carry__2/O[4]
                         net (fo=1, routed)           0.419     6.096    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v0[11]_88[28]
    SLICE_X109Y164       SRL16E                                       r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[11].phase_v0_r2_reg[11][28]_srl2___inst_signal_gen_top_i_signal_gen_i_ctrl_i_en_reg_r2_reg_r/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      2.604     2.604 r  
    HSDAC_X0Y0           HSDAC                        0.000     2.604 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.885 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     3.011    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     3.125 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       2.828     5.953    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X109Y164       SRL16E                                       r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[11].phase_v0_r2_reg[11][28]_srl2___inst_signal_gen_top_i_signal_gen_i_ctrl_i_en_reg_r2_reg_r/CLK
                         clock pessimism              0.281     6.234    
                         clock uncertainty           -0.035     6.199    
    SLICE_X109Y164       SRL16E (Setup_D5LUT_SLICEM_CLK_D)
                                                     -0.075     6.124    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[11].phase_v0_r2_reg[11][28]_srl2___inst_signal_gen_top_i_signal_gen_i_ctrl_i_en_reg_r2_reg_r
  -------------------------------------------------------------------
                         required time                          6.124    
                         arrival time                          -6.096    
  -------------------------------------------------------------------
                         slack                                  0.027    

Slack (MET) :             0.046ns  (required time - arrival time)
  Source:                 d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_18/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[2].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1/ENARDEN
                            (rising edge-triggered cell RAMB36E2 clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.604ns  (RFDAC0_CLK rise@2.604ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        2.186ns  (logic 0.079ns (3.615%)  route 2.107ns (96.385%))
  Logic Levels:           0  
  Clock Path Skew:        0.005ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.323ns = ( 5.927 - 2.604 ) 
    Source Clock Delay      (SCD):    3.749ns
    Clock Pessimism Removal (CPR):    0.431ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.076ns (routing 1.381ns, distribution 1.695ns)
  Clock Net Delay (Destination): 2.802ns (routing 1.256ns, distribution 1.546ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       3.076     3.749    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X106Y172       FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_18/C
  -------------------------------------------------------------------    -------------------
    SLICE_X106Y172       FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     3.828 r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_18/Q
                         net (fo=277, routed)         2.107     5.935    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[2].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/dds_tvalid_r_repN_18_alias
    RAMB36_X10Y31        RAMB36E2                                     r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[2].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1/ENARDEN
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      2.604     2.604 r  
    HSDAC_X0Y0           HSDAC                        0.000     2.604 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.885 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     3.011    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     3.125 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       2.802     5.927    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[2].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/aclk
    RAMB36_X10Y31        RAMB36E2                                     r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[2].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1/CLKARDCLK
                         clock pessimism              0.431     6.358    
                         clock uncertainty           -0.035     6.322    
    RAMB36_X10Y31        RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_ENARDEN)
                                                     -0.342     5.980    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[2].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1
  -------------------------------------------------------------------
                         required time                          5.980    
                         arrival time                          -5.935    
  -------------------------------------------------------------------
                         slack                                  0.046    

Slack (MET) :             0.046ns  (required time - arrival time)
  Source:                 d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_18/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[14].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_phase_final_speedup/opt_has_pipe.first_q_reg[27]/CE
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.604ns  (RFDAC0_CLK rise@2.604ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        2.384ns  (logic 0.079ns (3.314%)  route 2.305ns (96.686%))
  Logic Levels:           0  
  Clock Path Skew:        -0.078ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.289ns = ( 5.893 - 2.604 ) 
    Source Clock Delay      (SCD):    3.749ns
    Clock Pessimism Removal (CPR):    0.382ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.076ns (routing 1.381ns, distribution 1.695ns)
  Clock Net Delay (Destination): 2.768ns (routing 1.256ns, distribution 1.512ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       3.076     3.749    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X106Y172       FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_18/C
  -------------------------------------------------------------------    -------------------
    SLICE_X106Y172       FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     3.828 r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_18/Q
                         net (fo=277, routed)         2.305     6.133    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[14].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_phase_final_speedup/dds_tvalid_r_repN_18_alias
    SLICE_X107Y152       FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[14].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_phase_final_speedup/opt_has_pipe.first_q_reg[27]/CE
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      2.604     2.604 r  
    HSDAC_X0Y0           HSDAC                        0.000     2.604 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.885 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     3.011    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     3.125 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       2.768     5.893    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[14].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_phase_final_speedup/aclk
    SLICE_X107Y152       FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[14].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_phase_final_speedup/opt_has_pipe.first_q_reg[27]/C
                         clock pessimism              0.382     6.275    
                         clock uncertainty           -0.035     6.240    
    SLICE_X107Y152       FDRE (Setup_EFF2_SLICEM_C_CE)
                                                     -0.061     6.179    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[14].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_phase_final_speedup/opt_has_pipe.first_q_reg[27]
  -------------------------------------------------------------------
                         required time                          6.179    
                         arrival time                          -6.133    
  -------------------------------------------------------------------
                         slack                                  0.046    

Slack (MET) :             0.046ns  (required time - arrival time)
  Source:                 d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_18/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[14].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[1]/CE
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.604ns  (RFDAC0_CLK rise@2.604ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        2.384ns  (logic 0.079ns (3.314%)  route 2.305ns (96.686%))
  Logic Levels:           0  
  Clock Path Skew:        -0.078ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.289ns = ( 5.893 - 2.604 ) 
    Source Clock Delay      (SCD):    3.749ns
    Clock Pessimism Removal (CPR):    0.382ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.076ns (routing 1.381ns, distribution 1.695ns)
  Clock Net Delay (Destination): 2.768ns (routing 1.256ns, distribution 1.512ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       3.076     3.749    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X106Y172       FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_18/C
  -------------------------------------------------------------------    -------------------
    SLICE_X106Y172       FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     3.828 r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_18/Q
                         net (fo=277, routed)         2.305     6.133    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[14].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/dds_tvalid_r_repN_18_alias
    SLICE_X107Y152       FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[14].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[1]/CE
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      2.604     2.604 r  
    HSDAC_X0Y0           HSDAC                        0.000     2.604 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.885 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     3.011    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     3.125 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       2.768     5.893    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[14].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/aclk
    SLICE_X107Y152       FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[14].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[1]/C
                         clock pessimism              0.382     6.275    
                         clock uncertainty           -0.035     6.240    
    SLICE_X107Y152       FDRE (Setup_FFF2_SLICEM_C_CE)
                                                     -0.061     6.179    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[14].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[1]
  -------------------------------------------------------------------
                         required time                          6.179    
                         arrival time                          -6.133    
  -------------------------------------------------------------------
                         slack                                  0.046    

Slack (MET) :             0.046ns  (required time - arrival time)
  Source:                 d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_18/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[14].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_rom_reg_b/opt_has_pipe.first_q_reg[6]/CE
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.604ns  (RFDAC0_CLK rise@2.604ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        2.384ns  (logic 0.079ns (3.314%)  route 2.305ns (96.686%))
  Logic Levels:           0  
  Clock Path Skew:        -0.078ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.289ns = ( 5.893 - 2.604 ) 
    Source Clock Delay      (SCD):    3.749ns
    Clock Pessimism Removal (CPR):    0.382ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.076ns (routing 1.381ns, distribution 1.695ns)
  Clock Net Delay (Destination): 2.768ns (routing 1.256ns, distribution 1.512ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       3.076     3.749    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X106Y172       FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_18/C
  -------------------------------------------------------------------    -------------------
    SLICE_X106Y172       FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     3.828 r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_18/Q
                         net (fo=277, routed)         2.305     6.133    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[14].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_rom_reg_b/dds_tvalid_r_repN_18_alias
    SLICE_X107Y152       FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[14].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_rom_reg_b/opt_has_pipe.first_q_reg[6]/CE
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      2.604     2.604 r  
    HSDAC_X0Y0           HSDAC                        0.000     2.604 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.885 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     3.011    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     3.125 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       2.768     5.893    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[14].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_rom_reg_b/aclk
    SLICE_X107Y152       FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[14].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_rom_reg_b/opt_has_pipe.first_q_reg[6]/C
                         clock pessimism              0.382     6.275    
                         clock uncertainty           -0.035     6.240    
    SLICE_X107Y152       FDRE (Setup_GFF2_SLICEM_C_CE)
                                                     -0.061     6.179    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[14].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_rom_reg_b/opt_has_pipe.first_q_reg[6]
  -------------------------------------------------------------------
                         required time                          6.179    
                         arrival time                          -6.133    
  -------------------------------------------------------------------
                         slack                                  0.046    

Slack (MET) :             0.048ns  (required time - arrival time)
  Source:                 d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_18/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[14].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_phase_final_speedup/opt_has_pipe.first_q_reg[26]/CE
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.604ns  (RFDAC0_CLK rise@2.604ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        2.382ns  (logic 0.079ns (3.316%)  route 2.303ns (96.684%))
  Logic Levels:           0  
  Clock Path Skew:        -0.078ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.289ns = ( 5.893 - 2.604 ) 
    Source Clock Delay      (SCD):    3.749ns
    Clock Pessimism Removal (CPR):    0.382ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.076ns (routing 1.381ns, distribution 1.695ns)
  Clock Net Delay (Destination): 2.768ns (routing 1.256ns, distribution 1.512ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       3.076     3.749    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X106Y172       FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_18/C
  -------------------------------------------------------------------    -------------------
    SLICE_X106Y172       FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     3.828 r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_18/Q
                         net (fo=277, routed)         2.303     6.131    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[14].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_phase_final_speedup/dds_tvalid_r_repN_18_alias
    SLICE_X107Y152       FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[14].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_phase_final_speedup/opt_has_pipe.first_q_reg[26]/CE
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      2.604     2.604 r  
    HSDAC_X0Y0           HSDAC                        0.000     2.604 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.885 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     3.011    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     3.125 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       2.768     5.893    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[14].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_phase_final_speedup/aclk
    SLICE_X107Y152       FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[14].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_phase_final_speedup/opt_has_pipe.first_q_reg[26]/C
                         clock pessimism              0.382     6.275    
                         clock uncertainty           -0.035     6.240    
    SLICE_X107Y152       FDRE (Setup_EFF_SLICEM_C_CE)
                                                     -0.061     6.179    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[14].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_phase_final_speedup/opt_has_pipe.first_q_reg[26]
  -------------------------------------------------------------------
                         required time                          6.179    
                         arrival time                          -6.131    
  -------------------------------------------------------------------
                         slack                                  0.048    

Slack (MET) :             0.048ns  (required time - arrival time)
  Source:                 d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_18/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[14].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[0]/CE
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.604ns  (RFDAC0_CLK rise@2.604ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        2.382ns  (logic 0.079ns (3.316%)  route 2.303ns (96.684%))
  Logic Levels:           0  
  Clock Path Skew:        -0.078ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.289ns = ( 5.893 - 2.604 ) 
    Source Clock Delay      (SCD):    3.749ns
    Clock Pessimism Removal (CPR):    0.382ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.076ns (routing 1.381ns, distribution 1.695ns)
  Clock Net Delay (Destination): 2.768ns (routing 1.256ns, distribution 1.512ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       3.076     3.749    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X106Y172       FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_18/C
  -------------------------------------------------------------------    -------------------
    SLICE_X106Y172       FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     3.828 r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_18/Q
                         net (fo=277, routed)         2.303     6.131    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[14].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/dds_tvalid_r_repN_18_alias
    SLICE_X107Y152       FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[14].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[0]/CE
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      2.604     2.604 r  
    HSDAC_X0Y0           HSDAC                        0.000     2.604 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.885 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     3.011    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     3.125 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       2.768     5.893    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[14].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/aclk
    SLICE_X107Y152       FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[14].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[0]/C
                         clock pessimism              0.382     6.275    
                         clock uncertainty           -0.035     6.240    
    SLICE_X107Y152       FDRE (Setup_HFF_SLICEM_C_CE)
                                                     -0.061     6.179    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[14].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[0]
  -------------------------------------------------------------------
                         required time                          6.179    
                         arrival time                          -6.131    
  -------------------------------------------------------------------
                         slack                                  0.048    

Slack (MET) :             0.048ns  (required time - arrival time)
  Source:                 d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_18/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[14].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[1]/CE
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.604ns  (RFDAC0_CLK rise@2.604ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        2.382ns  (logic 0.079ns (3.316%)  route 2.303ns (96.684%))
  Logic Levels:           0  
  Clock Path Skew:        -0.078ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.289ns = ( 5.893 - 2.604 ) 
    Source Clock Delay      (SCD):    3.749ns
    Clock Pessimism Removal (CPR):    0.382ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.076ns (routing 1.381ns, distribution 1.695ns)
  Clock Net Delay (Destination): 2.768ns (routing 1.256ns, distribution 1.512ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       3.076     3.749    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X106Y172       FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_18/C
  -------------------------------------------------------------------    -------------------
    SLICE_X106Y172       FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     3.828 r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_18/Q
                         net (fo=277, routed)         2.303     6.131    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[14].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/dds_tvalid_r_repN_18_alias
    SLICE_X107Y152       FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[14].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[1]/CE
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      2.604     2.604 r  
    HSDAC_X0Y0           HSDAC                        0.000     2.604 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.885 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     3.011    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     3.125 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       2.768     5.893    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[14].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/aclk
    SLICE_X107Y152       FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[14].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[1]/C
                         clock pessimism              0.382     6.275    
                         clock uncertainty           -0.035     6.240    
    SLICE_X107Y152       FDRE (Setup_GFF_SLICEM_C_CE)
                                                     -0.061     6.179    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[14].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[1]
  -------------------------------------------------------------------
                         required time                          6.179    
                         arrival time                          -6.131    
  -------------------------------------------------------------------
                         slack                                  0.048    

Slack (MET) :             0.048ns  (required time - arrival time)
  Source:                 d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_18/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[14].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[0]/CE
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.604ns  (RFDAC0_CLK rise@2.604ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        2.382ns  (logic 0.079ns (3.316%)  route 2.303ns (96.684%))
  Logic Levels:           0  
  Clock Path Skew:        -0.078ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.289ns = ( 5.893 - 2.604 ) 
    Source Clock Delay      (SCD):    3.749ns
    Clock Pessimism Removal (CPR):    0.382ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.076ns (routing 1.381ns, distribution 1.695ns)
  Clock Net Delay (Destination): 2.768ns (routing 1.256ns, distribution 1.512ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       3.076     3.749    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X106Y172       FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_18/C
  -------------------------------------------------------------------    -------------------
    SLICE_X106Y172       FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     3.828 r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_18/Q
                         net (fo=277, routed)         2.303     6.131    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[14].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/dds_tvalid_r_repN_18_alias
    SLICE_X107Y152       FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[14].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[0]/CE
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      2.604     2.604 r  
    HSDAC_X0Y0           HSDAC                        0.000     2.604 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.885 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     3.011    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     3.125 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       2.768     5.893    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[14].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/aclk
    SLICE_X107Y152       FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[14].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[0]/C
                         clock pessimism              0.382     6.275    
                         clock uncertainty           -0.035     6.240    
    SLICE_X107Y152       FDRE (Setup_FFF_SLICEM_C_CE)
                                                     -0.061     6.179    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[14].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[0]
  -------------------------------------------------------------------
                         required time                          6.179    
                         arrival time                          -6.131    
  -------------------------------------------------------------------
                         slack                                  0.048    

Slack (MET) :             0.050ns  (required time - arrival time)
  Source:                 d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_18/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[10].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_rom_reg_b/opt_has_pipe.first_q_reg[6]/CE
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.604ns  (RFDAC0_CLK rise@2.604ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        2.381ns  (logic 0.079ns (3.318%)  route 2.302ns (96.682%))
  Logic Levels:           0  
  Clock Path Skew:        -0.077ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.290ns = ( 5.894 - 2.604 ) 
    Source Clock Delay      (SCD):    3.749ns
    Clock Pessimism Removal (CPR):    0.382ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.076ns (routing 1.381ns, distribution 1.695ns)
  Clock Net Delay (Destination): 2.769ns (routing 1.256ns, distribution 1.513ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       3.076     3.749    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X106Y172       FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_18/C
  -------------------------------------------------------------------    -------------------
    SLICE_X106Y172       FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     3.828 r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_18/Q
                         net (fo=277, routed)         2.302     6.130    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[10].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_rom_reg_b/dds_tvalid_r_repN_18_alias
    SLICE_X107Y152       FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[10].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_rom_reg_b/opt_has_pipe.first_q_reg[6]/CE
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      2.604     2.604 r  
    HSDAC_X0Y0           HSDAC                        0.000     2.604 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.885 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     3.011    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     3.125 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       2.769     5.894    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[10].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_rom_reg_b/aclk
    SLICE_X107Y152       FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[10].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_rom_reg_b/opt_has_pipe.first_q_reg[6]/C
                         clock pessimism              0.382     6.276    
                         clock uncertainty           -0.035     6.241    
    SLICE_X107Y152       FDRE (Setup_AFF_SLICEM_C_CE)
                                                     -0.061     6.180    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[10].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_rom_reg_b/opt_has_pipe.first_q_reg[6]
  -------------------------------------------------------------------
                         required time                          6.180    
                         arrival time                          -6.130    
  -------------------------------------------------------------------
                         slack                                  0.050    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.010ns  (arrival time - required time)
  Source:                 d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[4].phase_v1_r1_reg[4][3]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[323]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC0_CLK rise@0.000ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        0.167ns  (logic 0.059ns (35.329%)  route 0.108ns (64.671%))
  Logic Levels:           0  
  Clock Path Skew:        0.097ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.790ns
    Source Clock Delay      (SCD):    3.309ns
    Clock Pessimism Removal (CPR):    0.383ns
  Clock Net Delay (Source):      2.788ns (routing 1.256ns, distribution 1.532ns)
  Clock Net Delay (Destination): 3.117ns (routing 1.381ns, distribution 1.736ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       2.788     3.309    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X101Y257       FDRE                                         r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[4].phase_v1_r1_reg[4][3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y257       FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.059     3.368 r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[4].phase_v1_r1_reg[4][3]/Q
                         net (fo=1, routed)           0.108     3.476    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int[323]
    SLICE_X100Y256       FDRE                                         r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[323]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       3.117     3.790    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X100Y256       FDRE                                         r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[323]/C
                         clock pessimism             -0.383     3.407    
    SLICE_X100Y256       FDRE (Hold_EFF_SLICEL_C_D)
                                                      0.060     3.467    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[323]
  -------------------------------------------------------------------
                         required time                         -3.467    
                         arrival time                           3.476    
  -------------------------------------------------------------------
                         slack                                  0.010    

Slack (MET) :             0.011ns  (arrival time - required time)
  Source:                 d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/GEN_dds[10].mem_real_latency_reg_i/GEN_reg[7].shift_r_reg[7][1]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/GEN_dds[10].mem_mux_latency_reg_i/shift_r_reg[0][1]_srl3___inst_signal_gen_top_i_signal_gen_i_ctrl_i_en_reg_r3_reg_r/D
                            (rising edge-triggered cell SRL16E clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC0_CLK rise@0.000ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        0.260ns  (logic 0.060ns (23.101%)  route 0.200ns (76.899%))
  Logic Levels:           0  
  Clock Path Skew:        0.220ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.644ns
    Source Clock Delay      (SCD):    3.056ns
    Clock Pessimism Removal (CPR):    0.369ns
  Clock Net Delay (Source):      2.535ns (routing 1.256ns, distribution 1.279ns)
  Clock Net Delay (Destination): 2.971ns (routing 1.381ns, distribution 1.590ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       2.535     3.056    d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/GEN_dds[10].mem_real_latency_reg_i/aclk
    SLICE_X58Y369        FDRE                                         r  d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/GEN_dds[10].mem_real_latency_reg_i/GEN_reg[7].shift_r_reg[7][1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X58Y369        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.060     3.116 r  d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/GEN_dds[10].mem_real_latency_reg_i/GEN_reg[7].shift_r_reg[7][1]/Q
                         net (fo=2, routed)           0.200     3.316    d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/GEN_dds[10].mem_mux_latency_reg_i/B[1]
    SLICE_X63Y369        SRL16E                                       r  d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/GEN_dds[10].mem_mux_latency_reg_i/shift_r_reg[0][1]_srl3___inst_signal_gen_top_i_signal_gen_i_ctrl_i_en_reg_r3_reg_r/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       2.971     3.644    d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/GEN_dds[10].mem_mux_latency_reg_i/aclk
    SLICE_X63Y369        SRL16E                                       r  d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/GEN_dds[10].mem_mux_latency_reg_i/shift_r_reg[0][1]_srl3___inst_signal_gen_top_i_signal_gen_i_ctrl_i_en_reg_r3_reg_r/CLK
                         clock pessimism             -0.369     3.275    
    SLICE_X63Y369        SRL16E (Hold_B6LUT_SLICEM_CLK_D)
                                                      0.029     3.304    d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/GEN_dds[10].mem_mux_latency_reg_i/shift_r_reg[0][1]_srl3___inst_signal_gen_top_i_signal_gen_i_ctrl_i_en_reg_r3_reg_r
  -------------------------------------------------------------------
                         required time                         -3.304    
                         arrival time                           3.316    
  -------------------------------------------------------------------
                         slack                                  0.011    

Slack (MET) :             0.012ns  (arrival time - required time)
  Source:                 d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/GEN_dds[11].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_rom_reg_a/opt_has_pipe.first_q_reg[1]/CE
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC0_CLK rise@0.000ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        0.228ns  (logic 0.058ns (25.433%)  route 0.170ns (74.567%))
  Logic Levels:           0  
  Clock Path Skew:        0.230ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.774ns
    Source Clock Delay      (SCD):    3.245ns
    Clock Pessimism Removal (CPR):    0.299ns
  Clock Net Delay (Source):      2.724ns (routing 1.256ns, distribution 1.468ns)
  Clock Net Delay (Destination): 3.101ns (routing 1.381ns, distribution 1.720ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       2.724     3.245    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X96Y119        FDRE                                         r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y119        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.058     3.303 r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg/Q
                         net (fo=367, routed)         0.170     3.473    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/GEN_dds[11].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_rom_reg_a/s_axis_phase_tvalid
    SLICE_X97Y121        FDRE                                         r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/GEN_dds[11].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_rom_reg_a/opt_has_pipe.first_q_reg[1]/CE
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       3.101     3.774    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/GEN_dds[11].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_rom_reg_a/aclk
    SLICE_X97Y121        FDRE                                         r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/GEN_dds[11].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_rom_reg_a/opt_has_pipe.first_q_reg[1]/C
                         clock pessimism             -0.299     3.475    
    SLICE_X97Y121        FDRE (Hold_AFF_SLICEM_C_CE)
                                                     -0.014     3.461    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/GEN_dds[11].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_rom_reg_a/opt_has_pipe.first_q_reg[1]
  -------------------------------------------------------------------
                         required time                         -3.461    
                         arrival time                           3.473    
  -------------------------------------------------------------------
                         slack                                  0.012    

Slack (MET) :             0.012ns  (arrival time - required time)
  Source:                 d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[4].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms/opt_has_pipe.first_q_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[4].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ms/opt_has_pipe.first_q_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC0_CLK rise@0.000ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        0.211ns  (logic 0.080ns (37.889%)  route 0.131ns (62.111%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        0.139ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.481ns
    Source Clock Delay      (SCD):    3.025ns
    Clock Pessimism Removal (CPR):    0.317ns
  Clock Net Delay (Source):      2.504ns (routing 1.256ns, distribution 1.248ns)
  Clock Net Delay (Destination): 2.808ns (routing 1.381ns, distribution 1.427ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       2.504     3.025    d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[4].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms/aclk
    SLICE_X48Y58         FDRE                                         r  d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[4].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms/opt_has_pipe.first_q_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X48Y58         FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.058     3.083 r  d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[4].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms/opt_has_pipe.first_q_reg[5]/Q
                         net (fo=3, routed)           0.096     3.179    d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[4].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.cos_ms1[5]
    SLICE_X48Y61         LUT2 (Prop_C6LUT_SLICEM_I1_O)
                                                      0.022     3.201 r  d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[4].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/plusOp_inferred__2/opt_has_pipe.first_q[5]_i_1/O
                         net (fo=1, routed)           0.035     3.236    d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[4].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ms/D[5]
    SLICE_X48Y61         FDRE                                         r  d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[4].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ms/opt_has_pipe.first_q_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       2.808     3.481    d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[4].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ms/aclk
    SLICE_X48Y61         FDRE                                         r  d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[4].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ms/opt_has_pipe.first_q_reg[5]/C
                         clock pessimism             -0.317     3.164    
    SLICE_X48Y61         FDRE (Hold_CFF_SLICEM_C_D)
                                                      0.060     3.224    d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[4].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ms/opt_has_pipe.first_q_reg[5]
  -------------------------------------------------------------------
                         required time                         -3.224    
                         arrival time                           3.236    
  -------------------------------------------------------------------
                         slack                                  0.012    

Slack (MET) :             0.013ns  (arrival time - required time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[6][3]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/fifo_i/mem_i/RAM_reg_0_15_0_13/RAMB_D1/I
                            (rising edge-triggered cell RAMD32 clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC0_CLK rise@0.000ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        0.216ns  (logic 0.060ns (27.778%)  route 0.156ns (72.222%))
  Logic Levels:           0  
  Clock Path Skew:        0.143ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.734ns
    Source Clock Delay      (SCD):    3.215ns
    Clock Pessimism Removal (CPR):    0.375ns
  Clock Net Delay (Source):      2.694ns (routing 1.256ns, distribution 1.438ns)
  Clock Net Delay (Destination): 3.061ns (routing 1.381ns, distribution 1.680ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       2.694     3.215    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X16Y338        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[6][3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X16Y338        FDCE (Prop_AFF2_SLICEL_C_Q)
                                                      0.060     3.275 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[6][3]/Q
                         net (fo=1, routed)           0.156     3.431    d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/fifo_i/mem_i/RAM_reg_0_15_0_13/DIB1
    SLICE_X13Y338        RAMD32                                       r  d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/fifo_i/mem_i/RAM_reg_0_15_0_13/RAMB_D1/I
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       3.061     3.734    d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/fifo_i/mem_i/RAM_reg_0_15_0_13/WCLK
    SLICE_X13Y338        RAMD32                                       r  d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/fifo_i/mem_i/RAM_reg_0_15_0_13/RAMB_D1/CLK
                         clock pessimism             -0.375     3.359    
    SLICE_X13Y338        RAMD32 (Hold_B6LUT_SLICEM_CLK_I)
                                                      0.060     3.419    d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/fifo_i/mem_i/RAM_reg_0_15_0_13/RAMB_D1
  -------------------------------------------------------------------
                         required time                         -3.419    
                         arrival time                           3.431    
  -------------------------------------------------------------------
                         slack                                  0.013    

Slack (MET) :             0.013ns  (arrival time - required time)
  Source:                 d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[5].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.i_pipe[4].pipe_reg[4][1]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[5].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms/opt_has_pipe.first_q_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC0_CLK rise@0.000ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        0.158ns  (logic 0.058ns (36.761%)  route 0.100ns (63.239%))
  Logic Levels:           0  
  Clock Path Skew:        0.085ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.831ns
    Source Clock Delay      (SCD):    3.359ns
    Clock Pessimism Removal (CPR):    0.388ns
  Clock Net Delay (Source):      2.838ns (routing 1.256ns, distribution 1.582ns)
  Clock Net Delay (Destination): 3.158ns (routing 1.381ns, distribution 1.777ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       2.838     3.359    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[5].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/aclk
    SLICE_X110Y73        FDRE                                         r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[5].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.i_pipe[4].pipe_reg[4][1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X110Y73        FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.058     3.417 r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[5].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.i_pipe[4].pipe_reg[4][1]/Q
                         net (fo=31, routed)          0.100     3.516    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[5].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms/i_rtl.i_quarter_table.i_piped_map.invert_sin
    SLICE_X112Y73        FDRE                                         r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[5].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms/opt_has_pipe.first_q_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       3.158     3.831    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[5].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms/aclk
    SLICE_X112Y73        FDRE                                         r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[5].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms/opt_has_pipe.first_q_reg[7]/C
                         clock pessimism             -0.388     3.443    
    SLICE_X112Y73        FDRE (Hold_EFF_SLICEM_C_D)
                                                      0.060     3.503    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[5].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms/opt_has_pipe.first_q_reg[7]
  -------------------------------------------------------------------
                         required time                         -3.503    
                         arrival time                           3.516    
  -------------------------------------------------------------------
                         slack                                  0.013    

Slack (MET) :             0.013ns  (arrival time - required time)
  Source:                 d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/GEN_dds[9].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ls/opt_has_pipe.first_q_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/GEN_dds[9].dds_mux_latency_reg_i/shift_r_reg[0][6]_srl3___inst_signal_gen_top_i_signal_gen_i_ctrl_i_en_reg_r3_reg_r/D
                            (rising edge-triggered cell SRL16E clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC0_CLK rise@0.000ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        0.183ns  (logic 0.057ns (31.079%)  route 0.126ns (68.921%))
  Logic Levels:           0  
  Clock Path Skew:        0.150ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.830ns
    Source Clock Delay      (SCD):    3.297ns
    Clock Pessimism Removal (CPR):    0.384ns
  Clock Net Delay (Source):      2.776ns (routing 1.256ns, distribution 1.520ns)
  Clock Net Delay (Destination): 3.157ns (routing 1.381ns, distribution 1.776ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       2.776     3.297    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/GEN_dds[9].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ls/aclk
    SLICE_X93Y366        FDRE                                         r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/GEN_dds[9].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ls/opt_has_pipe.first_q_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y366        FDRE (Prop_FFF_SLICEM_C_Q)
                                                      0.057     3.354 r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/GEN_dds[9].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ls/opt_has_pipe.first_q_reg[6]/Q
                         net (fo=2, routed)           0.126     3.480    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/GEN_dds[9].dds_mux_latency_reg_i/m_axis_data_tdata[6]
    SLICE_X94Y367        SRL16E                                       r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/GEN_dds[9].dds_mux_latency_reg_i/shift_r_reg[0][6]_srl3___inst_signal_gen_top_i_signal_gen_i_ctrl_i_en_reg_r3_reg_r/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       3.157     3.830    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/GEN_dds[9].dds_mux_latency_reg_i/aclk
    SLICE_X94Y367        SRL16E                                       r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/GEN_dds[9].dds_mux_latency_reg_i/shift_r_reg[0][6]_srl3___inst_signal_gen_top_i_signal_gen_i_ctrl_i_en_reg_r3_reg_r/CLK
                         clock pessimism             -0.384     3.447    
    SLICE_X94Y367        SRL16E (Hold_G6LUT_SLICEM_CLK_D)
                                                      0.020     3.467    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/GEN_dds[9].dds_mux_latency_reg_i/shift_r_reg[0][6]_srl3___inst_signal_gen_top_i_signal_gen_i_ctrl_i_en_reg_r3_reg_r
  -------------------------------------------------------------------
                         required time                         -3.467    
                         arrival time                           3.480    
  -------------------------------------------------------------------
                         slack                                  0.013    

Slack (MET) :             0.014ns  (arrival time - required time)
  Source:                 d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/GEN_dds[8].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.first_q_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/GEN_dds[8].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.i_pipe[3].pipe_reg[3][0]_srl2/D
                            (rising edge-triggered cell SRL16E clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC0_CLK rise@0.000ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        0.174ns  (logic 0.061ns (35.057%)  route 0.113ns (64.942%))
  Logic Levels:           0  
  Clock Path Skew:        0.131ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.842ns
    Source Clock Delay      (SCD):    3.324ns
    Clock Pessimism Removal (CPR):    0.386ns
  Clock Net Delay (Source):      2.803ns (routing 1.256ns, distribution 1.547ns)
  Clock Net Delay (Destination): 3.169ns (routing 1.381ns, distribution 1.788ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       2.803     3.324    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/GEN_dds[8].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/aclk
    SLICE_X98Y342        FDRE                                         r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/GEN_dds[8].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.first_q_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X98Y342        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.061     3.385 r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/GEN_dds[8].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.first_q_reg[0]/Q
                         net (fo=1, routed)           0.113     3.498    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/GEN_dds[8].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.first_q[0]
    SLICE_X99Y341        SRL16E                                       r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/GEN_dds[8].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.i_pipe[3].pipe_reg[3][0]_srl2/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       3.169     3.842    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/GEN_dds[8].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/aclk
    SLICE_X99Y341        SRL16E                                       r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/GEN_dds[8].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.i_pipe[3].pipe_reg[3][0]_srl2/CLK
                         clock pessimism             -0.386     3.456    
    SLICE_X99Y341        SRL16E (Hold_A6LUT_SLICEM_CLK_D)
                                                      0.029     3.485    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/GEN_dds[8].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.i_pipe[3].pipe_reg[3][0]_srl2
  -------------------------------------------------------------------
                         required time                         -3.485    
                         arrival time                           3.498    
  -------------------------------------------------------------------
                         slack                                  0.014    

Slack (MET) :             0.014ns  (arrival time - required time)
  Source:                 d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[15].phase_v1_r1_reg[15][11]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[1123]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC0_CLK rise@0.000ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        0.176ns  (logic 0.059ns (33.523%)  route 0.117ns (66.477%))
  Logic Levels:           0  
  Clock Path Skew:        0.100ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.478ns
    Source Clock Delay      (SCD):    3.017ns
    Clock Pessimism Removal (CPR):    0.361ns
  Clock Net Delay (Source):      2.496ns (routing 1.256ns, distribution 1.240ns)
  Clock Net Delay (Destination): 2.805ns (routing 1.381ns, distribution 1.424ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       2.496     3.017    d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X51Y331        FDRE                                         r  d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[15].phase_v1_r1_reg[15][11]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X51Y331        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.059     3.076 r  d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[15].phase_v1_r1_reg[15][11]/Q
                         net (fo=1, routed)           0.117     3.193    d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int[1123]
    SLICE_X51Y328        FDRE                                         r  d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[1123]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       2.805     3.478    d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X51Y328        FDRE                                         r  d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[1123]/C
                         clock pessimism             -0.361     3.117    
    SLICE_X51Y328        FDRE (Hold_EFF2_SLICEL_C_D)
                                                      0.062     3.179    d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[1123]
  -------------------------------------------------------------------
                         required time                         -3.179    
                         arrival time                           3.193    
  -------------------------------------------------------------------
                         slack                                  0.014    

Slack (MET) :             0.014ns  (arrival time - required time)
  Source:                 d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[8].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms/opt_has_pipe.first_q_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[8].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ms/opt_has_pipe.first_q_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC0_CLK rise@0.000ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        0.296ns  (logic 0.119ns (40.183%)  route 0.177ns (59.817%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        0.222ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.875ns
    Source Clock Delay      (SCD):    3.368ns
    Clock Pessimism Removal (CPR):    0.285ns
  Clock Net Delay (Source):      2.847ns (routing 1.256ns, distribution 1.591ns)
  Clock Net Delay (Destination): 3.202ns (routing 1.381ns, distribution 1.821ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       2.847     3.368    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[8].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms/aclk
    SLICE_X111Y299       FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[8].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms/opt_has_pipe.first_q_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X111Y299       FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.061     3.429 r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[8].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms/opt_has_pipe.first_q_reg[4]/Q
                         net (fo=2, routed)           0.155     3.584    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[8].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.cos_ms1[4]
    SLICE_X111Y302       LUT6 (Prop_B6LUT_SLICEL_I5_O)
                                                      0.058     3.642 r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[8].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/plusOp_inferred__2/opt_has_pipe.first_q[4]_i_1/O
                         net (fo=1, routed)           0.022     3.664    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[8].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ms/D[4]
    SLICE_X111Y302       FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[8].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ms/opt_has_pipe.first_q_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       3.202     3.875    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[8].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ms/aclk
    SLICE_X111Y302       FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[8].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ms/opt_has_pipe.first_q_reg[4]/C
                         clock pessimism             -0.285     3.590    
    SLICE_X111Y302       FDRE (Hold_BFF_SLICEL_C_D)
                                                      0.060     3.650    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[8].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ms/opt_has_pipe.first_q_reg[4]
  -------------------------------------------------------------------
                         required time                         -3.650    
                         arrival time                           3.664    
  -------------------------------------------------------------------
                         slack                                  0.014    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         RFDAC0_CLK
Waveform(ns):       { 0.000 1.302 }
Period(ns):         2.604
Sources:            { d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX }

Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location      Pin
Min Period        n/a     HSDAC/CLK_DAC       n/a            2.000         2.604       0.604      HSDAC_X0Y0    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
Min Period        n/a     HSDAC/FABRIC_CLK    n/a            2.000         2.604       0.604      HSDAC_X0Y0    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/FABRIC_CLK
Min Period        n/a     HSDAC/FABRIC_CLK    n/a            2.000         2.604       0.604      HSDAC_X0Y1    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/FABRIC_CLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.355         2.604       1.249      RAMB36_X4Y51  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/GEN_mem[0].mem_imag_i/RAM_reg_bram_0/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.355         2.604       1.249      RAMB36_X4Y50  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/GEN_mem[0].mem_imag_i/RAM_reg_bram_1/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.355         2.604       1.249      RAMB36_X4Y52  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/GEN_mem[0].mem_real_i/RAM_reg_bram_0/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.355         2.604       1.249      RAMB36_X6Y57  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/GEN_mem[0].mem_real_i/RAM_reg_bram_1/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.355         2.604       1.249      RAMB36_X3Y65  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/GEN_mem[10].mem_imag_i/RAM_reg_bram_0/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.355         2.604       1.249      RAMB36_X3Y71  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/GEN_mem[10].mem_imag_i/RAM_reg_bram_1/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.355         2.604       1.249      RAMB36_X2Y72  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/GEN_mem[10].mem_real_i/RAM_reg_bram_0/CLKBWRCLK
Max Period        n/a     MMCME4_ADV/CLKIN1   n/a            100.000       2.604       97.396     MMCM_X0Y5     d_1_i/clk_core/inst/mmcme4_adv_inst/CLKIN1
Low Pulse Width   Slow    MMCME4_ADV/CLKIN1   n/a            0.911         1.302       0.391      MMCM_X0Y5     d_1_i/clk_core/inst/mmcme4_adv_inst/CLKIN1
Low Pulse Width   Fast    MMCME4_ADV/CLKIN1   n/a            0.911         1.302       0.391      MMCM_X0Y5     d_1_i/clk_core/inst/mmcme4_adv_inst/CLKIN1
Low Pulse Width   Slow    HSDAC/CLK_DAC       n/a            0.800         1.302       0.502      HSDAC_X0Y0    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
Low Pulse Width   Fast    HSDAC/CLK_DAC       n/a            0.800         1.302       0.502      HSDAC_X0Y0    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
Low Pulse Width   Slow    HSDAC/FABRIC_CLK    n/a            0.800         1.302       0.502      HSDAC_X0Y0    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/FABRIC_CLK
Low Pulse Width   Fast    HSDAC/FABRIC_CLK    n/a            0.800         1.302       0.502      HSDAC_X0Y0    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/FABRIC_CLK
Low Pulse Width   Slow    HSDAC/FABRIC_CLK    n/a            0.800         1.302       0.502      HSDAC_X0Y1    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/FABRIC_CLK
Low Pulse Width   Fast    HSDAC/FABRIC_CLK    n/a            0.800         1.302       0.502      HSDAC_X0Y1    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/FABRIC_CLK
Low Pulse Width   Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         1.302       0.760      RAMB36_X4Y51  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/GEN_mem[0].mem_imag_i/RAM_reg_bram_0/CLKBWRCLK
Low Pulse Width   Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         1.302       0.760      RAMB36_X4Y51  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/GEN_mem[0].mem_imag_i/RAM_reg_bram_0/CLKBWRCLK
High Pulse Width  Slow    MMCME4_ADV/CLKIN1   n/a            0.911         1.302       0.391      MMCM_X0Y5     d_1_i/clk_core/inst/mmcme4_adv_inst/CLKIN1
High Pulse Width  Fast    MMCME4_ADV/CLKIN1   n/a            0.911         1.302       0.391      MMCM_X0Y5     d_1_i/clk_core/inst/mmcme4_adv_inst/CLKIN1
High Pulse Width  Slow    HSDAC/CLK_DAC       n/a            0.800         1.302       0.502      HSDAC_X0Y0    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
High Pulse Width  Fast    HSDAC/CLK_DAC       n/a            0.800         1.302       0.502      HSDAC_X0Y0    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
High Pulse Width  Slow    HSDAC/FABRIC_CLK    n/a            0.800         1.302       0.502      HSDAC_X0Y0    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/FABRIC_CLK
High Pulse Width  Fast    HSDAC/FABRIC_CLK    n/a            0.800         1.302       0.502      HSDAC_X0Y0    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/FABRIC_CLK
High Pulse Width  Slow    HSDAC/FABRIC_CLK    n/a            0.800         1.302       0.502      HSDAC_X0Y1    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/FABRIC_CLK
High Pulse Width  Fast    HSDAC/FABRIC_CLK    n/a            0.800         1.302       0.502      HSDAC_X0Y1    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/FABRIC_CLK
High Pulse Width  Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         1.302       0.760      RAMB36_X4Y51  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/GEN_mem[0].mem_imag_i/RAM_reg_bram_0/CLKBWRCLK
High Pulse Width  Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         1.302       0.760      RAMB36_X4Y51  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/GEN_mem[0].mem_imag_i/RAM_reg_bram_0/CLKBWRCLK



---------------------------------------------------------------------------------------------------
From Clock:  clk_out1_d_1_clk_core_0
  To Clock:  clk_out1_d_1_clk_core_0

Setup :            0  Failing Endpoints,  Worst Slack        0.209ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.010ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        2.062ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.209ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_0/CLKBWRCLK
                            (rising edge-triggered cell RAMB36E2 clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[9][5]/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.208ns  (clk_out1_d_1_clk_core_0 rise@5.208ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        4.771ns  (logic 2.532ns (53.070%)  route 2.239ns (46.930%))
  Logic Levels:           8  (LUT6=1 RAMB36E2=7)
  Clock Path Skew:        -0.197ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.774ns = ( 10.982 - 5.208 ) 
    Source Clock Delay      (SCD):    5.811ns
    Clock Pessimism Removal (CPR):    -0.160ns
  Clock Uncertainty:      0.056ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.087ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.173ns (routing 0.920ns, distribution 1.253ns)
  Clock Net Delay (Destination): 1.835ns (routing 0.838ns, distribution 0.997ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.819     3.492    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.365 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.610    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.638 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        2.173     5.811    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/c_clk_i
    RAMB36_X5Y77         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_0/CLKBWRCLK
  -------------------------------------------------------------------    -------------------
    RAMB36_X5Y77         RAMB36E2 (Prop_RAMB36E2_RAMB36_CLKBWRCLK_CASDOUTB[5])
                                                      1.065     6.876 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_0/CASDOUTB[5]
                         net (fo=1, routed)           0.025     6.901    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_0_n_62
    RAMB36_X5Y78         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[5]_CASDOUTB[5])
                                                      0.210     7.111 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_1/CASDOUTB[5]
                         net (fo=1, routed)           0.025     7.136    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_1_n_62
    RAMB36_X5Y79         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[5]_CASDOUTB[5])
                                                      0.210     7.346 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_2/CASDOUTB[5]
                         net (fo=1, routed)           0.025     7.371    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_2_n_62
    RAMB36_X5Y80         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[5]_CASDOUTB[5])
                                                      0.210     7.581 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_3/CASDOUTB[5]
                         net (fo=1, routed)           0.025     7.606    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_3_n_62
    RAMB36_X5Y81         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[5]_CASDOUTB[5])
                                                      0.210     7.816 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_4/CASDOUTB[5]
                         net (fo=1, routed)           0.025     7.841    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_4_n_62
    RAMB36_X5Y82         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[5]_CASDOUTB[5])
                                                      0.210     8.051 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_5/CASDOUTB[5]
                         net (fo=1, routed)           0.025     8.076    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_5_n_62
    RAMB36_X5Y83         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[5]_CASDOUTB[5])
                                                      0.210     8.286 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_6/CASDOUTB[5]
                         net (fo=1, routed)           0.025     8.311    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_6_n_62
    RAMB36_X5Y84         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[5]_DOUTBDOUT[5])
                                                      0.117     8.428 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_7/DOUTBDOUT[5]
                         net (fo=3, routed)           1.078     9.506    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dmem_r_dt[5]
    SLICE_X37Y388        LUT6 (Prop_G6LUT_SLICEM_I4_O)
                                                      0.090     9.596 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/sreg_cfg_dt[5]_i_1/O
                         net (fo=21, routed)          0.986    10.582    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/p_1_in[5]
    SLICE_X18Y380        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[9][5]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.208     5.208 r  
    HSDAC_X0Y0           HSDAC                        0.000     5.208 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     5.489 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     5.615    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     5.729 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.549     8.278    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     8.908 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     9.123    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     9.147 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.835    10.982    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/c_clk_i
    SLICE_X18Y380        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[9][5]/C
                         clock pessimism             -0.160    10.822    
                         clock uncertainty           -0.056    10.766    
    SLICE_X18Y380        FDCE (Setup_DFF_SLICEM_C_D)
                                                      0.025    10.791    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[9][5]
  -------------------------------------------------------------------
                         required time                         10.791    
                         arrival time                         -10.582    
  -------------------------------------------------------------------
                         slack                                  0.209    

Slack (MET) :             0.245ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/c_fifo_time_in_r_reg[44]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/qick_processor_0/WAVE_FIFO[1].wave_fifo_inst/fifo_mem/RAM_reg_0/DINBDIN[12]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.208ns  (clk_out1_d_1_clk_core_0 rise@5.208ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        4.508ns  (logic 0.079ns (1.752%)  route 4.429ns (98.248%))
  Logic Levels:           0  
  Clock Path Skew:        -0.141ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.691ns = ( 10.899 - 5.208 ) 
    Source Clock Delay      (SCD):    5.613ns
    Clock Pessimism Removal (CPR):    -0.219ns
  Clock Uncertainty:      0.056ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.087ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.975ns (routing 0.920ns, distribution 1.055ns)
  Clock Net Delay (Destination): 1.752ns (routing 0.838ns, distribution 0.914ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.819     3.492    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.365 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.610    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.638 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.975     5.613    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/c_clk_i
    SLICE_X32Y381        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/c_fifo_time_in_r_reg[44]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X32Y381        FDCE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     5.692 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/c_fifo_time_in_r_reg[44]/Q
                         net (fo=27, routed)          4.429    10.121    d_1_i/qick_processor_0/QPROC/DISPATCHER/c_fifo_time_in_r[44]
    RAMB36_X2Y58         RAMB36E2                                     r  d_1_i/qick_processor_0/WAVE_FIFO[1].wave_fifo_inst/fifo_mem/RAM_reg_0/DINBDIN[12]
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.208     5.208 r  
    HSDAC_X0Y0           HSDAC                        0.000     5.208 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     5.489 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     5.615    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     5.729 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.549     8.278    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     8.908 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     9.123    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     9.147 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.752    10.899    d_1_i/qick_processor_0/c_clk_i
    RAMB36_X2Y58         RAMB36E2                                     r  d_1_i/qick_processor_0/WAVE_FIFO[1].wave_fifo_inst/fifo_mem/RAM_reg_0/CLKBWRCLK
                         clock pessimism             -0.219    10.680    
                         clock uncertainty           -0.056    10.624    
    RAMB36_X2Y58         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_DINBDIN[12])
                                                     -0.258    10.366    d_1_i/qick_processor_0/WAVE_FIFO[1].wave_fifo_inst/fifo_mem/RAM_reg_0
  -------------------------------------------------------------------
                         required time                         10.366    
                         arrival time                         -10.121    
  -------------------------------------------------------------------
                         slack                                  0.245    

Slack (MET) :             0.251ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/c_fifo_time_in_r_reg[44]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/qick_processor_0/WAVE_FIFO[3].wave_fifo_inst/fifo_mem/RAM_reg_0/DINBDIN[12]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.208ns  (clk_out1_d_1_clk_core_0 rise@5.208ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        4.489ns  (logic 0.079ns (1.760%)  route 4.410ns (98.240%))
  Logic Levels:           0  
  Clock Path Skew:        -0.154ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.678ns = ( 10.886 - 5.208 ) 
    Source Clock Delay      (SCD):    5.613ns
    Clock Pessimism Removal (CPR):    -0.219ns
  Clock Uncertainty:      0.056ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.087ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.975ns (routing 0.920ns, distribution 1.055ns)
  Clock Net Delay (Destination): 1.739ns (routing 0.838ns, distribution 0.901ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.819     3.492    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.365 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.610    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.638 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.975     5.613    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/c_clk_i
    SLICE_X32Y381        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/c_fifo_time_in_r_reg[44]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X32Y381        FDCE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     5.692 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/c_fifo_time_in_r_reg[44]/Q
                         net (fo=27, routed)          4.410    10.102    d_1_i/qick_processor_0/QPROC/DISPATCHER/c_fifo_time_in_r[44]
    RAMB36_X2Y55         RAMB36E2                                     r  d_1_i/qick_processor_0/WAVE_FIFO[3].wave_fifo_inst/fifo_mem/RAM_reg_0/DINBDIN[12]
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.208     5.208 r  
    HSDAC_X0Y0           HSDAC                        0.000     5.208 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     5.489 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     5.615    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     5.729 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.549     8.278    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     8.908 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     9.123    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     9.147 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.739    10.886    d_1_i/qick_processor_0/c_clk_i
    RAMB36_X2Y55         RAMB36E2                                     r  d_1_i/qick_processor_0/WAVE_FIFO[3].wave_fifo_inst/fifo_mem/RAM_reg_0/CLKBWRCLK
                         clock pessimism             -0.219    10.667    
                         clock uncertainty           -0.056    10.611    
    RAMB36_X2Y55         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_DINBDIN[12])
                                                     -0.258    10.353    d_1_i/qick_processor_0/WAVE_FIFO[3].wave_fifo_inst/fifo_mem/RAM_reg_0
  -------------------------------------------------------------------
                         required time                         10.353    
                         arrival time                         -10.102    
  -------------------------------------------------------------------
                         slack                                  0.251    

Slack (MET) :             0.253ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_0/CLKBWRCLK
                            (rising edge-triggered cell RAMB36E2 clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[2][5]/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.208ns  (clk_out1_d_1_clk_core_0 rise@5.208ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        4.737ns  (logic 2.532ns (53.449%)  route 2.205ns (46.551%))
  Logic Levels:           8  (LUT6=1 RAMB36E2=7)
  Clock Path Skew:        -0.187ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.784ns = ( 10.992 - 5.208 ) 
    Source Clock Delay      (SCD):    5.811ns
    Clock Pessimism Removal (CPR):    -0.160ns
  Clock Uncertainty:      0.056ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.087ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.173ns (routing 0.920ns, distribution 1.253ns)
  Clock Net Delay (Destination): 1.845ns (routing 0.838ns, distribution 1.007ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.819     3.492    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.365 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.610    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.638 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        2.173     5.811    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/c_clk_i
    RAMB36_X5Y77         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_0/CLKBWRCLK
  -------------------------------------------------------------------    -------------------
    RAMB36_X5Y77         RAMB36E2 (Prop_RAMB36E2_RAMB36_CLKBWRCLK_CASDOUTB[5])
                                                      1.065     6.876 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_0/CASDOUTB[5]
                         net (fo=1, routed)           0.025     6.901    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_0_n_62
    RAMB36_X5Y78         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[5]_CASDOUTB[5])
                                                      0.210     7.111 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_1/CASDOUTB[5]
                         net (fo=1, routed)           0.025     7.136    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_1_n_62
    RAMB36_X5Y79         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[5]_CASDOUTB[5])
                                                      0.210     7.346 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_2/CASDOUTB[5]
                         net (fo=1, routed)           0.025     7.371    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_2_n_62
    RAMB36_X5Y80         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[5]_CASDOUTB[5])
                                                      0.210     7.581 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_3/CASDOUTB[5]
                         net (fo=1, routed)           0.025     7.606    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_3_n_62
    RAMB36_X5Y81         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[5]_CASDOUTB[5])
                                                      0.210     7.816 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_4/CASDOUTB[5]
                         net (fo=1, routed)           0.025     7.841    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_4_n_62
    RAMB36_X5Y82         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[5]_CASDOUTB[5])
                                                      0.210     8.051 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_5/CASDOUTB[5]
                         net (fo=1, routed)           0.025     8.076    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_5_n_62
    RAMB36_X5Y83         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[5]_CASDOUTB[5])
                                                      0.210     8.286 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_6/CASDOUTB[5]
                         net (fo=1, routed)           0.025     8.311    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_6_n_62
    RAMB36_X5Y84         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[5]_DOUTBDOUT[5])
                                                      0.117     8.428 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_7/DOUTBDOUT[5]
                         net (fo=3, routed)           1.078     9.506    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dmem_r_dt[5]
    SLICE_X37Y388        LUT6 (Prop_G6LUT_SLICEM_I4_O)
                                                      0.090     9.596 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/sreg_cfg_dt[5]_i_1/O
                         net (fo=21, routed)          0.952    10.548    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/p_1_in[5]
    SLICE_X17Y379        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[2][5]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.208     5.208 r  
    HSDAC_X0Y0           HSDAC                        0.000     5.208 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     5.489 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     5.615    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     5.729 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.549     8.278    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     8.908 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     9.123    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     9.147 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.845    10.992    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/c_clk_i
    SLICE_X17Y379        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[2][5]/C
                         clock pessimism             -0.160    10.832    
                         clock uncertainty           -0.056    10.776    
    SLICE_X17Y379        FDCE (Setup_DFF_SLICEL_C_D)
                                                      0.025    10.801    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[2][5]
  -------------------------------------------------------------------
                         required time                         10.801    
                         arrival time                         -10.548    
  -------------------------------------------------------------------
                         slack                                  0.253    

Slack (MET) :             0.272ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_0/CLKBWRCLK
                            (rising edge-triggered cell RAMB36E2 clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[15][3]/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.208ns  (clk_out1_d_1_clk_core_0 rise@5.208ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        4.712ns  (logic 2.602ns (55.218%)  route 2.110ns (44.782%))
  Logic Levels:           8  (LUT6=1 RAMB36E2=7)
  Clock Path Skew:        -0.192ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.779ns = ( 10.987 - 5.208 ) 
    Source Clock Delay      (SCD):    5.811ns
    Clock Pessimism Removal (CPR):    -0.160ns
  Clock Uncertainty:      0.056ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.087ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.173ns (routing 0.920ns, distribution 1.253ns)
  Clock Net Delay (Destination): 1.840ns (routing 0.838ns, distribution 1.002ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.819     3.492    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.365 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.610    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.638 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        2.173     5.811    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/c_clk_i
    RAMB36_X5Y77         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_0/CLKBWRCLK
  -------------------------------------------------------------------    -------------------
    RAMB36_X5Y77         RAMB36E2 (Prop_RAMB36E2_RAMB36_CLKBWRCLK_CASDOUTB[3])
                                                      1.073     6.884 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_0/CASDOUTB[3]
                         net (fo=1, routed)           0.025     6.909    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_0_n_64
    RAMB36_X5Y78         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[3]_CASDOUTB[3])
                                                      0.210     7.119 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_1/CASDOUTB[3]
                         net (fo=1, routed)           0.025     7.144    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_1_n_64
    RAMB36_X5Y79         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[3]_CASDOUTB[3])
                                                      0.210     7.354 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_2/CASDOUTB[3]
                         net (fo=1, routed)           0.025     7.379    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_2_n_64
    RAMB36_X5Y80         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[3]_CASDOUTB[3])
                                                      0.210     7.589 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_3/CASDOUTB[3]
                         net (fo=1, routed)           0.025     7.614    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_3_n_64
    RAMB36_X5Y81         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[3]_CASDOUTB[3])
                                                      0.210     7.824 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_4/CASDOUTB[3]
                         net (fo=1, routed)           0.025     7.849    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_4_n_64
    RAMB36_X5Y82         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[3]_CASDOUTB[3])
                                                      0.210     8.059 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_5/CASDOUTB[3]
                         net (fo=1, routed)           0.025     8.084    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_5_n_64
    RAMB36_X5Y83         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[3]_CASDOUTB[3])
                                                      0.210     8.294 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_6/CASDOUTB[3]
                         net (fo=1, routed)           0.025     8.319    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_6_n_64
    RAMB36_X5Y84         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[3]_DOUTBDOUT[3])
                                                      0.117     8.436 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_7/DOUTBDOUT[3]
                         net (fo=3, routed)           1.047     9.483    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dmem_r_dt[3]
    SLICE_X31Y388        LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.152     9.635 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/sreg_cfg_dt[3]_i_1/O
                         net (fo=21, routed)          0.888    10.523    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/p_1_in[3]
    SLICE_X18Y374        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[15][3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.208     5.208 r  
    HSDAC_X0Y0           HSDAC                        0.000     5.208 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     5.489 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     5.615    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     5.729 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.549     8.278    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     8.908 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     9.123    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     9.147 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.840    10.987    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/c_clk_i
    SLICE_X18Y374        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[15][3]/C
                         clock pessimism             -0.160    10.827    
                         clock uncertainty           -0.056    10.771    
    SLICE_X18Y374        FDCE (Setup_DFF2_SLICEM_C_D)
                                                      0.025    10.796    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[15][3]
  -------------------------------------------------------------------
                         required time                         10.796    
                         arrival time                         -10.523    
  -------------------------------------------------------------------
                         slack                                  0.272    

Slack (MET) :             0.281ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_0/CLKBWRCLK
                            (rising edge-triggered cell RAMB36E2 clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[12][5]/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.208ns  (clk_out1_d_1_clk_core_0 rise@5.208ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        4.699ns  (logic 2.532ns (53.883%)  route 2.167ns (46.117%))
  Logic Levels:           8  (LUT6=1 RAMB36E2=7)
  Clock Path Skew:        -0.197ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.774ns = ( 10.982 - 5.208 ) 
    Source Clock Delay      (SCD):    5.811ns
    Clock Pessimism Removal (CPR):    -0.160ns
  Clock Uncertainty:      0.056ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.087ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.173ns (routing 0.920ns, distribution 1.253ns)
  Clock Net Delay (Destination): 1.835ns (routing 0.838ns, distribution 0.997ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.819     3.492    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.365 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.610    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.638 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        2.173     5.811    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/c_clk_i
    RAMB36_X5Y77         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_0/CLKBWRCLK
  -------------------------------------------------------------------    -------------------
    RAMB36_X5Y77         RAMB36E2 (Prop_RAMB36E2_RAMB36_CLKBWRCLK_CASDOUTB[5])
                                                      1.065     6.876 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_0/CASDOUTB[5]
                         net (fo=1, routed)           0.025     6.901    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_0_n_62
    RAMB36_X5Y78         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[5]_CASDOUTB[5])
                                                      0.210     7.111 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_1/CASDOUTB[5]
                         net (fo=1, routed)           0.025     7.136    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_1_n_62
    RAMB36_X5Y79         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[5]_CASDOUTB[5])
                                                      0.210     7.346 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_2/CASDOUTB[5]
                         net (fo=1, routed)           0.025     7.371    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_2_n_62
    RAMB36_X5Y80         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[5]_CASDOUTB[5])
                                                      0.210     7.581 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_3/CASDOUTB[5]
                         net (fo=1, routed)           0.025     7.606    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_3_n_62
    RAMB36_X5Y81         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[5]_CASDOUTB[5])
                                                      0.210     7.816 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_4/CASDOUTB[5]
                         net (fo=1, routed)           0.025     7.841    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_4_n_62
    RAMB36_X5Y82         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[5]_CASDOUTB[5])
                                                      0.210     8.051 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_5/CASDOUTB[5]
                         net (fo=1, routed)           0.025     8.076    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_5_n_62
    RAMB36_X5Y83         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[5]_CASDOUTB[5])
                                                      0.210     8.286 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_6/CASDOUTB[5]
                         net (fo=1, routed)           0.025     8.311    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_6_n_62
    RAMB36_X5Y84         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[5]_DOUTBDOUT[5])
                                                      0.117     8.428 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_7/DOUTBDOUT[5]
                         net (fo=3, routed)           1.078     9.506    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dmem_r_dt[5]
    SLICE_X37Y388        LUT6 (Prop_G6LUT_SLICEM_I4_O)
                                                      0.090     9.596 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/sreg_cfg_dt[5]_i_1/O
                         net (fo=21, routed)          0.914    10.510    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/p_1_in[5]
    SLICE_X18Y380        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[12][5]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.208     5.208 r  
    HSDAC_X0Y0           HSDAC                        0.000     5.208 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     5.489 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     5.615    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     5.729 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.549     8.278    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     8.908 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     9.123    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     9.147 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.835    10.982    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/c_clk_i
    SLICE_X18Y380        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[12][5]/C
                         clock pessimism             -0.160    10.822    
                         clock uncertainty           -0.056    10.766    
    SLICE_X18Y380        FDCE (Setup_DFF2_SLICEM_C_D)
                                                      0.025    10.791    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[12][5]
  -------------------------------------------------------------------
                         required time                         10.791    
                         arrival time                         -10.510    
  -------------------------------------------------------------------
                         slack                                  0.281    

Slack (MET) :             0.284ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_0/CLKBWRCLK
                            (rising edge-triggered cell RAMB36E2 clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[13][5]/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.208ns  (clk_out1_d_1_clk_core_0 rise@5.208ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        4.706ns  (logic 2.532ns (53.799%)  route 2.174ns (46.201%))
  Logic Levels:           8  (LUT6=1 RAMB36E2=7)
  Clock Path Skew:        -0.186ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.785ns = ( 10.993 - 5.208 ) 
    Source Clock Delay      (SCD):    5.811ns
    Clock Pessimism Removal (CPR):    -0.160ns
  Clock Uncertainty:      0.056ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.087ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.173ns (routing 0.920ns, distribution 1.253ns)
  Clock Net Delay (Destination): 1.846ns (routing 0.838ns, distribution 1.008ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.819     3.492    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.365 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.610    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.638 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        2.173     5.811    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/c_clk_i
    RAMB36_X5Y77         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_0/CLKBWRCLK
  -------------------------------------------------------------------    -------------------
    RAMB36_X5Y77         RAMB36E2 (Prop_RAMB36E2_RAMB36_CLKBWRCLK_CASDOUTB[5])
                                                      1.065     6.876 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_0/CASDOUTB[5]
                         net (fo=1, routed)           0.025     6.901    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_0_n_62
    RAMB36_X5Y78         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[5]_CASDOUTB[5])
                                                      0.210     7.111 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_1/CASDOUTB[5]
                         net (fo=1, routed)           0.025     7.136    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_1_n_62
    RAMB36_X5Y79         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[5]_CASDOUTB[5])
                                                      0.210     7.346 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_2/CASDOUTB[5]
                         net (fo=1, routed)           0.025     7.371    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_2_n_62
    RAMB36_X5Y80         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[5]_CASDOUTB[5])
                                                      0.210     7.581 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_3/CASDOUTB[5]
                         net (fo=1, routed)           0.025     7.606    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_3_n_62
    RAMB36_X5Y81         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[5]_CASDOUTB[5])
                                                      0.210     7.816 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_4/CASDOUTB[5]
                         net (fo=1, routed)           0.025     7.841    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_4_n_62
    RAMB36_X5Y82         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[5]_CASDOUTB[5])
                                                      0.210     8.051 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_5/CASDOUTB[5]
                         net (fo=1, routed)           0.025     8.076    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_5_n_62
    RAMB36_X5Y83         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[5]_CASDOUTB[5])
                                                      0.210     8.286 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_6/CASDOUTB[5]
                         net (fo=1, routed)           0.025     8.311    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_6_n_62
    RAMB36_X5Y84         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[5]_DOUTBDOUT[5])
                                                      0.117     8.428 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_7/DOUTBDOUT[5]
                         net (fo=3, routed)           1.078     9.506    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dmem_r_dt[5]
    SLICE_X37Y388        LUT6 (Prop_G6LUT_SLICEM_I4_O)
                                                      0.090     9.596 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/sreg_cfg_dt[5]_i_1/O
                         net (fo=21, routed)          0.922    10.517    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/p_1_in[5]
    SLICE_X17Y380        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[13][5]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.208     5.208 r  
    HSDAC_X0Y0           HSDAC                        0.000     5.208 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     5.489 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     5.615    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     5.729 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.549     8.278    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     8.908 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     9.123    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     9.147 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.846    10.993    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/c_clk_i
    SLICE_X17Y380        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[13][5]/C
                         clock pessimism             -0.160    10.833    
                         clock uncertainty           -0.056    10.777    
    SLICE_X17Y380        FDCE (Setup_GFF_SLICEL_C_D)
                                                      0.025    10.802    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[13][5]
  -------------------------------------------------------------------
                         required time                         10.802    
                         arrival time                         -10.517    
  -------------------------------------------------------------------
                         slack                                  0.284    

Slack (MET) :             0.297ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_0/CLKBWRCLK
                            (rising edge-triggered cell RAMB36E2 clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[4][5]/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.208ns  (clk_out1_d_1_clk_core_0 rise@5.208ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        4.691ns  (logic 2.532ns (53.971%)  route 2.159ns (46.029%))
  Logic Levels:           8  (LUT6=1 RAMB36E2=7)
  Clock Path Skew:        -0.188ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.783ns = ( 10.991 - 5.208 ) 
    Source Clock Delay      (SCD):    5.811ns
    Clock Pessimism Removal (CPR):    -0.160ns
  Clock Uncertainty:      0.056ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.087ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.173ns (routing 0.920ns, distribution 1.253ns)
  Clock Net Delay (Destination): 1.844ns (routing 0.838ns, distribution 1.006ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.819     3.492    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.365 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.610    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.638 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        2.173     5.811    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/c_clk_i
    RAMB36_X5Y77         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_0/CLKBWRCLK
  -------------------------------------------------------------------    -------------------
    RAMB36_X5Y77         RAMB36E2 (Prop_RAMB36E2_RAMB36_CLKBWRCLK_CASDOUTB[5])
                                                      1.065     6.876 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_0/CASDOUTB[5]
                         net (fo=1, routed)           0.025     6.901    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_0_n_62
    RAMB36_X5Y78         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[5]_CASDOUTB[5])
                                                      0.210     7.111 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_1/CASDOUTB[5]
                         net (fo=1, routed)           0.025     7.136    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_1_n_62
    RAMB36_X5Y79         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[5]_CASDOUTB[5])
                                                      0.210     7.346 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_2/CASDOUTB[5]
                         net (fo=1, routed)           0.025     7.371    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_2_n_62
    RAMB36_X5Y80         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[5]_CASDOUTB[5])
                                                      0.210     7.581 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_3/CASDOUTB[5]
                         net (fo=1, routed)           0.025     7.606    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_3_n_62
    RAMB36_X5Y81         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[5]_CASDOUTB[5])
                                                      0.210     7.816 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_4/CASDOUTB[5]
                         net (fo=1, routed)           0.025     7.841    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_4_n_62
    RAMB36_X5Y82         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[5]_CASDOUTB[5])
                                                      0.210     8.051 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_5/CASDOUTB[5]
                         net (fo=1, routed)           0.025     8.076    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_5_n_62
    RAMB36_X5Y83         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[5]_CASDOUTB[5])
                                                      0.210     8.286 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_6/CASDOUTB[5]
                         net (fo=1, routed)           0.025     8.311    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_6_n_62
    RAMB36_X5Y84         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[5]_DOUTBDOUT[5])
                                                      0.117     8.428 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_7/DOUTBDOUT[5]
                         net (fo=3, routed)           1.078     9.506    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dmem_r_dt[5]
    SLICE_X37Y388        LUT6 (Prop_G6LUT_SLICEM_I4_O)
                                                      0.090     9.596 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/sreg_cfg_dt[5]_i_1/O
                         net (fo=21, routed)          0.907    10.502    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/p_1_in[5]
    SLICE_X17Y380        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[4][5]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.208     5.208 r  
    HSDAC_X0Y0           HSDAC                        0.000     5.208 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     5.489 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     5.615    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     5.729 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.549     8.278    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     8.908 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     9.123    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     9.147 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.844    10.991    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/c_clk_i
    SLICE_X17Y380        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[4][5]/C
                         clock pessimism             -0.160    10.831    
                         clock uncertainty           -0.056    10.775    
    SLICE_X17Y380        FDCE (Setup_DFF2_SLICEL_C_D)
                                                      0.025    10.800    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[4][5]
  -------------------------------------------------------------------
                         required time                         10.800    
                         arrival time                         -10.502    
  -------------------------------------------------------------------
                         slack                                  0.297    

Slack (MET) :             0.297ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_0/CLKBWRCLK
                            (rising edge-triggered cell RAMB36E2 clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[15][5]/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.208ns  (clk_out1_d_1_clk_core_0 rise@5.208ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        4.691ns  (logic 2.532ns (53.971%)  route 2.159ns (46.029%))
  Logic Levels:           8  (LUT6=1 RAMB36E2=7)
  Clock Path Skew:        -0.188ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.783ns = ( 10.991 - 5.208 ) 
    Source Clock Delay      (SCD):    5.811ns
    Clock Pessimism Removal (CPR):    -0.160ns
  Clock Uncertainty:      0.056ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.087ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.173ns (routing 0.920ns, distribution 1.253ns)
  Clock Net Delay (Destination): 1.844ns (routing 0.838ns, distribution 1.006ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.819     3.492    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.365 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.610    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.638 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        2.173     5.811    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/c_clk_i
    RAMB36_X5Y77         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_0/CLKBWRCLK
  -------------------------------------------------------------------    -------------------
    RAMB36_X5Y77         RAMB36E2 (Prop_RAMB36E2_RAMB36_CLKBWRCLK_CASDOUTB[5])
                                                      1.065     6.876 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_0/CASDOUTB[5]
                         net (fo=1, routed)           0.025     6.901    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_0_n_62
    RAMB36_X5Y78         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[5]_CASDOUTB[5])
                                                      0.210     7.111 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_1/CASDOUTB[5]
                         net (fo=1, routed)           0.025     7.136    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_1_n_62
    RAMB36_X5Y79         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[5]_CASDOUTB[5])
                                                      0.210     7.346 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_2/CASDOUTB[5]
                         net (fo=1, routed)           0.025     7.371    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_2_n_62
    RAMB36_X5Y80         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[5]_CASDOUTB[5])
                                                      0.210     7.581 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_3/CASDOUTB[5]
                         net (fo=1, routed)           0.025     7.606    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_3_n_62
    RAMB36_X5Y81         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[5]_CASDOUTB[5])
                                                      0.210     7.816 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_4/CASDOUTB[5]
                         net (fo=1, routed)           0.025     7.841    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_4_n_62
    RAMB36_X5Y82         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[5]_CASDOUTB[5])
                                                      0.210     8.051 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_5/CASDOUTB[5]
                         net (fo=1, routed)           0.025     8.076    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_5_n_62
    RAMB36_X5Y83         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[5]_CASDOUTB[5])
                                                      0.210     8.286 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_6/CASDOUTB[5]
                         net (fo=1, routed)           0.025     8.311    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_6_n_62
    RAMB36_X5Y84         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[5]_DOUTBDOUT[5])
                                                      0.117     8.428 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_7/DOUTBDOUT[5]
                         net (fo=3, routed)           1.078     9.506    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dmem_r_dt[5]
    SLICE_X37Y388        LUT6 (Prop_G6LUT_SLICEM_I4_O)
                                                      0.090     9.596 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/sreg_cfg_dt[5]_i_1/O
                         net (fo=21, routed)          0.906    10.502    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/p_1_in[5]
    SLICE_X17Y380        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[15][5]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.208     5.208 r  
    HSDAC_X0Y0           HSDAC                        0.000     5.208 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     5.489 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     5.615    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     5.729 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.549     8.278    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     8.908 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     9.123    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     9.147 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.844    10.991    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/c_clk_i
    SLICE_X17Y380        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[15][5]/C
                         clock pessimism             -0.160    10.831    
                         clock uncertainty           -0.056    10.775    
    SLICE_X17Y380        FDCE (Setup_DFF_SLICEL_C_D)
                                                      0.025    10.800    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[15][5]
  -------------------------------------------------------------------
                         required time                         10.800    
                         arrival time                         -10.502    
  -------------------------------------------------------------------
                         slack                                  0.297    

Slack (MET) :             0.300ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_0/CLKBWRCLK
                            (rising edge-triggered cell RAMB36E2 clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[7][3]/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.208ns  (clk_out1_d_1_clk_core_0 rise@5.208ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        4.684ns  (logic 2.602ns (55.548%)  route 2.082ns (44.452%))
  Logic Levels:           8  (LUT6=1 RAMB36E2=7)
  Clock Path Skew:        -0.192ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.779ns = ( 10.987 - 5.208 ) 
    Source Clock Delay      (SCD):    5.811ns
    Clock Pessimism Removal (CPR):    -0.160ns
  Clock Uncertainty:      0.056ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.087ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.173ns (routing 0.920ns, distribution 1.253ns)
  Clock Net Delay (Destination): 1.840ns (routing 0.838ns, distribution 1.002ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.819     3.492    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.365 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.610    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.638 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        2.173     5.811    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/c_clk_i
    RAMB36_X5Y77         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_0/CLKBWRCLK
  -------------------------------------------------------------------    -------------------
    RAMB36_X5Y77         RAMB36E2 (Prop_RAMB36E2_RAMB36_CLKBWRCLK_CASDOUTB[3])
                                                      1.073     6.884 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_0/CASDOUTB[3]
                         net (fo=1, routed)           0.025     6.909    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_0_n_64
    RAMB36_X5Y78         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[3]_CASDOUTB[3])
                                                      0.210     7.119 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_1/CASDOUTB[3]
                         net (fo=1, routed)           0.025     7.144    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_1_n_64
    RAMB36_X5Y79         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[3]_CASDOUTB[3])
                                                      0.210     7.354 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_2/CASDOUTB[3]
                         net (fo=1, routed)           0.025     7.379    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_2_n_64
    RAMB36_X5Y80         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[3]_CASDOUTB[3])
                                                      0.210     7.589 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_3/CASDOUTB[3]
                         net (fo=1, routed)           0.025     7.614    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_3_n_64
    RAMB36_X5Y81         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[3]_CASDOUTB[3])
                                                      0.210     7.824 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_4/CASDOUTB[3]
                         net (fo=1, routed)           0.025     7.849    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_4_n_64
    RAMB36_X5Y82         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[3]_CASDOUTB[3])
                                                      0.210     8.059 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_5/CASDOUTB[3]
                         net (fo=1, routed)           0.025     8.084    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_5_n_64
    RAMB36_X5Y83         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[3]_CASDOUTB[3])
                                                      0.210     8.294 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_6/CASDOUTB[3]
                         net (fo=1, routed)           0.025     8.319    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_6_n_64
    RAMB36_X5Y84         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[3]_DOUTBDOUT[3])
                                                      0.117     8.436 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_7/DOUTBDOUT[3]
                         net (fo=3, routed)           1.047     9.483    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dmem_r_dt[3]
    SLICE_X31Y388        LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.152     9.635 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/sreg_cfg_dt[3]_i_1/O
                         net (fo=21, routed)          0.860    10.495    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/p_1_in[3]
    SLICE_X18Y374        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[7][3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.208     5.208 r  
    HSDAC_X0Y0           HSDAC                        0.000     5.208 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     5.489 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     5.615    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     5.729 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.549     8.278    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     8.908 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     9.123    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     9.147 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.840    10.987    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/c_clk_i
    SLICE_X18Y374        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[7][3]/C
                         clock pessimism             -0.160    10.827    
                         clock uncertainty           -0.056    10.771    
    SLICE_X18Y374        FDCE (Setup_DFF_SLICEM_C_D)
                                                      0.025    10.796    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[7][3]
  -------------------------------------------------------------------
                         required time                         10.796    
                         arrival time                         -10.495    
  -------------------------------------------------------------------
                         slack                                  0.300    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.010ns  (arrival time - required time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[11].trig_fifo_inst/clr_fifo_req_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[11].trig_fifo_inst/gcc_wr_ptr/clear_cdc_reg/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.146ns  (logic 0.059ns (40.464%)  route 0.087ns (59.536%))
  Logic Levels:           0  
  Clock Path Skew:        0.074ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.702ns
    Source Clock Delay      (SCD):    5.792ns
    Clock Pessimism Removal (CPR):    -0.163ns
  Clock Net Delay (Source):      1.853ns (routing 0.838ns, distribution 1.015ns)
  Clock Net Delay (Destination): 2.064ns (routing 0.920ns, distribution 1.144ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.549     3.070    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.700 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.915    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.939 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.853     5.792    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[11].trig_fifo_inst/c_clk_i
    SLICE_X5Y352         FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[11].trig_fifo_inst/clr_fifo_req_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X5Y352         FDCE (Prop_HFF2_SLICEM_C_Q)
                                                      0.059     5.851 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[11].trig_fifo_inst/clr_fifo_req_reg/Q
                         net (fo=5, routed)           0.087     5.937    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[11].trig_fifo_inst/gcc_wr_ptr/clr_fifo_req
    SLICE_X3Y352         FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[11].trig_fifo_inst/gcc_wr_ptr/clear_cdc_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.819     3.492    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.365 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.610    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.638 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        2.064     5.702    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[11].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X3Y352         FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[11].trig_fifo_inst/gcc_wr_ptr/clear_cdc_reg/C
                         clock pessimism              0.163     5.865    
    SLICE_X3Y352         FDCE (Hold_DFF2_SLICEL_C_D)
                                                      0.062     5.927    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[11].trig_fifo_inst/gcc_wr_ptr/clear_cdc_reg
  -------------------------------------------------------------------
                         required time                         -5.927    
                         arrival time                           5.937    
  -------------------------------------------------------------------
                         slack                                  0.010    

Slack (MET) :             0.015ns  (arrival time - required time)
  Source:                 d_1_i/rst_core/U0/SEQ/from_sys_reg/C
                            (rising edge-triggered cell FDSE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/rst_core/U0/SEQ/core_dec_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.168ns  (logic 0.083ns (49.487%)  route 0.085ns (50.512%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        0.093ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.703ns
    Source Clock Delay      (SCD):    5.775ns
    Clock Pessimism Removal (CPR):    -0.164ns
  Clock Net Delay (Source):      1.836ns (routing 0.838ns, distribution 0.998ns)
  Clock Net Delay (Destination): 2.065ns (routing 0.920ns, distribution 1.145ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.549     3.070    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.700 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.915    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.939 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.836     5.775    d_1_i/rst_core/U0/SEQ/slowest_sync_clk
    SLICE_X55Y310        FDSE                                         r  d_1_i/rst_core/U0/SEQ/from_sys_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X55Y310        FDSE (Prop_DFF2_SLICEL_C_Q)
                                                      0.061     5.836 r  d_1_i/rst_core/U0/SEQ/from_sys_reg/Q
                         net (fo=10, routed)          0.063     5.898    d_1_i/rst_core/U0/SEQ/seq_cnt_en
    SLICE_X57Y310        LUT4 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.022     5.920 r  d_1_i/rst_core/U0/SEQ/pr_dec0/O
                         net (fo=1, routed)           0.022     5.942    d_1_i/rst_core/U0/SEQ/pr_dec0__0
    SLICE_X57Y310        FDRE                                         r  d_1_i/rst_core/U0/SEQ/core_dec_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.819     3.492    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.365 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.610    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.638 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        2.065     5.703    d_1_i/rst_core/U0/SEQ/slowest_sync_clk
    SLICE_X57Y310        FDRE                                         r  d_1_i/rst_core/U0/SEQ/core_dec_reg[1]/C
                         clock pessimism              0.164     5.867    
    SLICE_X57Y310        FDRE (Hold_GFF_SLICEL_C_D)
                                                      0.060     5.927    d_1_i/rst_core/U0/SEQ/core_dec_reg[1]
  -------------------------------------------------------------------
                         required time                         -5.927    
                         arrival time                           5.942    
  -------------------------------------------------------------------
                         slack                                  0.015    

Slack (MET) :             0.015ns  (arrival time - required time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/qick_processor_0/WAVE_FIFO[2].wave_fifo_inst/fifo_mem/RAM_reg_0/ADDRBWRADDR[7]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.131ns  (logic 0.039ns (29.749%)  route 0.092ns (70.251%))
  Logic Levels:           0  
  Clock Path Skew:        0.110ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.357ns
    Source Clock Delay      (SCD):    3.398ns
    Clock Pessimism Removal (CPR):    -0.151ns
  Clock Net Delay (Source):      1.117ns (routing 0.503ns, distribution 0.614ns)
  Clock Net Delay (Destination): 1.311ns (routing 0.553ns, distribution 0.758ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       1.539     1.888    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     2.118 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.264    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.281 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.117     3.398    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X45Y338        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X45Y338        FDCE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     3.437 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[1]/Q
                         net (fo=4, routed)           0.092     3.529    d_1_i/qick_processor_0/inst_n_43
    RAMB36_X4Y67         RAMB36E2                                     r  d_1_i/qick_processor_0/WAVE_FIFO[2].wave_fifo_inst/fifo_mem/RAM_reg_0/ADDRBWRADDR[7]
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       1.708     2.156    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.861 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     2.027    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     2.046 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.311     3.357    d_1_i/qick_processor_0/c_clk_i
    RAMB36_X4Y67         RAMB36E2                                     r  d_1_i/qick_processor_0/WAVE_FIFO[2].wave_fifo_inst/fifo_mem/RAM_reg_0/CLKBWRCLK
                         clock pessimism              0.151     3.508    
    RAMB36_X4Y67         RAMB36E2 (Hold_RAMB36E2_RAMB36_CLKBWRCLK_ADDRBWRADDR[7])
                                                      0.006     3.514    d_1_i/qick_processor_0/WAVE_FIFO[2].wave_fifo_inst/fifo_mem/RAM_reg_0
  -------------------------------------------------------------------
                         required time                         -3.514    
                         arrival time                           3.529    
  -------------------------------------------------------------------
                         slack                                  0.015    

Slack (MET) :             0.018ns  (arrival time - required time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[10].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[5]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[10].trig_fifo_inst/fifo_mem/RAM_reg/ADDRBWRADDR[11]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.138ns  (logic 0.037ns (26.740%)  route 0.101ns (73.260%))
  Logic Levels:           0  
  Clock Path Skew:        0.115ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.385ns
    Source Clock Delay      (SCD):    3.417ns
    Clock Pessimism Removal (CPR):    -0.146ns
  Clock Net Delay (Source):      1.136ns (routing 0.503ns, distribution 0.633ns)
  Clock Net Delay (Destination): 1.339ns (routing 0.553ns, distribution 0.786ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       1.539     1.888    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     2.118 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.264    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.281 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.136     3.417    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[10].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X13Y398        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[10].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X13Y398        FDCE (Prop_FFF_SLICEM_C_Q)
                                                      0.037     3.454 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[10].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[5]/Q
                         net (fo=2, routed)           0.101     3.555    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[10].trig_fifo_inst/fifo_mem/RAM_reg_1[5]
    RAMB36_X1Y79         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[10].trig_fifo_inst/fifo_mem/RAM_reg/ADDRBWRADDR[11]
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       1.708     2.156    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.861 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     2.027    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     2.046 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.339     3.385    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[10].trig_fifo_inst/fifo_mem/c_clk_i
    RAMB36_X1Y79         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[10].trig_fifo_inst/fifo_mem/RAM_reg/CLKBWRCLK
                         clock pessimism              0.146     3.532    
    RAMB36_X1Y79         RAMB36E2 (Hold_RAMB36E2_RAMB36_CLKBWRCLK_ADDRBWRADDR[11])
                                                      0.006     3.538    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[10].trig_fifo_inst/fifo_mem/RAM_reg
  -------------------------------------------------------------------
                         required time                         -3.538    
                         arrival time                           3.555    
  -------------------------------------------------------------------
                         slack                                  0.018    

Slack (MET) :             0.024ns  (arrival time - required time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/gcc_wr_ptr/clear_r_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[5]/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.190ns  (logic 0.095ns (50.060%)  route 0.095ns (49.940%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        0.106ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.693ns
    Source Clock Delay      (SCD):    5.752ns
    Clock Pessimism Removal (CPR):    -0.164ns
  Clock Net Delay (Source):      1.813ns (routing 0.838ns, distribution 0.975ns)
  Clock Net Delay (Destination): 2.055ns (routing 0.920ns, distribution 1.135ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.549     3.070    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.700 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.915    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.939 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.813     5.752    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X48Y327        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/gcc_wr_ptr/clear_r_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X48Y327        FDCE (Prop_AFF2_SLICEM_C_Q)
                                                      0.060     5.812 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/gcc_wr_ptr/clear_r_reg/Q
                         net (fo=20, routed)          0.073     5.884    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/gcc_wr_ptr/clear_r
    SLICE_X47Y327        LUT2 (Prop_G6LUT_SLICEL_I1_O)
                                                      0.035     5.919 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/gcc_wr_ptr/count_gray_2r[5]_i_1__27/O
                         net (fo=1, routed)           0.022     5.941    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/gcc_wr_ptr/count_gray_2r[5]_i_1__27_n_0
    SLICE_X47Y327        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.819     3.492    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.365 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.610    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.638 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        2.055     5.693    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X47Y327        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[5]/C
                         clock pessimism              0.164     5.857    
    SLICE_X47Y327        FDCE (Hold_GFF_SLICEL_C_D)
                                                      0.060     5.917    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[5]
  -------------------------------------------------------------------
                         required time                         -5.917    
                         arrival time                           5.941    
  -------------------------------------------------------------------
                         slack                                  0.024    

Slack (MET) :             0.028ns  (arrival time - required time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/wreg_32_dt_reg[0][2]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/c_fifo_data_in_r_reg[2]/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.173ns  (logic 0.080ns (46.257%)  route 0.093ns (53.743%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        0.085ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.578ns
    Source Clock Delay      (SCD):    5.658ns
    Clock Pessimism Removal (CPR):    -0.164ns
  Clock Net Delay (Source):      1.719ns (routing 0.838ns, distribution 0.881ns)
  Clock Net Delay (Destination): 1.940ns (routing 0.920ns, distribution 1.020ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.549     3.070    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.700 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.915    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.939 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.719     5.658    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/c_clk_i
    SLICE_X34Y393        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/wreg_32_dt_reg[0][2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X34Y393        FDCE (Prop_CFF_SLICEM_C_Q)
                                                      0.058     5.716 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/wreg_32_dt_reg[0][2]/Q
                         net (fo=5, routed)           0.071     5.787    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/wreg_32_dt_reg[0][31]_0[2]
    SLICE_X33Y393        LUT5 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.022     5.809 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/c_fifo_data_in_r[2]_i_1/O
                         net (fo=1, routed)           0.022     5.831    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/c_fifo_data_in_r_reg[167]_0[2]
    SLICE_X33Y393        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/c_fifo_data_in_r_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.819     3.492    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.365 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.610    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.638 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.940     5.578    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/c_clk_i
    SLICE_X33Y393        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/c_fifo_data_in_r_reg[2]/C
                         clock pessimism              0.164     5.742    
    SLICE_X33Y393        FDCE (Hold_DFF_SLICEL_C_D)
                                                      0.060     5.802    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/c_fifo_data_in_r_reg[2]
  -------------------------------------------------------------------
                         required time                         -5.802    
                         arrival time                           5.831    
  -------------------------------------------------------------------
                         slack                                  0.028    

Slack (MET) :             0.029ns  (arrival time - required time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.DIV/q_temp_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.DIV/div_quotient_o_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.272ns  (logic 0.058ns (21.351%)  route 0.214ns (78.649%))
  Logic Levels:           0  
  Clock Path Skew:        0.181ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.708ns
    Source Clock Delay      (SCD):    5.746ns
    Clock Pessimism Removal (CPR):    -0.219ns
  Clock Net Delay (Source):      1.807ns (routing 0.838ns, distribution 0.969ns)
  Clock Net Delay (Destination): 2.070ns (routing 0.920ns, distribution 1.150ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.549     3.070    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.700 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.915    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.939 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.807     5.746    d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.DIV/c_clk_i
    SLICE_X16Y359        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.DIV/q_temp_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X16Y359        FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.058     5.804 r  d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.DIV/q_temp_reg[2]/Q
                         net (fo=2, routed)           0.214     6.018    d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.DIV/q_temp_reg_n_0_[2]
    SLICE_X18Y360        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.DIV/div_quotient_o_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.819     3.492    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.365 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.610    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.638 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        2.070     5.708    d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.DIV/c_clk_i
    SLICE_X18Y360        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.DIV/div_quotient_o_reg[2]/C
                         clock pessimism              0.219     5.927    
    SLICE_X18Y360        FDRE (Hold_EFF2_SLICEM_C_D)
                                                      0.062     5.989    d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.DIV/div_quotient_o_reg[2]
  -------------------------------------------------------------------
                         required time                         -5.989    
                         arrival time                           6.018    
  -------------------------------------------------------------------
                         slack                                  0.029    

Slack (MET) :             0.029ns  (arrival time - required time)
  Source:                 d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][43]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/IN_PORT_REG/genblk1[2].port_dt_r_reg[2][43]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.125ns  (logic 0.060ns (48.000%)  route 0.065ns (52.000%))
  Logic Levels:           0  
  Clock Path Skew:        0.034ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.699ns
    Source Clock Delay      (SCD):    5.775ns
    Clock Pessimism Removal (CPR):    -0.109ns
  Clock Net Delay (Source):      1.836ns (routing 0.838ns, distribution 0.998ns)
  Clock Net Delay (Destination): 2.061ns (routing 0.920ns, distribution 1.141ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.549     3.070    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.700 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.915    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.939 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.836     5.775    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X10Y344        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][43]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X10Y344        FDRE (Prop_BFF2_SLICEL_C_Q)
                                                      0.060     5.835 r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][43]/Q
                         net (fo=1, routed)           0.065     5.900    d_1_i/qick_processor_0/inst/QPROC/IN_PORT_REG/s2_axis_tdata[43]
    SLICE_X10Y345        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/IN_PORT_REG/genblk1[2].port_dt_r_reg[2][43]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.819     3.492    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.365 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.610    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.638 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        2.061     5.699    d_1_i/qick_processor_0/inst/QPROC/IN_PORT_REG/c_clk_i
    SLICE_X10Y345        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/IN_PORT_REG/genblk1[2].port_dt_r_reg[2][43]/C
                         clock pessimism              0.109     5.808    
    SLICE_X10Y345        FDRE (Hold_CFF2_SLICEL_C_D)
                                                      0.062     5.870    d_1_i/qick_processor_0/inst/QPROC/IN_PORT_REG/genblk1[2].port_dt_r_reg[2][43]
  -------------------------------------------------------------------
                         required time                         -5.870    
                         arrival time                           5.900    
  -------------------------------------------------------------------
                         slack                                  0.029    

Slack (MET) :             0.030ns  (arrival time - required time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[11].trig_fifo_inst/gcc_wr_ptr/clear_r_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[11].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.185ns  (logic 0.082ns (44.242%)  route 0.103ns (55.758%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        0.095ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.717ns
    Source Clock Delay      (SCD):    5.785ns
    Clock Pessimism Removal (CPR):    -0.163ns
  Clock Net Delay (Source):      1.846ns (routing 0.838ns, distribution 1.008ns)
  Clock Net Delay (Destination): 2.079ns (routing 0.920ns, distribution 1.159ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.549     3.070    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.700 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.915    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.939 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.846     5.785    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[11].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X3Y352         FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[11].trig_fifo_inst/gcc_wr_ptr/clear_r_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X3Y352         FDCE (Prop_AFF2_SLICEL_C_Q)
                                                      0.060     5.845 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[11].trig_fifo_inst/gcc_wr_ptr/clear_r_reg/Q
                         net (fo=20, routed)          0.068     5.913    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[11].trig_fifo_inst/gcc_wr_ptr/clear_r
    SLICE_X5Y352         LUT2 (Prop_F6LUT_SLICEM_I1_O)
                                                      0.022     5.935 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[11].trig_fifo_inst/gcc_wr_ptr/count_gray_2r[8]_i_1__21/O
                         net (fo=1, routed)           0.035     5.970    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[11].trig_fifo_inst/gcc_wr_ptr/count_gray_2r[8]_i_1__21_n_0
    SLICE_X5Y352         FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[11].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.819     3.492    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.365 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.610    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.638 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        2.079     5.717    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[11].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X5Y352         FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[11].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]/C
                         clock pessimism              0.163     5.880    
    SLICE_X5Y352         FDCE (Hold_FFF_SLICEM_C_D)
                                                      0.060     5.940    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[11].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]
  -------------------------------------------------------------------
                         required time                         -5.940    
                         arrival time                           5.970    
  -------------------------------------------------------------------
                         slack                                  0.030    

Slack (MET) :             0.030ns  (arrival time - required time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/PC_curr_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/PC_prev_reg[6]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.192ns  (logic 0.058ns (30.164%)  route 0.134ns (69.836%))
  Logic Levels:           0  
  Clock Path Skew:        0.100ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.618ns
    Source Clock Delay      (SCD):    5.683ns
    Clock Pessimism Removal (CPR):    -0.165ns
  Clock Net Delay (Source):      1.744ns (routing 0.838ns, distribution 0.906ns)
  Clock Net Delay (Destination): 1.980ns (routing 0.920ns, distribution 1.060ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.549     3.070    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.700 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.915    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.939 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.744     5.683    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/c_clk_i
    SLICE_X29Y410        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/PC_curr_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X29Y410        FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.058     5.741 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/PC_curr_reg[6]/Q
                         net (fo=15, routed)          0.134     5.875    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/PC_curr_reg[9]_0[6]
    SLICE_X32Y409        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/PC_prev_reg[6]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.819     3.492    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.365 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.610    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.638 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.980     5.618    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/c_clk_i
    SLICE_X32Y409        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/PC_prev_reg[6]/C
                         clock pessimism              0.165     5.783    
    SLICE_X32Y409        FDRE (Hold_GFF2_SLICEL_C_D)
                                                      0.062     5.845    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/PC_prev_reg[6]
  -------------------------------------------------------------------
                         required time                         -5.845    
                         arrival time                           5.875    
  -------------------------------------------------------------------
                         slack                                  0.030    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         clk_out1_d_1_clk_core_0
Waveform(ns):       { 0.000 2.604 }
Period(ns):         5.208
Sources:            { d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0 }

Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location       Pin
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.569         5.208       3.639      RAMB36_X5Y77   d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_0/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.569         5.208       3.639      RAMB36_X5Y78   d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_1/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.569         5.208       3.639      RAMB36_X6Y79   d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_10/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.569         5.208       3.639      RAMB36_X6Y80   d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_11/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.569         5.208       3.639      RAMB36_X2Y81   d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_12/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.569         5.208       3.639      RAMB36_X2Y82   d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_13/CLKBWRCLK
Min Period        n/a     RAMB18E2/CLKBWRCLK  n/a            1.569         5.208       3.639      RAMB18_X3Y176  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_14/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.569         5.208       3.639      RAMB36_X5Y79   d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_2/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.569         5.208       3.639      RAMB36_X5Y80   d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_3/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.569         5.208       3.639      RAMB36_X5Y81   d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_4/CLKBWRCLK
Low Pulse Width   Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         2.604       2.062      RAMB36_X4Y64   d_1_i/qick_processor_0/WAVE_FIFO[0].wave_fifo_inst/fifo_mem/RAM_reg_0/CLKBWRCLK
Low Pulse Width   Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         2.604       2.062      RAMB36_X4Y64   d_1_i/qick_processor_0/WAVE_FIFO[0].wave_fifo_inst/fifo_mem/RAM_reg_0/CLKBWRCLK
Low Pulse Width   Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         2.604       2.062      RAMB36_X5Y65   d_1_i/qick_processor_0/WAVE_FIFO[0].wave_fifo_inst/fifo_mem/RAM_reg_1/CLKBWRCLK
Low Pulse Width   Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         2.604       2.062      RAMB36_X5Y65   d_1_i/qick_processor_0/WAVE_FIFO[0].wave_fifo_inst/fifo_mem/RAM_reg_1/CLKBWRCLK
Low Pulse Width   Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         2.604       2.062      RAMB36_X4Y65   d_1_i/qick_processor_0/WAVE_FIFO[0].wave_fifo_inst/fifo_mem/RAM_reg_2/CLKBWRCLK
Low Pulse Width   Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         2.604       2.062      RAMB36_X4Y65   d_1_i/qick_processor_0/WAVE_FIFO[0].wave_fifo_inst/fifo_mem/RAM_reg_2/CLKBWRCLK
Low Pulse Width   Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         2.604       2.062      RAMB36_X2Y63   d_1_i/qick_processor_0/WAVE_FIFO[10].wave_fifo_inst/fifo_mem/RAM_reg_0/CLKBWRCLK
Low Pulse Width   Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         2.604       2.062      RAMB36_X2Y63   d_1_i/qick_processor_0/WAVE_FIFO[10].wave_fifo_inst/fifo_mem/RAM_reg_0/CLKBWRCLK
Low Pulse Width   Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         2.604       2.062      RAMB36_X2Y57   d_1_i/qick_processor_0/WAVE_FIFO[10].wave_fifo_inst/fifo_mem/RAM_reg_1/CLKBWRCLK
Low Pulse Width   Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         2.604       2.062      RAMB36_X2Y57   d_1_i/qick_processor_0/WAVE_FIFO[10].wave_fifo_inst/fifo_mem/RAM_reg_1/CLKBWRCLK
High Pulse Width  Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         2.604       2.062      RAMB36_X4Y64   d_1_i/qick_processor_0/WAVE_FIFO[0].wave_fifo_inst/fifo_mem/RAM_reg_0/CLKBWRCLK
High Pulse Width  Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         2.604       2.062      RAMB36_X4Y64   d_1_i/qick_processor_0/WAVE_FIFO[0].wave_fifo_inst/fifo_mem/RAM_reg_0/CLKBWRCLK
High Pulse Width  Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         2.604       2.062      RAMB36_X5Y65   d_1_i/qick_processor_0/WAVE_FIFO[0].wave_fifo_inst/fifo_mem/RAM_reg_1/CLKBWRCLK
High Pulse Width  Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         2.604       2.062      RAMB36_X5Y65   d_1_i/qick_processor_0/WAVE_FIFO[0].wave_fifo_inst/fifo_mem/RAM_reg_1/CLKBWRCLK
High Pulse Width  Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         2.604       2.062      RAMB36_X4Y65   d_1_i/qick_processor_0/WAVE_FIFO[0].wave_fifo_inst/fifo_mem/RAM_reg_2/CLKBWRCLK
High Pulse Width  Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         2.604       2.062      RAMB36_X4Y65   d_1_i/qick_processor_0/WAVE_FIFO[0].wave_fifo_inst/fifo_mem/RAM_reg_2/CLKBWRCLK
High Pulse Width  Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         2.604       2.062      RAMB36_X2Y63   d_1_i/qick_processor_0/WAVE_FIFO[10].wave_fifo_inst/fifo_mem/RAM_reg_0/CLKBWRCLK
High Pulse Width  Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         2.604       2.062      RAMB36_X2Y63   d_1_i/qick_processor_0/WAVE_FIFO[10].wave_fifo_inst/fifo_mem/RAM_reg_0/CLKBWRCLK
High Pulse Width  Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         2.604       2.062      RAMB36_X2Y57   d_1_i/qick_processor_0/WAVE_FIFO[10].wave_fifo_inst/fifo_mem/RAM_reg_1/CLKBWRCLK
High Pulse Width  Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         2.604       2.062      RAMB36_X2Y57   d_1_i/qick_processor_0/WAVE_FIFO[10].wave_fifo_inst/fifo_mem/RAM_reg_1/CLKBWRCLK



---------------------------------------------------------------------------------------------------
From Clock:  clk_pl_0
  To Clock:  clk_pl_0

Setup :            0  Failing Endpoints,  Worst Slack        0.935ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.011ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        3.400ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.935ns  (required time - arrival time)
  Source:                 d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/adc2_start_stage_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        8.843ns  (logic 0.433ns (4.896%)  route 8.410ns (95.104%))
  Logic Levels:           4  (LUT4=1 LUT5=1 LUT6=2)
  Clock Path Skew:        -0.117ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.315ns = ( 12.315 - 10.000 ) 
    Source Clock Delay      (SCD):    2.543ns
    Clock Pessimism Removal (CPR):    0.112ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.317ns (routing 0.662ns, distribution 1.655ns)
  Clock Net Delay (Destination): 2.133ns (routing 0.598ns, distribution 1.535ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.317     2.543    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/clk
    SLICE_X82Y40         FDRE                                         r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y40         FDRE (Prop_FFF2_SLICEM_C_Q)
                                                      0.079     2.622 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/Q
                         net (fo=8, routed)           0.107     2.729    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_data_inst/current_word_1_reg[1]_1[15]
    SLICE_X82Y40         LUT4 (Prop_F6LUT_SLICEM_I1_O)
                                                      0.088     2.817 f  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_data_inst/current_word_1[1]_i_2/O
                         net (fo=4, routed)           0.096     2.914    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/current_word_1_reg[1]
    SLICE_X82Y39         LUT6 (Prop_G6LUT_SLICEM_I5_O)
                                                      0.090     3.004 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_3/O
                         net (fo=2, routed)           0.173     3.176    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_3_n_0
    SLICE_X83Y39         LUT5 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.051     3.227 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_1/O
                         net (fo=36, routed)          2.474     5.701    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_1_n_0
    SLICE_X24Y45         LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.125     5.826 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[9]_INST_0/O
                         net (fo=138, routed)         5.560    11.387    d_1_i/usp_rf_data_converter_0/inst/s_axi_wdata[9]
    SLICE_X112Y211       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/adc2_start_stage_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.133    12.315    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X112Y211       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/adc2_start_stage_reg[1]/C
                         clock pessimism              0.112    12.427    
                         clock uncertainty           -0.130    12.297    
    SLICE_X112Y211       FDRE (Setup_GFF2_SLICEM_C_D)
                                                      0.025    12.322    d_1_i/usp_rf_data_converter_0/inst/adc2_start_stage_reg[1]
  -------------------------------------------------------------------
                         required time                         12.322    
                         arrival time                         -11.387    
  -------------------------------------------------------------------
                         slack                                  0.935    

Slack (MET) :             0.966ns  (required time - arrival time)
  Source:                 d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/adc3_ref_clk_freq_reg[24]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        8.839ns  (logic 0.360ns (4.073%)  route 8.479ns (95.927%))
  Logic Levels:           4  (LUT4=1 LUT5=1 LUT6=2)
  Clock Path Skew:        -0.090ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.342ns = ( 12.342 - 10.000 ) 
    Source Clock Delay      (SCD):    2.543ns
    Clock Pessimism Removal (CPR):    0.112ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.317ns (routing 0.662ns, distribution 1.655ns)
  Clock Net Delay (Destination): 2.160ns (routing 0.598ns, distribution 1.562ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.317     2.543    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/clk
    SLICE_X82Y40         FDRE                                         r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y40         FDRE (Prop_FFF2_SLICEM_C_Q)
                                                      0.079     2.622 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/Q
                         net (fo=8, routed)           0.107     2.729    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_data_inst/current_word_1_reg[1]_1[15]
    SLICE_X82Y40         LUT4 (Prop_F6LUT_SLICEM_I1_O)
                                                      0.088     2.817 f  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_data_inst/current_word_1[1]_i_2/O
                         net (fo=4, routed)           0.096     2.914    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/current_word_1_reg[1]
    SLICE_X82Y39         LUT6 (Prop_G6LUT_SLICEM_I5_O)
                                                      0.090     3.004 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_3/O
                         net (fo=2, routed)           0.173     3.176    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_3_n_0
    SLICE_X83Y39         LUT5 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.051     3.227 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_1/O
                         net (fo=36, routed)          2.463     5.690    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_1_n_0
    SLICE_X24Y48         LUT6 (Prop_G6LUT_SLICEM_I3_O)
                                                      0.052     5.742 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[24]_INST_0/O
                         net (fo=124, routed)         5.640    11.382    d_1_i/usp_rf_data_converter_0/inst/s_axi_wdata[24]
    SLICE_X113Y235       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/adc3_ref_clk_freq_reg[24]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.160    12.342    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y235       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/adc3_ref_clk_freq_reg[24]/C
                         clock pessimism              0.112    12.454    
                         clock uncertainty           -0.130    12.324    
    SLICE_X113Y235       FDRE (Setup_GFF_SLICEM_C_D)
                                                      0.025    12.349    d_1_i/usp_rf_data_converter_0/inst/adc3_ref_clk_freq_reg[24]
  -------------------------------------------------------------------
                         required time                         12.349    
                         arrival time                         -11.382    
  -------------------------------------------------------------------
                         slack                                  0.966    

Slack (MET) :             1.026ns  (required time - arrival time)
  Source:                 d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/adc2_cmn_en_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        8.735ns  (logic 0.433ns (4.957%)  route 8.302ns (95.043%))
  Logic Levels:           4  (LUT4=1 LUT5=1 LUT6=2)
  Clock Path Skew:        -0.135ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.297ns = ( 12.297 - 10.000 ) 
    Source Clock Delay      (SCD):    2.543ns
    Clock Pessimism Removal (CPR):    0.112ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.317ns (routing 0.662ns, distribution 1.655ns)
  Clock Net Delay (Destination): 2.115ns (routing 0.598ns, distribution 1.517ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.317     2.543    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/clk
    SLICE_X82Y40         FDRE                                         r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y40         FDRE (Prop_FFF2_SLICEM_C_Q)
                                                      0.079     2.622 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/Q
                         net (fo=8, routed)           0.107     2.729    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_data_inst/current_word_1_reg[1]_1[15]
    SLICE_X82Y40         LUT4 (Prop_F6LUT_SLICEM_I1_O)
                                                      0.088     2.817 f  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_data_inst/current_word_1[1]_i_2/O
                         net (fo=4, routed)           0.096     2.914    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/current_word_1_reg[1]
    SLICE_X82Y39         LUT6 (Prop_G6LUT_SLICEM_I5_O)
                                                      0.090     3.004 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_3/O
                         net (fo=2, routed)           0.173     3.176    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_3_n_0
    SLICE_X83Y39         LUT5 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.051     3.227 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_1/O
                         net (fo=36, routed)          2.474     5.701    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_1_n_0
    SLICE_X24Y45         LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.125     5.826 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[9]_INST_0/O
                         net (fo=138, routed)         5.452    11.278    d_1_i/usp_rf_data_converter_0/inst/s_axi_wdata[9]
    SLICE_X107Y216       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/adc2_cmn_en_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.115    12.297    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X107Y216       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/adc2_cmn_en_reg[9]/C
                         clock pessimism              0.112    12.409    
                         clock uncertainty           -0.130    12.279    
    SLICE_X107Y216       FDRE (Setup_AFF2_SLICEM_C_D)
                                                      0.025    12.304    d_1_i/usp_rf_data_converter_0/inst/adc2_cmn_en_reg[9]
  -------------------------------------------------------------------
                         required time                         12.304    
                         arrival time                         -11.278    
  -------------------------------------------------------------------
                         slack                                  1.026    

Slack (MET) :             1.027ns  (required time - arrival time)
  Source:                 d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/adc3_sample_rate_reg[24]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        8.779ns  (logic 0.360ns (4.101%)  route 8.419ns (95.899%))
  Logic Levels:           4  (LUT4=1 LUT5=1 LUT6=2)
  Clock Path Skew:        -0.089ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.343ns = ( 12.343 - 10.000 ) 
    Source Clock Delay      (SCD):    2.543ns
    Clock Pessimism Removal (CPR):    0.112ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.317ns (routing 0.662ns, distribution 1.655ns)
  Clock Net Delay (Destination): 2.161ns (routing 0.598ns, distribution 1.563ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.317     2.543    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/clk
    SLICE_X82Y40         FDRE                                         r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y40         FDRE (Prop_FFF2_SLICEM_C_Q)
                                                      0.079     2.622 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/Q
                         net (fo=8, routed)           0.107     2.729    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_data_inst/current_word_1_reg[1]_1[15]
    SLICE_X82Y40         LUT4 (Prop_F6LUT_SLICEM_I1_O)
                                                      0.088     2.817 f  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_data_inst/current_word_1[1]_i_2/O
                         net (fo=4, routed)           0.096     2.914    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/current_word_1_reg[1]
    SLICE_X82Y39         LUT6 (Prop_G6LUT_SLICEM_I5_O)
                                                      0.090     3.004 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_3/O
                         net (fo=2, routed)           0.173     3.176    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_3_n_0
    SLICE_X83Y39         LUT5 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.051     3.227 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_1/O
                         net (fo=36, routed)          2.463     5.690    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_1_n_0
    SLICE_X24Y48         LUT6 (Prop_G6LUT_SLICEM_I3_O)
                                                      0.052     5.742 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[24]_INST_0/O
                         net (fo=124, routed)         5.580    11.322    d_1_i/usp_rf_data_converter_0/inst/s_axi_wdata[24]
    SLICE_X113Y235       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/adc3_sample_rate_reg[24]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.161    12.343    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y235       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/adc3_sample_rate_reg[24]/C
                         clock pessimism              0.112    12.455    
                         clock uncertainty           -0.130    12.325    
    SLICE_X113Y235       FDRE (Setup_DFF2_SLICEM_C_D)
                                                      0.025    12.350    d_1_i/usp_rf_data_converter_0/inst/adc3_sample_rate_reg[24]
  -------------------------------------------------------------------
                         required time                         12.350    
                         arrival time                         -11.322    
  -------------------------------------------------------------------
                         slack                                  1.027    

Slack (MET) :             1.047ns  (required time - arrival time)
  Source:                 d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/adc0_ref_clk_freq_reg[24]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        8.751ns  (logic 0.360ns (4.114%)  route 8.391ns (95.886%))
  Logic Levels:           4  (LUT4=1 LUT5=1 LUT6=2)
  Clock Path Skew:        -0.097ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.335ns = ( 12.335 - 10.000 ) 
    Source Clock Delay      (SCD):    2.543ns
    Clock Pessimism Removal (CPR):    0.112ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.317ns (routing 0.662ns, distribution 1.655ns)
  Clock Net Delay (Destination): 2.153ns (routing 0.598ns, distribution 1.555ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.317     2.543    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/clk
    SLICE_X82Y40         FDRE                                         r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y40         FDRE (Prop_FFF2_SLICEM_C_Q)
                                                      0.079     2.622 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/Q
                         net (fo=8, routed)           0.107     2.729    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_data_inst/current_word_1_reg[1]_1[15]
    SLICE_X82Y40         LUT4 (Prop_F6LUT_SLICEM_I1_O)
                                                      0.088     2.817 f  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_data_inst/current_word_1[1]_i_2/O
                         net (fo=4, routed)           0.096     2.914    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/current_word_1_reg[1]
    SLICE_X82Y39         LUT6 (Prop_G6LUT_SLICEM_I5_O)
                                                      0.090     3.004 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_3/O
                         net (fo=2, routed)           0.173     3.176    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_3_n_0
    SLICE_X83Y39         LUT5 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.051     3.227 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_1/O
                         net (fo=36, routed)          2.463     5.690    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_1_n_0
    SLICE_X24Y48         LUT6 (Prop_G6LUT_SLICEM_I3_O)
                                                      0.052     5.742 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[24]_INST_0/O
                         net (fo=124, routed)         5.552    11.295    d_1_i/usp_rf_data_converter_0/inst/s_axi_wdata[24]
    SLICE_X111Y235       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/adc0_ref_clk_freq_reg[24]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.153    12.335    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y235       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/adc0_ref_clk_freq_reg[24]/C
                         clock pessimism              0.112    12.447    
                         clock uncertainty           -0.130    12.317    
    SLICE_X111Y235       FDRE (Setup_GFF2_SLICEL_C_D)
                                                      0.025    12.342    d_1_i/usp_rf_data_converter_0/inst/adc0_ref_clk_freq_reg[24]
  -------------------------------------------------------------------
                         required time                         12.342    
                         arrival time                         -11.295    
  -------------------------------------------------------------------
                         slack                                  1.047    

Slack (MET) :             1.069ns  (required time - arrival time)
  Source:                 d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/adc2_ref_clk_freq_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        8.691ns  (logic 0.433ns (4.982%)  route 8.258ns (95.018%))
  Logic Levels:           4  (LUT4=1 LUT5=1 LUT6=2)
  Clock Path Skew:        -0.136ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.296ns = ( 12.296 - 10.000 ) 
    Source Clock Delay      (SCD):    2.543ns
    Clock Pessimism Removal (CPR):    0.112ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.317ns (routing 0.662ns, distribution 1.655ns)
  Clock Net Delay (Destination): 2.114ns (routing 0.598ns, distribution 1.516ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.317     2.543    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/clk
    SLICE_X82Y40         FDRE                                         r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y40         FDRE (Prop_FFF2_SLICEM_C_Q)
                                                      0.079     2.622 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/Q
                         net (fo=8, routed)           0.107     2.729    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_data_inst/current_word_1_reg[1]_1[15]
    SLICE_X82Y40         LUT4 (Prop_F6LUT_SLICEM_I1_O)
                                                      0.088     2.817 f  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_data_inst/current_word_1[1]_i_2/O
                         net (fo=4, routed)           0.096     2.914    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/current_word_1_reg[1]
    SLICE_X82Y39         LUT6 (Prop_G6LUT_SLICEM_I5_O)
                                                      0.090     3.004 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_3/O
                         net (fo=2, routed)           0.173     3.176    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_3_n_0
    SLICE_X83Y39         LUT5 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.051     3.227 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_1/O
                         net (fo=36, routed)          2.474     5.701    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_1_n_0
    SLICE_X24Y45         LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.125     5.826 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[9]_INST_0/O
                         net (fo=138, routed)         5.408    11.234    d_1_i/usp_rf_data_converter_0/inst/s_axi_wdata[9]
    SLICE_X107Y216       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/adc2_ref_clk_freq_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.114    12.296    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X107Y216       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/adc2_ref_clk_freq_reg[9]/C
                         clock pessimism              0.112    12.408    
                         clock uncertainty           -0.130    12.278    
    SLICE_X107Y216       FDRE (Setup_FFF2_SLICEM_C_D)
                                                      0.025    12.303    d_1_i/usp_rf_data_converter_0/inst/adc2_ref_clk_freq_reg[9]
  -------------------------------------------------------------------
                         required time                         12.303    
                         arrival time                         -11.234    
  -------------------------------------------------------------------
                         slack                                  1.069    

Slack (MET) :             1.082ns  (required time - arrival time)
  Source:                 d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/dac0_ref_clk_freq_reg[24]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        8.726ns  (logic 0.360ns (4.125%)  route 8.366ns (95.874%))
  Logic Levels:           4  (LUT4=1 LUT5=1 LUT6=2)
  Clock Path Skew:        -0.087ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.348ns = ( 12.348 - 10.000 ) 
    Source Clock Delay      (SCD):    2.543ns
    Clock Pessimism Removal (CPR):    0.108ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.317ns (routing 0.662ns, distribution 1.655ns)
  Clock Net Delay (Destination): 2.166ns (routing 0.598ns, distribution 1.568ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.317     2.543    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/clk
    SLICE_X82Y40         FDRE                                         r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y40         FDRE (Prop_FFF2_SLICEM_C_Q)
                                                      0.079     2.622 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/Q
                         net (fo=8, routed)           0.107     2.729    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_data_inst/current_word_1_reg[1]_1[15]
    SLICE_X82Y40         LUT4 (Prop_F6LUT_SLICEM_I1_O)
                                                      0.088     2.817 f  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_data_inst/current_word_1[1]_i_2/O
                         net (fo=4, routed)           0.096     2.914    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/current_word_1_reg[1]
    SLICE_X82Y39         LUT6 (Prop_G6LUT_SLICEM_I5_O)
                                                      0.090     3.004 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_3/O
                         net (fo=2, routed)           0.173     3.176    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_3_n_0
    SLICE_X83Y39         LUT5 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.051     3.227 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_1/O
                         net (fo=36, routed)          2.463     5.690    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_1_n_0
    SLICE_X24Y48         LUT6 (Prop_G6LUT_SLICEM_I3_O)
                                                      0.052     5.742 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[24]_INST_0/O
                         net (fo=124, routed)         5.527    11.270    d_1_i/usp_rf_data_converter_0/inst/s_axi_wdata[24]
    SLICE_X107Y251       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/dac0_ref_clk_freq_reg[24]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.166    12.348    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X107Y251       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/dac0_ref_clk_freq_reg[24]/C
                         clock pessimism              0.108    12.456    
                         clock uncertainty           -0.130    12.326    
    SLICE_X107Y251       FDRE (Setup_DFF2_SLICEM_C_D)
                                                      0.025    12.351    d_1_i/usp_rf_data_converter_0/inst/dac0_ref_clk_freq_reg[24]
  -------------------------------------------------------------------
                         required time                         12.351    
                         arrival time                         -11.270    
  -------------------------------------------------------------------
                         slack                                  1.082    

Slack (MET) :             1.083ns  (required time - arrival time)
  Source:                 d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/adc03_irq_en_reg/D
                            (rising edge-triggered cell FDSE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        8.695ns  (logic 0.458ns (5.268%)  route 8.237ns (94.732%))
  Logic Levels:           4  (LUT4=1 LUT5=1 LUT6=2)
  Clock Path Skew:        -0.117ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.314ns = ( 12.314 - 10.000 ) 
    Source Clock Delay      (SCD):    2.543ns
    Clock Pessimism Removal (CPR):    0.112ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.317ns (routing 0.662ns, distribution 1.655ns)
  Clock Net Delay (Destination): 2.132ns (routing 0.598ns, distribution 1.534ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.317     2.543    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/clk
    SLICE_X82Y40         FDRE                                         r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y40         FDRE (Prop_FFF2_SLICEM_C_Q)
                                                      0.079     2.622 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/Q
                         net (fo=8, routed)           0.107     2.729    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_data_inst/current_word_1_reg[1]_1[15]
    SLICE_X82Y40         LUT4 (Prop_F6LUT_SLICEM_I1_O)
                                                      0.088     2.817 f  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_data_inst/current_word_1[1]_i_2/O
                         net (fo=4, routed)           0.096     2.914    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/current_word_1_reg[1]
    SLICE_X82Y39         LUT6 (Prop_G6LUT_SLICEM_I5_O)
                                                      0.090     3.004 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_3/O
                         net (fo=2, routed)           0.173     3.176    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_3_n_0
    SLICE_X83Y39         LUT5 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.051     3.227 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_1/O
                         net (fo=36, routed)          1.523     4.751    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_1_n_0
    SLICE_X34Y40         LUT6 (Prop_G6LUT_SLICEM_I3_O)
                                                      0.150     4.901 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[3]_INST_0/O
                         net (fo=160, routed)         6.337    11.238    d_1_i/usp_rf_data_converter_0/inst/s_axi_wdata[3]
    SLICE_X112Y214       FDSE                                         r  d_1_i/usp_rf_data_converter_0/inst/adc03_irq_en_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.132    12.314    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X112Y214       FDSE                                         r  d_1_i/usp_rf_data_converter_0/inst/adc03_irq_en_reg/C
                         clock pessimism              0.112    12.426    
                         clock uncertainty           -0.130    12.296    
    SLICE_X112Y214       FDSE (Setup_FFF2_SLICEM_C_D)
                                                      0.025    12.321    d_1_i/usp_rf_data_converter_0/inst/adc03_irq_en_reg
  -------------------------------------------------------------------
                         required time                         12.321    
                         arrival time                         -11.238    
  -------------------------------------------------------------------
                         slack                                  1.083    

Slack (MET) :             1.100ns  (required time - arrival time)
  Source:                 d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/adc1_sample_rate_reg[24]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        8.672ns  (logic 0.360ns (4.151%)  route 8.312ns (95.849%))
  Logic Levels:           4  (LUT4=1 LUT5=1 LUT6=2)
  Clock Path Skew:        -0.123ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.309ns = ( 12.309 - 10.000 ) 
    Source Clock Delay      (SCD):    2.543ns
    Clock Pessimism Removal (CPR):    0.112ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.317ns (routing 0.662ns, distribution 1.655ns)
  Clock Net Delay (Destination): 2.127ns (routing 0.598ns, distribution 1.529ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.317     2.543    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/clk
    SLICE_X82Y40         FDRE                                         r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y40         FDRE (Prop_FFF2_SLICEM_C_Q)
                                                      0.079     2.622 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/Q
                         net (fo=8, routed)           0.107     2.729    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_data_inst/current_word_1_reg[1]_1[15]
    SLICE_X82Y40         LUT4 (Prop_F6LUT_SLICEM_I1_O)
                                                      0.088     2.817 f  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_data_inst/current_word_1[1]_i_2/O
                         net (fo=4, routed)           0.096     2.914    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/current_word_1_reg[1]
    SLICE_X82Y39         LUT6 (Prop_G6LUT_SLICEM_I5_O)
                                                      0.090     3.004 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_3/O
                         net (fo=2, routed)           0.173     3.176    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_3_n_0
    SLICE_X83Y39         LUT5 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.051     3.227 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_1/O
                         net (fo=36, routed)          2.463     5.690    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_1_n_0
    SLICE_X24Y48         LUT6 (Prop_G6LUT_SLICEM_I3_O)
                                                      0.052     5.742 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[24]_INST_0/O
                         net (fo=124, routed)         5.473    11.216    d_1_i/usp_rf_data_converter_0/inst/s_axi_wdata[24]
    SLICE_X107Y232       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/adc1_sample_rate_reg[24]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.127    12.309    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X107Y232       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/adc1_sample_rate_reg[24]/C
                         clock pessimism              0.112    12.421    
                         clock uncertainty           -0.130    12.291    
    SLICE_X107Y232       FDRE (Setup_GFF2_SLICEM_C_D)
                                                      0.025    12.316    d_1_i/usp_rf_data_converter_0/inst/adc1_sample_rate_reg[24]
  -------------------------------------------------------------------
                         required time                         12.316    
                         arrival time                         -11.216    
  -------------------------------------------------------------------
                         slack                                  1.100    

Slack (MET) :             1.103ns  (required time - arrival time)
  Source:                 d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/adc2_sample_rate_reg[24]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        8.693ns  (logic 0.360ns (4.141%)  route 8.333ns (95.859%))
  Logic Levels:           4  (LUT4=1 LUT5=1 LUT6=2)
  Clock Path Skew:        -0.099ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.333ns = ( 12.333 - 10.000 ) 
    Source Clock Delay      (SCD):    2.543ns
    Clock Pessimism Removal (CPR):    0.112ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.317ns (routing 0.662ns, distribution 1.655ns)
  Clock Net Delay (Destination): 2.151ns (routing 0.598ns, distribution 1.553ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.317     2.543    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/clk
    SLICE_X82Y40         FDRE                                         r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y40         FDRE (Prop_FFF2_SLICEM_C_Q)
                                                      0.079     2.622 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/Q
                         net (fo=8, routed)           0.107     2.729    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_data_inst/current_word_1_reg[1]_1[15]
    SLICE_X82Y40         LUT4 (Prop_F6LUT_SLICEM_I1_O)
                                                      0.088     2.817 f  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_data_inst/current_word_1[1]_i_2/O
                         net (fo=4, routed)           0.096     2.914    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/current_word_1_reg[1]
    SLICE_X82Y39         LUT6 (Prop_G6LUT_SLICEM_I5_O)
                                                      0.090     3.004 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_3/O
                         net (fo=2, routed)           0.173     3.176    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_3_n_0
    SLICE_X83Y39         LUT5 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.051     3.227 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_1/O
                         net (fo=36, routed)          2.463     5.690    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_1_n_0
    SLICE_X24Y48         LUT6 (Prop_G6LUT_SLICEM_I3_O)
                                                      0.052     5.742 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[24]_INST_0/O
                         net (fo=124, routed)         5.494    11.237    d_1_i/usp_rf_data_converter_0/inst/s_axi_wdata[24]
    SLICE_X111Y234       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/adc2_sample_rate_reg[24]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.151    12.333    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y234       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/adc2_sample_rate_reg[24]/C
                         clock pessimism              0.112    12.445    
                         clock uncertainty           -0.130    12.315    
    SLICE_X111Y234       FDRE (Setup_BFF_SLICEL_C_D)
                                                      0.025    12.340    d_1_i/usp_rf_data_converter_0/inst/adc2_sample_rate_reg[24]
  -------------------------------------------------------------------
                         required time                         12.340    
                         arrival time                         -11.237    
  -------------------------------------------------------------------
                         slack                                  1.103    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.011ns  (arrival time - required time)
  Source:                 d_1_i/axi_smc/inst/s01_entry_pipeline/s01_mmu/inst/w_sreg/m_vector_i_reg[1158]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27/RAMA/I
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.244ns  (logic 0.059ns (24.180%)  route 0.185ns (75.820%))
  Logic Levels:           0  
  Clock Path Skew:        0.158ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.345ns
    Source Clock Delay      (SCD):    1.999ns
    Clock Pessimism Removal (CPR):    0.188ns
  Clock Net Delay (Source):      1.817ns (routing 0.598ns, distribution 1.219ns)
  Clock Net Delay (Destination): 2.119ns (routing 0.662ns, distribution 1.457ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.817     1.999    d_1_i/axi_smc/inst/s01_entry_pipeline/s01_mmu/inst/w_sreg/aclk
    SLICE_X38Y125        FDRE                                         r  d_1_i/axi_smc/inst/s01_entry_pipeline/s01_mmu/inst/w_sreg/m_vector_i_reg[1158]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X38Y125        FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.059     2.058 r  d_1_i/axi_smc/inst/s01_entry_pipeline/s01_mmu/inst/w_sreg/m_vector_i_reg[1158]/Q
                         net (fo=1, routed)           0.185     2.243    d_1_i/axi_smc/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27/DIA0
    SLICE_X42Y124        RAMD32                                       r  d_1_i/axi_smc/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27/RAMA/I
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.119     2.345    d_1_i/axi_smc/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27/WCLK
    SLICE_X42Y124        RAMD32                                       r  d_1_i/axi_smc/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27/RAMA/CLK
                         clock pessimism             -0.188     2.157    
    SLICE_X42Y124        RAMD32 (Hold_A5LUT_SLICEM_CLK_I)
                                                      0.075     2.232    d_1_i/axi_smc/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27/RAMA
  -------------------------------------------------------------------
                         required time                         -2.232    
                         arrival time                           2.243    
  -------------------------------------------------------------------
                         slack                                  0.011    

Slack (MET) :             0.011ns  (arrival time - required time)
  Source:                 d_1_i/axis_switch_gen/inst/gen_static_router.inst_static_router/inst_axi_ctrl_top/inst_axi_ctrl_write/data_r_reg[14]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_gen/inst/gen_static_router.inst_static_router/inst_axi_ctrl_top/inst_reg_bank_1/gen_reg[5].reg_data_reg[174]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.154ns  (logic 0.059ns (38.259%)  route 0.095ns (61.741%))
  Logic Levels:           0  
  Clock Path Skew:        0.083ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.459ns
    Source Clock Delay      (SCD):    2.172ns
    Clock Pessimism Removal (CPR):    0.204ns
  Clock Net Delay (Source):      1.990ns (routing 0.598ns, distribution 1.392ns)
  Clock Net Delay (Destination): 2.233ns (routing 0.662ns, distribution 1.571ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.990     2.172    d_1_i/axis_switch_gen/inst/gen_static_router.inst_static_router/inst_axi_ctrl_top/inst_axi_ctrl_write/s_axi_ctrl_aclk
    SLICE_X20Y245        FDRE                                         r  d_1_i/axis_switch_gen/inst/gen_static_router.inst_static_router/inst_axi_ctrl_top/inst_axi_ctrl_write/data_r_reg[14]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X20Y245        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.059     2.231 r  d_1_i/axis_switch_gen/inst/gen_static_router.inst_static_router/inst_axi_ctrl_top/inst_axi_ctrl_write/data_r_reg[14]/Q
                         net (fo=9, routed)           0.095     2.326    d_1_i/axis_switch_gen/inst/gen_static_router.inst_static_router/inst_axi_ctrl_top/inst_reg_bank_1/D[14]
    SLICE_X19Y245        FDRE                                         r  d_1_i/axis_switch_gen/inst/gen_static_router.inst_static_router/inst_axi_ctrl_top/inst_reg_bank_1/gen_reg[5].reg_data_reg[174]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.233     2.459    d_1_i/axis_switch_gen/inst/gen_static_router.inst_static_router/inst_axi_ctrl_top/inst_reg_bank_1/s_axi_ctrl_aclk
    SLICE_X19Y245        FDRE                                         r  d_1_i/axis_switch_gen/inst/gen_static_router.inst_static_router/inst_axi_ctrl_top/inst_reg_bank_1/gen_reg[5].reg_data_reg[174]/C
                         clock pessimism             -0.204     2.255    
    SLICE_X19Y245        FDRE (Hold_GFF_SLICEL_C_D)
                                                      0.060     2.315    d_1_i/axis_switch_gen/inst/gen_static_router.inst_static_router/inst_axi_ctrl_top/inst_reg_bank_1/gen_reg[5].reg_data_reg[174]
  -------------------------------------------------------------------
                         required time                         -2.315    
                         arrival time                           2.326    
  -------------------------------------------------------------------
                         slack                                  0.011    

Slack (MET) :             0.011ns  (arrival time - required time)
  Source:                 d_1_i/axi_smc/inst/s05_nodes/s05_w_node/inst/inst_mi_handler/gen_normal_area.gen_upsizer.inst_upsizer/gen_w_ch.accum_reg[bytes][2][userdata][1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/s05_nodes/s05_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAME/I
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.243ns  (logic 0.059ns (24.280%)  route 0.184ns (75.720%))
  Logic Levels:           0  
  Clock Path Skew:        0.155ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.370ns
    Source Clock Delay      (SCD):    2.021ns
    Clock Pessimism Removal (CPR):    0.195ns
  Clock Net Delay (Source):      1.839ns (routing 0.598ns, distribution 1.241ns)
  Clock Net Delay (Destination): 2.144ns (routing 0.662ns, distribution 1.482ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.839     2.021    d_1_i/axi_smc/inst/s05_nodes/s05_w_node/inst/inst_mi_handler/gen_normal_area.gen_upsizer.inst_upsizer/s_sc_aclk
    SLICE_X50Y113        FDRE                                         r  d_1_i/axi_smc/inst/s05_nodes/s05_w_node/inst/inst_mi_handler/gen_normal_area.gen_upsizer.inst_upsizer/gen_w_ch.accum_reg[bytes][2][userdata][1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X50Y113        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.059     2.080 r  d_1_i/axi_smc/inst/s05_nodes/s05_w_node/inst/inst_mi_handler/gen_normal_area.gen_upsizer.inst_upsizer/gen_w_ch.accum_reg[bytes][2][userdata][1]/Q
                         net (fo=1, routed)           0.184     2.264    d_1_i/axi_smc/inst/s05_nodes/s05_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/DIE0
    SLICE_X46Y113        RAMD32                                       r  d_1_i/axi_smc/inst/s05_nodes/s05_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAME/I
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.144     2.370    d_1_i/axi_smc/inst/s05_nodes/s05_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/WCLK
    SLICE_X46Y113        RAMD32                                       r  d_1_i/axi_smc/inst/s05_nodes/s05_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAME/CLK
                         clock pessimism             -0.195     2.175    
    SLICE_X46Y113        RAMD32 (Hold_E5LUT_SLICEM_CLK_I)
                                                      0.077     2.252    d_1_i/axi_smc/inst/s05_nodes/s05_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAME
  -------------------------------------------------------------------
                         required time                         -2.252    
                         arrival time                           2.264    
  -------------------------------------------------------------------
                         slack                                  0.011    

Slack (MET) :             0.012ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/m25_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/r.r_pipe/m_payload_i_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_data_inst/WORD_LANE[0].S_AXI_RDATA_II_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.171ns  (logic 0.059ns (34.532%)  route 0.112ns (65.468%))
  Logic Levels:           0  
  Clock Path Skew:        0.097ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.555ns
    Source Clock Delay      (SCD):    2.239ns
    Clock Pessimism Removal (CPR):    0.219ns
  Clock Net Delay (Source):      2.057ns (routing 0.598ns, distribution 1.459ns)
  Clock Net Delay (Destination): 2.329ns (routing 0.662ns, distribution 1.667ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.057     2.239    d_1_i/ps8_0_axi_periph/m25_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/r.r_pipe/aclk
    SLICE_X81Y11         FDRE                                         r  d_1_i/ps8_0_axi_periph/m25_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/r.r_pipe/m_payload_i_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y11         FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.059     2.298 r  d_1_i/ps8_0_axi_periph/m25_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/r.r_pipe/m_payload_i_reg[3]/Q
                         net (fo=8, routed)           0.112     2.410    d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_data_inst/m_axi_rdata[3]
    SLICE_X82Y9          FDRE                                         r  d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_data_inst/WORD_LANE[0].S_AXI_RDATA_II_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.329     2.555    d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_data_inst/CLK
    SLICE_X82Y9          FDRE                                         r  d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_data_inst/WORD_LANE[0].S_AXI_RDATA_II_reg[3]/C
                         clock pessimism             -0.219     2.336    
    SLICE_X82Y9          FDRE (Hold_HFF2_SLICEM_C_D)
                                                      0.062     2.398    d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_data_inst/WORD_LANE[0].S_AXI_RDATA_II_reg[3]
  -------------------------------------------------------------------
                         required time                         -2.398    
                         arrival time                           2.410    
  -------------------------------------------------------------------
                         slack                                  0.012    

Slack (MET) :             0.014ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/i02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/queue_id_reg[14]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_master_slots[2].reg_slice_mi/b.b_pipe/m_payload_i_reg[16]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.187ns  (logic 0.058ns (31.096%)  route 0.129ns (68.904%))
  Logic Levels:           0  
  Clock Path Skew:        0.111ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.401ns
    Source Clock Delay      (SCD):    2.083ns
    Clock Pessimism Removal (CPR):    0.207ns
  Clock Net Delay (Source):      1.901ns (routing 0.598ns, distribution 1.303ns)
  Clock Net Delay (Destination): 2.175ns (routing 0.662ns, distribution 1.513ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.901     2.083    d_1_i/ps8_0_axi_periph/i02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/CLK
    SLICE_X33Y6          FDRE                                         r  d_1_i/ps8_0_axi_periph/i02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/queue_id_reg[14]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X33Y6          FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.058     2.141 r  d_1_i/ps8_0_axi_periph/i02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/queue_id_reg[14]/Q
                         net (fo=2, routed)           0.129     2.269    d_1_i/ps8_0_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_master_slots[2].reg_slice_mi/b.b_pipe/m_payload_i_reg[17]_1[16]
    SLICE_X32Y6          FDRE                                         r  d_1_i/ps8_0_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_master_slots[2].reg_slice_mi/b.b_pipe/m_payload_i_reg[16]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.175     2.401    d_1_i/ps8_0_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_master_slots[2].reg_slice_mi/b.b_pipe/aclk
    SLICE_X32Y6          FDRE                                         r  d_1_i/ps8_0_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_master_slots[2].reg_slice_mi/b.b_pipe/m_payload_i_reg[16]/C
                         clock pessimism             -0.207     2.194    
    SLICE_X32Y6          FDRE (Hold_DFF2_SLICEL_C_D)
                                                      0.062     2.256    d_1_i/ps8_0_axi_periph/xbar/inst/gen_samd.crossbar_samd/gen_master_slots[2].reg_slice_mi/b.b_pipe/m_payload_i_reg[16]
  -------------------------------------------------------------------
                         required time                         -2.256    
                         arrival time                           2.269    
  -------------------------------------------------------------------
                         slack                                  0.014    

Slack (MET) :             0.014ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_depth_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_depth_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.177ns  (logic 0.081ns (45.775%)  route 0.096ns (54.225%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        0.103ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.443ns
    Source Clock Delay      (SCD):    2.132ns
    Clock Pessimism Removal (CPR):    0.208ns
  Clock Net Delay (Source):      1.950ns (routing 0.598ns, distribution 1.352ns)
  Clock Net Delay (Destination): 2.217ns (routing 0.662ns, distribution 1.555ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.950     2.132    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/CLK
    SLICE_X74Y24         FDRE                                         r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_depth_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y24         FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.058     2.190 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_depth_reg[2]/Q
                         net (fo=6, routed)           0.071     2.261    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/Q[2]
    SLICE_X75Y24         LUT5 (Prop_A6LUT_SLICEM_I2_O)
                                                      0.023     2.284 r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/cmd_depth[5]_i_2/O
                         net (fo=1, routed)           0.025     2.309    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue_n_33
    SLICE_X75Y24         FDRE                                         r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_depth_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.217     2.443    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/CLK
    SLICE_X75Y24         FDRE                                         r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_depth_reg[5]/C
                         clock pessimism             -0.208     2.235    
    SLICE_X75Y24         FDRE (Hold_AFF_SLICEM_C_D)
                                                      0.060     2.295    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_depth_reg[5]
  -------------------------------------------------------------------
                         required time                         -2.295    
                         arrival time                           2.309    
  -------------------------------------------------------------------
                         slack                                  0.014    

Slack (MET) :             0.014ns  (arrival time - required time)
  Source:                 d_1_i/axi_dma_mr/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_xfer_addr_reg_reg[15]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_dma_mr/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][39]_srl4/D
                            (rising edge-triggered cell SRL16E clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.211ns  (logic 0.057ns (27.014%)  route 0.154ns (72.986%))
  Logic Levels:           0  
  Clock Path Skew:        0.142ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.490ns
    Source Clock Delay      (SCD):    2.146ns
    Clock Pessimism Removal (CPR):    0.203ns
  Clock Net Delay (Source):      1.964ns (routing 0.598ns, distribution 1.366ns)
  Clock Net Delay (Destination): 2.264ns (routing 0.662ns, distribution 1.602ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.964     2.146    d_1_i/axi_dma_mr/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/m_axi_s2mm_aclk
    SLICE_X75Y63         FDRE                                         r  d_1_i/axi_dma_mr/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_xfer_addr_reg_reg[15]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X75Y63         FDRE (Prop_FFF_SLICEM_C_Q)
                                                      0.057     2.203 r  d_1_i/axi_dma_mr/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_xfer_addr_reg_reg[15]/Q
                         net (fo=1, routed)           0.154     2.357    d_1_i/axi_dma_mr/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/in[15]
    SLICE_X72Y63         SRL16E                                       r  d_1_i/axi_dma_mr/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][39]_srl4/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.264     2.490    d_1_i/axi_dma_mr/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/m_axi_s2mm_aclk
    SLICE_X72Y63         SRL16E                                       r  d_1_i/axi_dma_mr/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][39]_srl4/CLK
                         clock pessimism             -0.203     2.288    
    SLICE_X72Y63         SRL16E (Hold_A5LUT_SLICEM_CLK_D)
                                                      0.055     2.343    d_1_i/axi_dma_mr/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][39]_srl4
  -------------------------------------------------------------------
                         required time                         -2.343    
                         arrival time                           2.357    
  -------------------------------------------------------------------
                         slack                                  0.014    

Slack (MET) :             0.014ns  (arrival time - required time)
  Source:                 d_1_i/axi_smc/inst/s01_entry_pipeline/s01_mmu/inst/w_sreg/m_vector_i_reg[1125]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139/RAMB_D1/I
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.313ns  (logic 0.059ns (18.850%)  route 0.254ns (81.150%))
  Logic Levels:           0  
  Clock Path Skew:        0.239ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.381ns
    Source Clock Delay      (SCD):    2.012ns
    Clock Pessimism Removal (CPR):    0.131ns
  Clock Net Delay (Source):      1.830ns (routing 0.598ns, distribution 1.232ns)
  Clock Net Delay (Destination): 2.155ns (routing 0.662ns, distribution 1.493ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.830     2.012    d_1_i/axi_smc/inst/s01_entry_pipeline/s01_mmu/inst/w_sreg/aclk
    SLICE_X52Y132        FDRE                                         r  d_1_i/axi_smc/inst/s01_entry_pipeline/s01_mmu/inst/w_sreg/m_vector_i_reg[1125]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y132        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.059     2.071 r  d_1_i/axi_smc/inst/s01_entry_pipeline/s01_mmu/inst/w_sreg/m_vector_i_reg[1125]/Q
                         net (fo=1, routed)           0.254     2.325    d_1_i/axi_smc/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139/DIB1
    SLICE_X54Y117        RAMD32                                       r  d_1_i/axi_smc/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139/RAMB_D1/I
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.155     2.381    d_1_i/axi_smc/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139/WCLK
    SLICE_X54Y117        RAMD32                                       r  d_1_i/axi_smc/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139/RAMB_D1/CLK
                         clock pessimism             -0.131     2.250    
    SLICE_X54Y117        RAMD32 (Hold_B6LUT_SLICEM_CLK_I)
                                                      0.060     2.310    d_1_i/axi_smc/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139/RAMB_D1
  -------------------------------------------------------------------
                         required time                         -2.310    
                         arrival time                           2.325    
  -------------------------------------------------------------------
                         slack                                  0.014    

Slack (MET) :             0.015ns  (arrival time - required time)
  Source:                 d_1_i/axi_smc/inst/s04_nodes/s04_w_node/inst/inst_mi_handler/gen_normal_area.gen_upsizer.inst_upsizer/gen_w_ch.accum_reg[bytes][9][userdata][3]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/s04_nodes/s04_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111/RAMB_D1/I
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.231ns  (logic 0.061ns (26.407%)  route 0.170ns (73.593%))
  Logic Levels:           0  
  Clock Path Skew:        0.156ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.359ns
    Source Clock Delay      (SCD):    2.008ns
    Clock Pessimism Removal (CPR):    0.195ns
  Clock Net Delay (Source):      1.826ns (routing 0.598ns, distribution 1.228ns)
  Clock Net Delay (Destination): 2.133ns (routing 0.662ns, distribution 1.471ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.826     2.008    d_1_i/axi_smc/inst/s04_nodes/s04_w_node/inst/inst_mi_handler/gen_normal_area.gen_upsizer.inst_upsizer/s_sc_aclk
    SLICE_X38Y113        FDRE                                         r  d_1_i/axi_smc/inst/s04_nodes/s04_w_node/inst/inst_mi_handler/gen_normal_area.gen_upsizer.inst_upsizer/gen_w_ch.accum_reg[bytes][9][userdata][3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X38Y113        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.061     2.069 r  d_1_i/axi_smc/inst/s04_nodes/s04_w_node/inst/inst_mi_handler/gen_normal_area.gen_upsizer.inst_upsizer/gen_w_ch.accum_reg[bytes][9][userdata][3]/Q
                         net (fo=1, routed)           0.170     2.239    d_1_i/axi_smc/inst/s04_nodes/s04_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111/DIB1
    SLICE_X39Y112        RAMD32                                       r  d_1_i/axi_smc/inst/s04_nodes/s04_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111/RAMB_D1/I
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.133     2.359    d_1_i/axi_smc/inst/s04_nodes/s04_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111/WCLK
    SLICE_X39Y112        RAMD32                                       r  d_1_i/axi_smc/inst/s04_nodes/s04_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111/RAMB_D1/CLK
                         clock pessimism             -0.195     2.164    
    SLICE_X39Y112        RAMD32 (Hold_B6LUT_SLICEM_CLK_I)
                                                      0.060     2.224    d_1_i/axi_smc/inst/s04_nodes/s04_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111/RAMB_D1
  -------------------------------------------------------------------
                         required time                         -2.224    
                         arrival time                           2.239    
  -------------------------------------------------------------------
                         slack                                  0.015    

Slack (MET) :             0.015ns  (arrival time - required time)
  Source:                 d_1_i/axi_dma_tproc/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SINGLE_REG.sig_regfifo_dout_reg_reg[62]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_dma_tproc/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_input_addr_reg_reg[27]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.272ns  (logic 0.060ns (22.059%)  route 0.212ns (77.941%))
  Logic Levels:           0  
  Clock Path Skew:        0.195ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.418ns
    Source Clock Delay      (SCD):    2.025ns
    Clock Pessimism Removal (CPR):    0.198ns
  Clock Net Delay (Source):      1.843ns (routing 0.598ns, distribution 1.245ns)
  Clock Net Delay (Destination): 2.192ns (routing 0.662ns, distribution 1.530ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.843     2.025    d_1_i/axi_dma_tproc/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/m_axi_s2mm_aclk
    SLICE_X58Y72         FDRE                                         r  d_1_i/axi_dma_tproc/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SINGLE_REG.sig_regfifo_dout_reg_reg[62]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X58Y72         FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.060     2.085 r  d_1_i/axi_dma_tproc/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SINGLE_REG.sig_regfifo_dout_reg_reg[62]/Q
                         net (fo=1, routed)           0.212     2.297    d_1_i/axi_dma_tproc/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/Q[55]
    SLICE_X68Y74         FDRE                                         r  d_1_i/axi_dma_tproc/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_input_addr_reg_reg[27]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.192     2.418    d_1_i/axi_dma_tproc/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/m_axi_s2mm_aclk
    SLICE_X68Y74         FDRE                                         r  d_1_i/axi_dma_tproc/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_input_addr_reg_reg[27]/C
                         clock pessimism             -0.198     2.220    
    SLICE_X68Y74         FDRE (Hold_BFF2_SLICEL_C_D)
                                                      0.062     2.282    d_1_i/axi_dma_tproc/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_input_addr_reg_reg[27]
  -------------------------------------------------------------------
                         required time                         -2.282    
                         arrival time                           2.297    
  -------------------------------------------------------------------
                         slack                                  0.015    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         clk_pl_0
Waveform(ns):       { 0.000 5.000 }
Period(ns):         10.000
Sources:            { d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0] }

Check Type        Corner  Lib Pin           Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location    Pin
Min Period        n/a     HSADC/DCLK        n/a            4.000         10.000      6.000      HSADC_X0Y0  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/DCLK
Min Period        n/a     HSADC/DCLK        n/a            4.000         10.000      6.000      HSADC_X0Y1  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/DCLK
Min Period        n/a     HSADC/DCLK        n/a            4.000         10.000      6.000      HSADC_X0Y2  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/DCLK
Min Period        n/a     HSADC/DCLK        n/a            4.000         10.000      6.000      HSADC_X0Y3  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/DCLK
Min Period        n/a     HSDAC/DCLK        n/a            4.000         10.000      6.000      HSDAC_X0Y0  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/DCLK
Min Period        n/a     HSDAC/DCLK        n/a            4.000         10.000      6.000      HSDAC_X0Y1  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/DCLK
Min Period        n/a     PS8/MAXIGP0ACLK   n/a            3.000         10.000      7.000      PS8_X0Y0    d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0ACLK
Min Period        n/a     PS8/SAXIGP0RCLK   n/a            3.000         10.000      7.000      PS8_X0Y0    d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/SAXIGP0RCLK
Min Period        n/a     PS8/SAXIGP0WCLK   n/a            3.000         10.000      7.000      PS8_X0Y0    d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/SAXIGP0WCLK
Min Period        n/a     HSADC/PLL_MONCLK  n/a            2.500         10.000      7.500      HSADC_X0Y0  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/PLL_MONCLK
Low Pulse Width   Slow    HSADC/DCLK        n/a            1.600         5.000       3.400      HSADC_X0Y0  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/DCLK
Low Pulse Width   Fast    HSADC/DCLK        n/a            1.600         5.000       3.400      HSADC_X0Y0  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/DCLK
Low Pulse Width   Slow    HSADC/DCLK        n/a            1.600         5.000       3.400      HSADC_X0Y1  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/DCLK
Low Pulse Width   Fast    HSADC/DCLK        n/a            1.600         5.000       3.400      HSADC_X0Y1  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/DCLK
Low Pulse Width   Slow    HSADC/DCLK        n/a            1.600         5.000       3.400      HSADC_X0Y2  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/DCLK
Low Pulse Width   Fast    HSADC/DCLK        n/a            1.600         5.000       3.400      HSADC_X0Y2  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/DCLK
Low Pulse Width   Slow    HSADC/DCLK        n/a            1.600         5.000       3.400      HSADC_X0Y3  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/DCLK
Low Pulse Width   Fast    HSADC/DCLK        n/a            1.600         5.000       3.400      HSADC_X0Y3  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/DCLK
Low Pulse Width   Slow    HSDAC/DCLK        n/a            1.600         5.000       3.400      HSDAC_X0Y0  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/DCLK
Low Pulse Width   Fast    HSDAC/DCLK        n/a            1.600         5.000       3.400      HSDAC_X0Y0  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/DCLK
High Pulse Width  Slow    HSADC/DCLK        n/a            1.600         5.000       3.400      HSADC_X0Y0  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/DCLK
High Pulse Width  Fast    HSADC/DCLK        n/a            1.600         5.000       3.400      HSADC_X0Y0  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/DCLK
High Pulse Width  Slow    HSADC/DCLK        n/a            1.600         5.000       3.400      HSADC_X0Y1  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/DCLK
High Pulse Width  Fast    HSADC/DCLK        n/a            1.600         5.000       3.400      HSADC_X0Y1  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/DCLK
High Pulse Width  Slow    HSADC/DCLK        n/a            1.600         5.000       3.400      HSADC_X0Y2  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/DCLK
High Pulse Width  Fast    HSADC/DCLK        n/a            1.600         5.000       3.400      HSADC_X0Y2  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/DCLK
High Pulse Width  Slow    HSADC/DCLK        n/a            1.600         5.000       3.400      HSADC_X0Y3  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/DCLK
High Pulse Width  Fast    HSADC/DCLK        n/a            1.600         5.000       3.400      HSADC_X0Y3  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/DCLK
High Pulse Width  Slow    HSDAC/DCLK        n/a            1.600         5.000       3.400      HSDAC_X0Y0  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/DCLK
High Pulse Width  Fast    HSDAC/DCLK        n/a            1.600         5.000       3.400      HSDAC_X0Y0  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/DCLK



---------------------------------------------------------------------------------------------------
From Clock:  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  To Clock:  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK

Setup :            0  Failing Endpoints,  Worst Slack       10.588ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.030ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack       24.468ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             10.588ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/iTDO_reg/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TDO
                            (falling edge-triggered cell BSCANE2 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            25.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall@25.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        3.390ns  (logic 0.214ns (6.313%)  route 3.176ns (93.687%))
  Logic Levels:           2  (LUT3=1 LUT6=1)
  Clock Path Skew:        -10.787ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.000ns = ( 25.000 - 25.000 ) 
    Source Clock Delay      (SCD):    10.787ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Source):      2.893ns (routing 1.680ns, distribution 1.213ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.566     7.866    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.894 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.893    10.787    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/m_bscan_tck[0]
    SLICE_X111Y327       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/iTDO_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X111Y327       FDRE (Prop_BFF2_SLICEL_C_Q)
                                                      0.080    10.867 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/iTDO_reg/Q
                         net (fo=1, routed)           2.058    12.925    dbg_hub/inst/BSCANID.u_xsdbm_id/TDO
    SLICE_X106Y115       LUT3 (Prop_F6LUT_SLICEL_I2_O)
                                                      0.097    13.022 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch_i_1/O
                         net (fo=2, routed)           0.215    13.237    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_tdo[0]
    SLICE_X107Y114       LUT6 (Prop_C6LUT_SLICEM_I5_O)
                                                      0.037    13.274 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tdo_INST_0/O
                         net (fo=1, routed)           0.903    14.177    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/TDO
    CONFIG_SITE_X0Y0     BSCANE2                                      r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TDO
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall edge)
                                                     25.000    25.000 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    25.000 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
                         clock pessimism              0.000    25.000    
                         clock uncertainty           -0.235    24.765    
    CONFIG_SITE_X0Y0     BSCANE2 (Setup_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TDO)
                                                      0.000    24.765    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst
  -------------------------------------------------------------------
                         required time                         24.765    
                         arrival time                         -14.177    
  -------------------------------------------------------------------
                         slack                                 10.588    

Slack (MET) :             21.436ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
                            (falling edge-triggered cell BSCANE2 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[0]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Fast Process Corner)
  Requirement:            25.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall@25.000ns)
  Data Path Delay:        7.224ns  (logic 5.305ns (73.439%)  route 1.919ns (26.561%))
  Logic Levels:           3  (LUT4=1 LUT5=2)
  Clock Path Skew:        3.940ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.940ns = ( 53.940 - 50.000 ) 
    Source Clock Delay      (SCD):    0.000ns = ( 25.000 - 25.000 ) 
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Destination): 1.597ns (routing 0.916ns, distribution 0.681ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall edge)
                                                     25.000    25.000 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    25.000 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_SHIFT)
                                                      5.100    30.100 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/SHIFT
                         net (fo=37, routed)          0.361    30.461    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_shift
    SLICE_X107Y114       LUT5 (Prop_A6LUT_SLICEM_I4_O)
                                                      0.077    30.538 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_shift[0]_INST_0/O
                         net (fo=4, routed)           1.341    31.879    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/icn_cmd_en_reg[7]
    SLICE_X113Y327       LUT4 (Prop_C6LUT_SLICEM_I1_O)
                                                      0.076    31.955 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_4/O
                         net (fo=1, routed)           0.062    32.017    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_4_n_0
    SLICE_X113Y327       LUT5 (Prop_D6LUT_SLICEM_I4_O)
                                                      0.052    32.069 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_1/O
                         net (fo=6, routed)           0.155    32.224    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/SR[0]
    SLICE_X115Y327       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[0]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.861    52.326    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017    52.343 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.597    53.940    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/m_bscan_tck[0]
    SLICE_X115Y327       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[0]/C
                         clock pessimism              0.000    53.940    
                         clock uncertainty           -0.235    53.704    
    SLICE_X115Y327       FDRE (Setup_BFF2_SLICEM_C_R)
                                                     -0.044    53.660    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[0]
  -------------------------------------------------------------------
                         required time                         53.660    
                         arrival time                         -32.224    
  -------------------------------------------------------------------
                         slack                                 21.436    

Slack (MET) :             21.436ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
                            (falling edge-triggered cell BSCANE2 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[1]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Fast Process Corner)
  Requirement:            25.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall@25.000ns)
  Data Path Delay:        7.224ns  (logic 5.305ns (73.439%)  route 1.919ns (26.561%))
  Logic Levels:           3  (LUT4=1 LUT5=2)
  Clock Path Skew:        3.940ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.940ns = ( 53.940 - 50.000 ) 
    Source Clock Delay      (SCD):    0.000ns = ( 25.000 - 25.000 ) 
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Destination): 1.597ns (routing 0.916ns, distribution 0.681ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall edge)
                                                     25.000    25.000 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    25.000 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_SHIFT)
                                                      5.100    30.100 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/SHIFT
                         net (fo=37, routed)          0.361    30.461    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_shift
    SLICE_X107Y114       LUT5 (Prop_A6LUT_SLICEM_I4_O)
                                                      0.077    30.538 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_shift[0]_INST_0/O
                         net (fo=4, routed)           1.341    31.879    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/icn_cmd_en_reg[7]
    SLICE_X113Y327       LUT4 (Prop_C6LUT_SLICEM_I1_O)
                                                      0.076    31.955 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_4/O
                         net (fo=1, routed)           0.062    32.017    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_4_n_0
    SLICE_X113Y327       LUT5 (Prop_D6LUT_SLICEM_I4_O)
                                                      0.052    32.069 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_1/O
                         net (fo=6, routed)           0.155    32.224    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/SR[0]
    SLICE_X115Y327       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[1]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.861    52.326    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017    52.343 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.597    53.940    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/m_bscan_tck[0]
    SLICE_X115Y327       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[1]/C
                         clock pessimism              0.000    53.940    
                         clock uncertainty           -0.235    53.704    
    SLICE_X115Y327       FDRE (Setup_DFF_SLICEM_C_R)
                                                     -0.044    53.660    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[1]
  -------------------------------------------------------------------
                         required time                         53.660    
                         arrival time                         -32.224    
  -------------------------------------------------------------------
                         slack                                 21.436    

Slack (MET) :             21.436ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
                            (falling edge-triggered cell BSCANE2 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[2]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Fast Process Corner)
  Requirement:            25.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall@25.000ns)
  Data Path Delay:        7.224ns  (logic 5.305ns (73.439%)  route 1.919ns (26.561%))
  Logic Levels:           3  (LUT4=1 LUT5=2)
  Clock Path Skew:        3.940ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.940ns = ( 53.940 - 50.000 ) 
    Source Clock Delay      (SCD):    0.000ns = ( 25.000 - 25.000 ) 
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Destination): 1.597ns (routing 0.916ns, distribution 0.681ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall edge)
                                                     25.000    25.000 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    25.000 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_SHIFT)
                                                      5.100    30.100 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/SHIFT
                         net (fo=37, routed)          0.361    30.461    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_shift
    SLICE_X107Y114       LUT5 (Prop_A6LUT_SLICEM_I4_O)
                                                      0.077    30.538 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_shift[0]_INST_0/O
                         net (fo=4, routed)           1.341    31.879    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/icn_cmd_en_reg[7]
    SLICE_X113Y327       LUT4 (Prop_C6LUT_SLICEM_I1_O)
                                                      0.076    31.955 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_4/O
                         net (fo=1, routed)           0.062    32.017    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_4_n_0
    SLICE_X113Y327       LUT5 (Prop_D6LUT_SLICEM_I4_O)
                                                      0.052    32.069 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_1/O
                         net (fo=6, routed)           0.155    32.224    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/SR[0]
    SLICE_X115Y327       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[2]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.861    52.326    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017    52.343 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.597    53.940    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/m_bscan_tck[0]
    SLICE_X115Y327       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[2]/C
                         clock pessimism              0.000    53.940    
                         clock uncertainty           -0.235    53.704    
    SLICE_X115Y327       FDRE (Setup_DFF2_SLICEM_C_R)
                                                     -0.044    53.660    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[2]
  -------------------------------------------------------------------
                         required time                         53.660    
                         arrival time                         -32.224    
  -------------------------------------------------------------------
                         slack                                 21.436    

Slack (MET) :             21.436ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
                            (falling edge-triggered cell BSCANE2 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[3]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Fast Process Corner)
  Requirement:            25.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall@25.000ns)
  Data Path Delay:        7.224ns  (logic 5.305ns (73.439%)  route 1.919ns (26.561%))
  Logic Levels:           3  (LUT4=1 LUT5=2)
  Clock Path Skew:        3.940ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.940ns = ( 53.940 - 50.000 ) 
    Source Clock Delay      (SCD):    0.000ns = ( 25.000 - 25.000 ) 
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Destination): 1.597ns (routing 0.916ns, distribution 0.681ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall edge)
                                                     25.000    25.000 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    25.000 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_SHIFT)
                                                      5.100    30.100 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/SHIFT
                         net (fo=37, routed)          0.361    30.461    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_shift
    SLICE_X107Y114       LUT5 (Prop_A6LUT_SLICEM_I4_O)
                                                      0.077    30.538 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_shift[0]_INST_0/O
                         net (fo=4, routed)           1.341    31.879    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/icn_cmd_en_reg[7]
    SLICE_X113Y327       LUT4 (Prop_C6LUT_SLICEM_I1_O)
                                                      0.076    31.955 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_4/O
                         net (fo=1, routed)           0.062    32.017    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_4_n_0
    SLICE_X113Y327       LUT5 (Prop_D6LUT_SLICEM_I4_O)
                                                      0.052    32.069 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_1/O
                         net (fo=6, routed)           0.155    32.224    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/SR[0]
    SLICE_X115Y327       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[3]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.861    52.326    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017    52.343 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.597    53.940    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/m_bscan_tck[0]
    SLICE_X115Y327       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[3]/C
                         clock pessimism              0.000    53.940    
                         clock uncertainty           -0.235    53.704    
    SLICE_X115Y327       FDRE (Setup_CFF_SLICEM_C_R)
                                                     -0.044    53.660    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[3]
  -------------------------------------------------------------------
                         required time                         53.660    
                         arrival time                         -32.224    
  -------------------------------------------------------------------
                         slack                                 21.436    

Slack (MET) :             21.436ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
                            (falling edge-triggered cell BSCANE2 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[4]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Fast Process Corner)
  Requirement:            25.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall@25.000ns)
  Data Path Delay:        7.224ns  (logic 5.305ns (73.439%)  route 1.919ns (26.561%))
  Logic Levels:           3  (LUT4=1 LUT5=2)
  Clock Path Skew:        3.940ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.940ns = ( 53.940 - 50.000 ) 
    Source Clock Delay      (SCD):    0.000ns = ( 25.000 - 25.000 ) 
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Destination): 1.597ns (routing 0.916ns, distribution 0.681ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall edge)
                                                     25.000    25.000 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    25.000 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_SHIFT)
                                                      5.100    30.100 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/SHIFT
                         net (fo=37, routed)          0.361    30.461    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_shift
    SLICE_X107Y114       LUT5 (Prop_A6LUT_SLICEM_I4_O)
                                                      0.077    30.538 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_shift[0]_INST_0/O
                         net (fo=4, routed)           1.341    31.879    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/icn_cmd_en_reg[7]
    SLICE_X113Y327       LUT4 (Prop_C6LUT_SLICEM_I1_O)
                                                      0.076    31.955 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_4/O
                         net (fo=1, routed)           0.062    32.017    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_4_n_0
    SLICE_X113Y327       LUT5 (Prop_D6LUT_SLICEM_I4_O)
                                                      0.052    32.069 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_1/O
                         net (fo=6, routed)           0.155    32.224    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/SR[0]
    SLICE_X115Y327       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[4]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.861    52.326    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017    52.343 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.597    53.940    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/m_bscan_tck[0]
    SLICE_X115Y327       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[4]/C
                         clock pessimism              0.000    53.940    
                         clock uncertainty           -0.235    53.704    
    SLICE_X115Y327       FDRE (Setup_CFF2_SLICEM_C_R)
                                                     -0.044    53.660    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[4]
  -------------------------------------------------------------------
                         required time                         53.660    
                         arrival time                         -32.224    
  -------------------------------------------------------------------
                         slack                                 21.436    

Slack (MET) :             21.436ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
                            (falling edge-triggered cell BSCANE2 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[5]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Fast Process Corner)
  Requirement:            25.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall@25.000ns)
  Data Path Delay:        7.224ns  (logic 5.305ns (73.439%)  route 1.919ns (26.561%))
  Logic Levels:           3  (LUT4=1 LUT5=2)
  Clock Path Skew:        3.940ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.940ns = ( 53.940 - 50.000 ) 
    Source Clock Delay      (SCD):    0.000ns = ( 25.000 - 25.000 ) 
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Destination): 1.597ns (routing 0.916ns, distribution 0.681ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall edge)
                                                     25.000    25.000 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    25.000 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_SHIFT)
                                                      5.100    30.100 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/SHIFT
                         net (fo=37, routed)          0.361    30.461    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_shift
    SLICE_X107Y114       LUT5 (Prop_A6LUT_SLICEM_I4_O)
                                                      0.077    30.538 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_shift[0]_INST_0/O
                         net (fo=4, routed)           1.341    31.879    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/icn_cmd_en_reg[7]
    SLICE_X113Y327       LUT4 (Prop_C6LUT_SLICEM_I1_O)
                                                      0.076    31.955 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_4/O
                         net (fo=1, routed)           0.062    32.017    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_4_n_0
    SLICE_X113Y327       LUT5 (Prop_D6LUT_SLICEM_I4_O)
                                                      0.052    32.069 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_1/O
                         net (fo=6, routed)           0.155    32.224    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/SR[0]
    SLICE_X115Y327       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[5]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.861    52.326    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017    52.343 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.597    53.940    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/m_bscan_tck[0]
    SLICE_X115Y327       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[5]/C
                         clock pessimism              0.000    53.940    
                         clock uncertainty           -0.235    53.704    
    SLICE_X115Y327       FDRE (Setup_AFF_SLICEM_C_R)
                                                     -0.044    53.660    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[5]
  -------------------------------------------------------------------
                         required time                         53.660    
                         arrival time                         -32.224    
  -------------------------------------------------------------------
                         slack                                 21.436    

Slack (MET) :             21.519ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
                            (falling edge-triggered cell BSCANE2 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/icn_cmd_en_reg[4]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Fast Process Corner)
  Requirement:            25.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall@25.000ns)
  Data Path Delay:        7.138ns  (logic 5.267ns (73.792%)  route 1.871ns (26.208%))
  Logic Levels:           2  (LUT4=1 LUT5=1)
  Clock Path Skew:        3.937ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.937ns = ( 53.937 - 50.000 ) 
    Source Clock Delay      (SCD):    0.000ns = ( 25.000 - 25.000 ) 
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Destination): 1.594ns (routing 0.916ns, distribution 0.678ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall edge)
                                                     25.000    25.000 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    25.000 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_SHIFT)
                                                      5.100    30.100 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/SHIFT
                         net (fo=37, routed)          0.361    30.461    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_shift
    SLICE_X107Y114       LUT5 (Prop_A6LUT_SLICEM_I4_O)
                                                      0.077    30.538 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_shift[0]_INST_0/O
                         net (fo=4, routed)           1.341    31.879    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/icn_cmd_en_reg[7]
    SLICE_X113Y327       LUT4 (Prop_C5LUT_SLICEM_I0_O)
                                                      0.090    31.969 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/icn_cmd_en[7]_i_1/O
                         net (fo=4, routed)           0.169    32.138    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/icn_cmd_en_reg[7]_0
    SLICE_X112Y327       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/icn_cmd_en_reg[4]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.861    52.326    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017    52.343 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.594    53.937    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/m_bscan_tck[0]
    SLICE_X112Y327       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/icn_cmd_en_reg[4]/C
                         clock pessimism              0.000    53.937    
                         clock uncertainty           -0.235    53.701    
    SLICE_X112Y327       FDRE (Setup_EFF_SLICEM_C_R)
                                                     -0.044    53.657    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/icn_cmd_en_reg[4]
  -------------------------------------------------------------------
                         required time                         53.657    
                         arrival time                         -32.138    
  -------------------------------------------------------------------
                         slack                                 21.519    

Slack (MET) :             21.519ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
                            (falling edge-triggered cell BSCANE2 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/icn_cmd_en_reg[5]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Fast Process Corner)
  Requirement:            25.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall@25.000ns)
  Data Path Delay:        7.138ns  (logic 5.267ns (73.792%)  route 1.871ns (26.208%))
  Logic Levels:           2  (LUT4=1 LUT5=1)
  Clock Path Skew:        3.937ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.937ns = ( 53.937 - 50.000 ) 
    Source Clock Delay      (SCD):    0.000ns = ( 25.000 - 25.000 ) 
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Destination): 1.594ns (routing 0.916ns, distribution 0.678ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall edge)
                                                     25.000    25.000 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    25.000 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_SHIFT)
                                                      5.100    30.100 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/SHIFT
                         net (fo=37, routed)          0.361    30.461    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_shift
    SLICE_X107Y114       LUT5 (Prop_A6LUT_SLICEM_I4_O)
                                                      0.077    30.538 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_shift[0]_INST_0/O
                         net (fo=4, routed)           1.341    31.879    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/icn_cmd_en_reg[7]
    SLICE_X113Y327       LUT4 (Prop_C5LUT_SLICEM_I0_O)
                                                      0.090    31.969 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/icn_cmd_en[7]_i_1/O
                         net (fo=4, routed)           0.169    32.138    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/icn_cmd_en_reg[7]_0
    SLICE_X112Y327       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/icn_cmd_en_reg[5]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.861    52.326    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017    52.343 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.594    53.937    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/m_bscan_tck[0]
    SLICE_X112Y327       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/icn_cmd_en_reg[5]/C
                         clock pessimism              0.000    53.937    
                         clock uncertainty           -0.235    53.701    
    SLICE_X112Y327       FDRE (Setup_EFF2_SLICEM_C_R)
                                                     -0.044    53.657    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/icn_cmd_en_reg[5]
  -------------------------------------------------------------------
                         required time                         53.657    
                         arrival time                         -32.138    
  -------------------------------------------------------------------
                         slack                                 21.519    

Slack (MET) :             21.519ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
                            (falling edge-triggered cell BSCANE2 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/icn_cmd_en_reg[6]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Fast Process Corner)
  Requirement:            25.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall@25.000ns)
  Data Path Delay:        7.138ns  (logic 5.267ns (73.792%)  route 1.871ns (26.208%))
  Logic Levels:           2  (LUT4=1 LUT5=1)
  Clock Path Skew:        3.937ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.937ns = ( 53.937 - 50.000 ) 
    Source Clock Delay      (SCD):    0.000ns = ( 25.000 - 25.000 ) 
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Destination): 1.594ns (routing 0.916ns, distribution 0.678ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall edge)
                                                     25.000    25.000 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    25.000 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_SHIFT)
                                                      5.100    30.100 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/SHIFT
                         net (fo=37, routed)          0.361    30.461    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_shift
    SLICE_X107Y114       LUT5 (Prop_A6LUT_SLICEM_I4_O)
                                                      0.077    30.538 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_shift[0]_INST_0/O
                         net (fo=4, routed)           1.341    31.879    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/icn_cmd_en_reg[7]
    SLICE_X113Y327       LUT4 (Prop_C5LUT_SLICEM_I0_O)
                                                      0.090    31.969 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/icn_cmd_en[7]_i_1/O
                         net (fo=4, routed)           0.169    32.138    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/icn_cmd_en_reg[7]_0
    SLICE_X112Y327       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/icn_cmd_en_reg[6]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.861    52.326    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017    52.343 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.594    53.937    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/m_bscan_tck[0]
    SLICE_X112Y327       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/icn_cmd_en_reg[6]/C
                         clock pessimism              0.000    53.937    
                         clock uncertainty           -0.235    53.701    
    SLICE_X112Y327       FDRE (Setup_FFF_SLICEM_C_R)
                                                     -0.044    53.657    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/icn_cmd_en_reg[6]
  -------------------------------------------------------------------
                         required time                         53.657    
                         arrival time                         -32.138    
  -------------------------------------------------------------------
                         slack                                 21.519    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.030ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/icn_cmd_din_temp_reg/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[17]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.127ns  (logic 0.059ns (46.457%)  route 0.068ns (53.543%))
  Logic Levels:           0  
  Clock Path Skew:        0.035ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    10.814ns
    Source Clock Delay      (SCD):    5.452ns
    Clock Pessimism Removal (CPR):    5.328ns
  Clock Net Delay (Source):      2.610ns (routing 1.525ns, distribution 1.085ns)
  Clock Net Delay (Destination): 2.920ns (routing 1.680ns, distribution 1.240ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.353     2.818    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.842 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.610     5.452    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X108Y346       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/icn_cmd_din_temp_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X108Y346       FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.059     5.511 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/icn_cmd_din_temp_reg/Q
                         net (fo=1, routed)           0.068     5.579    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/icn_cmd_din_temp
    SLICE_X108Y345       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[17]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.566     7.866    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.894 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.920    10.814    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X108Y345       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[17]/C
                         clock pessimism             -5.328     5.486    
    SLICE_X108Y345       FDRE (Hold_HFF2_SLICEL_C_D)
                                                      0.062     5.548    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[17]
  -------------------------------------------------------------------
                         required time                         -5.548    
                         arrival time                           5.579    
  -------------------------------------------------------------------
                         slack                                  0.030    

Slack (MET) :             0.033ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_STATIC_STATUS/stat_addr_bit_cnt_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_STATIC_STATUS/stat_addr_bit_cnt_reg[6]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.172ns  (logic 0.080ns (46.540%)  route 0.092ns (53.460%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        0.079ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    10.796ns
    Source Clock Delay      (SCD):    5.437ns
    Clock Pessimism Removal (CPR):    5.280ns
  Clock Net Delay (Source):      2.595ns (routing 1.525ns, distribution 1.070ns)
  Clock Net Delay (Destination): 2.902ns (routing 1.680ns, distribution 1.222ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.353     2.818    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.842 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.595     5.437    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_STATIC_STATUS/m_bscan_tck[0]
    SLICE_X112Y328       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_STATIC_STATUS/stat_addr_bit_cnt_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X112Y328       FDRE (Prop_CFF_SLICEM_C_Q)
                                                      0.058     5.495 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_STATIC_STATUS/stat_addr_bit_cnt_reg[3]/Q
                         net (fo=7, routed)           0.068     5.563    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_STATIC_STATUS/stat_addr_bit_cnt_reg[3]
    SLICE_X111Y328       LUT6 (Prop_C6LUT_SLICEL_I4_O)
                                                      0.022     5.585 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_STATIC_STATUS/stat_addr_bit_cnt[6]_i_2/O
                         net (fo=1, routed)           0.024     5.609    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_STATIC_STATUS/p_0_in[6]
    SLICE_X111Y328       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_STATIC_STATUS/stat_addr_bit_cnt_reg[6]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.566     7.866    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.894 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.902    10.796    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_STATIC_STATUS/m_bscan_tck[0]
    SLICE_X111Y328       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_STATIC_STATUS/stat_addr_bit_cnt_reg[6]/C
                         clock pessimism             -5.280     5.516    
    SLICE_X111Y328       FDRE (Hold_CFF_SLICEL_C_D)
                                                      0.060     5.576    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_STATIC_STATUS/stat_addr_bit_cnt_reg[6]
  -------------------------------------------------------------------
                         required time                         -5.576    
                         arrival time                           5.609    
  -------------------------------------------------------------------
                         slack                                  0.033    

Slack (MET) :             0.034ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.129ns  (logic 0.058ns (44.821%)  route 0.071ns (55.179%))
  Logic Levels:           0  
  Clock Path Skew:        0.034ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    10.810ns
    Source Clock Delay      (SCD):    5.449ns
    Clock Pessimism Removal (CPR):    5.328ns
  Clock Net Delay (Source):      2.607ns (routing 1.525ns, distribution 1.082ns)
  Clock Net Delay (Destination): 2.916ns (routing 1.680ns, distribution 1.236ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.353     2.818    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.842 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.607     5.449    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X108Y345       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X108Y345       FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.058     5.507 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[2]/Q
                         net (fo=2, routed)           0.071     5.578    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in[2]
    SLICE_X108Y346       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.566     7.866    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.894 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.916    10.810    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X108Y346       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[1]/C
                         clock pessimism             -5.328     5.482    
    SLICE_X108Y346       FDRE (Hold_BFF2_SLICEL_C_D)
                                                      0.062     5.544    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[1]
  -------------------------------------------------------------------
                         required time                         -5.544    
                         arrival time                           5.578    
  -------------------------------------------------------------------
                         slack                                  0.034    

Slack (MET) :             0.039ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/shift_reg_in_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/shift_reg_in_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.198ns  (logic 0.093ns (46.970%)  route 0.105ns (53.030%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.099ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    10.814ns
    Source Clock Delay      (SCD):    5.435ns
    Clock Pessimism Removal (CPR):    5.280ns
  Clock Net Delay (Source):      2.593ns (routing 1.525ns, distribution 1.068ns)
  Clock Net Delay (Destination): 2.920ns (routing 1.680ns, distribution 1.240ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.353     2.818    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.842 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.593     5.435    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/m_bscan_tck[0]
    SLICE_X109Y334       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/shift_reg_in_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X109Y334       FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.058     5.493 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/shift_reg_in_reg[3]/Q
                         net (fo=1, routed)           0.070     5.563    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/shift_reg_in[3]
    SLICE_X110Y334       LUT3 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.035     5.598 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/shift_reg_in[2]_i_1/O
                         net (fo=1, routed)           0.035     5.633    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/shift_reg_in[2]_i_1_n_0
    SLICE_X110Y334       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/shift_reg_in_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.566     7.866    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.894 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.920    10.814    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/m_bscan_tck[0]
    SLICE_X110Y334       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/shift_reg_in_reg[2]/C
                         clock pessimism             -5.280     5.534    
    SLICE_X110Y334       FDRE (Hold_CFF_SLICEM_C_D)
                                                      0.060     5.594    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/shift_reg_in_reg[2]
  -------------------------------------------------------------------
                         required time                         -5.594    
                         arrival time                           5.633    
  -------------------------------------------------------------------
                         slack                                  0.039    

Slack (MET) :             0.040ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/icn_cmd_en_temp_reg/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/shift_en_reg/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.179ns  (logic 0.058ns (32.405%)  route 0.121ns (67.595%))
  Logic Levels:           0  
  Clock Path Skew:        0.077ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    10.793ns
    Source Clock Delay      (SCD):    5.436ns
    Clock Pessimism Removal (CPR):    5.280ns
  Clock Net Delay (Source):      2.594ns (routing 1.525ns, distribution 1.069ns)
  Clock Net Delay (Destination): 2.899ns (routing 1.680ns, distribution 1.219ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.353     2.818    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.842 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.594     5.436    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/m_bscan_tck[0]
    SLICE_X113Y332       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/icn_cmd_en_temp_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X113Y332       FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.058     5.494 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/icn_cmd_en_temp_reg/Q
                         net (fo=5, routed)           0.121     5.615    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/icn_cmd_en_temp
    SLICE_X111Y332       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/shift_en_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.566     7.866    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.894 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.899    10.793    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/m_bscan_tck[0]
    SLICE_X111Y332       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/shift_en_reg/C
                         clock pessimism             -5.280     5.513    
    SLICE_X111Y332       FDRE (Hold_CFF2_SLICEL_C_D)
                                                      0.062     5.575    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/shift_en_reg
  -------------------------------------------------------------------
                         required time                         -5.575    
                         arrival time                           5.615    
  -------------------------------------------------------------------
                         slack                                  0.040    

Slack (MET) :             0.040ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[25]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[24]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.092ns  (logic 0.037ns (40.356%)  route 0.055ns (59.643%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.567ns
    Source Clock Delay      (SCD):    3.939ns
    Clock Pessimism Removal (CPR):    4.623ns
  Clock Net Delay (Source):      1.596ns (routing 0.916ns, distribution 0.680ns)
  Clock Net Delay (Destination): 1.798ns (routing 1.028ns, distribution 0.770ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.861     2.326    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.343 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.596     3.939    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/m_bscan_tck[0]
    SLICE_X113Y337       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[25]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X113Y337       FDRE (Prop_FFF_SLICEM_C_Q)
                                                      0.037     3.976 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[25]/Q
                         net (fo=2, routed)           0.055     4.030    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in[25]
    SLICE_X113Y337       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[24]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.450     6.750    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.769 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.798     8.567    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/m_bscan_tck[0]
    SLICE_X113Y337       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[24]/C
                         clock pessimism             -4.623     3.945    
    SLICE_X113Y337       FDRE (Hold_EFF_SLICEM_C_D)
                                                      0.046     3.991    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[24]
  -------------------------------------------------------------------
                         required time                         -3.991    
                         arrival time                           4.030    
  -------------------------------------------------------------------
                         slack                                  0.040    

Slack (MET) :             0.040ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[2]/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.092ns  (logic 0.038ns (41.373%)  route 0.054ns (58.627%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.570ns
    Source Clock Delay      (SCD):    3.941ns
    Clock Pessimism Removal (CPR):    4.624ns
  Clock Net Delay (Source):      1.598ns (routing 0.916ns, distribution 0.682ns)
  Clock Net Delay (Destination): 1.801ns (routing 1.028ns, distribution 0.773ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.861     2.326    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.343 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.598     3.941    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/wr_clk
    SLICE_X109Y342       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X109Y342       FDCE (Prop_BFF_SLICEM_C_Q)
                                                      0.038     3.979 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[2]/Q
                         net (fo=2, routed)           0.054     4.032    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[3]_0[2]
    SLICE_X109Y342       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.450     6.750    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.769 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.801     8.570    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/wr_clk
    SLICE_X109Y342       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[2]/C
                         clock pessimism             -4.624     3.947    
    SLICE_X109Y342       FDCE (Hold_DFF_SLICEM_C_D)
                                                      0.046     3.993    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[2]
  -------------------------------------------------------------------
                         required time                         -3.993    
                         arrival time                           4.032    
  -------------------------------------------------------------------
                         slack                                  0.040    

Slack (MET) :             0.042ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[8]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/icn_cmd_en_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.135ns  (logic 0.063ns (46.541%)  route 0.072ns (53.459%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.047ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.565ns
    Source Clock Delay      (SCD):    3.938ns
    Clock Pessimism Removal (CPR):    4.581ns
  Clock Net Delay (Source):      1.595ns (routing 0.916ns, distribution 0.679ns)
  Clock Net Delay (Destination): 1.796ns (routing 1.028ns, distribution 0.768ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.861     2.326    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.343 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.595     3.938    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
    SLICE_X113Y327       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X113Y327       FDCE (Prop_HFF_SLICEM_C_Q)
                                                      0.039     3.977 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[8]/Q
                         net (fo=6, routed)           0.063     4.040    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/sel0[0]
    SLICE_X112Y327       LUT3 (Prop_F5LUT_SLICEM_I1_O)
                                                      0.024     4.064 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/icn_cmd_en[7]_i_2/O
                         net (fo=2, routed)           0.009     4.073    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/icn_cmd_en_reg[7]_1
    SLICE_X112Y327       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/icn_cmd_en_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.450     6.750    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.769 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.796     8.565    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/m_bscan_tck[0]
    SLICE_X112Y327       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/icn_cmd_en_reg[7]/C
                         clock pessimism             -4.581     3.984    
    SLICE_X112Y327       FDRE (Hold_FFF2_SLICEM_C_D)
                                                      0.047     4.031    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/icn_cmd_en_reg[7]
  -------------------------------------------------------------------
                         required time                         -4.031    
                         arrival time                           4.073    
  -------------------------------------------------------------------
                         slack                                  0.042    

Slack (MET) :             0.043ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[23]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[22]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.095ns  (logic 0.039ns (41.190%)  route 0.056ns (58.810%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.569ns
    Source Clock Delay      (SCD):    3.940ns
    Clock Pessimism Removal (CPR):    4.624ns
  Clock Net Delay (Source):      1.597ns (routing 0.916ns, distribution 0.681ns)
  Clock Net Delay (Destination): 1.800ns (routing 1.028ns, distribution 0.772ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.861     2.326    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.343 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.597     3.940    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/m_bscan_tck[0]
    SLICE_X113Y337       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[23]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X113Y337       FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     3.979 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[23]/Q
                         net (fo=2, routed)           0.056     4.034    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in[23]
    SLICE_X113Y337       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[22]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.450     6.750    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.769 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.800     8.569    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/m_bscan_tck[0]
    SLICE_X113Y337       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[22]/C
                         clock pessimism             -4.624     3.946    
    SLICE_X113Y337       FDRE (Hold_CFF_SLICEM_C_D)
                                                      0.046     3.992    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[22]
  -------------------------------------------------------------------
                         required time                         -3.992    
                         arrival time                           4.034    
  -------------------------------------------------------------------
                         slack                                  0.043    

Slack (MET) :             0.043ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[9]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.095ns  (logic 0.039ns (41.190%)  route 0.056ns (58.810%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.569ns
    Source Clock Delay      (SCD):    3.941ns
    Clock Pessimism Removal (CPR):    4.623ns
  Clock Net Delay (Source):      1.598ns (routing 0.916ns, distribution 0.682ns)
  Clock Net Delay (Destination): 1.800ns (routing 1.028ns, distribution 0.772ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.861     2.326    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.343 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.598     3.941    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/m_bscan_tck[0]
    SLICE_X113Y338       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[9]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X113Y338       FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     3.980 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[9]/Q
                         net (fo=2, routed)           0.056     4.035    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in[9]
    SLICE_X113Y338       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.450     6.750    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.769 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.800     8.569    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/m_bscan_tck[0]
    SLICE_X113Y338       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[8]/C
                         clock pessimism             -4.623     3.947    
    SLICE_X113Y338       FDRE (Hold_CFF_SLICEM_C_D)
                                                      0.046     3.993    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[8]
  -------------------------------------------------------------------
                         required time                         -3.993    
                         arrival time                           4.035    
  -------------------------------------------------------------------
                         slack                                  0.043    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
Waveform(ns):       { 0.000 25.000 }
Period(ns):         50.000
Sources:            { dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK }

Check Type        Corner  Lib Pin     Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location        Pin
Min Period        n/a     BUFGCE/I    n/a            1.290         50.000      48.710     BUFGCE_X0Y181   dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/I
Min Period        n/a     RAMD32/CLK  n/a            1.064         50.000      48.936     SLICE_X109Y335  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA/CLK
Min Period        n/a     RAMD32/CLK  n/a            1.064         50.000      48.936     SLICE_X109Y335  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA_D1/CLK
Min Period        n/a     RAMD32/CLK  n/a            1.064         50.000      48.936     SLICE_X109Y335  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB/CLK
Min Period        n/a     RAMD32/CLK  n/a            1.064         50.000      48.936     SLICE_X109Y335  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB_D1/CLK
Min Period        n/a     RAMD32/CLK  n/a            1.064         50.000      48.936     SLICE_X109Y335  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC/CLK
Min Period        n/a     RAMD32/CLK  n/a            1.064         50.000      48.936     SLICE_X109Y335  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC_D1/CLK
Min Period        n/a     RAMD32/CLK  n/a            1.064         50.000      48.936     SLICE_X109Y335  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMD/CLK
Min Period        n/a     RAMD32/CLK  n/a            1.064         50.000      48.936     SLICE_X109Y335  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMD_D1/CLK
Min Period        n/a     RAMD32/CLK  n/a            1.064         50.000      48.936     SLICE_X109Y335  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAME/CLK
Low Pulse Width   Slow    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X109Y335  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA/CLK
Low Pulse Width   Fast    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X109Y335  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA/CLK
Low Pulse Width   Slow    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X109Y335  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA_D1/CLK
Low Pulse Width   Fast    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X109Y335  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA_D1/CLK
Low Pulse Width   Slow    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X109Y335  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB/CLK
Low Pulse Width   Fast    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X109Y335  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB/CLK
Low Pulse Width   Slow    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X109Y335  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB_D1/CLK
Low Pulse Width   Fast    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X109Y335  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB_D1/CLK
Low Pulse Width   Slow    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X109Y335  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC/CLK
Low Pulse Width   Fast    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X109Y335  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC/CLK
High Pulse Width  Slow    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X109Y335  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA/CLK
High Pulse Width  Fast    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X109Y335  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA/CLK
High Pulse Width  Slow    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X109Y335  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA_D1/CLK
High Pulse Width  Fast    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X109Y335  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA_D1/CLK
High Pulse Width  Slow    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X109Y335  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB/CLK
High Pulse Width  Fast    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X109Y335  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB/CLK
High Pulse Width  Slow    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X109Y335  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB_D1/CLK
High Pulse Width  Fast    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X109Y335  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB_D1/CLK
High Pulse Width  Slow    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X109Y335  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC/CLK
High Pulse Width  Fast    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X109Y335  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC/CLK



---------------------------------------------------------------------------------------------------
From Clock:  sys_clk_ddr4_clk_p
  To Clock:  sys_clk_ddr4_clk_p

Setup :            0  Failing Endpoints,  Worst Slack        1.762ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.052ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        0.500ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.762ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design_reg/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.334ns  (sys_clk_ddr4_clk_p rise@3.334ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        1.435ns  (logic 0.204ns (14.216%)  route 1.231ns (85.784%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        -0.127ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.456ns = ( 5.790 - 3.334 ) 
    Source Clock Delay      (SCD):    2.819ns
    Clock Pessimism Removal (CPR):    0.236ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.733ns (routing 0.702ns, distribution 1.031ns)
  Clock Net Delay (Destination): 1.541ns (routing 0.637ns, distribution 0.904ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.733     2.819    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X95Y234        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y234        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.080     2.899 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design_reg/Q
                         net (fo=2, routed)           0.960     3.859    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design
    SLICE_X84Y302        LUT3 (Prop_A6LUT_SLICEL_I1_O)
                                                      0.124     3.983 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_i_1/O
                         net (fo=1, routed)           0.271     4.254    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg0
    SLICE_X84Y309        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      3.334     3.334 r  
    J19                                               0.000     3.334 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.413    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.888 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.928    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.928 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     4.225    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.249 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.541     5.790    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X84Y309        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/C
                         clock pessimism              0.236     6.026    
                         clock uncertainty           -0.035     5.990    
    SLICE_X84Y309        FDRE (Setup_AFF2_SLICEL_C_D)
                                                      0.025     6.015    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg
  -------------------------------------------------------------------
                         required time                          6.015    
                         arrival time                          -4.254    
  -------------------------------------------------------------------
                         slack                                  1.762    

Slack (MET) :             1.905ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[0]/R
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.334ns  (sys_clk_ddr4_clk_p rise@3.334ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        1.252ns  (logic 0.231ns (18.454%)  route 1.021ns (81.546%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        -0.068ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.449ns = ( 5.783 - 3.334 ) 
    Source Clock Delay      (SCD):    2.806ns
    Clock Pessimism Removal (CPR):    0.289ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.720ns (routing 0.702ns, distribution 1.018ns)
  Clock Net Delay (Destination): 1.534ns (routing 0.637ns, distribution 0.897ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.720     2.806    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X92Y181        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y181        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     2.887 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]/Q
                         net (fo=4, routed)           0.615     3.502    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r[3]
    SLICE_X95Y234        LUT5 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.150     3.652 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_1/O
                         net (fo=4, routed)           0.405     4.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_1_n_0
    SLICE_X96Y237        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[0]/R
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      3.334     3.334 r  
    J19                                               0.000     3.334 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.413    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.888 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.928    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.928 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     4.225    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.249 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.534     5.783    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X96Y237        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[0]/C
                         clock pessimism              0.289     6.072    
                         clock uncertainty           -0.035     6.037    
    SLICE_X96Y237        FDRE (Setup_BFF2_SLICEM_C_R)
                                                     -0.074     5.963    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[0]
  -------------------------------------------------------------------
                         required time                          5.963    
                         arrival time                          -4.058    
  -------------------------------------------------------------------
                         slack                                  1.905    

Slack (MET) :             1.905ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/R
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.334ns  (sys_clk_ddr4_clk_p rise@3.334ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        1.252ns  (logic 0.231ns (18.454%)  route 1.021ns (81.546%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        -0.068ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.449ns = ( 5.783 - 3.334 ) 
    Source Clock Delay      (SCD):    2.806ns
    Clock Pessimism Removal (CPR):    0.289ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.720ns (routing 0.702ns, distribution 1.018ns)
  Clock Net Delay (Destination): 1.534ns (routing 0.637ns, distribution 0.897ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.720     2.806    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X92Y181        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y181        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     2.887 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]/Q
                         net (fo=4, routed)           0.615     3.502    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r[3]
    SLICE_X95Y234        LUT5 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.150     3.652 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_1/O
                         net (fo=4, routed)           0.405     4.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_1_n_0
    SLICE_X96Y237        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/R
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      3.334     3.334 r  
    J19                                               0.000     3.334 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.413    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.888 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.928    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.928 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     4.225    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.249 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.534     5.783    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X96Y237        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
                         clock pessimism              0.289     6.072    
                         clock uncertainty           -0.035     6.037    
    SLICE_X96Y237        FDRE (Setup_DFF_SLICEM_C_R)
                                                     -0.074     5.963    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]
  -------------------------------------------------------------------
                         required time                          5.963    
                         arrival time                          -4.058    
  -------------------------------------------------------------------
                         slack                                  1.905    

Slack (MET) :             1.905ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/R
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.334ns  (sys_clk_ddr4_clk_p rise@3.334ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        1.252ns  (logic 0.231ns (18.454%)  route 1.021ns (81.546%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        -0.068ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.449ns = ( 5.783 - 3.334 ) 
    Source Clock Delay      (SCD):    2.806ns
    Clock Pessimism Removal (CPR):    0.289ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.720ns (routing 0.702ns, distribution 1.018ns)
  Clock Net Delay (Destination): 1.534ns (routing 0.637ns, distribution 0.897ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.720     2.806    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X92Y181        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y181        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     2.887 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]/Q
                         net (fo=4, routed)           0.615     3.502    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r[3]
    SLICE_X95Y234        LUT5 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.150     3.652 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_1/O
                         net (fo=4, routed)           0.405     4.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_1_n_0
    SLICE_X96Y237        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/R
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      3.334     3.334 r  
    J19                                               0.000     3.334 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.413    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.888 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.928    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.928 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     4.225    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.249 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.534     5.783    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X96Y237        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/C
                         clock pessimism              0.289     6.072    
                         clock uncertainty           -0.035     6.037    
    SLICE_X96Y237        FDRE (Setup_DFF2_SLICEM_C_R)
                                                     -0.074     5.963    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]
  -------------------------------------------------------------------
                         required time                          5.963    
                         arrival time                          -4.058    
  -------------------------------------------------------------------
                         slack                                  1.905    

Slack (MET) :             1.907ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[6]/R
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.334ns  (sys_clk_ddr4_clk_p rise@3.334ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        1.249ns  (logic 0.231ns (18.498%)  route 1.018ns (81.502%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        -0.069ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.448ns = ( 5.782 - 3.334 ) 
    Source Clock Delay      (SCD):    2.806ns
    Clock Pessimism Removal (CPR):    0.289ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.720ns (routing 0.702ns, distribution 1.018ns)
  Clock Net Delay (Destination): 1.533ns (routing 0.637ns, distribution 0.896ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.720     2.806    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X92Y181        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y181        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     2.887 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]/Q
                         net (fo=4, routed)           0.615     3.502    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r[3]
    SLICE_X95Y234        LUT5 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.150     3.652 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_1/O
                         net (fo=4, routed)           0.402     4.055    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_1_n_0
    SLICE_X96Y237        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[6]/R
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      3.334     3.334 r  
    J19                                               0.000     3.334 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.413    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.888 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.928    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.928 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     4.225    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.249 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.533     5.782    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X96Y237        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[6]/C
                         clock pessimism              0.289     6.071    
                         clock uncertainty           -0.035     6.036    
    SLICE_X96Y237        FDRE (Setup_EFF_SLICEM_C_R)
                                                     -0.074     5.962    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[6]
  -------------------------------------------------------------------
                         required time                          5.962    
                         arrival time                          -4.055    
  -------------------------------------------------------------------
                         slack                                  1.907    

Slack (MET) :             1.939ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design_reg/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.334ns  (sys_clk_ddr4_clk_p rise@3.334ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        1.259ns  (logic 0.147ns (11.678%)  route 1.112ns (88.322%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        -0.126ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.457ns = ( 5.791 - 3.334 ) 
    Source Clock Delay      (SCD):    2.819ns
    Clock Pessimism Removal (CPR):    0.236ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.733ns (routing 0.702ns, distribution 1.031ns)
  Clock Net Delay (Destination): 1.542ns (routing 0.637ns, distribution 0.905ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.733     2.819    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X95Y234        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y234        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.080     2.899 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design_reg/Q
                         net (fo=2, routed)           0.871     3.770    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design
    SLICE_X84Y300        LUT2 (Prop_G5LUT_SLICEL_I0_O)
                                                      0.067     3.837 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_i_1/O
                         net (fo=1, routed)           0.241     4.078    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg0
    SLICE_X84Y305        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      3.334     3.334 r  
    J19                                               0.000     3.334 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.413    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.888 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.928    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.928 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     4.225    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.249 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.542     5.791    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X84Y305        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/C
                         clock pessimism              0.236     6.027    
                         clock uncertainty           -0.035     5.991    
    SLICE_X84Y305        FDRE (Setup_AFF2_SLICEL_C_D)
                                                      0.025     6.016    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg
  -------------------------------------------------------------------
                         required time                          6.016    
                         arrival time                          -4.078    
  -------------------------------------------------------------------
                         slack                                  1.939    

Slack (MET) :             2.147ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/input_rst_mmcm_reg/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.334ns  (sys_clk_ddr4_clk_p rise@3.334ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        1.026ns  (logic 0.323ns (31.486%)  route 0.703ns (68.514%))
  Logic Levels:           2  (LUT3=1 LUT5=1)
  Clock Path Skew:        -0.151ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.429ns = ( 5.763 - 3.334 ) 
    Source Clock Delay      (SCD):    2.820ns
    Clock Pessimism Removal (CPR):    0.240ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.734ns (routing 0.702ns, distribution 1.032ns)
  Clock Net Delay (Destination): 1.514ns (routing 0.637ns, distribution 0.877ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.734     2.820    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X96Y237        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y237        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     2.896 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[6]/Q
                         net (fo=7, routed)           0.216     3.112    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]
    SLICE_X95Y234        LUT3 (Prop_C5LUT_SLICEL_I2_O)
                                                      0.136     3.248 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/input_rst_mmcm_i_2/O
                         net (fo=1, routed)           0.170     3.418    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/input_rst_mmcm_i_2_n_0
    SLICE_X96Y237        LUT5 (Prop_C5LUT_SLICEM_I3_O)
                                                      0.111     3.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/input_rst_mmcm_i_1/O
                         net (fo=1, routed)           0.317     3.846    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/input_rst_mmcm_i_1_n_0
    SLICE_X96Y241        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/input_rst_mmcm_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      3.334     3.334 r  
    J19                                               0.000     3.334 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.413    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.888 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.928    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.928 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     4.225    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.249 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.514     5.763    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X96Y241        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/input_rst_mmcm_reg/C
                         clock pessimism              0.240     6.003    
                         clock uncertainty           -0.035     5.967    
    SLICE_X96Y241        FDRE (Setup_EFF2_SLICEM_C_D)
                                                      0.025     5.992    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/input_rst_mmcm_reg
  -------------------------------------------------------------------
                         required time                          5.992    
                         arrival time                          -3.846    
  -------------------------------------------------------------------
                         slack                                  2.147    

Slack (MET) :             2.280ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/C
                            (rising edge-triggered cell FDSE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[6]/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.334ns  (sys_clk_ddr4_clk_p rise@3.334ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        0.966ns  (logic 0.217ns (22.452%)  route 0.749ns (77.548%))
  Logic Levels:           2  (LUT4=2)
  Clock Path Skew:        -0.077ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.448ns = ( 5.782 - 3.334 ) 
    Source Clock Delay      (SCD):    2.814ns
    Clock Pessimism Removal (CPR):    0.289ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.728ns (routing 0.702ns, distribution 1.026ns)
  Clock Net Delay (Destination): 1.533ns (routing 0.637ns, distribution 0.896ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.728     2.814    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X95Y234        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y234        FDSE (Prop_BFF_SLICEL_C_Q)
                                                      0.079     2.893 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/Q
                         net (fo=5, routed)           0.196     3.088    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[1]
    SLICE_X96Y237        LUT4 (Prop_C6LUT_SLICEM_I3_O)
                                                      0.088     3.176 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_3/O
                         net (fo=6, routed)           0.211     3.387    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_3_n_0
    SLICE_X95Y234        LUT4 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.050     3.437 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_2/O
                         net (fo=1, routed)           0.343     3.780    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst0[6]
    SLICE_X96Y237        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[6]/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      3.334     3.334 r  
    J19                                               0.000     3.334 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.413    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.888 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.928    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.928 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     4.225    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.249 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.533     5.782    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X96Y237        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[6]/C
                         clock pessimism              0.289     6.071    
                         clock uncertainty           -0.035     6.035    
    SLICE_X96Y237        FDRE (Setup_EFF_SLICEM_C_D)
                                                      0.025     6.060    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[6]
  -------------------------------------------------------------------
                         required time                          6.060    
                         arrival time                          -3.780    
  -------------------------------------------------------------------
                         slack                                  2.280    

Slack (MET) :             2.400ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/S
                            (rising edge-triggered cell FDSE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.334ns  (sys_clk_ddr4_clk_p rise@3.334ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        0.751ns  (logic 0.081ns (10.779%)  route 0.670ns (89.221%))
  Logic Levels:           0  
  Clock Path Skew:        -0.073ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.444ns = ( 5.778 - 3.334 ) 
    Source Clock Delay      (SCD):    2.806ns
    Clock Pessimism Removal (CPR):    0.289ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.720ns (routing 0.702ns, distribution 1.018ns)
  Clock Net Delay (Destination): 1.529ns (routing 0.637ns, distribution 0.892ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.720     2.806    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X92Y181        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y181        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     2.887 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]/Q
                         net (fo=4, routed)           0.670     3.557    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r[3]
    SLICE_X95Y234        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/S
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      3.334     3.334 r  
    J19                                               0.000     3.334 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.413    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.888 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.928    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.928 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     4.225    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.249 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.529     5.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X95Y234        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/C
                         clock pessimism              0.289     6.067    
                         clock uncertainty           -0.035     6.032    
    SLICE_X95Y234        FDSE (Setup_BFF_SLICEL_C_S)
                                                     -0.074     5.958    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]
  -------------------------------------------------------------------
                         required time                          5.958    
                         arrival time                          -3.557    
  -------------------------------------------------------------------
                         slack                                  2.400    

Slack (MET) :             2.400ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/S
                            (rising edge-triggered cell FDSE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.334ns  (sys_clk_ddr4_clk_p rise@3.334ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        0.751ns  (logic 0.081ns (10.779%)  route 0.670ns (89.221%))
  Logic Levels:           0  
  Clock Path Skew:        -0.073ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.444ns = ( 5.778 - 3.334 ) 
    Source Clock Delay      (SCD):    2.806ns
    Clock Pessimism Removal (CPR):    0.289ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.720ns (routing 0.702ns, distribution 1.018ns)
  Clock Net Delay (Destination): 1.529ns (routing 0.637ns, distribution 0.892ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.720     2.806    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X92Y181        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y181        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     2.887 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]/Q
                         net (fo=4, routed)           0.670     3.557    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r[3]
    SLICE_X95Y234        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/S
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      3.334     3.334 r  
    J19                                               0.000     3.334 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.413    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.888 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.928    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.928 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     4.225    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.249 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.529     5.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X95Y234        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/C
                         clock pessimism              0.289     6.067    
                         clock uncertainty           -0.035     6.032    
    SLICE_X95Y234        FDSE (Setup_DFF_SLICEL_C_S)
                                                     -0.074     5.958    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]
  -------------------------------------------------------------------
                         required time                          5.958    
                         arrival time                          -3.557    
  -------------------------------------------------------------------
                         slack                                  2.400    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.052ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/C
                            (rising edge-triggered cell FDSE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/D
                            (rising edge-triggered cell FDSE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (sys_clk_ddr4_clk_p rise@0.000ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        0.104ns  (logic 0.062ns (59.798%)  route 0.042ns (40.202%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.875ns
    Source Clock Delay      (SCD):    1.578ns
    Clock Pessimism Removal (CPR):    0.291ns
  Clock Net Delay (Source):      0.961ns (routing 0.389ns, distribution 0.572ns)
  Clock Net Delay (Destination): 1.088ns (routing 0.434ns, distribution 0.654ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          0.961     1.578    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X95Y234        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y234        FDSE (Prop_BFF_SLICEL_C_Q)
                                                      0.039     1.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/Q
                         net (fo=5, routed)           0.027     1.643    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[1]
    SLICE_X95Y234        LUT6 (Prop_B6LUT_SLICEL_I1_O)
                                                      0.023     1.666 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[1]_i_1/O
                         net (fo=1, routed)           0.015     1.681    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[1]_i_1_n_0
    SLICE_X95Y234        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.088     1.875    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X95Y234        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/C
                         clock pessimism             -0.291     1.584    
    SLICE_X95Y234        FDSE (Hold_BFF_SLICEL_C_D)
                                                      0.046     1.630    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]
  -------------------------------------------------------------------
                         required time                         -1.630    
                         arrival time                           1.681    
  -------------------------------------------------------------------
                         slack                                  0.052    

Slack (MET) :             0.053ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[1]/C
                            (rising edge-triggered cell FDPE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (sys_clk_ddr4_clk_p rise@0.000ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        0.118ns  (logic 0.040ns (33.898%)  route 0.078ns (66.102%))
  Logic Levels:           0  
  Clock Path Skew:        0.018ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.873ns
    Source Clock Delay      (SCD):    1.575ns
    Clock Pessimism Removal (CPR):    0.280ns
  Clock Net Delay (Source):      0.958ns (routing 0.389ns, distribution 0.569ns)
  Clock Net Delay (Destination): 1.086ns (routing 0.434ns, distribution 0.652ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          0.958     1.575    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X92Y180        FDPE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y180        FDPE (Prop_BFF2_SLICEL_C_Q)
                                                      0.040     1.615 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[1]/Q
                         net (fo=1, routed)           0.078     1.693    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async[1]
    SLICE_X92Y181        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.086     1.873    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X92Y181        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[0]/C
                         clock pessimism             -0.280     1.593    
    SLICE_X92Y181        FDRE (Hold_AFF2_SLICEL_C_D)
                                                      0.047     1.640    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[0]
  -------------------------------------------------------------------
                         required time                         -1.640    
                         arrival time                           1.693    
  -------------------------------------------------------------------
                         slack                                  0.053    

Slack (MET) :             0.055ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/C
                            (rising edge-triggered cell FDSE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[5]/D
                            (rising edge-triggered cell FDSE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (sys_clk_ddr4_clk_p rise@0.000ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        0.108ns  (logic 0.072ns (66.433%)  route 0.036ns (33.566%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.875ns
    Source Clock Delay      (SCD):    1.578ns
    Clock Pessimism Removal (CPR):    0.291ns
  Clock Net Delay (Source):      0.961ns (routing 0.389ns, distribution 0.572ns)
  Clock Net Delay (Destination): 1.088ns (routing 0.434ns, distribution 0.654ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          0.961     1.578    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X95Y234        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y234        FDSE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     1.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/Q
                         net (fo=7, routed)           0.030     1.647    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[4]
    SLICE_X95Y234        LUT4 (Prop_D5LUT_SLICEL_I2_O)
                                                      0.033     1.680 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[5]_i_1/O
                         net (fo=1, routed)           0.006     1.686    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[5]_i_1_n_0
    SLICE_X95Y234        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.088     1.875    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X95Y234        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[5]/C
                         clock pessimism             -0.291     1.584    
    SLICE_X95Y234        FDSE (Hold_DFF2_SLICEL_C_D)
                                                      0.047     1.631    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[5]
  -------------------------------------------------------------------
                         required time                         -1.631    
                         arrival time                           1.686    
  -------------------------------------------------------------------
                         slack                                  0.055    

Slack (MET) :             0.061ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (sys_clk_ddr4_clk_p rise@0.000ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        0.114ns  (logic 0.076ns (66.657%)  route 0.038ns (33.343%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.881ns
    Source Clock Delay      (SCD):    1.581ns
    Clock Pessimism Removal (CPR):    0.294ns
  Clock Net Delay (Source):      0.964ns (routing 0.389ns, distribution 0.575ns)
  Clock Net Delay (Destination): 1.094ns (routing 0.434ns, distribution 0.660ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          0.964     1.581    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X96Y237        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y237        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     1.620 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/Q
                         net (fo=4, routed)           0.029     1.649    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[2]
    SLICE_X96Y237        LUT4 (Prop_D5LUT_SLICEM_I1_O)
                                                      0.037     1.686 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[3]_i_1/O
                         net (fo=1, routed)           0.009     1.695    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst0[3]
    SLICE_X96Y237        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.094     1.881    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X96Y237        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/C
                         clock pessimism             -0.294     1.587    
    SLICE_X96Y237        FDRE (Hold_DFF2_SLICEM_C_D)
                                                      0.047     1.634    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]
  -------------------------------------------------------------------
                         required time                         -1.634    
                         arrival time                           1.695    
  -------------------------------------------------------------------
                         slack                                  0.061    

Slack (MET) :             0.068ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/C
                            (rising edge-triggered cell FDSE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/D
                            (rising edge-triggered cell FDSE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (sys_clk_ddr4_clk_p rise@0.000ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        0.120ns  (logic 0.074ns (61.472%)  route 0.046ns (38.527%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.875ns
    Source Clock Delay      (SCD):    1.578ns
    Clock Pessimism Removal (CPR):    0.291ns
  Clock Net Delay (Source):      0.961ns (routing 0.389ns, distribution 0.572ns)
  Clock Net Delay (Destination): 1.088ns (routing 0.434ns, distribution 0.654ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          0.961     1.578    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X95Y234        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y234        FDSE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     1.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/Q
                         net (fo=7, routed)           0.030     1.647    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[4]
    SLICE_X95Y234        LUT4 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.035     1.682 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[4]_i_1/O
                         net (fo=1, routed)           0.016     1.698    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[4]_i_1_n_0
    SLICE_X95Y234        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.088     1.875    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X95Y234        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/C
                         clock pessimism             -0.291     1.584    
    SLICE_X95Y234        FDSE (Hold_DFF_SLICEL_C_D)
                                                      0.046     1.630    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]
  -------------------------------------------------------------------
                         required time                         -1.630    
                         arrival time                           1.698    
  -------------------------------------------------------------------
                         slack                                  0.068    

Slack (MET) :             0.069ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (sys_clk_ddr4_clk_p rise@0.000ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        0.122ns  (logic 0.040ns (32.787%)  route 0.082ns (67.213%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.873ns
    Source Clock Delay      (SCD):    1.575ns
    Clock Pessimism Removal (CPR):    0.292ns
  Clock Net Delay (Source):      0.958ns (routing 0.389ns, distribution 0.569ns)
  Clock Net Delay (Destination): 1.086ns (routing 0.434ns, distribution 0.652ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          0.958     1.575    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X92Y181        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y181        FDRE (Prop_CFF2_SLICEL_C_Q)
                                                      0.040     1.615 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[2]/Q
                         net (fo=1, routed)           0.082     1.697    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r[2]
    SLICE_X92Y181        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.086     1.873    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X92Y181        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]/C
                         clock pessimism             -0.292     1.581    
    SLICE_X92Y181        FDRE (Hold_DFF2_SLICEL_C_D)
                                                      0.047     1.628    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]
  -------------------------------------------------------------------
                         required time                         -1.628    
                         arrival time                           1.697    
  -------------------------------------------------------------------
                         slack                                  0.069    

Slack (MET) :             0.077ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (sys_clk_ddr4_clk_p rise@0.000ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        0.129ns  (logic 0.074ns (57.357%)  route 0.055ns (42.643%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.881ns
    Source Clock Delay      (SCD):    1.581ns
    Clock Pessimism Removal (CPR):    0.294ns
  Clock Net Delay (Source):      0.964ns (routing 0.389ns, distribution 0.575ns)
  Clock Net Delay (Destination): 1.094ns (routing 0.434ns, distribution 0.660ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          0.964     1.581    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X96Y237        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y237        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     1.620 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/Q
                         net (fo=4, routed)           0.029     1.649    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[2]
    SLICE_X96Y237        LUT3 (Prop_D6LUT_SLICEM_I2_O)
                                                      0.035     1.684 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[2]_i_1/O
                         net (fo=1, routed)           0.026     1.710    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst0[2]
    SLICE_X96Y237        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.094     1.881    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X96Y237        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
                         clock pessimism             -0.294     1.587    
    SLICE_X96Y237        FDRE (Hold_DFF_SLICEM_C_D)
                                                      0.046     1.633    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]
  -------------------------------------------------------------------
                         required time                         -1.633    
                         arrival time                           1.710    
  -------------------------------------------------------------------
                         slack                                  0.077    

Slack (MET) :             0.077ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design_reg/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (sys_clk_ddr4_clk_p rise@0.000ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        0.173ns  (logic 0.058ns (33.520%)  route 0.115ns (66.480%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        0.049ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.879ns
    Source Clock Delay      (SCD):    1.580ns
    Clock Pessimism Removal (CPR):    0.251ns
  Clock Net Delay (Source):      0.963ns (routing 0.389ns, distribution 0.574ns)
  Clock Net Delay (Destination): 1.092ns (routing 0.434ns, distribution 0.658ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          0.963     1.580    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X96Y237        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y237        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     1.618 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[6]/Q
                         net (fo=7, routed)           0.109     1.727    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]
    SLICE_X95Y234        LUT4 (Prop_H5LUT_SLICEL_I0_O)
                                                      0.020     1.747 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design_i_1/O
                         net (fo=1, routed)           0.006     1.753    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design_i_1_n_0
    SLICE_X95Y234        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.092     1.879    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X95Y234        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design_reg/C
                         clock pessimism             -0.251     1.628    
    SLICE_X95Y234        FDRE (Hold_HFF2_SLICEL_C_D)
                                                      0.047     1.675    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design_reg
  -------------------------------------------------------------------
                         required time                         -1.675    
                         arrival time                           1.753    
  -------------------------------------------------------------------
                         slack                                  0.077    

Slack (MET) :             0.089ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[0]/C
                            (rising edge-triggered cell FDPE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[1]/D
                            (rising edge-triggered cell FDPE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (sys_clk_ddr4_clk_p rise@0.000ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        0.142ns  (logic 0.040ns (28.169%)  route 0.102ns (71.831%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.873ns
    Source Clock Delay      (SCD):    1.575ns
    Clock Pessimism Removal (CPR):    0.292ns
  Clock Net Delay (Source):      0.958ns (routing 0.389ns, distribution 0.569ns)
  Clock Net Delay (Destination): 1.086ns (routing 0.434ns, distribution 0.652ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          0.958     1.575    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X92Y180        FDPE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y180        FDPE (Prop_AFF2_SLICEL_C_Q)
                                                      0.040     1.615 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[0]/Q
                         net (fo=1, routed)           0.102     1.717    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async[0]
    SLICE_X92Y180        FDPE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.086     1.873    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X92Y180        FDPE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[1]/C
                         clock pessimism             -0.292     1.581    
    SLICE_X92Y180        FDPE (Hold_BFF2_SLICEL_C_D)
                                                      0.047     1.628    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[1]
  -------------------------------------------------------------------
                         required time                         -1.628    
                         arrival time                           1.717    
  -------------------------------------------------------------------
                         slack                                  0.089    

Slack (MET) :             0.090ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (sys_clk_ddr4_clk_p rise@0.000ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        0.143ns  (logic 0.040ns (27.972%)  route 0.103ns (72.028%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.873ns
    Source Clock Delay      (SCD):    1.575ns
    Clock Pessimism Removal (CPR):    0.292ns
  Clock Net Delay (Source):      0.958ns (routing 0.389ns, distribution 0.569ns)
  Clock Net Delay (Destination): 1.086ns (routing 0.434ns, distribution 0.652ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          0.958     1.575    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X92Y181        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y181        FDRE (Prop_BFF2_SLICEL_C_Q)
                                                      0.040     1.615 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[1]/Q
                         net (fo=1, routed)           0.103     1.718    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r[1]
    SLICE_X92Y181        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.086     1.873    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X92Y181        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[2]/C
                         clock pessimism             -0.292     1.581    
    SLICE_X92Y181        FDRE (Hold_CFF2_SLICEL_C_D)
                                                      0.047     1.628    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[2]
  -------------------------------------------------------------------
                         required time                         -1.628    
                         arrival time                           1.718    
  -------------------------------------------------------------------
                         slack                                  0.090    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         sys_clk_ddr4_clk_p
Waveform(ns):       { 0.000 1.667 }
Period(ns):         3.334
Sources:            { sys_clk_ddr4_clk_p }

Check Type        Corner  Lib Pin            Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location       Pin
Min Period        n/a     BUFGCE/I           n/a            1.290         3.334       2.044      BUFGCE_X0Y124  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/I
Min Period        n/a     MMCME4_ADV/CLKIN1  n/a            1.071         3.334       2.263      MMCM_X0Y4      d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKIN1
Min Period        n/a     FDRE/C             n/a            0.550         3.334       2.784      SLICE_X96Y237  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[0]/C
Min Period        n/a     FDSE/C             n/a            0.550         3.334       2.784      SLICE_X95Y234  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/C
Min Period        n/a     FDRE/C             n/a            0.550         3.334       2.784      SLICE_X96Y237  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
Min Period        n/a     FDRE/C             n/a            0.550         3.334       2.784      SLICE_X96Y237  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/C
Min Period        n/a     FDSE/C             n/a            0.550         3.334       2.784      SLICE_X95Y234  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/C
Min Period        n/a     FDSE/C             n/a            0.550         3.334       2.784      SLICE_X95Y234  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[5]/C
Min Period        n/a     FDRE/C             n/a            0.550         3.334       2.784      SLICE_X96Y237  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[6]/C
Min Period        n/a     FDRE/C             n/a            0.550         3.334       2.784      SLICE_X95Y234  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design_reg/C
Max Period        n/a     MMCME4_ADV/CLKIN1  n/a            100.000       3.334       96.666     MMCM_X0Y4      d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKIN1
Low Pulse Width   Slow    MMCME4_ADV/CLKIN1  n/a            1.167         1.667       0.500      MMCM_X0Y4      d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKIN1
Low Pulse Width   Fast    MMCME4_ADV/CLKIN1  n/a            1.167         1.667       0.500      MMCM_X0Y4      d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKIN1
Low Pulse Width   Slow    FDRE/C             n/a            0.275         1.667       1.392      SLICE_X96Y237  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[0]/C
Low Pulse Width   Fast    FDRE/C             n/a            0.275         1.667       1.392      SLICE_X96Y237  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[0]/C
Low Pulse Width   Slow    FDSE/C             n/a            0.275         1.667       1.392      SLICE_X95Y234  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/C
Low Pulse Width   Fast    FDSE/C             n/a            0.275         1.667       1.392      SLICE_X95Y234  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/C
Low Pulse Width   Slow    FDRE/C             n/a            0.275         1.667       1.392      SLICE_X96Y237  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
Low Pulse Width   Fast    FDRE/C             n/a            0.275         1.667       1.392      SLICE_X96Y237  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
Low Pulse Width   Slow    FDRE/C             n/a            0.275         1.667       1.392      SLICE_X96Y237  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/C
Low Pulse Width   Fast    FDRE/C             n/a            0.275         1.667       1.392      SLICE_X96Y237  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/C
High Pulse Width  Slow    MMCME4_ADV/CLKIN1  n/a            1.167         1.667       0.500      MMCM_X0Y4      d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKIN1
High Pulse Width  Fast    MMCME4_ADV/CLKIN1  n/a            1.167         1.667       0.500      MMCM_X0Y4      d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKIN1
High Pulse Width  Slow    FDRE/C             n/a            0.275         1.667       1.392      SLICE_X96Y237  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[0]/C
High Pulse Width  Fast    FDRE/C             n/a            0.275         1.667       1.392      SLICE_X96Y237  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[0]/C
High Pulse Width  Slow    FDSE/C             n/a            0.275         1.667       1.392      SLICE_X95Y234  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/C
High Pulse Width  Fast    FDSE/C             n/a            0.275         1.667       1.392      SLICE_X95Y234  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/C
High Pulse Width  Slow    FDRE/C             n/a            0.275         1.667       1.392      SLICE_X96Y237  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
High Pulse Width  Fast    FDRE/C             n/a            0.275         1.667       1.392      SLICE_X96Y237  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
High Pulse Width  Slow    FDRE/C             n/a            0.275         1.667       1.392      SLICE_X96Y237  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/C
High Pulse Width  Fast    FDRE/C             n/a            0.275         1.667       1.392      SLICE_X96Y237  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/C



---------------------------------------------------------------------------------------------------
From Clock:  mmcm_clkout0
  To Clock:  mmcm_clkout0

Setup :            0  Failing Endpoints,  Worst Slack        0.062ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.010ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        0.000ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.062ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[26]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (mmcm_clkout0 rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        2.828ns  (logic 0.857ns (30.306%)  route 1.971ns (69.694%))
  Logic Levels:           8  (CARRY8=1 LUT3=1 LUT5=1 LUT6=5)
  Clock Path Skew:        -0.073ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.985ns = ( 7.985 - 3.001 ) 
    Source Clock Delay      (SCD):    4.809ns
    Clock Pessimism Removal (CPR):    -0.249ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.047ns (routing 0.788ns, distribution 1.259ns)
  Clock Net Delay (Destination): 1.832ns (routing 0.716ns, distribution 1.116ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.047     4.809    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cmdGroupP_reg[0]_0
    SLICE_X85Y314        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y314        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     4.888 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[0]/Q
                         net (fo=46, routed)          0.405     5.293    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/Q[0]
    SLICE_X82Y320        LUT6 (Prop_F6LUT_SLICEM_I3_O)
                                                      0.088     5.381 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/i__carry_i_17__2/O
                         net (fo=1, routed)           0.174     5.555    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/i__carry_i_17__2_n_0
    SLICE_X82Y325        LUT6 (Prop_B6LUT_SLICEM_I0_O)
                                                      0.149     5.704 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/i__carry_i_5__2/O
                         net (fo=1, routed)           0.016     5.720    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/i__carry_i_5__2_n_0
    SLICE_X82Y325        CARRY8 (Prop_CARRY8_SLICEM_S[1]_CO[5])
                                                      0.199     5.919 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/issue_cas3_inferred__0/i__carry/CO[5]
                         net (fo=5, routed)           0.334     6.253    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/issue_cas3_inferred__0/i__carry_n_2
    SLICE_X85Y325        LUT5 (Prop_C6LUT_SLICEL_I2_O)
                                                      0.050     6.303 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/FSM_sequential_grSt[1]_i_6/O
                         net (fo=1, routed)           0.132     6.435    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/FSM_sequential_grSt[1]_i_6_n_0
    SLICE_X85Y328        LUT6 (Prop_A6LUT_SLICEL_I3_O)
                                                      0.098     6.533 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/FSM_sequential_grSt[1]_i_3__0/O
                         net (fo=4, routed)           0.044     6.577    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/FSM_sequential_grSt[1]_i_3__0_n_0
    SLICE_X85Y328        LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.035     6.612 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cas_fifo_wptr[1]_i_2__0/O
                         net (fo=75, routed)          0.390     7.002    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cas_fifo_wptr[1]_i_2__0_n_0
    SLICE_X85Y314        LUT3 (Prop_E5LUT_SLICEL_I1_O)
                                                      0.070     7.072 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output[47]_i_5/O
                         net (fo=30, routed)          0.416     7.489    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output[47]_i_5_n_0
    SLICE_X82Y314        LUT6 (Prop_B6LUT_SLICEM_I0_O)
                                                      0.089     7.578 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output[26]_i_1__0/O
                         net (fo=1, routed)           0.059     7.637    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output[26]_i_1__0_n_0
    SLICE_X82Y314        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[26]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     5.285    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     6.130    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.154 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.832     7.985    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cmdGroupP_reg[0]_0
    SLICE_X82Y314        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[26]/C
                         clock pessimism             -0.249     7.736    
                         clock uncertainty           -0.062     7.674    
    SLICE_X82Y314        FDRE (Setup_BFF_SLICEM_C_D)
                                                      0.025     7.699    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[26]
  -------------------------------------------------------------------
                         required time                          7.699    
                         arrival time                          -7.637    
  -------------------------------------------------------------------
                         slack                                  0.062    

Slack (MET) :             0.073ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/areset_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/w_payld_fifo/cmd_fifo/fifoaddr_reg[0]/S
                            (rising edge-triggered cell FDSE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (mmcm_clkout0 rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        2.431ns  (logic 0.080ns (3.291%)  route 2.351ns (96.709%))
  Logic Levels:           0  
  Clock Path Skew:        -0.361ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.168ns = ( 8.169 - 3.001 ) 
    Source Clock Delay      (SCD):    5.214ns
    Clock Pessimism Removal (CPR):    -0.315ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.452ns (routing 0.788ns, distribution 1.664ns)
  Clock Net Delay (Destination): 2.015ns (routing 0.716ns, distribution 1.299ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.452     5.214    d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/aclk
    SLICE_X15Y182        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/areset_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X15Y182        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.080     5.294 r  d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/areset_reg/Q
                         net (fo=178, routed)         2.351     7.645    d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/w_payld_fifo/cmd_fifo/areset
    SLICE_X47Y130        FDSE                                         r  d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/w_payld_fifo/cmd_fifo/fifoaddr_reg[0]/S
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     5.285    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     6.130    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.154 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.015     8.169    d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/w_payld_fifo/cmd_fifo/aclk
    SLICE_X47Y130        FDSE                                         r  d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/w_payld_fifo/cmd_fifo/fifoaddr_reg[0]/C
                         clock pessimism             -0.315     7.853    
                         clock uncertainty           -0.062     7.791    
    SLICE_X47Y130        FDSE (Setup_DFF_SLICEL_C_S)
                                                     -0.074     7.717    d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/w_payld_fifo/cmd_fifo/fifoaddr_reg[0]
  -------------------------------------------------------------------
                         required time                          7.717    
                         arrival time                          -7.645    
  -------------------------------------------------------------------
                         slack                                  0.073    

Slack (MET) :             0.073ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/areset_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/w_payld_fifo/cmd_fifo/fifoaddr_reg[1]/S
                            (rising edge-triggered cell FDSE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (mmcm_clkout0 rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        2.431ns  (logic 0.080ns (3.291%)  route 2.351ns (96.709%))
  Logic Levels:           0  
  Clock Path Skew:        -0.361ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.168ns = ( 8.169 - 3.001 ) 
    Source Clock Delay      (SCD):    5.214ns
    Clock Pessimism Removal (CPR):    -0.315ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.452ns (routing 0.788ns, distribution 1.664ns)
  Clock Net Delay (Destination): 2.015ns (routing 0.716ns, distribution 1.299ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.452     5.214    d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/aclk
    SLICE_X15Y182        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/areset_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X15Y182        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.080     5.294 r  d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/areset_reg/Q
                         net (fo=178, routed)         2.351     7.645    d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/w_payld_fifo/cmd_fifo/areset
    SLICE_X47Y130        FDSE                                         r  d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/w_payld_fifo/cmd_fifo/fifoaddr_reg[1]/S
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     5.285    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     6.130    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.154 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.015     8.169    d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/w_payld_fifo/cmd_fifo/aclk
    SLICE_X47Y130        FDSE                                         r  d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/w_payld_fifo/cmd_fifo/fifoaddr_reg[1]/C
                         clock pessimism             -0.315     7.853    
                         clock uncertainty           -0.062     7.791    
    SLICE_X47Y130        FDSE (Setup_DFF2_SLICEL_C_S)
                                                     -0.074     7.717    d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/w_payld_fifo/cmd_fifo/fifoaddr_reg[1]
  -------------------------------------------------------------------
                         required time                          7.717    
                         arrival time                          -7.645    
  -------------------------------------------------------------------
                         slack                                  0.073    

Slack (MET) :             0.073ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/areset_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/w_payld_fifo/cmd_fifo/fifoaddr_reg[2]/S
                            (rising edge-triggered cell FDSE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (mmcm_clkout0 rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        2.431ns  (logic 0.080ns (3.291%)  route 2.351ns (96.709%))
  Logic Levels:           0  
  Clock Path Skew:        -0.361ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.168ns = ( 8.169 - 3.001 ) 
    Source Clock Delay      (SCD):    5.214ns
    Clock Pessimism Removal (CPR):    -0.315ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.452ns (routing 0.788ns, distribution 1.664ns)
  Clock Net Delay (Destination): 2.015ns (routing 0.716ns, distribution 1.299ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.452     5.214    d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/aclk
    SLICE_X15Y182        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/areset_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X15Y182        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.080     5.294 r  d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/areset_reg/Q
                         net (fo=178, routed)         2.351     7.645    d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/w_payld_fifo/cmd_fifo/areset
    SLICE_X47Y130        FDSE                                         r  d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/w_payld_fifo/cmd_fifo/fifoaddr_reg[2]/S
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     5.285    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     6.130    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.154 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.015     8.169    d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/w_payld_fifo/cmd_fifo/aclk
    SLICE_X47Y130        FDSE                                         r  d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/w_payld_fifo/cmd_fifo/fifoaddr_reg[2]/C
                         clock pessimism             -0.315     7.853    
                         clock uncertainty           -0.062     7.791    
    SLICE_X47Y130        FDSE (Setup_CFF_SLICEL_C_S)
                                                     -0.074     7.717    d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/w_payld_fifo/cmd_fifo/fifoaddr_reg[2]
  -------------------------------------------------------------------
                         required time                          7.717    
                         arrival time                          -7.645    
  -------------------------------------------------------------------
                         slack                                  0.073    

Slack (MET) :             0.073ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/areset_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/w_payld_fifo/cmd_fifo/fifoaddr_reg[3]/S
                            (rising edge-triggered cell FDSE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (mmcm_clkout0 rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        2.431ns  (logic 0.080ns (3.291%)  route 2.351ns (96.709%))
  Logic Levels:           0  
  Clock Path Skew:        -0.361ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.168ns = ( 8.169 - 3.001 ) 
    Source Clock Delay      (SCD):    5.214ns
    Clock Pessimism Removal (CPR):    -0.315ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.452ns (routing 0.788ns, distribution 1.664ns)
  Clock Net Delay (Destination): 2.015ns (routing 0.716ns, distribution 1.299ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.452     5.214    d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/aclk
    SLICE_X15Y182        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/areset_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X15Y182        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.080     5.294 r  d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/areset_reg/Q
                         net (fo=178, routed)         2.351     7.645    d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/w_payld_fifo/cmd_fifo/areset
    SLICE_X47Y130        FDSE                                         r  d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/w_payld_fifo/cmd_fifo/fifoaddr_reg[3]/S
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     5.285    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     6.130    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.154 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.015     8.169    d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/w_payld_fifo/cmd_fifo/aclk
    SLICE_X47Y130        FDSE                                         r  d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/w_payld_fifo/cmd_fifo/fifoaddr_reg[3]/C
                         clock pessimism             -0.315     7.853    
                         clock uncertainty           -0.062     7.791    
    SLICE_X47Y130        FDSE (Setup_CFF2_SLICEL_C_S)
                                                     -0.074     7.717    d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/w_payld_fifo/cmd_fifo/fifoaddr_reg[3]
  -------------------------------------------------------------------
                         required time                          7.717    
                         arrival time                          -7.645    
  -------------------------------------------------------------------
                         slack                                  0.073    

Slack (MET) :             0.077ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/wrQ_reg[0][7]_rep__1/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_wr_data/wr_buf_out_data_reg[85]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (mmcm_clkout0 rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        2.805ns  (logic 0.168ns (5.989%)  route 2.637ns (94.011%))
  Logic Levels:           1  (RAMD32=1)
  Clock Path Skew:        -0.081ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.970ns = ( 7.970 - 3.001 ) 
    Source Clock Delay      (SCD):    4.797ns
    Clock Pessimism Removal (CPR):    -0.254ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.035ns (routing 0.788ns, distribution 1.247ns)
  Clock Net Delay (Destination): 1.817ns (routing 0.716ns, distribution 1.101ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.035     4.797    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/dReg_reg[10]
    SLICE_X87Y261        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/wrQ_reg[0][7]_rep__1/C
  -------------------------------------------------------------------    -------------------
    SLICE_X87Y261        FDRE (Prop_DFF2_SLICEM_C_Q)
                                                      0.080     4.877 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/wrQ_reg[0][7]_rep__1/Q
                         net (fo=193, routed)         2.571     7.448    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_wr_data/wr_buffer_ram[14].RAM32M0/ADDRC3
    SLICE_X82Y296        RAMD32 (Prop_C6LUT_SLICEM_RADR3_O)
                                                      0.088     7.536 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_wr_data/wr_buffer_ram[14].RAM32M0/RAMC_D1/O
                         net (fo=1, routed)           0.066     7.602    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_wr_data/wr_buf_out_data_w[85]
    SLICE_X82Y296        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_wr_data/wr_buf_out_data_reg[85]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     5.285    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     6.130    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.154 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.817     7.970    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_wr_data/rd_data_indx_r_reg[3]_0
    SLICE_X82Y296        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_wr_data/wr_buf_out_data_reg[85]/C
                         clock pessimism             -0.254     7.716    
                         clock uncertainty           -0.062     7.654    
    SLICE_X82Y296        FDRE (Setup_CFF_SLICEM_C_D)
                                                      0.025     7.679    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_wr_data/wr_buf_out_data_reg[85]
  -------------------------------------------------------------------
                         required time                          7.679    
                         arrival time                          -7.602    
  -------------------------------------------------------------------
                         slack                                  0.077    

Slack (MET) :             0.083ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/wrQ_reg[0][7]_rep__1/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_wr_data/wr_buf_out_data_reg[79]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (mmcm_clkout0 rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        2.798ns  (logic 0.170ns (6.076%)  route 2.628ns (93.924%))
  Logic Levels:           1  (RAMD32=1)
  Clock Path Skew:        -0.082ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.969ns = ( 7.969 - 3.001 ) 
    Source Clock Delay      (SCD):    4.797ns
    Clock Pessimism Removal (CPR):    -0.254ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.035ns (routing 0.788ns, distribution 1.247ns)
  Clock Net Delay (Destination): 1.816ns (routing 0.716ns, distribution 1.100ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.035     4.797    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/dReg_reg[10]
    SLICE_X87Y261        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/wrQ_reg[0][7]_rep__1/C
  -------------------------------------------------------------------    -------------------
    SLICE_X87Y261        FDRE (Prop_DFF2_SLICEM_C_Q)
                                                      0.080     4.877 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/wrQ_reg[0][7]_rep__1/Q
                         net (fo=193, routed)         2.569     7.446    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_wr_data/wr_buffer_ram[13].RAM32M0/ADDRC3
    SLICE_X82Y296        RAMD32 (Prop_G6LUT_SLICEM_RADR3_O)
                                                      0.090     7.536 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_wr_data/wr_buffer_ram[13].RAM32M0/RAMC_D1/O
                         net (fo=1, routed)           0.059     7.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_wr_data/wr_buf_out_data_w[79]
    SLICE_X82Y296        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_wr_data/wr_buf_out_data_reg[79]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     5.285    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     6.130    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.154 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.816     7.969    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_wr_data/rd_data_indx_r_reg[3]_0
    SLICE_X82Y296        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_wr_data/wr_buf_out_data_reg[79]/C
                         clock pessimism             -0.254     7.715    
                         clock uncertainty           -0.062     7.653    
    SLICE_X82Y296        FDRE (Setup_GFF_SLICEM_C_D)
                                                      0.025     7.678    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_wr_data/wr_buf_out_data_reg[79]
  -------------------------------------------------------------------
                         required time                          7.678    
                         arrival time                          -7.595    
  -------------------------------------------------------------------
                         slack                                  0.083    

Slack (MET) :             0.092ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/pageInfo_reg[0][0][3][4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[16]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (mmcm_clkout0 rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        2.785ns  (logic 0.867ns (31.135%)  route 1.918ns (68.865%))
  Logic Levels:           8  (CARRY8=1 LUT3=1 LUT5=1 LUT6=5)
  Clock Path Skew:        -0.087ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.975ns = ( 7.975 - 3.001 ) 
    Source Clock Delay      (SCD):    4.813ns
    Clock Pessimism Removal (CPR):    -0.249ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.051ns (routing 0.788ns, distribution 1.263ns)
  Clock Net Delay (Destination): 1.822ns (routing 0.716ns, distribution 1.106ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.051     4.813    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cmdGroupP_reg[0]_0
    SLICE_X82Y321        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/pageInfo_reg[0][0][3][4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y321        FDRE (Prop_GFF_SLICEM_C_Q)
                                                      0.078     4.891 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/pageInfo_reg[0][0][3][4]/Q
                         net (fo=1, routed)           0.345     5.236    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/pageInfo_reg_n_0_[0][0][3][4]
    SLICE_X82Y314        LUT6 (Prop_E6LUT_SLICEM_I0_O)
                                                      0.148     5.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/i__carry_i_22__2/O
                         net (fo=1, routed)           0.269     5.653    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/i__carry_i_22__2_n_0
    SLICE_X82Y325        LUT6 (Prop_A6LUT_SLICEM_I5_O)
                                                      0.038     5.691 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/i__carry_i_6__2/O
                         net (fo=1, routed)           0.013     5.704    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/i__carry_i_6__2_n_0
    SLICE_X82Y325        CARRY8 (Prop_CARRY8_SLICEM_S[0]_CO[5])
                                                      0.201     5.905 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/issue_cas3_inferred__0/i__carry/CO[5]
                         net (fo=5, routed)           0.334     6.239    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/issue_cas3_inferred__0/i__carry_n_2
    SLICE_X85Y325        LUT5 (Prop_C6LUT_SLICEL_I2_O)
                                                      0.050     6.289 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/FSM_sequential_grSt[1]_i_6/O
                         net (fo=1, routed)           0.132     6.421    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/FSM_sequential_grSt[1]_i_6_n_0
    SLICE_X85Y328        LUT6 (Prop_A6LUT_SLICEL_I3_O)
                                                      0.098     6.519 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/FSM_sequential_grSt[1]_i_3__0/O
                         net (fo=4, routed)           0.044     6.563    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/FSM_sequential_grSt[1]_i_3__0_n_0
    SLICE_X85Y328        LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.035     6.598 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cas_fifo_wptr[1]_i_2__0/O
                         net (fo=75, routed)          0.390     6.988    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cas_fifo_wptr[1]_i_2__0_n_0
    SLICE_X85Y314        LUT3 (Prop_E5LUT_SLICEL_I1_O)
                                                      0.070     7.058 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output[47]_i_5/O
                         net (fo=30, routed)          0.342     7.400    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output[47]_i_5_n_0
    SLICE_X85Y305        LUT6 (Prop_A6LUT_SLICEL_I5_O)
                                                      0.149     7.549 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output[16]_i_1__0/O
                         net (fo=1, routed)           0.048     7.597    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output[16]_i_1__0_n_0
    SLICE_X85Y305        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[16]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     5.285    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     6.130    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.154 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.822     7.975    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cmdGroupP_reg[0]_0
    SLICE_X85Y305        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[16]/C
                         clock pessimism             -0.249     7.726    
                         clock uncertainty           -0.062     7.664    
    SLICE_X85Y305        FDRE (Setup_AFF_SLICEL_C_D)
                                                      0.025     7.689    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[16]
  -------------------------------------------------------------------
                         required time                          7.689    
                         arrival time                          -7.597    
  -------------------------------------------------------------------
                         slack                                  0.092    

Slack (MET) :             0.092ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (mmcm_clkout0 rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        2.798ns  (logic 0.819ns (29.273%)  route 1.979ns (70.727%))
  Logic Levels:           8  (CARRY8=1 LUT3=1 LUT5=1 LUT6=5)
  Clock Path Skew:        -0.073ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.985ns = ( 7.985 - 3.001 ) 
    Source Clock Delay      (SCD):    4.809ns
    Clock Pessimism Removal (CPR):    -0.249ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.047ns (routing 0.788ns, distribution 1.259ns)
  Clock Net Delay (Destination): 1.832ns (routing 0.716ns, distribution 1.116ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.047     4.809    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cmdGroupP_reg[0]_0
    SLICE_X85Y314        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y314        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     4.888 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[0]/Q
                         net (fo=46, routed)          0.405     5.293    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/Q[0]
    SLICE_X82Y320        LUT6 (Prop_F6LUT_SLICEM_I3_O)
                                                      0.088     5.381 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/i__carry_i_17__2/O
                         net (fo=1, routed)           0.174     5.555    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/i__carry_i_17__2_n_0
    SLICE_X82Y325        LUT6 (Prop_B6LUT_SLICEM_I0_O)
                                                      0.149     5.704 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/i__carry_i_5__2/O
                         net (fo=1, routed)           0.016     5.720    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/i__carry_i_5__2_n_0
    SLICE_X82Y325        CARRY8 (Prop_CARRY8_SLICEM_S[1]_CO[5])
                                                      0.199     5.919 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/issue_cas3_inferred__0/i__carry/CO[5]
                         net (fo=5, routed)           0.334     6.253    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/issue_cas3_inferred__0/i__carry_n_2
    SLICE_X85Y325        LUT5 (Prop_C6LUT_SLICEL_I2_O)
                                                      0.050     6.303 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/FSM_sequential_grSt[1]_i_6/O
                         net (fo=1, routed)           0.132     6.435    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/FSM_sequential_grSt[1]_i_6_n_0
    SLICE_X85Y328        LUT6 (Prop_A6LUT_SLICEL_I3_O)
                                                      0.098     6.533 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/FSM_sequential_grSt[1]_i_3__0/O
                         net (fo=4, routed)           0.044     6.577    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/FSM_sequential_grSt[1]_i_3__0_n_0
    SLICE_X85Y328        LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.035     6.612 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cas_fifo_wptr[1]_i_2__0/O
                         net (fo=75, routed)          0.390     7.002    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cas_fifo_wptr[1]_i_2__0_n_0
    SLICE_X85Y314        LUT3 (Prop_E5LUT_SLICEL_I1_O)
                                                      0.070     7.072 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output[47]_i_5/O
                         net (fo=30, routed)          0.417     7.490    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output[47]_i_5_n_0
    SLICE_X82Y314        LUT6 (Prop_C6LUT_SLICEM_I5_O)
                                                      0.051     7.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output[14]_i_1__0/O
                         net (fo=1, routed)           0.066     7.607    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output[14]_i_1__0_n_0
    SLICE_X82Y314        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     5.285    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     6.130    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.154 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.832     7.985    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cmdGroupP_reg[0]_0
    SLICE_X82Y314        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[14]/C
                         clock pessimism             -0.249     7.736    
                         clock uncertainty           -0.062     7.674    
    SLICE_X82Y314        FDRE (Setup_CFF_SLICEM_C_D)
                                                      0.025     7.699    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[14]
  -------------------------------------------------------------------
                         required time                          7.699    
                         arrival time                          -7.607    
  -------------------------------------------------------------------
                         slack                                  0.092    

Slack (MET) :             0.092ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/u_ddr_cal_cplx/cplx_config_byte_select_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/u_ddr_cal_cplx/cplx_dqin_byte_103_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (mmcm_clkout0 rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        2.650ns  (logic 0.242ns (9.132%)  route 2.408ns (90.868%))
  Logic Levels:           2  (LUT6=1 MUXF7=1)
  Clock Path Skew:        -0.221ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.885ns = ( 7.886 - 3.001 ) 
    Source Clock Delay      (SCD):    4.787ns
    Clock Pessimism Removal (CPR):    -0.319ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.025ns (routing 0.788ns, distribution 1.237ns)
  Clock Net Delay (Destination): 1.732ns (routing 0.716ns, distribution 1.016ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.025     4.787    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/u_ddr_cal_cplx/rd_addr_101_reg[7]
    SLICE_X95Y296        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/u_ddr_cal_cplx/cplx_config_byte_select_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y296        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.081     4.868 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/u_ddr_cal_cplx/cplx_config_byte_select_reg[1]/Q
                         net (fo=192, routed)         2.367     7.235    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/u_ddr_cal_cplx/cplx_config_byte_select[1]
    SLICE_X95Y214        LUT6 (Prop_F6LUT_SLICEL_I2_O)
                                                      0.097     7.332 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/u_ddr_cal_cplx/cplx_dqin_byte_103[12]_i_2/O
                         net (fo=1, routed)           0.011     7.343    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/u_ddr_cal_cplx/cplx_dqin_byte_103[12]_i_2_n_0
    SLICE_X95Y214        MUXF7 (Prop_F7MUX_EF_SLICEL_I0_O)
                                                      0.064     7.407 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/u_ddr_cal_cplx/cplx_dqin_byte_103_reg[12]_i_1/O
                         net (fo=1, routed)           0.030     7.437    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/u_ddr_cal_cplx/cplx_dqin_byte_103_reg[12]_i_1_n_0
    SLICE_X95Y214        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/u_ddr_cal_cplx/cplx_dqin_byte_103_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     5.285    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     6.130    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.154 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.732     7.886    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/u_ddr_cal_cplx/rd_addr_101_reg[7]
    SLICE_X95Y214        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/u_ddr_cal_cplx/cplx_dqin_byte_103_reg[12]/C
                         clock pessimism             -0.319     7.567    
                         clock uncertainty           -0.062     7.504    
    SLICE_X95Y214        FDRE (Setup_FFF_SLICEL_C_D)
                                                      0.025     7.529    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/u_ddr_cal_cplx/cplx_dqin_byte_103_reg[12]
  -------------------------------------------------------------------
                         required time                          7.529    
                         arrival time                          -7.437    
  -------------------------------------------------------------------
                         slack                                  0.092    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.010ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_clb2phy_fifo_rden_reg[89]/C
                            (rising edge-triggered cell FDSE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/FIFO_RD_EN
                            (rising edge-triggered cell RXTX_BITSLICE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout0 rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.193ns  (logic 0.039ns (20.207%)  route 0.154ns (79.793%))
  Logic Levels:           0  
  Clock Path Skew:        0.139ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.968ns
    Source Clock Delay      (SCD):    2.946ns
    Clock Pessimism Removal (CPR):    -0.116ns
  Clock Net Delay (Source):      1.093ns (routing 0.435ns, distribution 0.658ns)
  Clock Net Delay (Destination): 1.350ns (routing 0.485ns, distribution 0.865ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.836    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.853 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.093     2.946    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X81Y204        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_clb2phy_fifo_rden_reg[89]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y204        FDSE (Prop_GFF_SLICEL_C_Q)
                                                      0.039     2.985 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_clb2phy_fifo_rden_reg[89]/Q
                         net (fo=1, routed)           0.154     3.139    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/ch0_mcal_clb2phy_fifo_rden[0]
    BITSLICE_RX_TX_X0Y180
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/FIFO_RD_EN
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.350     2.968    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/div_clk
    BITSLICE_RX_TX_X0Y180
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/FIFO_RD_CLK
                         clock pessimism              0.116     3.084    
    BITSLICE_RX_TX_X0Y180
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_FIFO_RD_CLK_FIFO_RD_EN)
                                                      0.044     3.128    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -3.128    
                         arrival time                           3.139    
  -------------------------------------------------------------------
                         slack                                  0.010    

Slack (MET) :             0.012ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/mcal_DQIn_r_reg[325]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/mcal_DQIn_r_valid_reg[325]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout0 rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.286ns  (logic 0.059ns (20.663%)  route 0.227ns (79.337%))
  Logic Levels:           0  
  Clock Path Skew:        0.211ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.795ns
    Source Clock Delay      (SCD):    4.903ns
    Clock Pessimism Removal (CPR):    -0.319ns
  Clock Net Delay (Source):      1.750ns (routing 0.716ns, distribution 1.034ns)
  Clock Net Delay (Destination): 2.033ns (routing 0.788ns, distribution 1.245ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.129    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.750     4.903    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/odt_shift_reg[0][17]
    SLICE_X95Y228        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/mcal_DQIn_r_reg[325]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y228        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.059     4.962 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/mcal_DQIn_r_reg[325]/Q
                         net (fo=5, routed)           0.227     5.188    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/mcal_DQIn_r_reg_n_0_[325]
    SLICE_X94Y246        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/mcal_DQIn_r_valid_reg[325]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.033     4.795    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/odt_shift_reg[0][17]
    SLICE_X94Y246        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/mcal_DQIn_r_valid_reg[325]/C
                         clock pessimism              0.319     5.114    
    SLICE_X94Y246        FDRE (Hold_FFF2_SLICEM_C_D)
                                                      0.062     5.176    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/mcal_DQIn_r_valid_reg[325]
  -------------------------------------------------------------------
                         required time                         -5.176    
                         arrival time                           5.188    
  -------------------------------------------------------------------
                         slack                                  0.012    

Slack (MET) :             0.014ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/converter.wrap_narrow_inst/w_payld_fifo/mesg_reg_reg[355]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMB/I
                            (rising edge-triggered cell RAMD32 clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout0 rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.215ns  (logic 0.060ns (27.907%)  route 0.155ns (72.093%))
  Logic Levels:           0  
  Clock Path Skew:        0.123ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.918ns
    Source Clock Delay      (SCD):    5.045ns
    Clock Pessimism Removal (CPR):    -0.250ns
  Clock Net Delay (Source):      1.892ns (routing 0.716ns, distribution 1.176ns)
  Clock Net Delay (Destination): 2.156ns (routing 0.788ns, distribution 1.368ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.129    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.892     5.045    d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/converter.wrap_narrow_inst/w_payld_fifo/aclk
    SLICE_X75Y221        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/converter.wrap_narrow_inst/w_payld_fifo/mesg_reg_reg[355]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X75Y221        FDRE (Prop_AFF2_SLICEM_C_Q)
                                                      0.060     5.105 r  d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/converter.wrap_narrow_inst/w_payld_fifo/mesg_reg_reg[355]/Q
                         net (fo=1, routed)           0.155     5.260    d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/DIB0
    SLICE_X72Y221        RAMD32                                       r  d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMB/I
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.156     4.918    d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/WCLK
    SLICE_X72Y221        RAMD32                                       r  d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMB/CLK
                         clock pessimism              0.250     5.168    
    SLICE_X72Y221        RAMD32 (Hold_B5LUT_SLICEM_CLK_I)
                                                      0.078     5.246    d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMB
  -------------------------------------------------------------------
                         required time                         -5.246    
                         arrival time                           5.260    
  -------------------------------------------------------------------
                         slack                                  0.014    

Slack (MET) :             0.014ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_clb2phy_fifo_rden_reg[42]/C
                            (rising edge-triggered cell FDSE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/FIFO_RD_EN
                            (rising edge-triggered cell RXTX_BITSLICE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout0 rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.191ns  (logic 0.040ns (20.942%)  route 0.151ns (79.058%))
  Logic Levels:           0  
  Clock Path Skew:        0.137ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.006ns
    Source Clock Delay      (SCD):    2.982ns
    Clock Pessimism Removal (CPR):    -0.113ns
  Clock Net Delay (Source):      1.129ns (routing 0.435ns, distribution 0.694ns)
  Clock Net Delay (Destination): 1.387ns (routing 0.485ns, distribution 0.902ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.836    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.853 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.129     2.982    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X81Y246        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_clb2phy_fifo_rden_reg[42]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y246        FDSE (Prop_EFF2_SLICEL_C_Q)
                                                      0.040     3.022 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_clb2phy_fifo_rden_reg[42]/Q
                         net (fo=1, routed)           0.151     3.173    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/ch0_mcal_clb2phy_fifo_rden[0]
    BITSLICE_RX_TX_X0Y211
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/FIFO_RD_EN
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.387     3.006    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/div_clk
    BITSLICE_RX_TX_X0Y211
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/FIFO_RD_CLK
                         clock pessimism              0.113     3.119    
    BITSLICE_RX_TX_X0Y211
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_FIFO_RD_CLK_FIFO_RD_EN)
                                                      0.040     3.159    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -3.159    
                         arrival time                           3.173    
  -------------------------------------------------------------------
                         slack                                  0.014    

Slack (MET) :             0.015ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/fifo_dout_r_reg[260]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/w_sreg/skid_buffer_reg[1285]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout0 rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.195ns  (logic 0.058ns (29.749%)  route 0.137ns (70.251%))
  Logic Levels:           0  
  Clock Path Skew:        0.118ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.009ns
    Source Clock Delay      (SCD):    5.129ns
    Clock Pessimism Removal (CPR):    -0.238ns
  Clock Net Delay (Source):      1.976ns (routing 0.716ns, distribution 1.260ns)
  Clock Net Delay (Destination): 2.247ns (routing 0.788ns, distribution 1.459ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.129    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.976     5.129    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X52Y232        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/fifo_dout_r_reg[260]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y232        FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.058     5.187 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/fifo_dout_r_reg[260]/Q
                         net (fo=2, routed)           0.137     5.324    d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/w_sreg/skid_buffer_reg[2112]_0[261]
    SLICE_X51Y233        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/w_sreg/skid_buffer_reg[1285]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.247     5.009    d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/w_sreg/aclk
    SLICE_X51Y233        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/w_sreg/skid_buffer_reg[1285]/C
                         clock pessimism              0.238     5.247    
    SLICE_X51Y233        FDRE (Hold_HFF2_SLICEL_C_D)
                                                      0.062     5.309    d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/w_sreg/skid_buffer_reg[1285]
  -------------------------------------------------------------------
                         required time                         -5.309    
                         arrival time                           5.324    
  -------------------------------------------------------------------
                         slack                                  0.015    

Slack (MET) :             0.016ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_clb2phy_fifo_rden_reg[88]/C
                            (rising edge-triggered cell FDSE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/FIFO_RD_EN
                            (rising edge-triggered cell RXTX_BITSLICE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout0 rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.192ns  (logic 0.040ns (20.833%)  route 0.152ns (79.167%))
  Logic Levels:           0  
  Clock Path Skew:        0.135ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.964ns
    Source Clock Delay      (SCD):    2.946ns
    Clock Pessimism Removal (CPR):    -0.116ns
  Clock Net Delay (Source):      1.093ns (routing 0.435ns, distribution 0.658ns)
  Clock Net Delay (Destination): 1.346ns (routing 0.485ns, distribution 0.861ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.836    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.853 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.093     2.946    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X81Y204        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_clb2phy_fifo_rden_reg[88]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y204        FDSE (Prop_FFF2_SLICEL_C_Q)
                                                      0.040     2.986 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_clb2phy_fifo_rden_reg[88]/Q
                         net (fo=1, routed)           0.152     3.138    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/ch0_mcal_clb2phy_fifo_rden[0]
    BITSLICE_RX_TX_X0Y179
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/FIFO_RD_EN
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.346     2.964    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/div_clk
    BITSLICE_RX_TX_X0Y179
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/FIFO_RD_CLK
                         clock pessimism              0.116     3.080    
    BITSLICE_RX_TX_X0Y179
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_FIFO_RD_CLK_FIFO_RD_EN)
                                                      0.041     3.121    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -3.121    
                         arrival time                           3.138    
  -------------------------------------------------------------------
                         slack                                  0.016    

Slack (MET) :             0.018ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/rdData_reg[396]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0/RAMC/I
                            (rising edge-triggered cell RAMD32 clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout0 rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.162ns  (logic 0.059ns (36.378%)  route 0.103ns (63.623%))
  Logic Levels:           0  
  Clock Path Skew:        0.066ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.747ns
    Source Clock Delay      (SCD):    4.889ns
    Clock Pessimism Removal (CPR):    -0.208ns
  Clock Net Delay (Source):      1.736ns (routing 0.716ns, distribution 1.020ns)
  Clock Net Delay (Destination): 1.985ns (routing 0.788ns, distribution 1.197ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.129    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.736     4.889    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X95Y197        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/rdData_reg[396]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y197        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.059     4.948 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/rdData_reg[396]/Q
                         net (fo=3, routed)           0.103     5.051    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0/DIC0
    SLICE_X94Y195        RAMD32                                       r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0/RAMC/I
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.985     4.747    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0/WCLK
    SLICE_X94Y195        RAMD32                                       r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0/RAMC/CLK
                         clock pessimism              0.208     4.955    
    SLICE_X94Y195        RAMD32 (Hold_G5LUT_SLICEM_CLK_I)
                                                      0.078     5.033    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0/RAMC
  -------------------------------------------------------------------
                         required time                         -5.033    
                         arrival time                           5.051    
  -------------------------------------------------------------------
                         slack                                  0.018    

Slack (MET) :             0.018ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[2].inst_xpm_memory/xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[73]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/w_reg/skid_buffer_reg[1347]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout0 rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.195ns  (logic 0.058ns (29.788%)  route 0.137ns (70.212%))
  Logic Levels:           0  
  Clock Path Skew:        0.114ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.896ns
    Source Clock Delay      (SCD):    5.032ns
    Clock Pessimism Removal (CPR):    -0.250ns
  Clock Net Delay (Source):      1.879ns (routing 0.716ns, distribution 1.163ns)
  Clock Net Delay (Destination): 2.134ns (routing 0.788ns, distribution 1.346ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.129    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.879     5.032    d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[2].inst_xpm_memory/xpm_memory_base_inst/clka
    SLICE_X78Y205        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[2].inst_xpm_memory/xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[73]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X78Y205        FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.058     5.090 r  d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[2].inst_xpm_memory/xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[73]/Q
                         net (fo=2, routed)           0.137     5.226    d_1_i/ddr4/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/w_reg/D[323]
    SLICE_X77Y203        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/w_reg/skid_buffer_reg[1347]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.134     4.896    d_1_i/ddr4/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/w_reg/aclk
    SLICE_X77Y203        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/w_reg/skid_buffer_reg[1347]/C
                         clock pessimism              0.250     5.146    
    SLICE_X77Y203        FDRE (Hold_GFF2_SLICEL_C_D)
                                                      0.062     5.208    d_1_i/ddr4/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/w_reg/skid_buffer_reg[1347]
  -------------------------------------------------------------------
                         required time                         -5.208    
                         arrival time                           5.226    
  -------------------------------------------------------------------
                         slack                                  0.018    

Slack (MET) :             0.018ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_wr.inst_wr_addra_p1/count_r_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_wr.inst_wr_addra_p1/count_r_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout0 rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.167ns  (logic 0.090ns (53.805%)  route 0.077ns (46.195%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        0.087ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.971ns
    Source Clock Delay      (SCD):    5.122ns
    Clock Pessimism Removal (CPR):    -0.238ns
  Clock Net Delay (Source):      1.969ns (routing 0.716ns, distribution 1.253ns)
  Clock Net Delay (Destination): 2.209ns (routing 0.788ns, distribution 1.421ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.129    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.969     5.122    d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_wr.inst_wr_addra_p1/s_sc_aclk
    SLICE_X55Y195        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_wr.inst_wr_addra_p1/count_r_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X55Y195        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.058     5.180 r  d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_wr.inst_wr_addra_p1/count_r_reg[3]/Q
                         net (fo=5, routed)           0.067     5.247    d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_wr.inst_wr_addra_p1/gen_wr.wr_addra_p1[3]
    SLICE_X57Y195        LUT5 (Prop_B5LUT_SLICEL_I4_O)
                                                      0.032     5.279 r  d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_wr.inst_wr_addra_p1/count_r[4]_i_1__5/O
                         net (fo=1, routed)           0.010     5.289    d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_wr.inst_wr_addra_p1/count_r[4]_i_1__5_n_0
    SLICE_X57Y195        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_wr.inst_wr_addra_p1/count_r_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.209     4.971    d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_wr.inst_wr_addra_p1/s_sc_aclk
    SLICE_X57Y195        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_wr.inst_wr_addra_p1/count_r_reg[4]/C
                         clock pessimism              0.238     5.209    
    SLICE_X57Y195        FDRE (Hold_BFF2_SLICEL_C_D)
                                                      0.062     5.271    d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_wr.inst_wr_addra_p1/count_r_reg[4]
  -------------------------------------------------------------------
                         required time                         -5.271    
                         arrival time                           5.289    
  -------------------------------------------------------------------
                         slack                                  0.018    

Slack (MET) :             0.019ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[41]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/w_reg/skid_buffer_reg[1047]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout0 rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.288ns  (logic 0.058ns (20.173%)  route 0.230ns (79.827%))
  Logic Levels:           0  
  Clock Path Skew:        0.206ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.944ns
    Source Clock Delay      (SCD):    5.057ns
    Clock Pessimism Removal (CPR):    -0.319ns
  Clock Net Delay (Source):      1.904ns (routing 0.716ns, distribution 1.188ns)
  Clock Net Delay (Destination): 2.182ns (routing 0.788ns, distribution 1.394ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.129    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.904     5.057    d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/clka
    SLICE_X69Y220        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[41]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X69Y220        FDRE (Prop_GFF_SLICEM_C_Q)
                                                      0.058     5.115 r  d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[41]/Q
                         net (fo=2, routed)           0.230     5.344    d_1_i/ddr4/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/w_reg/D[23]
    SLICE_X68Y248        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/w_reg/skid_buffer_reg[1047]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.182     4.944    d_1_i/ddr4/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/w_reg/aclk
    SLICE_X68Y248        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/w_reg/skid_buffer_reg[1047]/C
                         clock pessimism              0.319     5.263    
    SLICE_X68Y248        FDRE (Hold_EFF2_SLICEL_C_D)
                                                      0.062     5.325    d_1_i/ddr4/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/w_reg/skid_buffer_reg[1047]
  -------------------------------------------------------------------
                         required time                         -5.325    
                         arrival time                           5.344    
  -------------------------------------------------------------------
                         slack                                  0.019    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         mmcm_clkout0
Waveform(ns):       { 0.000 1.500 }
Period(ns):         3.001
Sources:            { d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0 }

Check Type        Corner  Lib Pin                    Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location               Pin
Min Period        n/a     PS8/MAXIGP1ACLK            n/a            3.000         3.001       0.001      PS8_X0Y0               d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP1ACLK
Min Period        n/a     RXTX_BITSLICE/FIFO_RD_CLK  n/a            1.694         3.001       1.307      BITSLICE_RX_TX_X0Y156  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/FIFO_RD_CLK
Min Period        n/a     RXTX_BITSLICE/FIFO_RD_CLK  n/a            1.694         3.001       1.307      BITSLICE_RX_TX_X0Y158  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/FIFO_RD_CLK
Min Period        n/a     RXTX_BITSLICE/FIFO_RD_CLK  n/a            1.694         3.001       1.307      BITSLICE_RX_TX_X0Y159  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/FIFO_RD_CLK
Min Period        n/a     RXTX_BITSLICE/FIFO_RD_CLK  n/a            1.694         3.001       1.307      BITSLICE_RX_TX_X0Y160  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/FIFO_RD_CLK
Min Period        n/a     RXTX_BITSLICE/FIFO_RD_CLK  n/a            1.694         3.001       1.307      BITSLICE_RX_TX_X0Y161  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/FIFO_RD_CLK
Min Period        n/a     RXTX_BITSLICE/FIFO_RD_CLK  n/a            1.694         3.001       1.307      BITSLICE_RX_TX_X0Y162  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/FIFO_RD_CLK
Min Period        n/a     RXTX_BITSLICE/FIFO_RD_CLK  n/a            1.694         3.001       1.307      BITSLICE_RX_TX_X0Y164  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/FIFO_RD_CLK
Min Period        n/a     RXTX_BITSLICE/FIFO_RD_CLK  n/a            1.694         3.001       1.307      BITSLICE_RX_TX_X0Y165  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/FIFO_RD_CLK
Min Period        n/a     RXTX_BITSLICE/FIFO_RD_CLK  n/a            1.694         3.001       1.307      BITSLICE_RX_TX_X0Y166  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/FIFO_RD_CLK
Max Period        n/a     PLLE4_ADV/CLKIN            n/a            14.286        3.001       11.285     PLL_X0Y7               d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
Max Period        n/a     PLLE4_ADV/CLKIN            n/a            14.286        3.001       11.285     PLL_X0Y8               d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
Max Period        n/a     PLLE4_ADV/CLKIN            n/a            14.286        3.001       11.285     PLL_X0Y11              d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
Low Pulse Width   Fast    PS8/MAXIGP1ACLK            n/a            1.500         1.500       0.000      PS8_X0Y0               d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP1ACLK
Low Pulse Width   Slow    PS8/MAXIGP1ACLK            n/a            1.500         1.500       0.000      PS8_X0Y0               d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP1ACLK
Low Pulse Width   Slow    PLLE4_ADV/CLKIN            n/a            1.050         1.500       0.450      PLL_X0Y7               d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
Low Pulse Width   Fast    PLLE4_ADV/CLKIN            n/a            1.050         1.500       0.450      PLL_X0Y7               d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
Low Pulse Width   Slow    PLLE4_ADV/CLKIN            n/a            1.050         1.500       0.450      PLL_X0Y8               d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
Low Pulse Width   Fast    PLLE4_ADV/CLKIN            n/a            1.050         1.500       0.450      PLL_X0Y8               d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
Low Pulse Width   Slow    PLLE4_ADV/CLKIN            n/a            1.050         1.500       0.450      PLL_X0Y11              d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
Low Pulse Width   Fast    PLLE4_ADV/CLKIN            n/a            1.050         1.500       0.450      PLL_X0Y11              d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
Low Pulse Width   Slow    RXTX_BITSLICE/FIFO_RD_CLK  n/a            0.762         1.500       0.738      BITSLICE_RX_TX_X0Y156  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/FIFO_RD_CLK
Low Pulse Width   Fast    RXTX_BITSLICE/FIFO_RD_CLK  n/a            0.762         1.500       0.738      BITSLICE_RX_TX_X0Y156  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/FIFO_RD_CLK
High Pulse Width  Slow    PS8/MAXIGP1ACLK            n/a            1.500         1.500       0.000      PS8_X0Y0               d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP1ACLK
High Pulse Width  Fast    PS8/MAXIGP1ACLK            n/a            1.500         1.500       0.000      PS8_X0Y0               d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP1ACLK
High Pulse Width  Slow    PLLE4_ADV/CLKIN            n/a            1.050         1.500       0.450      PLL_X0Y7               d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
High Pulse Width  Fast    PLLE4_ADV/CLKIN            n/a            1.050         1.500       0.450      PLL_X0Y7               d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
High Pulse Width  Slow    PLLE4_ADV/CLKIN            n/a            1.050         1.500       0.450      PLL_X0Y8               d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
High Pulse Width  Fast    PLLE4_ADV/CLKIN            n/a            1.050         1.500       0.450      PLL_X0Y8               d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
High Pulse Width  Slow    PLLE4_ADV/CLKIN            n/a            1.050         1.500       0.450      PLL_X0Y11              d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
High Pulse Width  Fast    PLLE4_ADV/CLKIN            n/a            1.050         1.500       0.450      PLL_X0Y11              d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
High Pulse Width  Slow    RXTX_BITSLICE/FIFO_RD_CLK  n/a            0.762         1.500       0.738      BITSLICE_RX_TX_X0Y156  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/FIFO_RD_CLK
High Pulse Width  Fast    RXTX_BITSLICE/FIFO_RD_CLK  n/a            0.762         1.500       0.738      BITSLICE_RX_TX_X0Y156  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/FIFO_RD_CLK



---------------------------------------------------------------------------------------------------
From Clock:  pll_clk[0]
  To Clock:  pll_clk[0]

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        0.000ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         pll_clk[0]
Waveform(ns):       { 0.000 0.188 }
Period(ns):         0.375
Sources:            { d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY }

Check Type        Corner  Lib Pin                   Reference Pin             Required(ns)  Actual(ns)  Slack(ns)  Location                Pin
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y24  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y25  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y26  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y27  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y28  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y29  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y30  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y31  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     PLLE4_ADV/CLKOUTPHY       n/a                       0.333         0.375       0.042      PLL_X0Y7                d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y25  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y28  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y29  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y31  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y24  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y24  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y25  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y26  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y26  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y27  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y24  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y24  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y25  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y26  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y26  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y27  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y27  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y28  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y29  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y30  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.316      1.016      BITSLICE_CONTROL_X0Y28  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.319      1.019      BITSLICE_CONTROL_X0Y30  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.322      1.022      BITSLICE_CONTROL_X0Y29  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.323      1.023      BITSLICE_CONTROL_X0Y26  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.323      1.023      BITSLICE_CONTROL_X0Y27  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.323      1.023      BITSLICE_CONTROL_X0Y31  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.324      1.024      BITSLICE_CONTROL_X0Y24  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.326      1.026      BITSLICE_CONTROL_X0Y25  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Slow    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.469      1.169      BITSLICE_CONTROL_X0Y28  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Slow    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.476      1.176      BITSLICE_CONTROL_X0Y30  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK



---------------------------------------------------------------------------------------------------
From Clock:  pll_clk[0]_DIV
  To Clock:  pll_clk[0]_DIV

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        0.300ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         pll_clk[0]_DIV
Waveform(ns):       { 0.000 1.500 }
Period(ns):         3.001
Sources:            { d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q }

Check Type        Corner  Lib Pin                           Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location               Pin
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y156  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y158  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y159  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y160  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y161  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y162  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y164  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y165  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y166  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y167  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y156  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y156  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y158  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y158  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y159  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y159  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y160  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y160  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y161  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y161  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y156  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y156  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y158  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y158  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y159  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y159  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y160  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y160  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y161  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y161  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]



---------------------------------------------------------------------------------------------------
From Clock:  pll_clk[1]
  To Clock:  pll_clk[1]

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        0.000ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         pll_clk[1]
Waveform(ns):       { 0.000 0.188 }
Period(ns):         0.375
Sources:            { d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY }

Check Type        Corner  Lib Pin                   Reference Pin             Required(ns)  Actual(ns)  Slack(ns)  Location                Pin
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y32  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y33  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y34  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y35  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y36  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y37  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y38  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y39  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     PLLE4_ADV/CLKOUTPHY       n/a                       0.333         0.375       0.042      PLL_X0Y8                d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y32  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y32  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y33  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y33  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y34  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y35  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y36  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y36  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y37  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y37  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y34  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y35  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y38  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y33  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y33  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y34  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y35  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y36  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y36  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y37  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.308      1.008      BITSLICE_CONTROL_X0Y36  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.312      1.012      BITSLICE_CONTROL_X0Y38  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.314      1.014      BITSLICE_CONTROL_X0Y37  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.315      1.015      BITSLICE_CONTROL_X0Y34  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.316      1.016      BITSLICE_CONTROL_X0Y32  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.316      1.016      BITSLICE_CONTROL_X0Y39  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.318      1.018      BITSLICE_CONTROL_X0Y33  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.318      1.018      BITSLICE_CONTROL_X0Y35  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Slow    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.456      1.156      BITSLICE_CONTROL_X0Y36  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Slow    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.464      1.164      BITSLICE_CONTROL_X0Y38  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK



---------------------------------------------------------------------------------------------------
From Clock:  pll_clk[1]_DIV
  To Clock:  pll_clk[1]_DIV

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        0.300ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         pll_clk[1]_DIV
Waveform(ns):       { 0.000 1.500 }
Period(ns):         3.001
Sources:            { d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q }

Check Type        Corner  Lib Pin                           Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location               Pin
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y208  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y210  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y211  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y212  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y213  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y214  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y216  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y217  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y218  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y219  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y208  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y208  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y210  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y210  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y211  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y211  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y212  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y212  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y213  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y213  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y208  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y208  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y210  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y210  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y211  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y211  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y212  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y212  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y213  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y213  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]



---------------------------------------------------------------------------------------------------
From Clock:  pll_clk[2]
  To Clock:  pll_clk[2]

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        0.000ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         pll_clk[2]
Waveform(ns):       { 0.000 0.188 }
Period(ns):         0.375
Sources:            { d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY }

Check Type        Corner  Lib Pin                   Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location                Pin
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a            0.375         0.375       0.000      BITSLICE_CONTROL_X0Y44  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a            0.375         0.375       0.000      BITSLICE_CONTROL_X0Y45  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a            0.375         0.375       0.000      BITSLICE_CONTROL_X0Y46  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a            0.375         0.375       0.000      BITSLICE_CONTROL_X0Y47  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a            0.375         0.375       0.000      BITSLICE_CONTROL_X0Y42  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a            0.375         0.375       0.000      BITSLICE_CONTROL_X0Y43  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     PLLE4_ADV/CLKOUTPHY       n/a            0.333         0.375       0.042      PLL_X0Y11               d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y44  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y45  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y44  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y45  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y46  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y46  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y47  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y47  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y42  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y42  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y44  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y45  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y46  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y46  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y47  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y47  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y44  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y45  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y42  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y42  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK



---------------------------------------------------------------------------------------------------
From Clock:  pll_clk[2]_DIV
  To Clock:  pll_clk[2]_DIV

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        0.300ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         pll_clk[2]_DIV
Waveform(ns):       { 0.000 1.500 }
Period(ns):         3.001
Sources:            { d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q }

Check Type        Corner  Lib Pin                           Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location               Pin
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y286  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y288  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y289  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y290  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y291  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y292  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y293  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y294  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y295  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y296  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y286  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y286  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y288  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y288  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y289  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y289  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y290  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y290  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y291  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y291  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y286  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y286  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y288  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y288  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y289  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y289  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y290  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y290  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y291  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y291  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]



---------------------------------------------------------------------------------------------------
From Clock:  mmcm_clkout5
  To Clock:  mmcm_clkout5

Setup :            0  Failing Endpoints,  Worst Slack        9.638ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.017ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        5.469ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             9.638ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_MSTR2SL_PORT_IFACE/SL_DRDY_O_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_rst_r_reg[0]/CE
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        2.191ns  (logic 0.394ns (17.981%)  route 1.797ns (82.019%))
  Logic Levels:           4  (LUT4=1 LUT5=1 LUT6=2)
  Clock Path Skew:        -0.037ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.439ns = ( 16.441 - 12.002 ) 
    Source Clock Delay      (SCD):    4.176ns
    Clock Pessimism Removal (CPR):    -0.300ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.423ns (routing 0.539ns, distribution 0.884ns)
  Clock Net Delay (Destination): 1.294ns (routing 0.490ns, distribution 0.804ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.725    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.753 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.423     4.176    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_MSTR2SL_PORT_IFACE/clk
    SLICE_X106Y330       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_MSTR2SL_PORT_IFACE/SL_DRDY_O_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X106Y330       FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     4.255 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_MSTR2SL_PORT_IFACE/SL_DRDY_O_reg/Q
                         net (fo=11, routed)          0.552     4.806    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_drdy
    SLICE_X108Y331       LUT4 (Prop_D5LUT_SLICEL_I1_O)
                                                      0.066     4.872 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/in_normal_mode_i_5/O
                         net (fo=1, routed)           0.524     5.396    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/in_normal_mode_reg_1
    SLICE_X108Y331       LUT6 (Prop_F6LUT_SLICEL_I4_O)
                                                      0.148     5.544 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/in_normal_mode_i_4/O
                         net (fo=1, routed)           0.040     5.584    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/in_normal_mode_i_4_n_0
    SLICE_X108Y331       LUT6 (Prop_G6LUT_SLICEL_I5_O)
                                                      0.050     5.634 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/in_normal_mode_i_1/O
                         net (fo=24, routed)          0.389     6.023    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/FSM_onehot_current_state_reg[11]
    SLICE_X110Y332       LUT5 (Prop_F6LUT_SLICEM_I3_O)
                                                      0.051     6.074 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/sl_rst_r[0]_i_1/O
                         net (fo=2, routed)           0.293     6.367    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/in_normal_mode
    SLICE_X109Y332       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_rst_r_reg[0]/CE
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369    14.286    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    15.123    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    15.147 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.294    16.441    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X109Y332       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_rst_r_reg[0]/C
                         clock pessimism             -0.300    16.141    
                         clock uncertainty           -0.076    16.066    
    SLICE_X109Y332       FDCE (Setup_GFF2_SLICEM_C_CE)
                                                     -0.061    16.005    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_rst_r_reg[0]
  -------------------------------------------------------------------
                         required time                         16.005    
                         arrival time                          -6.367    
  -------------------------------------------------------------------
                         slack                                  9.638    

Slack (MET) :             9.646ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_MSTR2SL_PORT_IFACE/SL_DRDY_O_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/auto_sl_drdy_reg/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        2.263ns  (logic 0.490ns (21.648%)  route 1.773ns (78.352%))
  Logic Levels:           5  (LUT3=1 LUT4=1 LUT5=1 LUT6=2)
  Clock Path Skew:        -0.042ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.434ns = ( 16.436 - 12.002 ) 
    Source Clock Delay      (SCD):    4.176ns
    Clock Pessimism Removal (CPR):    -0.300ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.423ns (routing 0.539ns, distribution 0.884ns)
  Clock Net Delay (Destination): 1.289ns (routing 0.490ns, distribution 0.799ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.725    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.753 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.423     4.176    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_MSTR2SL_PORT_IFACE/clk
    SLICE_X106Y330       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_MSTR2SL_PORT_IFACE/SL_DRDY_O_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X106Y330       FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     4.255 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_MSTR2SL_PORT_IFACE/SL_DRDY_O_reg/Q
                         net (fo=11, routed)          0.552     4.806    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_drdy
    SLICE_X108Y331       LUT4 (Prop_D5LUT_SLICEL_I1_O)
                                                      0.066     4.872 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/in_normal_mode_i_5/O
                         net (fo=1, routed)           0.524     5.396    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/in_normal_mode_reg_1
    SLICE_X108Y331       LUT6 (Prop_F6LUT_SLICEL_I4_O)
                                                      0.148     5.544 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/in_normal_mode_i_4/O
                         net (fo=1, routed)           0.040     5.584    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/in_normal_mode_i_4_n_0
    SLICE_X108Y331       LUT6 (Prop_G6LUT_SLICEL_I5_O)
                                                      0.050     5.634 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/in_normal_mode_i_1/O
                         net (fo=24, routed)          0.342     5.976    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/FSM_onehot_current_state_reg[11]
    SLICE_X110Y332       LUT5 (Prop_D5LUT_SLICEM_I3_O)
                                                      0.097     6.073 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__1/O
                         net (fo=1, routed)           0.267     6.340    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__1_n_0
    SLICE_X108Y332       LUT3 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.050     6.390 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/auto_sl_drdy_i_1/O
                         net (fo=1, routed)           0.049     6.439    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER_n_8
    SLICE_X108Y332       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/auto_sl_drdy_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369    14.286    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    15.123    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    15.147 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.289    16.436    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X108Y332       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/auto_sl_drdy_reg/C
                         clock pessimism             -0.300    16.136    
                         clock uncertainty           -0.076    16.061    
    SLICE_X108Y332       FDCE (Setup_DFF_SLICEL_C_D)
                                                      0.025    16.086    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/auto_sl_drdy_reg
  -------------------------------------------------------------------
                         required time                         16.086    
                         arrival time                          -6.439    
  -------------------------------------------------------------------
                         slack                                  9.646    

Slack (MET) :             9.648ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_MSTR2SL_PORT_IFACE/SL_DRDY_O_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/dec_wdc_r_reg/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        2.264ns  (logic 0.594ns (26.231%)  route 1.670ns (73.769%))
  Logic Levels:           5  (LUT3=1 LUT4=1 LUT5=1 LUT6=2)
  Clock Path Skew:        -0.040ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.436ns = ( 16.438 - 12.002 ) 
    Source Clock Delay      (SCD):    4.176ns
    Clock Pessimism Removal (CPR):    -0.300ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.423ns (routing 0.539ns, distribution 0.884ns)
  Clock Net Delay (Destination): 1.291ns (routing 0.490ns, distribution 0.801ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.725    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.753 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.423     4.176    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_MSTR2SL_PORT_IFACE/clk
    SLICE_X106Y330       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_MSTR2SL_PORT_IFACE/SL_DRDY_O_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X106Y330       FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     4.255 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_MSTR2SL_PORT_IFACE/SL_DRDY_O_reg/Q
                         net (fo=11, routed)          0.552     4.806    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_drdy
    SLICE_X108Y331       LUT4 (Prop_D5LUT_SLICEL_I1_O)
                                                      0.066     4.872 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/in_normal_mode_i_5/O
                         net (fo=1, routed)           0.524     5.396    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/in_normal_mode_reg_1
    SLICE_X108Y331       LUT6 (Prop_F6LUT_SLICEL_I4_O)
                                                      0.148     5.544 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/in_normal_mode_i_4/O
                         net (fo=1, routed)           0.040     5.584    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/in_normal_mode_i_4_n_0
    SLICE_X108Y331       LUT6 (Prop_G6LUT_SLICEL_I5_O)
                                                      0.050     5.634 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/in_normal_mode_i_1/O
                         net (fo=24, routed)          0.342     5.976    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/FSM_onehot_current_state_reg[11]
    SLICE_X110Y332       LUT5 (Prop_C5LUT_SLICEM_I3_O)
                                                      0.099     6.075 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__7/O
                         net (fo=1, routed)           0.155     6.230    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__7_n_0
    SLICE_X110Y332       LUT3 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.152     6.382 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/dec_wdc_r_i_1/O
                         net (fo=1, routed)           0.058     6.440    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER_n_10
    SLICE_X110Y332       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/dec_wdc_r_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369    14.286    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    15.123    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    15.147 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.291    16.438    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X110Y332       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/dec_wdc_r_reg/C
                         clock pessimism             -0.300    16.139    
                         clock uncertainty           -0.076    16.063    
    SLICE_X110Y332       FDCE (Setup_HFF_SLICEM_C_D)
                                                      0.025    16.088    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/dec_wdc_r_reg
  -------------------------------------------------------------------
                         required time                         16.088    
                         arrival time                          -6.440    
  -------------------------------------------------------------------
                         slack                                  9.648    

Slack (MET) :             9.766ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_MSTR2SL_PORT_IFACE/SL_DRDY_O_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/inc_addr_r_reg/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        2.149ns  (logic 0.531ns (24.704%)  route 1.618ns (75.296%))
  Logic Levels:           5  (LUT3=1 LUT4=1 LUT5=1 LUT6=2)
  Clock Path Skew:        -0.036ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.440ns = ( 16.442 - 12.002 ) 
    Source Clock Delay      (SCD):    4.176ns
    Clock Pessimism Removal (CPR):    -0.300ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.423ns (routing 0.539ns, distribution 0.884ns)
  Clock Net Delay (Destination): 1.295ns (routing 0.490ns, distribution 0.805ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.725    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.753 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.423     4.176    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_MSTR2SL_PORT_IFACE/clk
    SLICE_X106Y330       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_MSTR2SL_PORT_IFACE/SL_DRDY_O_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X106Y330       FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     4.255 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_MSTR2SL_PORT_IFACE/SL_DRDY_O_reg/Q
                         net (fo=11, routed)          0.552     4.806    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_drdy
    SLICE_X108Y331       LUT4 (Prop_D5LUT_SLICEL_I1_O)
                                                      0.066     4.872 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/in_normal_mode_i_5/O
                         net (fo=1, routed)           0.524     5.396    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/in_normal_mode_reg_1
    SLICE_X108Y331       LUT6 (Prop_F6LUT_SLICEL_I4_O)
                                                      0.148     5.544 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/in_normal_mode_i_4/O
                         net (fo=1, routed)           0.040     5.584    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/in_normal_mode_i_4_n_0
    SLICE_X108Y331       LUT6 (Prop_G6LUT_SLICEL_I5_O)
                                                      0.050     5.634 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/in_normal_mode_i_1/O
                         net (fo=24, routed)          0.342     5.976    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/FSM_onehot_current_state_reg[11]
    SLICE_X110Y332       LUT5 (Prop_C6LUT_SLICEM_I3_O)
                                                      0.088     6.064 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__5/O
                         net (fo=1, routed)           0.102     6.166    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__5_n_0
    SLICE_X109Y332       LUT3 (Prop_B6LUT_SLICEM_I0_O)
                                                      0.100     6.266 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/inc_addr_r_i_1/O
                         net (fo=1, routed)           0.059     6.325    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER_n_9
    SLICE_X109Y332       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/inc_addr_r_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369    14.286    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    15.123    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    15.147 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.295    16.442    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X109Y332       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/inc_addr_r_reg/C
                         clock pessimism             -0.300    16.142    
                         clock uncertainty           -0.076    16.067    
    SLICE_X109Y332       FDCE (Setup_BFF_SLICEM_C_D)
                                                      0.025    16.092    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/inc_addr_r_reg
  -------------------------------------------------------------------
                         required time                         16.092    
                         arrival time                          -6.325    
  -------------------------------------------------------------------
                         slack                                  9.766    

Slack (MET) :             9.788ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_MSTR2SL_PORT_IFACE/SL_DRDY_O_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/in_normal_mode_reg/CE
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        2.038ns  (logic 0.394ns (19.331%)  route 1.644ns (80.669%))
  Logic Levels:           4  (LUT4=1 LUT5=1 LUT6=2)
  Clock Path Skew:        -0.040ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.436ns = ( 16.438 - 12.002 ) 
    Source Clock Delay      (SCD):    4.176ns
    Clock Pessimism Removal (CPR):    -0.300ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.423ns (routing 0.539ns, distribution 0.884ns)
  Clock Net Delay (Destination): 1.291ns (routing 0.490ns, distribution 0.801ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.725    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.753 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.423     4.176    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_MSTR2SL_PORT_IFACE/clk
    SLICE_X106Y330       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_MSTR2SL_PORT_IFACE/SL_DRDY_O_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X106Y330       FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     4.255 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_MSTR2SL_PORT_IFACE/SL_DRDY_O_reg/Q
                         net (fo=11, routed)          0.552     4.806    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_drdy
    SLICE_X108Y331       LUT4 (Prop_D5LUT_SLICEL_I1_O)
                                                      0.066     4.872 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/in_normal_mode_i_5/O
                         net (fo=1, routed)           0.524     5.396    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/in_normal_mode_reg_1
    SLICE_X108Y331       LUT6 (Prop_F6LUT_SLICEL_I4_O)
                                                      0.148     5.544 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/in_normal_mode_i_4/O
                         net (fo=1, routed)           0.040     5.584    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/in_normal_mode_i_4_n_0
    SLICE_X108Y331       LUT6 (Prop_G6LUT_SLICEL_I5_O)
                                                      0.050     5.634 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/in_normal_mode_i_1/O
                         net (fo=24, routed)          0.389     6.023    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/FSM_onehot_current_state_reg[11]
    SLICE_X110Y332       LUT5 (Prop_F6LUT_SLICEM_I3_O)
                                                      0.051     6.074 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/sl_rst_r[0]_i_1/O
                         net (fo=2, routed)           0.140     6.214    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/in_normal_mode
    SLICE_X110Y332       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/in_normal_mode_reg/CE
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369    14.286    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    15.123    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    15.147 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.291    16.438    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X110Y332       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/in_normal_mode_reg/C
                         clock pessimism             -0.300    16.139    
                         clock uncertainty           -0.076    16.063    
    SLICE_X110Y332       FDCE (Setup_HFF2_SLICEM_C_CE)
                                                     -0.061    16.002    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/in_normal_mode_reg
  -------------------------------------------------------------------
                         required time                         16.002    
                         arrival time                          -6.214    
  -------------------------------------------------------------------
                         slack                                  9.788    

Slack (MET) :             9.798ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/addr_reg[15]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_test_reg[15]/CE
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        1.895ns  (logic 0.293ns (15.463%)  route 1.602ns (84.537%))
  Logic Levels:           2  (LUT6=2)
  Clock Path Skew:        -0.174ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.336ns = ( 16.338 - 12.002 ) 
    Source Clock Delay      (SCD):    4.206ns
    Clock Pessimism Removal (CPR):    -0.304ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.453ns (routing 0.539ns, distribution 0.914ns)
  Clock Net Delay (Destination): 1.191ns (routing 0.490ns, distribution 0.701ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.725    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.753 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.453     4.206    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/clk
    SLICE_X106Y340       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/addr_reg[15]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X106Y340       FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     4.285 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/addr_reg[15]/Q
                         net (fo=3, routed)           0.760     5.045    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[19]
    SLICE_X96Y337        LUT6 (Prop_H6LUT_SLICEM_I5_O)
                                                      0.125     5.170 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_den_r_i_2/O
                         net (fo=3, routed)           0.378     5.548    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_den_r_i_2_n_0
    SLICE_X95Y329        LUT6 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.089     5.637 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_test[15]_i_1/O
                         net (fo=16, routed)          0.464     6.101    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_test0
    SLICE_X94Y330        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_test_reg[15]/CE
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369    14.286    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    15.123    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    15.147 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.191    16.338    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X94Y330        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_test_reg[15]/C
                         clock pessimism             -0.304    16.034    
                         clock uncertainty           -0.076    15.958    
    SLICE_X94Y330        FDRE (Setup_DFF2_SLICEM_C_CE)
                                                     -0.060    15.898    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_test_reg[15]
  -------------------------------------------------------------------
                         required time                         15.898    
                         arrival time                          -6.101    
  -------------------------------------------------------------------
                         slack                                  9.798    

Slack (MET) :             9.798ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_MSTR2SL_PORT_IFACE/SL_DRDY_O_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_berr_r_reg[0]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        2.124ns  (logic 0.521ns (24.524%)  route 1.603ns (75.476%))
  Logic Levels:           5  (LUT4=1 LUT5=1 LUT6=3)
  Clock Path Skew:        -0.029ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.446ns = ( 16.449 - 12.002 ) 
    Source Clock Delay      (SCD):    4.176ns
    Clock Pessimism Removal (CPR):    -0.300ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.423ns (routing 0.539ns, distribution 0.884ns)
  Clock Net Delay (Destination): 1.301ns (routing 0.490ns, distribution 0.811ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.725    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.753 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.423     4.176    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_MSTR2SL_PORT_IFACE/clk
    SLICE_X106Y330       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_MSTR2SL_PORT_IFACE/SL_DRDY_O_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X106Y330       FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     4.255 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_MSTR2SL_PORT_IFACE/SL_DRDY_O_reg/Q
                         net (fo=11, routed)          0.552     4.806    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_drdy
    SLICE_X108Y331       LUT4 (Prop_D5LUT_SLICEL_I1_O)
                                                      0.066     4.872 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/in_normal_mode_i_5/O
                         net (fo=1, routed)           0.524     5.396    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/in_normal_mode_reg_1
    SLICE_X108Y331       LUT6 (Prop_F6LUT_SLICEL_I4_O)
                                                      0.148     5.544 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/in_normal_mode_i_4/O
                         net (fo=1, routed)           0.040     5.584    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/in_normal_mode_i_4_n_0
    SLICE_X108Y331       LUT6 (Prop_G6LUT_SLICEL_I5_O)
                                                      0.050     5.634 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/in_normal_mode_i_1/O
                         net (fo=24, routed)          0.342     5.976    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/FSM_onehot_current_state_reg[11]
    SLICE_X110Y332       LUT5 (Prop_D6LUT_SLICEM_I3_O)
                                                      0.088     6.064 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__0/O
                         net (fo=1, routed)           0.088     6.152    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__0_n_0
    SLICE_X110Y333       LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.090     6.242 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/sl_berr_r[0]_i_1/O
                         net (fo=1, routed)           0.058     6.300    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER_n_5
    SLICE_X110Y333       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_berr_r_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369    14.286    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    15.123    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    15.147 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.301    16.449    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X110Y333       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_berr_r_reg[0]/C
                         clock pessimism             -0.300    16.149    
                         clock uncertainty           -0.076    16.073    
    SLICE_X110Y333       FDCE (Setup_HFF_SLICEM_C_D)
                                                      0.025    16.098    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_berr_r_reg[0]
  -------------------------------------------------------------------
                         required time                         16.098    
                         arrival time                          -6.300    
  -------------------------------------------------------------------
                         slack                                  9.798    

Slack (MET) :             9.799ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/addr_reg[15]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_test_reg[6]/CE
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        1.890ns  (logic 0.293ns (15.504%)  route 1.597ns (84.496%))
  Logic Levels:           2  (LUT6=2)
  Clock Path Skew:        -0.178ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.332ns = ( 16.334 - 12.002 ) 
    Source Clock Delay      (SCD):    4.206ns
    Clock Pessimism Removal (CPR):    -0.304ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.453ns (routing 0.539ns, distribution 0.914ns)
  Clock Net Delay (Destination): 1.187ns (routing 0.490ns, distribution 0.697ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.725    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.753 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.453     4.206    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/clk
    SLICE_X106Y340       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/addr_reg[15]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X106Y340       FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     4.285 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/addr_reg[15]/Q
                         net (fo=3, routed)           0.760     5.045    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[19]
    SLICE_X96Y337        LUT6 (Prop_H6LUT_SLICEM_I5_O)
                                                      0.125     5.170 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_den_r_i_2/O
                         net (fo=3, routed)           0.378     5.548    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_den_r_i_2_n_0
    SLICE_X95Y329        LUT6 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.089     5.637 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_test[15]_i_1/O
                         net (fo=16, routed)          0.459     6.096    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_test0
    SLICE_X95Y330        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_test_reg[6]/CE
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369    14.286    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    15.123    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    15.147 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.187    16.334    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X95Y330        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_test_reg[6]/C
                         clock pessimism             -0.304    16.030    
                         clock uncertainty           -0.076    15.954    
    SLICE_X95Y330        FDRE (Setup_DFF_SLICEL_C_CE)
                                                     -0.060    15.894    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_test_reg[6]
  -------------------------------------------------------------------
                         required time                         15.894    
                         arrival time                          -6.096    
  -------------------------------------------------------------------
                         slack                                  9.799    

Slack (MET) :             9.801ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/addr_reg[15]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_test_reg[8]/CE
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        1.897ns  (logic 0.293ns (15.447%)  route 1.604ns (84.553%))
  Logic Levels:           2  (LUT6=2)
  Clock Path Skew:        -0.169ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.341ns = ( 16.344 - 12.002 ) 
    Source Clock Delay      (SCD):    4.206ns
    Clock Pessimism Removal (CPR):    -0.304ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.453ns (routing 0.539ns, distribution 0.914ns)
  Clock Net Delay (Destination): 1.196ns (routing 0.490ns, distribution 0.706ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.725    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.753 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.453     4.206    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/clk
    SLICE_X106Y340       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/addr_reg[15]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X106Y340       FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     4.285 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/addr_reg[15]/Q
                         net (fo=3, routed)           0.760     5.045    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[19]
    SLICE_X96Y337        LUT6 (Prop_H6LUT_SLICEM_I5_O)
                                                      0.125     5.170 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_den_r_i_2/O
                         net (fo=3, routed)           0.378     5.548    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_den_r_i_2_n_0
    SLICE_X95Y329        LUT6 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.089     5.637 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_test[15]_i_1/O
                         net (fo=16, routed)          0.466     6.103    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_test0
    SLICE_X95Y323        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_test_reg[8]/CE
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369    14.286    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    15.123    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    15.147 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.196    16.344    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X95Y323        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_test_reg[8]/C
                         clock pessimism             -0.304    16.039    
                         clock uncertainty           -0.076    15.964    
    SLICE_X95Y323        FDRE (Setup_HFF2_SLICEL_C_CE)
                                                     -0.060    15.904    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_test_reg[8]
  -------------------------------------------------------------------
                         required time                         15.904    
                         arrival time                          -6.103    
  -------------------------------------------------------------------
                         slack                                  9.801    

Slack (MET) :             9.801ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/addr_reg[15]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_test_reg[9]/CE
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        1.897ns  (logic 0.293ns (15.447%)  route 1.604ns (84.553%))
  Logic Levels:           2  (LUT6=2)
  Clock Path Skew:        -0.169ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.341ns = ( 16.344 - 12.002 ) 
    Source Clock Delay      (SCD):    4.206ns
    Clock Pessimism Removal (CPR):    -0.304ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.453ns (routing 0.539ns, distribution 0.914ns)
  Clock Net Delay (Destination): 1.196ns (routing 0.490ns, distribution 0.706ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.725    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.753 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.453     4.206    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/clk
    SLICE_X106Y340       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/addr_reg[15]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X106Y340       FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     4.285 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/addr_reg[15]/Q
                         net (fo=3, routed)           0.760     5.045    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[19]
    SLICE_X96Y337        LUT6 (Prop_H6LUT_SLICEM_I5_O)
                                                      0.125     5.170 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_den_r_i_2/O
                         net (fo=3, routed)           0.378     5.548    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_den_r_i_2_n_0
    SLICE_X95Y329        LUT6 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.089     5.637 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_test[15]_i_1/O
                         net (fo=16, routed)          0.466     6.103    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_test0
    SLICE_X95Y323        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_test_reg[9]/CE
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369    14.286    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    15.123    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    15.147 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.196    16.344    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X95Y323        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_test_reg[9]/C
                         clock pessimism             -0.304    16.039    
                         clock uncertainty           -0.076    15.964    
    SLICE_X95Y323        FDRE (Setup_GFF2_SLICEL_C_CE)
                                                     -0.060    15.904    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_test_reg[9]
  -------------------------------------------------------------------
                         required time                         15.904    
                         arrival time                          -6.103    
  -------------------------------------------------------------------
                         slack                                  9.801    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.017ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_MSTR2SL_PORT_IFACE/MA_RD_DIN_O_reg[15]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_14_15__0/DP/I
                            (rising edge-triggered cell RAMD32 clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.219ns  (logic 0.058ns (26.525%)  route 0.161ns (73.475%))
  Logic Levels:           0  
  Clock Path Skew:        0.123ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.265ns
    Source Clock Delay      (SCD):    4.442ns
    Clock Pessimism Removal (CPR):    -0.300ns
  Clock Net Delay (Source):      1.297ns (routing 0.490ns, distribution 0.807ns)
  Clock Net Delay (Destination): 1.512ns (routing 0.539ns, distribution 0.973ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207     3.121    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.145 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.297     4.442    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_MSTR2SL_PORT_IFACE/clk
    SLICE_X108Y337       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_MSTR2SL_PORT_IFACE/MA_RD_DIN_O_reg[15]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X108Y337       FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.058     4.500 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_MSTR2SL_PORT_IFACE/MA_RD_DIN_O_reg[15]/Q
                         net (fo=2, routed)           0.161     4.660    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_14_15__0/D
    SLICE_X109Y345       RAMD32                                       r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_14_15__0/DP/I
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.725    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.753 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.512     4.265    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_14_15__0/WCLK
    SLICE_X109Y345       RAMD32                                       r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_14_15__0/DP/CLK
                         clock pessimism              0.300     4.565    
    SLICE_X109Y345       RAMD32 (Hold_G5LUT_SLICEM_CLK_I)
                                                      0.078     4.643    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_14_15__0/DP
  -------------------------------------------------------------------
                         required time                         -4.643    
                         arrival time                           4.660    
  -------------------------------------------------------------------
                         slack                                  0.017    

Slack (MET) :             0.029ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[14]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.081ns  (logic 0.039ns (48.148%)  route 0.042ns (51.852%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.469ns
    Source Clock Delay      (SCD):    2.600ns
    Clock Pessimism Removal (CPR):    -0.137ns
  Clock Net Delay (Source):      0.753ns (routing 0.299ns, distribution 0.454ns)
  Clock Net Delay (Destination): 0.857ns (routing 0.333ns, distribution 0.524ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.830    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.847 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.753     2.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X96Y329        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[14]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y329        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.039     2.639 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[14]/Q
                         net (fo=2, routed)           0.042     2.681    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp[14]
    SLICE_X96Y329        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.593    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.612 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.857     2.469    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X96Y329        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[14]/C
                         clock pessimism              0.137     2.606    
    SLICE_X96Y329        FDRE (Hold_HFF_SLICEM_C_D)
                                                      0.046     2.652    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[14]
  -------------------------------------------------------------------
                         required time                         -2.652    
                         arrival time                           2.681    
  -------------------------------------------------------------------
                         slack                                  0.029    

Slack (MET) :             0.029ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[56]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[56]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.081ns  (logic 0.039ns (48.148%)  route 0.042ns (51.852%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.472ns
    Source Clock Delay      (SCD):    2.603ns
    Clock Pessimism Removal (CPR):    -0.137ns
  Clock Net Delay (Source):      0.756ns (routing 0.299ns, distribution 0.457ns)
  Clock Net Delay (Destination): 0.860ns (routing 0.333ns, distribution 0.527ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.830    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.847 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.756     2.603    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X96Y325        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[56]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y325        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.039     2.642 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[56]/Q
                         net (fo=2, routed)           0.042     2.684    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp[56]
    SLICE_X96Y325        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[56]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.593    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.612 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.860     2.472    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X96Y325        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[56]/C
                         clock pessimism              0.137     2.609    
    SLICE_X96Y325        FDRE (Hold_HFF_SLICEM_C_D)
                                                      0.046     2.655    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[56]
  -------------------------------------------------------------------
                         required time                         -2.655    
                         arrival time                           2.684    
  -------------------------------------------------------------------
                         slack                                  0.029    

Slack (MET) :             0.031ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[79]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[79]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.083ns  (logic 0.039ns (46.935%)  route 0.044ns (53.065%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.473ns
    Source Clock Delay      (SCD):    2.604ns
    Clock Pessimism Removal (CPR):    -0.136ns
  Clock Net Delay (Source):      0.757ns (routing 0.299ns, distribution 0.458ns)
  Clock Net Delay (Destination): 0.862ns (routing 0.333ns, distribution 0.529ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.830    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.847 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.757     2.604    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X94Y330        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[79]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y330        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.039     2.643 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[79]/Q
                         net (fo=2, routed)           0.044     2.687    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp[79]
    SLICE_X94Y330        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[79]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.593    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.612 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.862     2.473    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X94Y330        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[79]/C
                         clock pessimism              0.136     2.610    
    SLICE_X94Y330        FDRE (Hold_HFF_SLICEM_C_D)
                                                      0.046     2.656    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[79]
  -------------------------------------------------------------------
                         required time                         -2.656    
                         arrival time                           2.687    
  -------------------------------------------------------------------
                         slack                                  0.031    

Slack (MET) :             0.031ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[13]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.083ns  (logic 0.039ns (46.935%)  route 0.044ns (53.065%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.470ns
    Source Clock Delay      (SCD):    2.600ns
    Clock Pessimism Removal (CPR):    -0.136ns
  Clock Net Delay (Source):      0.753ns (routing 0.299ns, distribution 0.454ns)
  Clock Net Delay (Destination): 0.858ns (routing 0.333ns, distribution 0.525ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.830    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.847 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.753     2.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X96Y328        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[13]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y328        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.039     2.639 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[13]/Q
                         net (fo=2, routed)           0.044     2.683    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp[13]
    SLICE_X96Y328        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.593    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.612 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.858     2.470    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X96Y328        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[13]/C
                         clock pessimism              0.136     2.606    
    SLICE_X96Y328        FDRE (Hold_HFF_SLICEM_C_D)
                                                      0.046     2.652    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[13]
  -------------------------------------------------------------------
                         required time                         -2.652    
                         arrival time                           2.683    
  -------------------------------------------------------------------
                         slack                                  0.031    

Slack (MET) :             0.036ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_14_15/DP/WADR2
                            (rising edge-triggered cell RAMD32 clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.233ns  (logic 0.058ns (24.840%)  route 0.175ns (75.160%))
  Logic Levels:           0  
  Clock Path Skew:        0.107ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.265ns
    Source Clock Delay      (SCD):    4.458ns
    Clock Pessimism Removal (CPR):    -0.300ns
  Clock Net Delay (Source):      1.313ns (routing 0.490ns, distribution 0.823ns)
  Clock Net Delay (Destination): 1.512ns (routing 0.539ns, distribution 0.973ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207     3.121    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.145 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.313     4.458    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/wr_clk
    SLICE_X112Y347       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X112Y347       FDCE (Prop_HFF_SLICEM_C_Q)
                                                      0.058     4.516 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[2]/Q
                         net (fo=24, routed)          0.175     4.691    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_14_15/A2
    SLICE_X109Y345       RAMD32                                       r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_14_15/DP/WADR2
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.725    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.753 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.512     4.265    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_14_15/WCLK
    SLICE_X109Y345       RAMD32                                       r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_14_15/DP/CLK
                         clock pessimism              0.300     4.565    
    SLICE_X109Y345       RAMD32 (Hold_G6LUT_SLICEM_CLK_WADR2)
                                                      0.090     4.655    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_14_15/DP
  -------------------------------------------------------------------
                         required time                         -4.655    
                         arrival time                           4.691    
  -------------------------------------------------------------------
                         slack                                  0.036    

Slack (MET) :             0.036ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_14_15/SP/WADR2
                            (rising edge-triggered cell RAMD32 clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.233ns  (logic 0.058ns (24.840%)  route 0.175ns (75.160%))
  Logic Levels:           0  
  Clock Path Skew:        0.107ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.265ns
    Source Clock Delay      (SCD):    4.458ns
    Clock Pessimism Removal (CPR):    -0.300ns
  Clock Net Delay (Source):      1.313ns (routing 0.490ns, distribution 0.823ns)
  Clock Net Delay (Destination): 1.512ns (routing 0.539ns, distribution 0.973ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207     3.121    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.145 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.313     4.458    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/wr_clk
    SLICE_X112Y347       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X112Y347       FDCE (Prop_HFF_SLICEM_C_Q)
                                                      0.058     4.516 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[2]/Q
                         net (fo=24, routed)          0.175     4.691    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_14_15/A2
    SLICE_X109Y345       RAMD32                                       r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_14_15/SP/WADR2
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.725    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.753 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.512     4.265    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_14_15/WCLK
    SLICE_X109Y345       RAMD32                                       r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_14_15/SP/CLK
                         clock pessimism              0.300     4.565    
    SLICE_X109Y345       RAMD32 (Hold_H6LUT_SLICEM_CLK_WADR2)
                                                      0.090     4.655    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_14_15/SP
  -------------------------------------------------------------------
                         required time                         -4.655    
                         arrival time                           4.691    
  -------------------------------------------------------------------
                         slack                                  0.036    

Slack (MET) :             0.036ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_14_15__0/DP/WADR2
                            (rising edge-triggered cell RAMD32 clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.233ns  (logic 0.058ns (24.840%)  route 0.175ns (75.160%))
  Logic Levels:           0  
  Clock Path Skew:        0.107ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.265ns
    Source Clock Delay      (SCD):    4.458ns
    Clock Pessimism Removal (CPR):    -0.300ns
  Clock Net Delay (Source):      1.313ns (routing 0.490ns, distribution 0.823ns)
  Clock Net Delay (Destination): 1.512ns (routing 0.539ns, distribution 0.973ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207     3.121    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.145 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.313     4.458    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/wr_clk
    SLICE_X112Y347       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X112Y347       FDCE (Prop_HFF_SLICEM_C_Q)
                                                      0.058     4.516 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[2]/Q
                         net (fo=24, routed)          0.175     4.691    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_14_15__0/A2
    SLICE_X109Y345       RAMD32                                       r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_14_15__0/DP/WADR2
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.725    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.753 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.512     4.265    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_14_15__0/WCLK
    SLICE_X109Y345       RAMD32                                       r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_14_15__0/DP/CLK
                         clock pessimism              0.300     4.565    
    SLICE_X109Y345       RAMD32 (Hold_G5LUT_SLICEM_CLK_WADR2)
                                                      0.090     4.655    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_14_15__0/DP
  -------------------------------------------------------------------
                         required time                         -4.655    
                         arrival time                           4.691    
  -------------------------------------------------------------------
                         slack                                  0.036    

Slack (MET) :             0.036ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_14_15__0/SP/WADR2
                            (rising edge-triggered cell RAMD32 clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.233ns  (logic 0.058ns (24.840%)  route 0.175ns (75.160%))
  Logic Levels:           0  
  Clock Path Skew:        0.107ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.265ns
    Source Clock Delay      (SCD):    4.458ns
    Clock Pessimism Removal (CPR):    -0.300ns
  Clock Net Delay (Source):      1.313ns (routing 0.490ns, distribution 0.823ns)
  Clock Net Delay (Destination): 1.512ns (routing 0.539ns, distribution 0.973ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207     3.121    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.145 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.313     4.458    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/wr_clk
    SLICE_X112Y347       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X112Y347       FDCE (Prop_HFF_SLICEM_C_Q)
                                                      0.058     4.516 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[2]/Q
                         net (fo=24, routed)          0.175     4.691    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_14_15__0/A2
    SLICE_X109Y345       RAMD32                                       r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_14_15__0/SP/WADR2
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.725    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.753 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.512     4.265    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_14_15__0/WCLK
    SLICE_X109Y345       RAMD32                                       r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_14_15__0/SP/CLK
                         clock pessimism              0.300     4.565    
    SLICE_X109Y345       RAMD32 (Hold_H5LUT_SLICEM_CLK_WADR2)
                                                      0.090     4.655    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_14_15__0/SP
  -------------------------------------------------------------------
                         required time                         -4.655    
                         arrival time                           4.691    
  -------------------------------------------------------------------
                         slack                                  0.036    

Slack (MET) :             0.037ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_MSTR2SL_PORT_IFACE/MA_RD_DIN_O_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB/I
                            (rising edge-triggered cell RAMD32 clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.238ns  (logic 0.060ns (25.210%)  route 0.178ns (74.790%))
  Logic Levels:           0  
  Clock Path Skew:        0.123ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.265ns
    Source Clock Delay      (SCD):    4.442ns
    Clock Pessimism Removal (CPR):    -0.300ns
  Clock Net Delay (Source):      1.297ns (routing 0.490ns, distribution 0.807ns)
  Clock Net Delay (Destination): 1.512ns (routing 0.539ns, distribution 0.973ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207     3.121    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.145 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.297     4.442    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_MSTR2SL_PORT_IFACE/clk
    SLICE_X108Y337       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_MSTR2SL_PORT_IFACE/MA_RD_DIN_O_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X108Y337       FDRE (Prop_FFF2_SLICEL_C_Q)
                                                      0.060     4.502 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_MSTR2SL_PORT_IFACE/MA_RD_DIN_O_reg[2]/Q
                         net (fo=1, routed)           0.178     4.680    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/DIB0
    SLICE_X109Y344       RAMD32                                       r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB/I
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.725    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.753 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.512     4.265    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/WCLK
    SLICE_X109Y344       RAMD32                                       r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB/CLK
                         clock pessimism              0.300     4.565    
    SLICE_X109Y344       RAMD32 (Hold_B5LUT_SLICEM_CLK_I)
                                                      0.078     4.643    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB
  -------------------------------------------------------------------
                         required time                         -4.643    
                         arrival time                           4.680    
  -------------------------------------------------------------------
                         slack                                  0.037    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         mmcm_clkout5
Waveform(ns):       { 0.000 6.001 }
Period(ns):         12.002
Sources:            { d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5 }

Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location        Pin
Min Period        n/a     BUFGCE/I            n/a            1.290         12.002      10.712     BUFGCE_X0Y102   d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/I
Min Period        n/a     MMCME4_ADV/CLKOUT5  n/a            1.071         12.002      10.931     MMCM_X0Y4       d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
Min Period        n/a     RAMD32/CLK          n/a            1.064         12.002      10.938     SLICE_X109Y344  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA/CLK
Min Period        n/a     RAMD32/CLK          n/a            1.064         12.002      10.938     SLICE_X109Y344  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA_D1/CLK
Min Period        n/a     RAMD32/CLK          n/a            1.064         12.002      10.938     SLICE_X109Y344  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB/CLK
Min Period        n/a     RAMD32/CLK          n/a            1.064         12.002      10.938     SLICE_X109Y344  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB_D1/CLK
Min Period        n/a     RAMD32/CLK          n/a            1.064         12.002      10.938     SLICE_X109Y344  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC/CLK
Min Period        n/a     RAMD32/CLK          n/a            1.064         12.002      10.938     SLICE_X109Y344  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC_D1/CLK
Min Period        n/a     RAMD32/CLK          n/a            1.064         12.002      10.938     SLICE_X109Y344  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMD/CLK
Min Period        n/a     RAMD32/CLK          n/a            1.064         12.002      10.938     SLICE_X109Y344  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMD_D1/CLK
Low Pulse Width   Slow    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X109Y344  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA/CLK
Low Pulse Width   Fast    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X109Y344  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA/CLK
Low Pulse Width   Slow    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X109Y344  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA_D1/CLK
Low Pulse Width   Fast    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X109Y344  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA_D1/CLK
Low Pulse Width   Slow    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X109Y344  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB/CLK
Low Pulse Width   Fast    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X109Y344  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB/CLK
Low Pulse Width   Slow    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X109Y344  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB_D1/CLK
Low Pulse Width   Fast    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X109Y344  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB_D1/CLK
Low Pulse Width   Slow    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X109Y344  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC/CLK
Low Pulse Width   Fast    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X109Y344  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC/CLK
High Pulse Width  Slow    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X109Y344  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA/CLK
High Pulse Width  Fast    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X109Y344  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA/CLK
High Pulse Width  Slow    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X109Y344  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA_D1/CLK
High Pulse Width  Fast    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X109Y344  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA_D1/CLK
High Pulse Width  Slow    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X109Y344  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB/CLK
High Pulse Width  Fast    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X109Y344  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB/CLK
High Pulse Width  Slow    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X109Y344  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB_D1/CLK
High Pulse Width  Fast    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X109Y344  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB_D1/CLK
High Pulse Width  Slow    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X109Y344  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC/CLK
High Pulse Width  Fast    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X109Y344  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC/CLK



---------------------------------------------------------------------------------------------------
From Clock:  mmcm_clkout6
  To Clock:  mmcm_clkout6

Setup :            0  Failing Endpoints,  Worst Slack        0.924ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.024ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        0.975ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.924ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_addr_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_ADDR[1]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.001ns  (mmcm_clkout6 rise@6.001ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        5.025ns  (logic 0.079ns (1.572%)  route 4.946ns (98.428%))
  Logic Levels:           0  
  Clock Path Skew:        -0.139ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.998ns = ( 10.999 - 6.001 ) 
    Source Clock Delay      (SCD):    4.824ns
    Clock Pessimism Removal (CPR):    -0.313ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.045ns (routing 0.799ns, distribution 1.246ns)
  Clock Net Delay (Destination): 1.833ns (routing 0.726ns, distribution 1.107ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     2.751    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.779 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        2.045     4.824    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X85Y296        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_addr_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y296        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     4.903 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_addr_reg[1]/Q
                         net (fo=22, routed)          4.946     9.849    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control_11[1]
    BITSLICE_CONTROL_X0Y24
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_ADDR[1]
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      6.001     6.001 r  
    J19                                               0.000     6.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     6.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     6.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     6.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     6.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     6.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     8.285    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     8.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.227     9.142    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     9.166 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.833    10.999    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/riu_clk
    BITSLICE_CONTROL_X0Y24
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
                         clock pessimism             -0.313    10.686    
                         clock uncertainty           -0.068    10.618    
    BITSLICE_CONTROL_X0Y24
                         BITSLICE_CONTROL (Setup_CONTROL_BITSLICE_CONTROL_RIU_CLK_RIU_ADDR[1])
                                                      0.155    10.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                         10.773    
                         arrival time                          -9.849    
  -------------------------------------------------------------------
                         slack                                  0.924    

Slack (MET) :             1.037ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_addr_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_ADDR[1]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.001ns  (mmcm_clkout6 rise@6.001ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        5.025ns  (logic 0.079ns (1.572%)  route 4.946ns (98.428%))
  Logic Levels:           0  
  Clock Path Skew:        -0.139ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.998ns = ( 10.999 - 6.001 ) 
    Source Clock Delay      (SCD):    4.824ns
    Clock Pessimism Removal (CPR):    -0.313ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.045ns (routing 0.799ns, distribution 1.246ns)
  Clock Net Delay (Destination): 1.833ns (routing 0.726ns, distribution 1.107ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     2.751    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.779 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        2.045     4.824    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X85Y296        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_addr_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y296        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     4.903 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_addr_reg[1]/Q
                         net (fo=22, routed)          4.946     9.849    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control_13[1]
    BITSLICE_CONTROL_X0Y25
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_ADDR[1]
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      6.001     6.001 r  
    J19                                               0.000     6.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     6.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     6.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     6.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     6.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     6.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     8.285    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     8.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.227     9.142    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     9.166 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.833    10.999    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/riu_clk
    BITSLICE_CONTROL_X0Y25
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
                         clock pessimism             -0.313    10.686    
                         clock uncertainty           -0.068    10.618    
    BITSLICE_CONTROL_X0Y25
                         BITSLICE_CONTROL (Setup_CONTROL_BITSLICE_CONTROL_RIU_CLK_RIU_ADDR[1])
                                                      0.268    10.886    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                         10.886    
                         arrival time                          -9.849    
  -------------------------------------------------------------------
                         slack                                  1.037    

Slack (MET) :             1.144ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[11]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[11]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.001ns  (mmcm_clkout6 rise@6.001ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        4.808ns  (logic 0.079ns (1.643%)  route 4.729ns (98.357%))
  Logic Levels:           0  
  Clock Path Skew:        -0.170ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.990ns = ( 10.991 - 6.001 ) 
    Source Clock Delay      (SCD):    4.847ns
    Clock Pessimism Removal (CPR):    -0.313ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.068ns (routing 0.799ns, distribution 1.269ns)
  Clock Net Delay (Destination): 1.825ns (routing 0.726ns, distribution 1.099ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     2.751    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.779 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        2.068     4.847    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X87Y334        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[11]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X87Y334        FDRE (Prop_GFF2_SLICEM_C_Q)
                                                      0.079     4.926 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[11]/Q
                         net (fo=22, routed)          4.729     9.655    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control_2[11]
    BITSLICE_CONTROL_X0Y26
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[11]
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      6.001     6.001 r  
    J19                                               0.000     6.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     6.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     6.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     6.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     6.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     6.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     8.285    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     8.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.227     9.142    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     9.166 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.825    10.991    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/riu_clk
    BITSLICE_CONTROL_X0Y26
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
                         clock pessimism             -0.313    10.678    
                         clock uncertainty           -0.068    10.610    
    BITSLICE_CONTROL_X0Y26
                         BITSLICE_CONTROL (Setup_CONTROL_BITSLICE_CONTROL_RIU_CLK_RIU_WR_DATA[11])
                                                      0.189    10.799    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                         10.799    
                         arrival time                          -9.655    
  -------------------------------------------------------------------
                         slack                                  1.144    

Slack (MET) :             1.167ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[11]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[11]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.001ns  (mmcm_clkout6 rise@6.001ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        4.809ns  (logic 0.079ns (1.643%)  route 4.730ns (98.357%))
  Logic Levels:           0  
  Clock Path Skew:        -0.178ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.982ns = ( 10.983 - 6.001 ) 
    Source Clock Delay      (SCD):    4.847ns
    Clock Pessimism Removal (CPR):    -0.313ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.068ns (routing 0.799ns, distribution 1.269ns)
  Clock Net Delay (Destination): 1.817ns (routing 0.726ns, distribution 1.091ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     2.751    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.779 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        2.068     4.847    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X87Y334        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[11]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X87Y334        FDRE (Prop_GFF2_SLICEM_C_Q)
                                                      0.079     4.926 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[11]/Q
                         net (fo=22, routed)          4.730     9.656    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control_4[11]
    BITSLICE_CONTROL_X0Y27
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[11]
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      6.001     6.001 r  
    J19                                               0.000     6.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     6.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     6.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     6.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     6.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     6.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     8.285    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     8.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.227     9.142    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     9.166 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.817    10.983    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/riu_clk
    BITSLICE_CONTROL_X0Y27
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
                         clock pessimism             -0.313    10.670    
                         clock uncertainty           -0.068    10.602    
    BITSLICE_CONTROL_X0Y27
                         BITSLICE_CONTROL (Setup_CONTROL_BITSLICE_CONTROL_RIU_CLK_RIU_WR_DATA[11])
                                                      0.221    10.823    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                         10.823    
                         arrival time                          -9.656    
  -------------------------------------------------------------------
                         slack                                  1.167    

Slack (MET) :             1.226ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Op2_reg[31]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/ADDRBWRADDR[6]
                            (rising edge-triggered cell RAMB36E2 clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.001ns  (mmcm_clkout6 rise@6.001ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        4.318ns  (logic 0.569ns (13.177%)  route 3.749ns (86.824%))
  Logic Levels:           4  (CARRY8=2 LUT3=1 LUT6=1)
  Clock Path Skew:        -0.101ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.015ns = ( 11.016 - 6.001 ) 
    Source Clock Delay      (SCD):    4.811ns
    Clock Pessimism Removal (CPR):    -0.305ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.032ns (routing 0.799ns, distribution 1.233ns)
  Clock Net Delay (Destination): 1.850ns (routing 0.726ns, distribution 1.124ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     2.751    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.779 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        2.032     4.811    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/Clk
    SLICE_X90Y325        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Op2_reg[31]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X90Y325        FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.078     4.889 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Op2_reg[31]/Q
                         net (fo=50, routed)          0.895     5.784    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[31].ALU_Bit_I1/Not_Last_Bit.I_ALU_LUT_V5/Using_FPGA.Native/I0
    SLICE_X87Y313        LUT6 (Prop_B6LUT_SLICEM_I0_O)
                                                      0.149     5.933 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[31].ALU_Bit_I1/Not_Last_Bit.I_ALU_LUT_V5/Using_FPGA.Native/LUT6/O
                         net (fo=1, routed)           0.016     5.949    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Use_Carry_Decoding.CarryIn_MUXCY/lopt_3
    SLICE_X87Y313        CARRY8 (Prop_CARRY8_SLICEM_S[1]_CO[7])
                                                      0.190     6.139 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Use_Carry_Decoding.CarryIn_MUXCY/Using_FPGA.Native_CARRY4_CARRY8/CO[7]
                         net (fo=1, routed)           0.026     6.165    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[24].ALU_Bit_I1/Not_Last_Bit.MUXCY_XOR_I/LO
    SLICE_X87Y314        CARRY8 (Prop_CARRY8_SLICEM_CI_O[0])
                                                      0.063     6.228 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[24].ALU_Bit_I1/Not_Last_Bit.MUXCY_XOR_I/Using_FPGA.Native_I1_CARRY4_CARRY8/O[0]
                         net (fo=27, routed)          0.882     7.110    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/jump_logic_I1/MUXCY_JUMP_CARRY6/Data_Addr[5]
    SLICE_X91Y332        LUT3 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.089     7.199 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/jump_logic_I1/MUXCY_JUMP_CARRY6/Instr_Addr[24]_INST_0/O
                         net (fo=25, routed)          1.930     9.129    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/addrb[5]
    RAMB36_X8Y56         RAMB36E2                                     r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/ADDRBWRADDR[6]
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      6.001     6.001 r  
    J19                                               0.000     6.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     6.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     6.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     6.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     6.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     6.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     8.285    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     8.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.227     9.142    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     9.166 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.850    11.016    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/clkb
    RAMB36_X8Y56         RAMB36E2                                     r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/CLKBWRCLK
                         clock pessimism             -0.305    10.711    
                         clock uncertainty           -0.068    10.642    
    RAMB36_X8Y56         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_ADDRBWRADDR[6])
                                                     -0.287    10.355    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram
  -------------------------------------------------------------------
                         required time                         10.355    
                         arrival time                          -9.129    
  -------------------------------------------------------------------
                         slack                                  1.226    

Slack (MET) :             1.335ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Op2_reg[31]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[10].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/ADDRBWRADDR[6]
                            (rising edge-triggered cell RAMB36E2 clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.001ns  (mmcm_clkout6 rise@6.001ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        4.189ns  (logic 0.569ns (13.582%)  route 3.620ns (86.418%))
  Logic Levels:           4  (CARRY8=2 LUT3=1 LUT6=1)
  Clock Path Skew:        -0.121ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.995ns = ( 10.996 - 6.001 ) 
    Source Clock Delay      (SCD):    4.811ns
    Clock Pessimism Removal (CPR):    -0.305ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.032ns (routing 0.799ns, distribution 1.233ns)
  Clock Net Delay (Destination): 1.830ns (routing 0.726ns, distribution 1.104ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     2.751    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.779 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        2.032     4.811    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/Clk
    SLICE_X90Y325        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Op2_reg[31]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X90Y325        FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.078     4.889 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Op2_reg[31]/Q
                         net (fo=50, routed)          0.895     5.784    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[31].ALU_Bit_I1/Not_Last_Bit.I_ALU_LUT_V5/Using_FPGA.Native/I0
    SLICE_X87Y313        LUT6 (Prop_B6LUT_SLICEM_I0_O)
                                                      0.149     5.933 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[31].ALU_Bit_I1/Not_Last_Bit.I_ALU_LUT_V5/Using_FPGA.Native/LUT6/O
                         net (fo=1, routed)           0.016     5.949    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Use_Carry_Decoding.CarryIn_MUXCY/lopt_3
    SLICE_X87Y313        CARRY8 (Prop_CARRY8_SLICEM_S[1]_CO[7])
                                                      0.190     6.139 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Use_Carry_Decoding.CarryIn_MUXCY/Using_FPGA.Native_CARRY4_CARRY8/CO[7]
                         net (fo=1, routed)           0.026     6.165    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[24].ALU_Bit_I1/Not_Last_Bit.MUXCY_XOR_I/LO
    SLICE_X87Y314        CARRY8 (Prop_CARRY8_SLICEM_CI_O[0])
                                                      0.063     6.228 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[24].ALU_Bit_I1/Not_Last_Bit.MUXCY_XOR_I/Using_FPGA.Native_I1_CARRY4_CARRY8/O[0]
                         net (fo=27, routed)          0.882     7.110    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/jump_logic_I1/MUXCY_JUMP_CARRY6/Data_Addr[5]
    SLICE_X91Y332        LUT3 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.089     7.199 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/jump_logic_I1/MUXCY_JUMP_CARRY6/Instr_Addr[24]_INST_0/O
                         net (fo=25, routed)          1.801     9.000    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[10].ram.r/prim_noinit.ram/addrb[5]
    RAMB36_X9Y50         RAMB36E2                                     r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[10].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/ADDRBWRADDR[6]
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      6.001     6.001 r  
    J19                                               0.000     6.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     6.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     6.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     6.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     6.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     6.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     8.285    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     8.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.227     9.142    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     9.166 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.830    10.996    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[10].ram.r/prim_noinit.ram/clkb
    RAMB36_X9Y50         RAMB36E2                                     r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[10].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/CLKBWRCLK
                         clock pessimism             -0.305    10.691    
                         clock uncertainty           -0.068    10.622    
    RAMB36_X9Y50         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_ADDRBWRADDR[6])
                                                     -0.287    10.335    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[10].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram
  -------------------------------------------------------------------
                         required time                         10.335    
                         arrival time                          -9.000    
  -------------------------------------------------------------------
                         slack                                  1.335    

Slack (MET) :             1.441ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Op2_reg[31]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[10].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/ADDRBWRADDR[4]
                            (rising edge-triggered cell RAMB36E2 clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.001ns  (mmcm_clkout6 rise@6.001ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        4.028ns  (logic 0.568ns (14.102%)  route 3.460ns (85.898%))
  Logic Levels:           3  (CARRY8=1 LUT3=1 LUT6=1)
  Clock Path Skew:        -0.121ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.995ns = ( 10.996 - 6.001 ) 
    Source Clock Delay      (SCD):    4.811ns
    Clock Pessimism Removal (CPR):    -0.305ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.032ns (routing 0.799ns, distribution 1.233ns)
  Clock Net Delay (Destination): 1.830ns (routing 0.726ns, distribution 1.104ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     2.751    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.779 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        2.032     4.811    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/Clk
    SLICE_X90Y325        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Op2_reg[31]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X90Y325        FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.078     4.889 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Op2_reg[31]/Q
                         net (fo=50, routed)          0.895     5.784    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[31].ALU_Bit_I1/Not_Last_Bit.I_ALU_LUT_V5/Using_FPGA.Native/I0
    SLICE_X87Y313        LUT6 (Prop_B6LUT_SLICEM_I0_O)
                                                      0.149     5.933 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[31].ALU_Bit_I1/Not_Last_Bit.I_ALU_LUT_V5/Using_FPGA.Native/LUT6/O
                         net (fo=1, routed)           0.016     5.949    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Use_Carry_Decoding.CarryIn_MUXCY/lopt_3
    SLICE_X87Y313        CARRY8 (Prop_CARRY8_SLICEM_S[1]_O[6])
                                                      0.231     6.180 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Use_Carry_Decoding.CarryIn_MUXCY/Using_FPGA.Native_CARRY4_CARRY8/O[6]
                         net (fo=27, routed)          0.677     6.857    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/jump_logic_I1/MUXCY_JUMP_CARRY6/Data_Addr[3]
    SLICE_X88Y329        LUT3 (Prop_C5LUT_SLICEL_I0_O)
                                                      0.110     6.967 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/jump_logic_I1/MUXCY_JUMP_CARRY6/Instr_Addr[26]_INST_0/O
                         net (fo=25, routed)          1.871     8.839    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[10].ram.r/prim_noinit.ram/addrb[3]
    RAMB36_X9Y50         RAMB36E2                                     r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[10].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/ADDRBWRADDR[4]
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      6.001     6.001 r  
    J19                                               0.000     6.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     6.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     6.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     6.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     6.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     6.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     8.285    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     8.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.227     9.142    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     9.166 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.830    10.996    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[10].ram.r/prim_noinit.ram/clkb
    RAMB36_X9Y50         RAMB36E2                                     r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[10].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/CLKBWRCLK
                         clock pessimism             -0.305    10.691    
                         clock uncertainty           -0.068    10.622    
    RAMB36_X9Y50         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_ADDRBWRADDR[4])
                                                     -0.343    10.279    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[10].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram
  -------------------------------------------------------------------
                         required time                         10.279    
                         arrival time                          -8.839    
  -------------------------------------------------------------------
                         slack                                  1.441    

Slack (MET) :             1.463ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Op2_reg[31]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[10].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/ADDRBWRADDR[11]
                            (rising edge-triggered cell RAMB36E2 clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.001ns  (mmcm_clkout6 rise@6.001ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        4.046ns  (logic 0.638ns (15.770%)  route 3.408ns (84.230%))
  Logic Levels:           4  (CARRY8=2 LUT3=1 LUT6=1)
  Clock Path Skew:        -0.121ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.995ns = ( 10.996 - 6.001 ) 
    Source Clock Delay      (SCD):    4.811ns
    Clock Pessimism Removal (CPR):    -0.305ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.032ns (routing 0.799ns, distribution 1.233ns)
  Clock Net Delay (Destination): 1.830ns (routing 0.726ns, distribution 1.104ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     2.751    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.779 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        2.032     4.811    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/Clk
    SLICE_X90Y325        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Op2_reg[31]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X90Y325        FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.078     4.889 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Op2_reg[31]/Q
                         net (fo=50, routed)          0.895     5.784    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[31].ALU_Bit_I1/Not_Last_Bit.I_ALU_LUT_V5/Using_FPGA.Native/I0
    SLICE_X87Y313        LUT6 (Prop_B6LUT_SLICEM_I0_O)
                                                      0.149     5.933 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[31].ALU_Bit_I1/Not_Last_Bit.I_ALU_LUT_V5/Using_FPGA.Native/LUT6/O
                         net (fo=1, routed)           0.016     5.949    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Use_Carry_Decoding.CarryIn_MUXCY/lopt_3
    SLICE_X87Y313        CARRY8 (Prop_CARRY8_SLICEM_S[1]_CO[7])
                                                      0.190     6.139 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Use_Carry_Decoding.CarryIn_MUXCY/Using_FPGA.Native_CARRY4_CARRY8/CO[7]
                         net (fo=1, routed)           0.026     6.165    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[24].ALU_Bit_I1/Not_Last_Bit.MUXCY_XOR_I/LO
    SLICE_X87Y314        CARRY8 (Prop_CARRY8_SLICEM_CI_O[5])
                                                      0.123     6.288 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[24].ALU_Bit_I1/Not_Last_Bit.MUXCY_XOR_I/Using_FPGA.Native_I1_CARRY4_CARRY8/O[5]
                         net (fo=27, routed)          0.690     6.978    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/jump_logic_I1/MUXCY_JUMP_CARRY6/Data_Addr[10]
    SLICE_X86Y330        LUT3 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.098     7.076 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/jump_logic_I1/MUXCY_JUMP_CARRY6/Instr_Addr[19]_INST_0/O
                         net (fo=25, routed)          1.780     8.856    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[10].ram.r/prim_noinit.ram/addrb[10]
    RAMB36_X9Y50         RAMB36E2                                     r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[10].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/ADDRBWRADDR[11]
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      6.001     6.001 r  
    J19                                               0.000     6.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     6.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     6.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     6.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     6.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     6.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     8.285    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     8.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.227     9.142    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     9.166 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.830    10.996    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[10].ram.r/prim_noinit.ram/clkb
    RAMB36_X9Y50         RAMB36E2                                     r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[10].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/CLKBWRCLK
                         clock pessimism             -0.305    10.691    
                         clock uncertainty           -0.068    10.622    
    RAMB36_X9Y50         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_ADDRBWRADDR[11])
                                                     -0.303    10.319    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[10].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram
  -------------------------------------------------------------------
                         required time                         10.319    
                         arrival time                          -8.856    
  -------------------------------------------------------------------
                         slack                                  1.463    

Slack (MET) :             1.479ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Branch_CMP_Op1_reg[17]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[10].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/ADDRBWRADDR[7]
                            (rising edge-triggered cell RAMB36E2 clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.001ns  (mmcm_clkout6 rise@6.001ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        4.016ns  (logic 0.519ns (12.922%)  route 3.497ns (87.078%))
  Logic Levels:           4  (CARRY8=2 LUT3=1 LUT6=1)
  Clock Path Skew:        -0.152ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.995ns = ( 10.996 - 6.001 ) 
    Source Clock Delay      (SCD):    4.842ns
    Clock Pessimism Removal (CPR):    -0.305ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.063ns (routing 0.799ns, distribution 1.264ns)
  Clock Net Delay (Destination): 1.830ns (routing 0.726ns, distribution 1.104ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     2.751    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.779 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        2.063     4.842    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/Clk
    SLICE_X88Y334        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Branch_CMP_Op1_reg[17]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y334        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     4.923 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Branch_CMP_Op1_reg[17]/Q
                         net (fo=1, routed)           0.539     5.462    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Zero_Detect_I/Using_FPGA.Native_3[12]
    SLICE_X88Y340        LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.089     5.551 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Zero_Detect_I/S0_inferred__2/i_/O
                         net (fo=1, routed)           0.009     5.560    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Zero_Detect_I/Part_Of_Zero_Carry_Start/lopt_7
    SLICE_X88Y340        CARRY8 (Prop_CARRY8_SLICEL_S[3]_CO[7])
                                                      0.154     5.714 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Zero_Detect_I/Part_Of_Zero_Carry_Start/Using_FPGA.Native_CARRY4_CARRY8/CO[7]
                         net (fo=1, routed)           0.026     5.740    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/jump_logic_I1/MUXCY_JUMP_CARRY2/jump_carry1
    SLICE_X88Y341        CARRY8 (Prop_CARRY8_SLICEL_CI_CO[4])
                                                      0.092     5.832 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/jump_logic_I1/MUXCY_JUMP_CARRY2/Using_FPGA.Native_CARRY4_CARRY8/CO[4]
                         net (fo=49, routed)          0.816     6.648    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/jump_logic_I1/MUXCY_JUMP_CARRY6/in0
    SLICE_X86Y330        LUT3 (Prop_B5LUT_SLICEM_I1_O)
                                                      0.103     6.751 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/jump_logic_I1/MUXCY_JUMP_CARRY6/Instr_Addr[23]_INST_0/O
                         net (fo=25, routed)          2.107     8.858    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[10].ram.r/prim_noinit.ram/addrb[6]
    RAMB36_X9Y50         RAMB36E2                                     r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[10].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/ADDRBWRADDR[7]
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      6.001     6.001 r  
    J19                                               0.000     6.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     6.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     6.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     6.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     6.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     6.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     8.285    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     8.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.227     9.142    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     9.166 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.830    10.996    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[10].ram.r/prim_noinit.ram/clkb
    RAMB36_X9Y50         RAMB36E2                                     r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[10].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/CLKBWRCLK
                         clock pessimism             -0.305    10.691    
                         clock uncertainty           -0.068    10.622    
    RAMB36_X9Y50         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_ADDRBWRADDR[7])
                                                     -0.285    10.337    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[10].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram
  -------------------------------------------------------------------
                         required time                         10.337    
                         arrival time                          -8.858    
  -------------------------------------------------------------------
                         slack                                  1.479    

Slack (MET) :             1.485ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Op2_reg[31]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[11].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/ADDRBWRADDR[9]
                            (rising edge-triggered cell RAMB36E2 clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.001ns  (mmcm_clkout6 rise@6.001ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        4.045ns  (logic 0.578ns (14.288%)  route 3.467ns (85.712%))
  Logic Levels:           4  (CARRY8=2 LUT3=1 LUT6=1)
  Clock Path Skew:        -0.097ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.019ns = ( 11.020 - 6.001 ) 
    Source Clock Delay      (SCD):    4.811ns
    Clock Pessimism Removal (CPR):    -0.305ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.032ns (routing 0.799ns, distribution 1.233ns)
  Clock Net Delay (Destination): 1.854ns (routing 0.726ns, distribution 1.128ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     2.751    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.779 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        2.032     4.811    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/Clk
    SLICE_X90Y325        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Op2_reg[31]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X90Y325        FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.078     4.889 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Op2_reg[31]/Q
                         net (fo=50, routed)          0.895     5.784    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[31].ALU_Bit_I1/Not_Last_Bit.I_ALU_LUT_V5/Using_FPGA.Native/I0
    SLICE_X87Y313        LUT6 (Prop_B6LUT_SLICEM_I0_O)
                                                      0.149     5.933 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[31].ALU_Bit_I1/Not_Last_Bit.I_ALU_LUT_V5/Using_FPGA.Native/LUT6/O
                         net (fo=1, routed)           0.016     5.949    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Use_Carry_Decoding.CarryIn_MUXCY/lopt_3
    SLICE_X87Y313        CARRY8 (Prop_CARRY8_SLICEM_S[1]_CO[7])
                                                      0.190     6.139 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Use_Carry_Decoding.CarryIn_MUXCY/Using_FPGA.Native_CARRY4_CARRY8/CO[7]
                         net (fo=1, routed)           0.026     6.165    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[24].ALU_Bit_I1/Not_Last_Bit.MUXCY_XOR_I/LO
    SLICE_X87Y314        CARRY8 (Prop_CARRY8_SLICEM_CI_O[3])
                                                      0.089     6.254 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[24].ALU_Bit_I1/Not_Last_Bit.MUXCY_XOR_I/Using_FPGA.Native_I1_CARRY4_CARRY8/O[3]
                         net (fo=27, routed)          0.936     7.191    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/jump_logic_I1/MUXCY_JUMP_CARRY6/Data_Addr[8]
    SLICE_X90Y328        LUT3 (Prop_B5LUT_SLICEM_I0_O)
                                                      0.072     7.263 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/jump_logic_I1/MUXCY_JUMP_CARRY6/Instr_Addr[21]_INST_0/O
                         net (fo=25, routed)          1.594     8.856    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[11].ram.r/prim_noinit.ram/addrb[8]
    RAMB36_X8Y57         RAMB36E2                                     r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[11].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/ADDRBWRADDR[9]
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      6.001     6.001 r  
    J19                                               0.000     6.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     6.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     6.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     6.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     6.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     6.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     8.285    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     8.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.227     9.142    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     9.166 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.854    11.020    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[11].ram.r/prim_noinit.ram/clkb
    RAMB36_X8Y57         RAMB36E2                                     r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[11].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/CLKBWRCLK
                         clock pessimism             -0.305    10.715    
                         clock uncertainty           -0.068    10.646    
    RAMB36_X8Y57         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_ADDRBWRADDR[9])
                                                     -0.305    10.341    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[11].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram
  -------------------------------------------------------------------
                         required time                         10.341    
                         arrival time                          -8.856    
  -------------------------------------------------------------------
                         slack                                  1.485    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.024ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/D_reg[30]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/R_reg[30]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout6 rise@0.000ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        0.187ns  (logic 0.107ns (57.219%)  route 0.080ns (42.781%))
  Logic Levels:           2  (CARRY8=1 LUT3=1)
  Clock Path Skew:        0.103ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.860ns
    Source Clock Delay      (SCD):    4.999ns
    Clock Pessimism Removal (CPR):    -0.242ns
  Clock Net Delay (Source):      1.834ns (routing 0.726ns, distribution 1.108ns)
  Clock Net Delay (Destination): 2.081ns (routing 0.799ns, distribution 1.282ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.227     3.141    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.165 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.834     4.999    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/Clk
    SLICE_X86Y321        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/D_reg[30]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X86Y321        FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.058     5.057 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/D_reg[30]/Q
                         net (fo=1, routed)           0.061     5.118    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/D_2[30]
    SLICE_X85Y321        LUT3 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.023     5.141 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/R1_carry_i_7/O
                         net (fo=1, routed)           0.009     5.150    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/R1_carry_i_7_n_0
    SLICE_X85Y321        CARRY8 (Prop_CARRY8_SLICEL_S[1]_O[1])
                                                      0.026     5.176 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/R1_carry/O[1]
                         net (fo=1, routed)           0.010     5.186    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/p_2_in[2]
    SLICE_X85Y321        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/R_reg[30]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     2.751    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.779 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        2.081     4.860    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/Clk
    SLICE_X85Y321        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/R_reg[30]/C
                         clock pessimism              0.242     5.102    
    SLICE_X85Y321        FDRE (Hold_BFF_SLICEL_C_D)
                                                      0.060     5.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/R_reg[30]
  -------------------------------------------------------------------
                         required time                         -5.162    
                         arrival time                           5.186    
  -------------------------------------------------------------------
                         slack                                  0.024    

Slack (MET) :             0.026ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/D_reg[29]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/R_reg[29]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout6 rise@0.000ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        0.189ns  (logic 0.106ns (56.085%)  route 0.083ns (43.915%))
  Logic Levels:           2  (CARRY8=1 LUT3=1)
  Clock Path Skew:        0.103ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.860ns
    Source Clock Delay      (SCD):    4.999ns
    Clock Pessimism Removal (CPR):    -0.242ns
  Clock Net Delay (Source):      1.834ns (routing 0.726ns, distribution 1.108ns)
  Clock Net Delay (Destination): 2.081ns (routing 0.799ns, distribution 1.282ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.227     3.141    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.165 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.834     4.999    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/Clk
    SLICE_X86Y321        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/D_reg[29]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X86Y321        FDRE (Prop_CFF_SLICEM_C_Q)
                                                      0.058     5.057 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/D_reg[29]/Q
                         net (fo=1, routed)           0.063     5.120    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/D_2[29]
    SLICE_X85Y321        LUT3 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.022     5.142 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/R1_carry_i_6/O
                         net (fo=1, routed)           0.010     5.152    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/R1_carry_i_6_n_0
    SLICE_X85Y321        CARRY8 (Prop_CARRY8_SLICEL_S[2]_O[2])
                                                      0.026     5.178 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/R1_carry/O[2]
                         net (fo=1, routed)           0.010     5.188    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/p_2_in[3]
    SLICE_X85Y321        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/R_reg[29]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     2.751    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.779 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        2.081     4.860    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/Clk
    SLICE_X85Y321        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/R_reg[29]/C
                         clock pessimism              0.242     5.102    
    SLICE_X85Y321        FDRE (Hold_CFF_SLICEL_C_D)
                                                      0.060     5.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/R_reg[29]
  -------------------------------------------------------------------
                         required time                         -5.162    
                         arrival time                           5.188    
  -------------------------------------------------------------------
                         slack                                  0.026    

Slack (MET) :             0.026ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/D_reg[13]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/R_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout6 rise@0.000ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        0.189ns  (logic 0.106ns (56.085%)  route 0.083ns (43.915%))
  Logic Levels:           2  (CARRY8=1 LUT3=1)
  Clock Path Skew:        0.103ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.858ns
    Source Clock Delay      (SCD):    4.997ns
    Clock Pessimism Removal (CPR):    -0.242ns
  Clock Net Delay (Source):      1.832ns (routing 0.726ns, distribution 1.106ns)
  Clock Net Delay (Destination): 2.079ns (routing 0.799ns, distribution 1.280ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.227     3.141    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.165 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.832     4.997    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/Clk
    SLICE_X86Y323        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/D_reg[13]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X86Y323        FDRE (Prop_CFF_SLICEM_C_Q)
                                                      0.058     5.055 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/D_reg[13]/Q
                         net (fo=1, routed)           0.063     5.118    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/D_2[13]
    SLICE_X85Y323        LUT3 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.022     5.140 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/R1_carry__1_i_6/O
                         net (fo=1, routed)           0.010     5.150    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/R1_carry__1_i_6_n_0
    SLICE_X85Y323        CARRY8 (Prop_CARRY8_SLICEL_S[2]_O[2])
                                                      0.026     5.176 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/R1_carry__1/O[2]
                         net (fo=1, routed)           0.010     5.186    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/p_2_in[19]
    SLICE_X85Y323        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/R_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     2.751    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.779 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        2.079     4.858    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/Clk
    SLICE_X85Y323        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/R_reg[13]/C
                         clock pessimism              0.242     5.100    
    SLICE_X85Y323        FDRE (Hold_CFF_SLICEL_C_D)
                                                      0.060     5.160    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/R_reg[13]
  -------------------------------------------------------------------
                         required time                         -5.160    
                         arrival time                           5.186    
  -------------------------------------------------------------------
                         slack                                  0.026    

Slack (MET) :             0.028ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/second_lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[4].ram.r/SAFETY_CKT_GEN.ENB_NO_REG.ENB_dly_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/second_lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[4].ram.r/SAFETY_CKT_GEN.ENB_NO_REG.ENB_dly_D_reg/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout6 rise@0.000ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        0.080ns  (logic 0.039ns (48.750%)  route 0.041ns (51.250%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.907ns
    Source Clock Delay      (SCD):    2.993ns
    Clock Pessimism Removal (CPR):    -0.092ns
  Clock Net Delay (Source):      1.130ns (routing 0.439ns, distribution 0.691ns)
  Clock Net Delay (Destination): 1.277ns (routing 0.492ns, distribution 0.785ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     1.846    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.863 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.130     2.993    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/second_lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[4].ram.r/clkb
    SLICE_X91Y347        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/second_lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[4].ram.r/SAFETY_CKT_GEN.ENB_NO_REG.ENB_dly_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y347        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     3.032 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/second_lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[4].ram.r/SAFETY_CKT_GEN.ENB_NO_REG.ENB_dly_reg/Q
                         net (fo=1, routed)           0.041     3.073    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/second_lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[4].ram.r/ENB_dly
    SLICE_X91Y347        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/second_lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[4].ram.r/SAFETY_CKT_GEN.ENB_NO_REG.ENB_dly_D_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     1.611    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.630 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.277     2.907    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/second_lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[4].ram.r/clkb
    SLICE_X91Y347        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/second_lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[4].ram.r/SAFETY_CKT_GEN.ENB_NO_REG.ENB_dly_D_reg/C
                         clock pessimism              0.092     2.999    
    SLICE_X91Y347        FDRE (Hold_CFF_SLICEL_C_D)
                                                      0.046     3.045    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/second_lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[4].ram.r/SAFETY_CKT_GEN.ENB_NO_REG.ENB_dly_D_reg
  -------------------------------------------------------------------
                         required time                         -3.045    
                         arrival time                           3.073    
  -------------------------------------------------------------------
                         slack                                  0.028    

Slack (MET) :             0.032ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/ex_gpr_write_addr_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/mem_gpr_write_addr_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout6 rise@0.000ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        0.183ns  (logic 0.059ns (32.256%)  route 0.124ns (67.744%))
  Logic Levels:           0  
  Clock Path Skew:        0.089ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.834ns
    Source Clock Delay      (SCD):    4.987ns
    Clock Pessimism Removal (CPR):    -0.242ns
  Clock Net Delay (Source):      1.822ns (routing 0.726ns, distribution 1.096ns)
  Clock Net Delay (Destination): 2.055ns (routing 0.799ns, distribution 1.256ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.227     3.141    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.165 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.822     4.987    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/Clk
    SLICE_X89Y345        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/ex_gpr_write_addr_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y345        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.059     5.046 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/ex_gpr_write_addr_reg[4]/Q
                         net (fo=8, routed)           0.124     5.170    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/ex_gpr_write_addr_reg_n_0_[4]
    SLICE_X88Y347        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/mem_gpr_write_addr_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     2.751    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.779 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        2.055     4.834    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/Clk
    SLICE_X88Y347        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/mem_gpr_write_addr_reg[4]/C
                         clock pessimism              0.242     5.076    
    SLICE_X88Y347        FDRE (Hold_BFF2_SLICEL_C_D)
                                                      0.062     5.138    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/mem_gpr_write_addr_reg[4]
  -------------------------------------------------------------------
                         required time                         -5.138    
                         arrival time                           5.170    
  -------------------------------------------------------------------
                         slack                                  0.032    

Slack (MET) :             0.037ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/ex_gpr_write_addr_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/mem_gpr_write_addr_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout6 rise@0.000ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        0.179ns  (logic 0.060ns (33.566%)  route 0.119ns (66.434%))
  Logic Levels:           0  
  Clock Path Skew:        0.080ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.834ns
    Source Clock Delay      (SCD):    4.996ns
    Clock Pessimism Removal (CPR):    -0.242ns
  Clock Net Delay (Source):      1.831ns (routing 0.726ns, distribution 1.105ns)
  Clock Net Delay (Destination): 2.055ns (routing 0.799ns, distribution 1.256ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.227     3.141    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.165 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.831     4.996    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/Clk
    SLICE_X88Y347        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/ex_gpr_write_addr_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y347        FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.060     5.056 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/ex_gpr_write_addr_reg[1]/Q
                         net (fo=7, routed)           0.119     5.174    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/I2
    SLICE_X89Y346        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/mem_gpr_write_addr_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     2.751    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.779 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        2.055     4.834    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/Clk
    SLICE_X89Y346        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/mem_gpr_write_addr_reg[1]/C
                         clock pessimism              0.242     5.076    
    SLICE_X89Y346        FDRE (Hold_HFF2_SLICEM_C_D)
                                                      0.062     5.138    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/mem_gpr_write_addr_reg[1]
  -------------------------------------------------------------------
                         required time                         -5.138    
                         arrival time                           5.174    
  -------------------------------------------------------------------
                         slack                                  0.037    

Slack (MET) :             0.038ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/D_reg[14]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/R_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout6 rise@0.000ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        0.201ns  (logic 0.120ns (59.701%)  route 0.081ns (40.298%))
  Logic Levels:           2  (CARRY8=1 LUT3=1)
  Clock Path Skew:        0.103ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.858ns
    Source Clock Delay      (SCD):    4.997ns
    Clock Pessimism Removal (CPR):    -0.242ns
  Clock Net Delay (Source):      1.832ns (routing 0.726ns, distribution 1.106ns)
  Clock Net Delay (Destination): 2.079ns (routing 0.799ns, distribution 1.280ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.227     3.141    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.165 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.832     4.997    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/Clk
    SLICE_X86Y323        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/D_reg[14]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X86Y323        FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.058     5.055 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/D_reg[14]/Q
                         net (fo=1, routed)           0.062     5.117    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/D_2[14]
    SLICE_X85Y323        LUT3 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.036     5.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/R1_carry__1_i_7/O
                         net (fo=1, routed)           0.009     5.162    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/R1_carry__1_i_7_n_0
    SLICE_X85Y323        CARRY8 (Prop_CARRY8_SLICEL_S[1]_O[1])
                                                      0.026     5.188 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/R1_carry__1/O[1]
                         net (fo=1, routed)           0.010     5.198    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/p_2_in[18]
    SLICE_X85Y323        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/R_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     2.751    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.779 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        2.079     4.858    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/Clk
    SLICE_X85Y323        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/R_reg[14]/C
                         clock pessimism              0.242     5.100    
    SLICE_X85Y323        FDRE (Hold_BFF_SLICEL_C_D)
                                                      0.060     5.160    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/R_reg[14]
  -------------------------------------------------------------------
                         required time                         -5.160    
                         arrival time                           5.198    
  -------------------------------------------------------------------
                         slack                                  0.038    

Slack (MET) :             0.039ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/SEQ/Core_reg/C
                            (rising edge-triggered cell FDSE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/SEQ/from_sys_reg/D
                            (rising edge-triggered cell FDSE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout6 rise@0.000ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        0.092ns  (logic 0.059ns (64.352%)  route 0.033ns (35.648%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.920ns
    Source Clock Delay      (SCD):    3.005ns
    Clock Pessimism Removal (CPR):    -0.091ns
  Clock Net Delay (Source):      1.142ns (routing 0.439ns, distribution 0.703ns)
  Clock Net Delay (Destination): 1.290ns (routing 0.492ns, distribution 0.798ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     1.846    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.863 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.142     3.005    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/SEQ/slowest_sync_clk
    SLICE_X85Y310        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/SEQ/Core_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y310        FDSE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     3.044 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/SEQ/Core_reg/Q
                         net (fo=3, routed)           0.027     3.070    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/SEQ/MB_out
    SLICE_X85Y310        LUT2 (Prop_H5LUT_SLICEL_I0_O)
                                                      0.020     3.090 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/SEQ/from_sys_i_1/O
                         net (fo=1, routed)           0.006     3.096    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/SEQ/from_sys_i_1_n_0
    SLICE_X85Y310        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/SEQ/from_sys_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     1.611    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.630 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.290     2.920    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/SEQ/slowest_sync_clk
    SLICE_X85Y310        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/SEQ/from_sys_reg/C
                         clock pessimism              0.091     3.011    
    SLICE_X85Y310        FDSE (Hold_HFF2_SLICEL_C_D)
                                                      0.047     3.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/SEQ/from_sys_reg
  -------------------------------------------------------------------
                         required time                         -3.058    
                         arrival time                           3.096    
  -------------------------------------------------------------------
                         slack                                  0.039    

Slack (MET) :             0.039ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/D_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/R_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout6 rise@0.000ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        0.137ns  (logic 0.071ns (51.825%)  route 0.066ns (48.175%))
  Logic Levels:           2  (CARRY8=1 LUT3=1)
  Clock Path Skew:        0.052ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.913ns
    Source Clock Delay      (SCD):    2.995ns
    Clock Pessimism Removal (CPR):    -0.133ns
  Clock Net Delay (Source):      1.132ns (routing 0.439ns, distribution 0.693ns)
  Clock Net Delay (Destination): 1.283ns (routing 0.492ns, distribution 0.791ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     1.846    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.863 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.132     2.995    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/Clk
    SLICE_X86Y324        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/D_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X86Y324        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.039     3.034 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/D_reg[0]/Q
                         net (fo=1, routed)           0.051     3.085    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/D_2[0]
    SLICE_X85Y324        LUT3 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.015     3.100 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/R1_carry__2_i_1/O
                         net (fo=1, routed)           0.008     3.108    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/R1_carry__2_i_1_n_0
    SLICE_X85Y324        CARRY8 (Prop_CARRY8_SLICEL_S[7]_O[7])
                                                      0.017     3.125 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/R1_carry__2/O[7]
                         net (fo=1, routed)           0.007     3.132    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/p_2_in[32]
    SLICE_X85Y324        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/R_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     1.611    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.630 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.283     2.913    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/Clk
    SLICE_X85Y324        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/R_reg[0]/C
                         clock pessimism              0.133     3.046    
    SLICE_X85Y324        FDRE (Hold_HFF_SLICEL_C_D)
                                                      0.046     3.092    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/R_reg[0]
  -------------------------------------------------------------------
                         required time                         -3.092    
                         arrival time                           3.132    
  -------------------------------------------------------------------
                         slack                                  0.039    

Slack (MET) :             0.041ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/D_reg[22]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/R_reg[22]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout6 rise@0.000ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        0.134ns  (logic 0.070ns (52.239%)  route 0.064ns (47.761%))
  Logic Levels:           2  (CARRY8=1 LUT3=1)
  Clock Path Skew:        0.047ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.911ns
    Source Clock Delay      (SCD):    2.998ns
    Clock Pessimism Removal (CPR):    -0.133ns
  Clock Net Delay (Source):      1.135ns (routing 0.439ns, distribution 0.696ns)
  Clock Net Delay (Destination): 1.281ns (routing 0.492ns, distribution 0.789ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     1.846    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.863 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.135     2.998    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/Clk
    SLICE_X86Y322        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/D_reg[22]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X86Y322        FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.038     3.036 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/D_reg[22]/Q
                         net (fo=1, routed)           0.050     3.086    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/D_2[22]
    SLICE_X85Y322        LUT3 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.015     3.101 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/R1_carry__0_i_7/O
                         net (fo=1, routed)           0.007     3.108    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/R1_carry__0_i_7_n_0
    SLICE_X85Y322        CARRY8 (Prop_CARRY8_SLICEL_S[1]_O[1])
                                                      0.017     3.125 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/R1_carry__0/O[1]
                         net (fo=1, routed)           0.007     3.132    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/p_2_in[10]
    SLICE_X85Y322        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/R_reg[22]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     1.611    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.630 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.281     2.911    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/Clk
    SLICE_X85Y322        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/R_reg[22]/C
                         clock pessimism              0.133     3.044    
    SLICE_X85Y322        FDRE (Hold_BFF_SLICEL_C_D)
                                                      0.046     3.090    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/R_reg[22]
  -------------------------------------------------------------------
                         required time                         -3.090    
                         arrival time                           3.132    
  -------------------------------------------------------------------
                         slack                                  0.041    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         mmcm_clkout6
Waveform(ns):       { 0.000 3.001 }
Period(ns):         6.001
Sources:            { d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6 }

Check Type        Corner  Lib Pin                   Reference Pin             Required(ns)  Actual(ns)  Slack(ns)  Location                Pin
Min Period        n/a     BITSLICE_CONTROL/RIU_CLK  n/a                       3.846         6.001       2.155      BITSLICE_CONTROL_X0Y24  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Min Period        n/a     BITSLICE_CONTROL/RIU_CLK  n/a                       3.846         6.001       2.155      BITSLICE_CONTROL_X0Y25  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Min Period        n/a     BITSLICE_CONTROL/RIU_CLK  n/a                       3.846         6.001       2.155      BITSLICE_CONTROL_X0Y44  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Min Period        n/a     BITSLICE_CONTROL/RIU_CLK  n/a                       3.846         6.001       2.155      BITSLICE_CONTROL_X0Y45  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Min Period        n/a     BITSLICE_CONTROL/RIU_CLK  n/a                       3.846         6.001       2.155      BITSLICE_CONTROL_X0Y46  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Min Period        n/a     BITSLICE_CONTROL/RIU_CLK  n/a                       3.846         6.001       2.155      BITSLICE_CONTROL_X0Y47  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Min Period        n/a     BITSLICE_CONTROL/RIU_CLK  n/a                       3.846         6.001       2.155      BITSLICE_CONTROL_X0Y26  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Min Period        n/a     BITSLICE_CONTROL/RIU_CLK  n/a                       3.846         6.001       2.155      BITSLICE_CONTROL_X0Y27  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Min Period        n/a     BITSLICE_CONTROL/RIU_CLK  n/a                       3.846         6.001       2.155      BITSLICE_CONTROL_X0Y28  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Min Period        n/a     BITSLICE_CONTROL/RIU_CLK  n/a                       3.846         6.001       2.155      BITSLICE_CONTROL_X0Y29  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y24  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y24  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y25  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y25  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y44  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y44  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y45  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y45  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y46  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y46  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y24  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y24  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y25  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y25  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y44  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y44  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y45  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y45  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y46  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y46  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Max Skew          Fast    BITSLICE_CONTROL/RIU_CLK  BITSLICE_CONTROL/PLL_CLK  1.818         0.843       0.975      BITSLICE_CONTROL_X0Y24  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Max Skew          Fast    BITSLICE_CONTROL/RIU_CLK  BITSLICE_CONTROL/PLL_CLK  1.818         0.843       0.975      BITSLICE_CONTROL_X0Y25  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Max Skew          Fast    BITSLICE_CONTROL/RIU_CLK  BITSLICE_CONTROL/PLL_CLK  1.818         0.841       0.977      BITSLICE_CONTROL_X0Y32  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Max Skew          Fast    BITSLICE_CONTROL/RIU_CLK  BITSLICE_CONTROL/PLL_CLK  1.818         0.841       0.977      BITSLICE_CONTROL_X0Y33  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Max Skew          Fast    BITSLICE_CONTROL/RIU_CLK  BITSLICE_CONTROL/PLL_CLK  1.818         0.840       0.978      BITSLICE_CONTROL_X0Y35  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Max Skew          Fast    BITSLICE_CONTROL/RIU_CLK  BITSLICE_CONTROL/PLL_CLK  1.818         0.840       0.978      BITSLICE_CONTROL_X0Y26  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Max Skew          Fast    BITSLICE_CONTROL/RIU_CLK  BITSLICE_CONTROL/PLL_CLK  1.818         0.840       0.978      BITSLICE_CONTROL_X0Y31  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Max Skew          Fast    BITSLICE_CONTROL/RIU_CLK  BITSLICE_CONTROL/PLL_CLK  1.818         0.838       0.980      BITSLICE_CONTROL_X0Y27  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Max Skew          Fast    BITSLICE_CONTROL/RIU_CLK  BITSLICE_CONTROL/PLL_CLK  1.818         0.838       0.980      BITSLICE_CONTROL_X0Y29  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Max Skew          Fast    BITSLICE_CONTROL/RIU_CLK  BITSLICE_CONTROL/PLL_CLK  1.818         0.838       0.980      BITSLICE_CONTROL_X0Y34  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK



---------------------------------------------------------------------------------------------------
From Clock:  mmcm_clkout5
  To Clock:  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK

Setup :            0  Failing Endpoints,  Worst Slack       11.619ns,  Total Violation        0.000ns
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             11.619ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[0]/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (MaxDelay Path 12.002ns)
  Data Path Delay:        0.408ns  (logic 0.076ns (18.627%)  route 0.332ns (81.373%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.002ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X109Y338                                    0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[0]/C
    SLICE_X109Y338       FDCE (Prop_FFF_SLICEM_C_Q)
                                                      0.076     0.076 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[0]/Q
                         net (fo=1, routed)           0.332     0.408    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q[0]
    SLICE_X109Y341       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.002    12.002    
    SLICE_X109Y341       FDCE (Setup_GFF2_SLICEM_C_D)
                                                      0.025    12.027    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         12.027    
                         arrival time                          -0.408    
  -------------------------------------------------------------------
                         slack                                 11.619    

Slack (MET) :             11.632ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[1]/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (MaxDelay Path 12.002ns)
  Data Path Delay:        0.395ns  (logic 0.078ns (19.747%)  route 0.317ns (80.253%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.002ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X112Y344                                    0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[1]/C
    SLICE_X112Y344       FDCE (Prop_HFF2_SLICEM_C_Q)
                                                      0.078     0.078 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[1]/Q
                         net (fo=1, routed)           0.317     0.395    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q[1]
    SLICE_X112Y345       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.002    12.002    
    SLICE_X112Y345       FDCE (Setup_DFF2_SLICEM_C_D)
                                                      0.025    12.027    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[1]
  -------------------------------------------------------------------
                         required time                         12.027    
                         arrival time                          -0.395    
  -------------------------------------------------------------------
                         slack                                 11.632    

Slack (MET) :             11.656ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[3]/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (MaxDelay Path 12.002ns)
  Data Path Delay:        0.371ns  (logic 0.076ns (20.485%)  route 0.295ns (79.515%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.002ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X109Y339                                    0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[3]/C
    SLICE_X109Y339       FDCE (Prop_FFF_SLICEM_C_Q)
                                                      0.076     0.076 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[3]/Q
                         net (fo=1, routed)           0.295     0.371    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q[3]
    SLICE_X109Y339       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.002    12.002    
    SLICE_X109Y339       FDCE (Setup_CFF2_SLICEM_C_D)
                                                      0.025    12.027    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[3]
  -------------------------------------------------------------------
                         required time                         12.027    
                         arrival time                          -0.371    
  -------------------------------------------------------------------
                         slack                                 11.656    

Slack (MET) :             11.665ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[3]/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (MaxDelay Path 12.002ns)
  Data Path Delay:        0.362ns  (logic 0.076ns (20.994%)  route 0.286ns (79.006%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.002ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X112Y344                                    0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[3]/C
    SLICE_X112Y344       FDCE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     0.076 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[3]/Q
                         net (fo=1, routed)           0.286     0.362    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q[3]
    SLICE_X112Y344       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.002    12.002    
    SLICE_X112Y344       FDCE (Setup_CFF2_SLICEM_C_D)
                                                      0.025    12.027    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[3]
  -------------------------------------------------------------------
                         required time                         12.027    
                         arrival time                          -0.362    
  -------------------------------------------------------------------
                         slack                                 11.665    

Slack (MET) :             11.675ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (MaxDelay Path 12.002ns)
  Data Path Delay:        0.352ns  (logic 0.079ns (22.443%)  route 0.273ns (77.557%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.002ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X112Y344                                    0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[0]/C
    SLICE_X112Y344       FDCE (Prop_HFF_SLICEM_C_Q)
                                                      0.079     0.079 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[0]/Q
                         net (fo=1, routed)           0.273     0.352    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q[0]
    SLICE_X112Y345       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.002    12.002    
    SLICE_X112Y345       FDCE (Setup_GFF2_SLICEM_C_D)
                                                      0.025    12.027    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         12.027    
                         arrival time                          -0.352    
  -------------------------------------------------------------------
                         slack                                 11.675    

Slack (MET) :             11.692ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[2]/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (MaxDelay Path 12.002ns)
  Data Path Delay:        0.335ns  (logic 0.078ns (23.284%)  route 0.257ns (76.716%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.002ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X112Y344                                    0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[2]/C
    SLICE_X112Y344       FDCE (Prop_GFF_SLICEM_C_Q)
                                                      0.078     0.078 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[2]/Q
                         net (fo=1, routed)           0.257     0.335    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q[2]
    SLICE_X112Y344       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.002    12.002    
    SLICE_X112Y344       FDCE (Setup_DFF2_SLICEM_C_D)
                                                      0.025    12.027    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[2]
  -------------------------------------------------------------------
                         required time                         12.027    
                         arrival time                          -0.335    
  -------------------------------------------------------------------
                         slack                                 11.692    

Slack (MET) :             11.729ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[1]/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (MaxDelay Path 12.002ns)
  Data Path Delay:        0.298ns  (logic 0.078ns (26.174%)  route 0.220ns (73.826%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.002ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X109Y338                                    0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[1]/C
    SLICE_X109Y338       FDCE (Prop_HFF2_SLICEM_C_Q)
                                                      0.078     0.078 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[1]/Q
                         net (fo=1, routed)           0.220     0.298    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q[1]
    SLICE_X109Y341       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.002    12.002    
    SLICE_X109Y341       FDCE (Setup_CFF2_SLICEM_C_D)
                                                      0.025    12.027    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[1]
  -------------------------------------------------------------------
                         required time                         12.027    
                         arrival time                          -0.298    
  -------------------------------------------------------------------
                         slack                                 11.729    

Slack (MET) :             11.731ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[2]/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (MaxDelay Path 12.002ns)
  Data Path Delay:        0.296ns  (logic 0.076ns (25.676%)  route 0.220ns (74.324%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.002ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X109Y339                                    0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[2]/C
    SLICE_X109Y339       FDCE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     0.076 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[2]/Q
                         net (fo=1, routed)           0.220     0.296    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q[2]
    SLICE_X109Y341       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.002    12.002    
    SLICE_X109Y341       FDCE (Setup_BFF2_SLICEM_C_D)
                                                      0.025    12.027    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[2]
  -------------------------------------------------------------------
                         required time                         12.027    
                         arrival time                          -0.296    
  -------------------------------------------------------------------
                         slack                                 11.731    





---------------------------------------------------------------------------------------------------
From Clock:  mmcm_clkout5
  To Clock:  mmcm_clkout0

Setup :            0  Failing Endpoints,  Worst Slack        2.357ns,  Total Violation        0.000ns
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             2.357ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[11]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[11].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        0.668ns  (logic 0.079ns (11.826%)  route 0.589ns (88.174%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y331                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[11]/C
    SLICE_X92Y331        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[11]/Q
                         net (fo=1, routed)           0.589     0.668    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/out[11]
    SLICE_X92Y323        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[11].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X92Y323        FDRE (Setup_HFF2_SLICEL_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[11].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -0.668    
  -------------------------------------------------------------------
                         slack                                  2.357    

Slack (MET) :             2.392ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[3].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        0.633ns  (logic 0.079ns (12.480%)  route 0.554ns (87.520%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y330                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[3]/C
    SLICE_X95Y330        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[3]/Q
                         net (fo=1, routed)           0.554     0.633    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/out[3]
    SLICE_X92Y332        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[3].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X92Y332        FDRE (Setup_DFF2_SLICEL_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[3].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -0.633    
  -------------------------------------------------------------------
                         slack                                  2.392    

Slack (MET) :             2.435ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[4].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        0.590ns  (logic 0.078ns (13.220%)  route 0.512ns (86.780%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y337                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[4]/C
    SLICE_X96Y337        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.078     0.078 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[4]/Q
                         net (fo=1, routed)           0.512     0.590    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/out[4]
    SLICE_X90Y340        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[4].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X90Y340        FDRE (Setup_DFF2_SLICEM_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[4].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -0.590    
  -------------------------------------------------------------------
                         slack                                  2.435    

Slack (MET) :             2.463ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[5].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        0.562ns  (logic 0.081ns (14.413%)  route 0.481ns (85.587%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y331                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[5]/C
    SLICE_X92Y331        FDRE (Prop_FFF2_SLICEL_C_Q)
                                                      0.081     0.081 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[5]/Q
                         net (fo=1, routed)           0.481     0.562    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/out[5]
    SLICE_X92Y332        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[5].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X92Y332        FDRE (Setup_CFF2_SLICEL_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[5].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -0.562    
  -------------------------------------------------------------------
                         slack                                  2.463    

Slack (MET) :             2.467ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[5].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        0.558ns  (logic 0.081ns (14.516%)  route 0.477ns (85.484%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y348                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[5]/C
    SLICE_X91Y348        FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.081     0.081 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[5]/Q
                         net (fo=1, routed)           0.477     0.558    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/out[5]
    SLICE_X91Y334        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[5].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X91Y334        FDRE (Setup_DFF2_SLICEL_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[5].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -0.558    
  -------------------------------------------------------------------
                         slack                                  2.467    

Slack (MET) :             2.483ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[13]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[13].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        0.542ns  (logic 0.078ns (14.391%)  route 0.464ns (85.609%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y337                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[13]/C
    SLICE_X96Y337        FDRE (Prop_GFF_SLICEM_C_Q)
                                                      0.078     0.078 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[13]/Q
                         net (fo=1, routed)           0.464     0.542    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/out[13]
    SLICE_X93Y336        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[13].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X93Y336        FDRE (Setup_DFF2_SLICEM_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[13].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -0.542    
  -------------------------------------------------------------------
                         slack                                  2.483    

Slack (MET) :             2.486ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_en_lvl_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_en_sync/SYNC[0].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        0.539ns  (logic 0.079ns (14.666%)  route 0.460ns (85.334%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y328                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_en_lvl_reg/C
    SLICE_X95Y328        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_en_lvl_reg/Q
                         net (fo=2, routed)           0.460     0.539    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_en_sync/D[0]
    SLICE_X95Y332        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_en_sync/SYNC[0].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X95Y332        FDRE (Setup_DFF2_SLICEL_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_en_sync/SYNC[0].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -0.539    
  -------------------------------------------------------------------
                         slack                                  2.486    

Slack (MET) :             2.487ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[8]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[8].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        0.538ns  (logic 0.079ns (14.684%)  route 0.459ns (85.316%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y348                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[8]/C
    SLICE_X91Y348        FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[8]/Q
                         net (fo=1, routed)           0.459     0.538    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/out[8]
    SLICE_X90Y340        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[8].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X90Y340        FDRE (Setup_CFF2_SLICEM_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[8].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -0.538    
  -------------------------------------------------------------------
                         slack                                  2.487    

Slack (MET) :             2.489ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[7].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        0.536ns  (logic 0.079ns (14.739%)  route 0.457ns (85.261%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y331                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[7]/C
    SLICE_X96Y331        FDRE (Prop_EFF2_SLICEM_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[7]/Q
                         net (fo=1, routed)           0.457     0.536    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/out[7]
    SLICE_X91Y332        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[7].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X91Y332        FDRE (Setup_DFF2_SLICEL_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[7].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -0.536    
  -------------------------------------------------------------------
                         slack                                  2.489    

Slack (MET) :             2.557ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[0].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        0.468ns  (logic 0.080ns (17.094%)  route 0.388ns (82.906%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y337                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[0]/C
    SLICE_X96Y337        FDRE (Prop_DFF2_SLICEM_C_Q)
                                                      0.080     0.080 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[0]/Q
                         net (fo=1, routed)           0.388     0.468    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/out[0]
    SLICE_X91Y339        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[0].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X91Y339        FDRE (Setup_FFF2_SLICEL_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[0].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -0.468    
  -------------------------------------------------------------------
                         slack                                  2.557    





---------------------------------------------------------------------------------------------------
From Clock:  mmcm_clkout6
  To Clock:  mmcm_clkout0

Setup :            0  Failing Endpoints,  Worst Slack        1.242ns,  Total Violation        0.000ns
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.242ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[11]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[11].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        1.783ns  (logic 0.076ns (4.263%)  route 1.707ns (95.737%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X87Y334                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[11]/C
    SLICE_X87Y334        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     0.076 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[11]/Q
                         net (fo=2, routed)           1.707     1.783    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[31].sync_reg_reg[0]_0[11]
    SLICE_X86Y331        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[11].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X86Y331        FDRE (Setup_DFF2_SLICEM_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[11].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -1.783    
  -------------------------------------------------------------------
                         slack                                  1.242    

Slack (MET) :             1.260ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[1].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        1.765ns  (logic 0.081ns (4.588%)  route 1.684ns (95.412%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y312                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[1]/C
    SLICE_X88Y312        FDRE (Prop_FFF2_SLICEL_C_Q)
                                                      0.081     0.081 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[1]/Q
                         net (fo=33, routed)          1.684     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[31].sync_reg_reg[0]_0[1]
    SLICE_X83Y279        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[1].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X83Y279        FDRE (Setup_DFF2_SLICEM_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[1].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -1.765    
  -------------------------------------------------------------------
                         slack                                  1.260    

Slack (MET) :             1.492ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[15]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[15].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        1.533ns  (logic 0.077ns (5.024%)  route 1.456ns (94.976%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X87Y346                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[15]/C
    SLICE_X87Y346        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     0.077 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[15]/Q
                         net (fo=2, routed)           1.456     1.533    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[31].sync_reg_reg[0]_0[15]
    SLICE_X85Y338        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[15].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X85Y338        FDRE (Setup_GFF2_SLICEL_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[15].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -1.533    
  -------------------------------------------------------------------
                         slack                                  1.492    

Slack (MET) :             1.540ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[23]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[23].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        1.485ns  (logic 0.076ns (5.119%)  route 1.409ns (94.881%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X86Y314                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[23]/C
    SLICE_X86Y314        FDRE (Prop_FFF_SLICEM_C_Q)
                                                      0.076     0.076 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[23]/Q
                         net (fo=46, routed)          1.409     1.485    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[31].sync_reg_reg[0]_0[23]
    SLICE_X90Y287        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[23].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X90Y287        FDRE (Setup_DFF2_SLICEM_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[23].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -1.485    
  -------------------------------------------------------------------
                         slack                                  1.540    

Slack (MET) :             1.790ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[3].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        1.235ns  (logic 0.079ns (6.398%)  route 1.156ns (93.602%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X87Y307                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[3]/C
    SLICE_X87Y307        FDRE (Prop_GFF2_SLICEM_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[3]/Q
                         net (fo=39, routed)          1.156     1.235    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[31].sync_reg_reg[0]_0[3]
    SLICE_X90Y286        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[3].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X90Y286        FDRE (Setup_DFF2_SLICEM_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[3].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -1.235    
  -------------------------------------------------------------------
                         slack                                  1.790    

Slack (MET) :             1.828ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[6].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        1.197ns  (logic 0.079ns (6.599%)  route 1.118ns (93.401%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y312                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[6]/C
    SLICE_X88Y312        FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[6]/Q
                         net (fo=39, routed)          1.118     1.197    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[31].sync_reg_reg[0]_0[6]
    SLICE_X89Y269        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[6].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X89Y269        FDRE (Setup_HFF2_SLICEM_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[6].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -1.197    
  -------------------------------------------------------------------
                         slack                                  1.828    

Slack (MET) :             1.921ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[7].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        1.104ns  (logic 0.081ns (7.336%)  route 1.023ns (92.664%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y312                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[7]/C
    SLICE_X88Y312        FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.081     0.081 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[7]/Q
                         net (fo=46, routed)          1.023     1.104    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[31].sync_reg_reg[0]_0[7]
    SLICE_X90Y286        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[7].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X90Y286        FDRE (Setup_CFF2_SLICEM_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[7].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -1.104    
  -------------------------------------------------------------------
                         slack                                  1.921    

Slack (MET) :             1.978ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[5].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        1.047ns  (logic 0.081ns (7.735%)  route 0.966ns (92.265%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y303                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[5]/C
    SLICE_X88Y303        FDRE (Prop_FFF2_SLICEL_C_Q)
                                                      0.081     0.081 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[5]/Q
                         net (fo=45, routed)          0.966     1.047    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[31].sync_reg_reg[0]_0[5]
    SLICE_X89Y286        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[5].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X89Y286        FDRE (Setup_DFF2_SLICEM_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[5].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -1.047    
  -------------------------------------------------------------------
                         slack                                  1.978    

Slack (MET) :             2.036ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[8]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[8].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        0.989ns  (logic 0.079ns (7.991%)  route 0.910ns (92.009%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X87Y305                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[8]/C
    SLICE_X87Y305        FDRE (Prop_EFF2_SLICEM_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[8]/Q
                         net (fo=38, routed)          0.910     0.989    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[31].sync_reg_reg[0]_0[8]
    SLICE_X90Y288        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[8].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X90Y288        FDRE (Setup_CFF2_SLICEM_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[8].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -0.989    
  -------------------------------------------------------------------
                         slack                                  2.036    

Slack (MET) :             2.112ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[13]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[13].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        0.913ns  (logic 0.081ns (8.868%)  route 0.832ns (91.132%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y312                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[13]/C
    SLICE_X88Y312        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.081     0.081 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[13]/Q
                         net (fo=40, routed)          0.832     0.913    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[31].sync_reg_reg[0]_0[13]
    SLICE_X85Y305        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[13].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X85Y305        FDRE (Setup_DFF2_SLICEL_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[13].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -0.913    
  -------------------------------------------------------------------
                         slack                                  2.112    





---------------------------------------------------------------------------------------------------
From Clock:  mmcm_clkout0
  To Clock:  pll_clk[0]_DIV

Setup :            0  Failing Endpoints,  Worst Slack        0.182ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.622ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.182ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_upp_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[0]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[0]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.790ns  (logic 0.078ns (4.359%)  route 1.712ns (95.641%))
  Logic Levels:           0  
  Clock Path Skew:        -0.701ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.429ns = ( 7.430 - 3.001 ) 
    Source Clock Delay      (SCD):    4.806ns
    Clock Pessimism Removal (CPR):    -0.324ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      2.044ns (routing 0.788ns, distribution 1.256ns)
  Clock Net Delay (Destination): 1.629ns (routing 0.716ns, distribution 0.913ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.044     4.806    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/dReg_reg[10]
    SLICE_X94Y304        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_upp_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y304        FDRE (Prop_GFF_SLICEM_C_Q)
                                                      0.078     4.884 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_upp_reg[0]/Q
                         net (fo=8, routed)           1.712     6.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_t_b_upp[0]
    BITSLICE_CONTROL_X0Y25
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[0]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     5.285    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     6.130    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.154 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.629     7.783    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y7             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     7.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.096     7.249    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y25
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     7.355 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y25
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     7.430 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
                         clock pessimism             -0.324     7.106    
                         clock uncertainty           -0.170     6.936    
    BITSLICE_CONTROL_X0Y25
                         BITSLICE_CONTROL (Setup_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TBYTE_IN[0])
                                                     -0.158     6.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                          6.778    
                         arrival time                          -6.595    
  -------------------------------------------------------------------
                         slack                                  0.182    

Slack (MET) :             0.183ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_upp_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[2]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[0]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.792ns  (logic 0.079ns (4.408%)  route 1.713ns (95.592%))
  Logic Levels:           0  
  Clock Path Skew:        -0.688ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.429ns = ( 7.430 - 3.001 ) 
    Source Clock Delay      (SCD):    4.793ns
    Clock Pessimism Removal (CPR):    -0.324ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      2.031ns (routing 0.788ns, distribution 1.243ns)
  Clock Net Delay (Destination): 1.629ns (routing 0.716ns, distribution 0.913ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.031     4.793    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/dReg_reg[10]
    SLICE_X92Y301        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_upp_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y301        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     4.872 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_upp_reg[2]/Q
                         net (fo=8, routed)           1.713     6.585    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_t_b_upp[2]
    BITSLICE_CONTROL_X0Y25
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[2]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     5.285    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     6.130    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.154 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.629     7.783    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y7             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     7.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.096     7.249    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y25
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     7.355 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y25
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     7.430 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
                         clock pessimism             -0.324     7.106    
                         clock uncertainty           -0.170     6.936    
    BITSLICE_CONTROL_X0Y25
                         BITSLICE_CONTROL (Setup_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TBYTE_IN[2])
                                                     -0.168     6.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                          6.768    
                         arrival time                          -6.585    
  -------------------------------------------------------------------
                         slack                                  0.183    

Slack (MET) :             0.251ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_upp_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[3]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[0]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.799ns  (logic 0.079ns (4.392%)  route 1.720ns (95.609%))
  Logic Levels:           0  
  Clock Path Skew:        -0.688ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.429ns = ( 7.430 - 3.001 ) 
    Source Clock Delay      (SCD):    4.793ns
    Clock Pessimism Removal (CPR):    -0.324ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      2.031ns (routing 0.788ns, distribution 1.243ns)
  Clock Net Delay (Destination): 1.629ns (routing 0.716ns, distribution 0.913ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.031     4.793    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/dReg_reg[10]
    SLICE_X92Y301        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_upp_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y301        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.079     4.872 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_upp_reg[3]/Q
                         net (fo=8, routed)           1.720     6.592    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_t_b_upp[3]
    BITSLICE_CONTROL_X0Y25
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[3]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     5.285    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     6.130    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.154 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.629     7.783    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y7             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     7.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.096     7.249    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y25
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     7.355 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y25
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     7.430 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
                         clock pessimism             -0.324     7.106    
                         clock uncertainty           -0.170     6.936    
    BITSLICE_CONTROL_X0Y25
                         BITSLICE_CONTROL (Setup_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TBYTE_IN[3])
                                                     -0.093     6.843    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                          6.843    
                         arrival time                          -6.592    
  -------------------------------------------------------------------
                         slack                                  0.251    

Slack (MET) :             0.263ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_upp_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[0]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[0]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.704ns  (logic 0.078ns (4.577%)  route 1.626ns (95.423%))
  Logic Levels:           0  
  Clock Path Skew:        -0.706ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.424ns = ( 7.425 - 3.001 ) 
    Source Clock Delay      (SCD):    4.806ns
    Clock Pessimism Removal (CPR):    -0.324ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      2.044ns (routing 0.788ns, distribution 1.256ns)
  Clock Net Delay (Destination): 1.629ns (routing 0.716ns, distribution 0.913ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.044     4.806    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/dReg_reg[10]
    SLICE_X94Y304        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_upp_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y304        FDRE (Prop_GFF_SLICEM_C_Q)
                                                      0.078     4.884 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_upp_reg[0]/Q
                         net (fo=8, routed)           1.626     6.510    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_t_b_upp[0]
    BITSLICE_CONTROL_X0Y27
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[0]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     5.285    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     6.130    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.154 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.629     7.783    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y7             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     7.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.091     7.244    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y27
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     7.350 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y27
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     7.425 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
                         clock pessimism             -0.324     7.101    
                         clock uncertainty           -0.170     6.931    
    BITSLICE_CONTROL_X0Y27
                         BITSLICE_CONTROL (Setup_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TBYTE_IN[0])
                                                     -0.158     6.773    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                          6.773    
                         arrival time                          -6.510    
  -------------------------------------------------------------------
                         slack                                  0.263    

Slack (MET) :             0.330ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_upp_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[2]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[0]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.640ns  (logic 0.079ns (4.816%)  route 1.561ns (95.184%))
  Logic Levels:           0  
  Clock Path Skew:        -0.693ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.424ns = ( 7.425 - 3.001 ) 
    Source Clock Delay      (SCD):    4.793ns
    Clock Pessimism Removal (CPR):    -0.324ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      2.031ns (routing 0.788ns, distribution 1.243ns)
  Clock Net Delay (Destination): 1.629ns (routing 0.716ns, distribution 0.913ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.031     4.793    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/dReg_reg[10]
    SLICE_X92Y301        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_upp_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y301        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     4.872 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_upp_reg[2]/Q
                         net (fo=8, routed)           1.561     6.433    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_t_b_upp[2]
    BITSLICE_CONTROL_X0Y27
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[2]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     5.285    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     6.130    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.154 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.629     7.783    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y7             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     7.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.091     7.244    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y27
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     7.350 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y27
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     7.425 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
                         clock pessimism             -0.324     7.101    
                         clock uncertainty           -0.170     6.931    
    BITSLICE_CONTROL_X0Y27
                         BITSLICE_CONTROL (Setup_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TBYTE_IN[2])
                                                     -0.168     6.763    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                          6.763    
                         arrival time                          -6.433    
  -------------------------------------------------------------------
                         slack                                  0.330    

Slack (MET) :             0.335ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_upp_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[1]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[0]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.642ns  (logic 0.079ns (4.811%)  route 1.563ns (95.189%))
  Logic Levels:           0  
  Clock Path Skew:        -0.701ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.429ns = ( 7.430 - 3.001 ) 
    Source Clock Delay      (SCD):    4.806ns
    Clock Pessimism Removal (CPR):    -0.324ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      2.044ns (routing 0.788ns, distribution 1.256ns)
  Clock Net Delay (Destination): 1.629ns (routing 0.716ns, distribution 0.913ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.044     4.806    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/dReg_reg[10]
    SLICE_X94Y304        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_upp_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y304        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.079     4.885 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_upp_reg[1]/Q
                         net (fo=8, routed)           1.563     6.448    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_t_b_upp[1]
    BITSLICE_CONTROL_X0Y25
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[1]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     5.285    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     6.130    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.154 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.629     7.783    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y7             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     7.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.096     7.249    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y25
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     7.355 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y25
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     7.430 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
                         clock pessimism             -0.324     7.106    
                         clock uncertainty           -0.170     6.936    
    BITSLICE_CONTROL_X0Y25
                         BITSLICE_CONTROL (Setup_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TBYTE_IN[1])
                                                     -0.153     6.783    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                          6.783    
                         arrival time                          -6.448    
  -------------------------------------------------------------------
                         slack                                  0.335    

Slack (MET) :             0.356ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_upp_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[3]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[0]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.688ns  (logic 0.079ns (4.679%)  route 1.609ns (95.321%))
  Logic Levels:           0  
  Clock Path Skew:        -0.693ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.424ns = ( 7.425 - 3.001 ) 
    Source Clock Delay      (SCD):    4.793ns
    Clock Pessimism Removal (CPR):    -0.324ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      2.031ns (routing 0.788ns, distribution 1.243ns)
  Clock Net Delay (Destination): 1.629ns (routing 0.716ns, distribution 0.913ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.031     4.793    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/dReg_reg[10]
    SLICE_X92Y301        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_upp_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y301        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.079     4.872 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_upp_reg[3]/Q
                         net (fo=8, routed)           1.609     6.481    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_t_b_upp[3]
    BITSLICE_CONTROL_X0Y27
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[3]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     5.285    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     6.130    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.154 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.629     7.783    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y7             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     7.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.091     7.244    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y27
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     7.350 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y27
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     7.425 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
                         clock pessimism             -0.324     7.101    
                         clock uncertainty           -0.170     6.931    
    BITSLICE_CONTROL_X0Y27
                         BITSLICE_CONTROL (Setup_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TBYTE_IN[3])
                                                     -0.093     6.838    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                          6.838    
                         arrival time                          -6.481    
  -------------------------------------------------------------------
                         slack                                  0.356    

Slack (MET) :             0.397ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_upp_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[1]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[0]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.580ns  (logic 0.079ns (5.000%)  route 1.501ns (95.000%))
  Logic Levels:           0  
  Clock Path Skew:        -0.701ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.429ns = ( 7.430 - 3.001 ) 
    Source Clock Delay      (SCD):    4.806ns
    Clock Pessimism Removal (CPR):    -0.324ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      2.044ns (routing 0.788ns, distribution 1.256ns)
  Clock Net Delay (Destination): 1.629ns (routing 0.716ns, distribution 0.913ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.044     4.806    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/dReg_reg[10]
    SLICE_X94Y304        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_upp_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y304        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.079     4.885 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_upp_reg[1]/Q
                         net (fo=8, routed)           1.501     6.386    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_t_b_upp[1]
    BITSLICE_CONTROL_X0Y29
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[1]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      3.001     3.001 f  
    J19                                               0.000     3.001 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     5.285    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.915 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     6.130    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.154 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.629     7.783    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y7             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     7.153 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.096     7.249    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y29
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     7.355 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y29
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     7.430 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
                         clock pessimism             -0.324     7.106    
                         clock uncertainty           -0.170     6.936    
    BITSLICE_CONTROL_X0Y29
                         BITSLICE_CONTROL (Setup_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TBYTE_IN[1])
                                                     -0.153     6.783    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                          6.783    
                         arrival time                          -6.386    
  -------------------------------------------------------------------
                         slack                                  0.397    

Slack (MET) :             0.413ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_upp_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[1]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[0]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.559ns  (logic 0.079ns (5.067%)  route 1.480ns (94.933%))
  Logic Levels:           0  
  Clock Path Skew:        -0.706ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.424ns = ( 7.425 - 3.001 ) 
    Source Clock Delay      (SCD):    4.806ns
    Clock Pessimism Removal (CPR):    -0.324ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      2.044ns (routing 0.788ns, distribution 1.256ns)
  Clock Net Delay (Destination): 1.629ns (routing 0.716ns, distribution 0.913ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.044     4.806    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/dReg_reg[10]
    SLICE_X94Y304        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_upp_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y304        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.079     4.885 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_upp_reg[1]/Q
                         net (fo=8, routed)           1.480     6.365    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_t_b_upp[1]
    BITSLICE_CONTROL_X0Y27
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[1]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     5.285    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     6.130    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.154 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.629     7.783    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y7             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     7.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.091     7.244    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y27
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     7.350 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y27
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     7.425 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
                         clock pessimism             -0.324     7.101    
                         clock uncertainty           -0.170     6.931    
    BITSLICE_CONTROL_X0Y27
                         BITSLICE_CONTROL (Setup_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TBYTE_IN[1])
                                                     -0.153     6.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                          6.778    
                         arrival time                          -6.365    
  -------------------------------------------------------------------
                         slack                                  0.413    

Slack (MET) :             0.426ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_upp_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[0]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[0]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.546ns  (logic 0.078ns (5.045%)  route 1.468ns (94.955%))
  Logic Levels:           0  
  Clock Path Skew:        -0.701ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.429ns = ( 7.430 - 3.001 ) 
    Source Clock Delay      (SCD):    4.806ns
    Clock Pessimism Removal (CPR):    -0.324ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      2.044ns (routing 0.788ns, distribution 1.256ns)
  Clock Net Delay (Destination): 1.629ns (routing 0.716ns, distribution 0.913ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.044     4.806    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/dReg_reg[10]
    SLICE_X94Y304        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_upp_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y304        FDRE (Prop_GFF_SLICEM_C_Q)
                                                      0.078     4.884 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_upp_reg[0]/Q
                         net (fo=8, routed)           1.468     6.352    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_t_b_upp[0]
    BITSLICE_CONTROL_X0Y29
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[0]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      3.001     3.001 f  
    J19                                               0.000     3.001 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     5.285    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.915 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     6.130    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.154 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.629     7.783    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y7             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     7.153 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.096     7.249    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y29
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     7.355 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y29
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     7.430 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
                         clock pessimism             -0.324     7.106    
                         clock uncertainty           -0.170     6.936    
    BITSLICE_CONTROL_X0Y29
                         BITSLICE_CONTROL (Setup_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TBYTE_IN[0])
                                                     -0.158     6.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                          6.778    
                         arrival time                          -6.352    
  -------------------------------------------------------------------
                         slack                                  0.426    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.622ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[5].u_ddr_mc_wr_byte/genBit[0].u_ddr_mc_wr_bit/dReg_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[5]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[0]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.371ns  (logic 0.057ns (15.364%)  route 0.314ns (84.636%))
  Logic Levels:           0  
  Clock Path Skew:        -0.495ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.150ns
    Source Clock Delay      (SCD):    4.907ns
    Clock Pessimism Removal (CPR):    -0.262ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.754ns (routing 0.716ns, distribution 1.038ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.129    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.754     4.907    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[5].u_ddr_mc_wr_byte/genBit[0].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X82Y212        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[5].u_ddr_mc_wr_byte/genBit[0].u_ddr_mc_wr_bit/dReg_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y212        FDRE (Prop_FFF_SLICEM_C_Q)
                                                      0.057     4.964 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[5].u_ddr_mc_wr_byte/genBit[0].u_ddr_mc_wr_bit/dReg_reg[5]/Q
                         net (fo=1, routed)           0.314     5.278    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/ch0_mcal_DQOut[5]
    BITSLICE_RX_TX_X0Y187
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[5]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41415, routed)       1.812     4.574    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y7             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.516 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.132     3.648    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y28
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     3.825 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y28
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.934 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y28
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT5[26])
                                                      0.192     4.126 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT5[26]
                         net (fo=1, routed)           0.024     4.150    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT5[26]
    BITSLICE_RX_TX_X0Y187
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.262     4.412    
                         clock uncertainty            0.170     4.582    
    BITSLICE_RX_TX_X0Y187
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[5])
                                                      0.074     4.656    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.656    
                         arrival time                           5.278    
  -------------------------------------------------------------------
                         slack                                  0.622    

Slack (MET) :             0.624ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[5].u_ddr_mc_wr_byte/genBit[0].u_ddr_mc_wr_bit/dReg_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[4]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[0]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.323ns  (logic 0.058ns (17.957%)  route 0.265ns (82.043%))
  Logic Levels:           0  
  Clock Path Skew:        -0.501ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.150ns
    Source Clock Delay      (SCD):    4.913ns
    Clock Pessimism Removal (CPR):    -0.262ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.760ns (routing 0.716ns, distribution 1.044ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.129    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.760     4.913    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[5].u_ddr_mc_wr_byte/genBit[0].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X82Y216        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[5].u_ddr_mc_wr_byte/genBit[0].u_ddr_mc_wr_bit/dReg_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y216        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.058     4.971 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[5].u_ddr_mc_wr_byte/genBit[0].u_ddr_mc_wr_bit/dReg_reg[4]/Q
                         net (fo=1, routed)           0.265     5.236    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/ch0_mcal_DQOut[4]
    BITSLICE_RX_TX_X0Y187
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[4]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41415, routed)       1.812     4.574    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y7             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.516 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.132     3.648    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y28
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     3.825 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y28
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.934 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y28
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT5[26])
                                                      0.192     4.126 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT5[26]
                         net (fo=1, routed)           0.024     4.150    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT5[26]
    BITSLICE_RX_TX_X0Y187
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.262     4.412    
                         clock uncertainty            0.170     4.582    
    BITSLICE_RX_TX_X0Y187
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[4])
                                                      0.030     4.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.612    
                         arrival time                           5.236    
  -------------------------------------------------------------------
                         slack                                  0.624    

Slack (MET) :             0.626ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[5].u_ddr_mc_wr_byte/genBit[0].u_ddr_mc_wr_bit/dReg_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[6]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[0]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.335ns  (logic 0.058ns (17.313%)  route 0.277ns (82.687%))
  Logic Levels:           0  
  Clock Path Skew:        -0.504ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.150ns
    Source Clock Delay      (SCD):    4.915ns
    Clock Pessimism Removal (CPR):    -0.262ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.762ns (routing 0.716ns, distribution 1.046ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.129    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.762     4.915    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[5].u_ddr_mc_wr_byte/genBit[0].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X81Y216        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[5].u_ddr_mc_wr_byte/genBit[0].u_ddr_mc_wr_bit/dReg_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y216        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.058     4.973 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[5].u_ddr_mc_wr_byte/genBit[0].u_ddr_mc_wr_bit/dReg_reg[6]/Q
                         net (fo=1, routed)           0.277     5.250    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/ch0_mcal_DQOut[6]
    BITSLICE_RX_TX_X0Y187
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[6]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41415, routed)       1.812     4.574    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y7             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.516 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.132     3.648    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y28
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     3.825 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y28
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.934 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y28
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT5[26])
                                                      0.192     4.126 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT5[26]
                         net (fo=1, routed)           0.024     4.150    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT5[26]
    BITSLICE_RX_TX_X0Y187
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.262     4.412    
                         clock uncertainty            0.170     4.582    
    BITSLICE_RX_TX_X0Y187
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[6])
                                                      0.043     4.625    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.625    
                         arrival time                           5.250    
  -------------------------------------------------------------------
                         slack                                  0.626    

Slack (MET) :             0.639ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[5].u_ddr_mc_wr_byte/genBit[0].u_ddr_mc_wr_bit/dReg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[0]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[0]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.318ns  (logic 0.060ns (18.868%)  route 0.258ns (81.132%))
  Logic Levels:           0  
  Clock Path Skew:        -0.506ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.150ns
    Source Clock Delay      (SCD):    4.917ns
    Clock Pessimism Removal (CPR):    -0.262ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.764ns (routing 0.716ns, distribution 1.048ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.129    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.764     4.917    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[5].u_ddr_mc_wr_byte/genBit[0].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X81Y216        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[5].u_ddr_mc_wr_byte/genBit[0].u_ddr_mc_wr_bit/dReg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y216        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.060     4.977 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[5].u_ddr_mc_wr_byte/genBit[0].u_ddr_mc_wr_bit/dReg_reg[0]/Q
                         net (fo=1, routed)           0.258     5.235    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/ch0_mcal_DQOut[0]
    BITSLICE_RX_TX_X0Y187
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[0]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41415, routed)       1.812     4.574    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y7             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.516 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.132     3.648    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y28
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     3.825 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y28
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.934 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y28
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT5[26])
                                                      0.192     4.126 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT5[26]
                         net (fo=1, routed)           0.024     4.150    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT5[26]
    BITSLICE_RX_TX_X0Y187
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.262     4.412    
                         clock uncertainty            0.170     4.582    
    BITSLICE_RX_TX_X0Y187
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[0])
                                                      0.015     4.597    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.597    
                         arrival time                           5.235    
  -------------------------------------------------------------------
                         slack                                  0.639    

Slack (MET) :             0.641ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[4].u_ddr_mc_wr_byte/genBit[0].u_ddr_mc_wr_bit/dReg_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[6]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[0]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.348ns  (logic 0.058ns (16.667%)  route 0.290ns (83.333%))
  Logic Levels:           0  
  Clock Path Skew:        -0.506ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.158ns
    Source Clock Delay      (SCD):    4.926ns
    Clock Pessimism Removal (CPR):    -0.262ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.773ns (routing 0.716ns, distribution 1.057ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.129    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.773     4.926    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[4].u_ddr_mc_wr_byte/genBit[0].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X82Y232        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[4].u_ddr_mc_wr_byte/genBit[0].u_ddr_mc_wr_bit/dReg_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y232        FDRE (Prop_CFF_SLICEM_C_Q)
                                                      0.058     4.984 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[4].u_ddr_mc_wr_byte/genBit[0].u_ddr_mc_wr_bit/dReg_reg[6]/Q
                         net (fo=1, routed)           0.290     5.274    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/ch0_mcal_DQOut[6]
    BITSLICE_RX_TX_X0Y200
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[6]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41415, routed)       1.812     4.574    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y7             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.516 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.140     3.656    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y30
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     3.833 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y30
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.942 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y30
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT5[26])
                                                      0.192     4.134 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT5[26]
                         net (fo=1, routed)           0.024     4.158    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT5[26]
    BITSLICE_RX_TX_X0Y200
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.262     4.420    
                         clock uncertainty            0.170     4.590    
    BITSLICE_RX_TX_X0Y200
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[6])
                                                      0.043     4.633    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.633    
                         arrival time                           5.274    
  -------------------------------------------------------------------
                         slack                                  0.641    

Slack (MET) :             0.648ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[5].u_ddr_mc_wr_byte/genBit[0].u_ddr_mc_wr_bit/dReg_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[2]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[0]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.340ns  (logic 0.058ns (17.059%)  route 0.282ns (82.941%))
  Logic Levels:           0  
  Clock Path Skew:        -0.501ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.150ns
    Source Clock Delay      (SCD):    4.913ns
    Clock Pessimism Removal (CPR):    -0.262ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.760ns (routing 0.716ns, distribution 1.044ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.129    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.760     4.913    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[5].u_ddr_mc_wr_byte/genBit[0].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X82Y216        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[5].u_ddr_mc_wr_byte/genBit[0].u_ddr_mc_wr_bit/dReg_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y216        FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.058     4.971 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[5].u_ddr_mc_wr_byte/genBit[0].u_ddr_mc_wr_bit/dReg_reg[2]/Q
                         net (fo=1, routed)           0.282     5.253    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/ch0_mcal_DQOut[2]
    BITSLICE_RX_TX_X0Y187
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[2]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41415, routed)       1.812     4.574    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y7             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.516 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.132     3.648    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y28
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     3.825 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y28
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.934 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y28
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT5[26])
                                                      0.192     4.126 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT5[26]
                         net (fo=1, routed)           0.024     4.150    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT5[26]
    BITSLICE_RX_TX_X0Y187
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.262     4.412    
                         clock uncertainty            0.170     4.582    
    BITSLICE_RX_TX_X0Y187
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[2])
                                                      0.023     4.605    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.605    
                         arrival time                           5.253    
  -------------------------------------------------------------------
                         slack                                  0.648    

Slack (MET) :             0.651ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[7].u_ddr_mc_wr_byte/u_ddr_mc_wr_dm/dReg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[0]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[0]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.383ns  (logic 0.059ns (15.405%)  route 0.324ns (84.595%))
  Logic Levels:           0  
  Clock Path Skew:        -0.514ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.146ns
    Source Clock Delay      (SCD):    4.922ns
    Clock Pessimism Removal (CPR):    -0.262ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.769ns (routing 0.716ns, distribution 1.053ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.129    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.769     4.922    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[7].u_ddr_mc_wr_byte/u_ddr_mc_wr_dm/dReg_reg[10]_0
    SLICE_X84Y181        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[7].u_ddr_mc_wr_byte/u_ddr_mc_wr_dm/dReg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X84Y181        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.059     4.981 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[7].u_ddr_mc_wr_byte/u_ddr_mc_wr_dm/dReg_reg[0]/Q
                         net (fo=1, routed)           0.324     5.305    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/clb2phy_wr_dq0[0]
    BITSLICE_RX_TX_X0Y156
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[0]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41415, routed)       1.812     4.574    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y7             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.516 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.139     3.655    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y24
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     3.832 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y24
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.941 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y24
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT0[26])
                                                      0.162     4.103 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT0[26]
                         net (fo=1, routed)           0.043     4.146    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT0[26]
    BITSLICE_RX_TX_X0Y156
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.262     4.408    
                         clock uncertainty            0.170     4.578    
    BITSLICE_RX_TX_X0Y156
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[0])
                                                      0.076     4.654    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.654    
                         arrival time                           5.305    
  -------------------------------------------------------------------
                         slack                                  0.651    

Slack (MET) :             0.653ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[4].u_ddr_mc_wr_byte/genBit[0].u_ddr_mc_wr_bit/dReg_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[1]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[0]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.352ns  (logic 0.058ns (16.477%)  route 0.294ns (83.523%))
  Logic Levels:           0  
  Clock Path Skew:        -0.506ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.158ns
    Source Clock Delay      (SCD):    4.926ns
    Clock Pessimism Removal (CPR):    -0.262ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.773ns (routing 0.716ns, distribution 1.057ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.129    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.773     4.926    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[4].u_ddr_mc_wr_byte/genBit[0].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X82Y231        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[4].u_ddr_mc_wr_byte/genBit[0].u_ddr_mc_wr_bit/dReg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y231        FDRE (Prop_CFF_SLICEM_C_Q)
                                                      0.058     4.984 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[4].u_ddr_mc_wr_byte/genBit[0].u_ddr_mc_wr_bit/dReg_reg[1]/Q
                         net (fo=1, routed)           0.294     5.278    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/ch0_mcal_DQOut[1]
    BITSLICE_RX_TX_X0Y200
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[1]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41415, routed)       1.812     4.574    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y7             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.516 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.140     3.656    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y30
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     3.833 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y30
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.942 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y30
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT5[26])
                                                      0.192     4.134 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT5[26]
                         net (fo=1, routed)           0.024     4.158    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT5[26]
    BITSLICE_RX_TX_X0Y200
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.262     4.420    
                         clock uncertainty            0.170     4.590    
    BITSLICE_RX_TX_X0Y200
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[1])
                                                      0.035     4.625    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.625    
                         arrival time                           5.278    
  -------------------------------------------------------------------
                         slack                                  0.653    

Slack (MET) :             0.657ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[5].u_ddr_mc_wr_byte/genBit[6].u_ddr_mc_wr_bit/dReg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[0]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[0]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.375ns  (logic 0.059ns (15.733%)  route 0.316ns (84.267%))
  Logic Levels:           0  
  Clock Path Skew:        -0.504ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.142ns
    Source Clock Delay      (SCD):    4.908ns
    Clock Pessimism Removal (CPR):    -0.262ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.755ns (routing 0.716ns, distribution 1.039ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.129    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.755     4.908    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[5].u_ddr_mc_wr_byte/genBit[6].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X81Y212        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[5].u_ddr_mc_wr_byte/genBit[6].u_ddr_mc_wr_bit/dReg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y212        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.059     4.967 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[5].u_ddr_mc_wr_byte/genBit[6].u_ddr_mc_wr_bit/dReg_reg[0]/Q
                         net (fo=1, routed)           0.316     5.283    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/ch0_mcal_DQOut[0]
    BITSLICE_RX_TX_X0Y185
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[0]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41415, routed)       1.812     4.574    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y7             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.516 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.132     3.648    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y28
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     3.825 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y28
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.934 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y28
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT3[26])
                                                      0.187     4.121 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT3[26]
                         net (fo=1, routed)           0.021     4.142    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT3[26]
    BITSLICE_RX_TX_X0Y185
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.262     4.404    
                         clock uncertainty            0.170     4.574    
    BITSLICE_RX_TX_X0Y185
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[0])
                                                      0.052     4.626    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.626    
                         arrival time                           5.283    
  -------------------------------------------------------------------
                         slack                                  0.657    

Slack (MET) :             0.657ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[4].u_ddr_mc_wr_byte/genBit[2].u_ddr_mc_wr_bit/dReg_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[6]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[0]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.344ns  (logic 0.058ns (16.860%)  route 0.286ns (83.140%))
  Logic Levels:           0  
  Clock Path Skew:        -0.547ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.124ns
    Source Clock Delay      (SCD):    4.933ns
    Clock Pessimism Removal (CPR):    -0.262ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.780ns (routing 0.716ns, distribution 1.064ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.129    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.780     4.933    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[4].u_ddr_mc_wr_byte/genBit[2].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X83Y238        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[4].u_ddr_mc_wr_byte/genBit[2].u_ddr_mc_wr_bit/dReg_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y238        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.058     4.991 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[4].u_ddr_mc_wr_byte/genBit[2].u_ddr_mc_wr_bit/dReg_reg[6]/Q
                         net (fo=1, routed)           0.286     5.277    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/ch0_mcal_DQOut[6]
    BITSLICE_RX_TX_X0Y206
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[6]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      0.000     0.000 f  
    J19                                               0.000     0.000 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41415, routed)       1.812     4.574    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y7             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.516 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.142     3.658    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y31
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.151     3.809 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y31
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.918 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y31
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT5[26])
                                                      0.182     4.100 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT5[26]
                         net (fo=1, routed)           0.024     4.124    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT5[26]
    BITSLICE_RX_TX_X0Y206
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.262     4.386    
                         clock uncertainty            0.170     4.556    
    BITSLICE_RX_TX_X0Y206
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[6])
                                                      0.064     4.620    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.620    
                         arrival time                           5.277    
  -------------------------------------------------------------------
                         slack                                  0.657    





---------------------------------------------------------------------------------------------------
From Clock:  mmcm_clkout0
  To Clock:  pll_clk[1]_DIV

Setup :            0  Failing Endpoints,  Worst Slack        0.676ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.536ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.676ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/u_ddr_mc_wr_dm/dReg_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[4]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[1]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.685ns  (logic 0.079ns (4.688%)  route 1.606ns (95.312%))
  Logic Levels:           0  
  Clock Path Skew:        -0.442ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.614ns = ( 7.615 - 3.001 ) 
    Source Clock Delay      (SCD):    4.798ns
    Clock Pessimism Removal (CPR):    -0.258ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      2.036ns (routing 0.788ns, distribution 1.248ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.036     4.798    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/u_ddr_mc_wr_dm/dReg_reg[10]_0
    SLICE_X88Y253        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/u_ddr_mc_wr_dm/dReg_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y253        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     4.877 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/u_ddr_mc_wr_dm/dReg_reg[4]/Q
                         net (fo=1, routed)           1.606     6.483    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/clb2phy_wr_dq0[4]
    BITSLICE_RX_TX_X0Y247
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[4]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     5.285    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     6.130    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.154 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41415, routed)       1.672     7.826    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y8             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     7.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.104     7.300    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y38
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.117     7.417 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y38
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     7.492 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y38
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT0[26])
                                                      0.109     7.601 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT0[26]
                         net (fo=1, routed)           0.014     7.615    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT0[26]
    BITSLICE_RX_TX_X0Y247
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.258     7.357    
                         clock uncertainty           -0.170     7.187    
    BITSLICE_RX_TX_X0Y247
                         RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[4])
                                                     -0.028     7.159    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          7.159    
                         arrival time                          -6.483    
  -------------------------------------------------------------------
                         slack                                  0.676    

Slack (MET) :             0.750ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[0].u_ddr_mc_wr_byte/u_ddr_mc_wr_dm/dReg_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[3]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[1]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.590ns  (logic 0.078ns (4.906%)  route 1.512ns (95.094%))
  Logic Levels:           0  
  Clock Path Skew:        -0.454ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.609ns = ( 7.610 - 3.001 ) 
    Source Clock Delay      (SCD):    4.805ns
    Clock Pessimism Removal (CPR):    -0.258ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      2.043ns (routing 0.788ns, distribution 1.255ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.043     4.805    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[0].u_ddr_mc_wr_byte/u_ddr_mc_wr_dm/dReg_reg[10]_0
    SLICE_X87Y253        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[0].u_ddr_mc_wr_byte/u_ddr_mc_wr_dm/dReg_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X87Y253        FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.078     4.883 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[0].u_ddr_mc_wr_byte/u_ddr_mc_wr_dm/dReg_reg[3]/Q
                         net (fo=1, routed)           1.512     6.395    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/clb2phy_wr_dq0[3]
    BITSLICE_RX_TX_X0Y234
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[3]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      3.001     3.001 f  
    J19                                               0.000     3.001 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     5.285    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.915 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     6.130    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.154 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41415, routed)       1.672     7.826    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y8             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     7.196 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.099     7.295    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y36
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.117     7.412 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y36
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     7.487 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y36
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT0[26])
                                                      0.109     7.596 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT0[26]
                         net (fo=1, routed)           0.014     7.610    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT0[26]
    BITSLICE_RX_TX_X0Y234
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.258     7.352    
                         clock uncertainty           -0.170     7.182    
    BITSLICE_RX_TX_X0Y234
                         RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[3])
                                                     -0.037     7.145    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          7.145    
                         arrival time                          -6.395    
  -------------------------------------------------------------------
                         slack                                  0.750    

Slack (MET) :             0.755ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_upp_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[3]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[1]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.343ns  (logic 0.079ns (5.883%)  route 1.264ns (94.117%))
  Logic Levels:           0  
  Clock Path Skew:        -0.640ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.473ns = ( 7.474 - 3.001 ) 
    Source Clock Delay      (SCD):    4.793ns
    Clock Pessimism Removal (CPR):    -0.320ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      2.031ns (routing 0.788ns, distribution 1.243ns)
  Clock Net Delay (Destination): 1.672ns (routing 0.716ns, distribution 0.956ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.031     4.793    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/dReg_reg[10]
    SLICE_X92Y301        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_upp_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y301        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.079     4.872 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_upp_reg[3]/Q
                         net (fo=8, routed)           1.264     6.136    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_t_b_upp[3]
    BITSLICE_CONTROL_X0Y35
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[3]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     5.285    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     6.130    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.154 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.672     7.826    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y8             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     7.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.097     7.293    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y35
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     7.399 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y35
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     7.474 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
                         clock pessimism             -0.320     7.154    
                         clock uncertainty           -0.170     6.984    
    BITSLICE_CONTROL_X0Y35
                         BITSLICE_CONTROL (Setup_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TBYTE_IN[3])
                                                     -0.093     6.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                          6.891    
                         arrival time                          -6.136    
  -------------------------------------------------------------------
                         slack                                  0.755    

Slack (MET) :             0.759ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[2].u_ddr_mc_rd_en_upp/rdEn_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[3]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[1]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.477ns  (logic 0.079ns (5.349%)  route 1.398ns (94.651%))
  Logic Levels:           0  
  Clock Path Skew:        -0.546ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.482ns = ( 7.483 - 3.001 ) 
    Source Clock Delay      (SCD):    4.770ns
    Clock Pessimism Removal (CPR):    -0.258ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      2.008ns (routing 0.788ns, distribution 1.220ns)
  Clock Net Delay (Destination): 1.672ns (routing 0.716ns, distribution 0.956ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.008     4.770    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[2].u_ddr_mc_rd_en_upp/rsMask_reg[7][9]_0
    SLICE_X88Y297        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[2].u_ddr_mc_rd_en_upp/rdEn_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y297        FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.079     4.849 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[2].u_ddr_mc_rd_en_upp/rdEn_reg[3]/Q
                         net (fo=1, routed)           1.398     6.247    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_rden_upp[3]
    BITSLICE_CONTROL_X0Y35
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[3]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     5.285    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     6.130    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.154 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.672     7.826    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y8             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     7.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.097     7.293    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y35
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_RX_DIV2_CLK_Q)
                                                      0.112     7.405 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y35
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_RX_DIV2_CLK_Q_RX_DIV4_CLK_Q)
                                                      0.078     7.483 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q
                         clock pessimism             -0.258     7.225    
                         clock uncertainty           -0.170     7.055    
    BITSLICE_CONTROL_X0Y35
                         BITSLICE_CONTROL (Setup_CONTROL_BITSLICE_CONTROL_RX_DIV4_CLK_Q_PHY_RDEN[3])
                                                     -0.049     7.006    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                          7.006    
                         arrival time                          -6.247    
  -------------------------------------------------------------------
                         slack                                  0.759    

Slack (MET) :             0.774ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/u_ddr_mc_wr_dm/dReg_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[7]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[1]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.560ns  (logic 0.078ns (5.000%)  route 1.482ns (95.000%))
  Logic Levels:           0  
  Clock Path Skew:        -0.448ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.614ns = ( 7.615 - 3.001 ) 
    Source Clock Delay      (SCD):    4.804ns
    Clock Pessimism Removal (CPR):    -0.258ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      2.042ns (routing 0.788ns, distribution 1.254ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.042     4.804    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/u_ddr_mc_wr_dm/dReg_reg[10]_0
    SLICE_X87Y254        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/u_ddr_mc_wr_dm/dReg_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X87Y254        FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.078     4.882 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/u_ddr_mc_wr_dm/dReg_reg[7]/Q
                         net (fo=1, routed)           1.482     6.364    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/clb2phy_wr_dq0[7]
    BITSLICE_RX_TX_X0Y247
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[7]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     5.285    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     6.130    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.154 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41415, routed)       1.672     7.826    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y8             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     7.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.104     7.300    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y38
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.117     7.417 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y38
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     7.492 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y38
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT0[26])
                                                      0.109     7.601 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT0[26]
                         net (fo=1, routed)           0.014     7.615    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT0[26]
    BITSLICE_RX_TX_X0Y247
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.258     7.357    
                         clock uncertainty           -0.170     7.187    
    BITSLICE_RX_TX_X0Y247
                         RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[7])
                                                     -0.049     7.138    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          7.138    
                         arrival time                          -6.364    
  -------------------------------------------------------------------
                         slack                                  0.774    

Slack (MET) :             0.781ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/genBit[1].u_ddr_mc_wr_bit/dReg_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[5]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[1]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.553ns  (logic 0.079ns (5.087%)  route 1.474ns (94.913%))
  Logic Levels:           0  
  Clock Path Skew:        -0.443ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.610ns = ( 7.611 - 3.001 ) 
    Source Clock Delay      (SCD):    4.795ns
    Clock Pessimism Removal (CPR):    -0.258ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      2.033ns (routing 0.788ns, distribution 1.245ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.033     4.795    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/genBit[1].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X81Y274        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/genBit[1].u_ddr_mc_wr_bit/dReg_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y274        FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.079     4.874 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/genBit[1].u_ddr_mc_wr_bit/dReg_reg[5]/Q
                         net (fo=1, routed)           1.474     6.348    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/ch0_mcal_DQOut[5]
    BITSLICE_RX_TX_X0Y229
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[5]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     5.285    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     6.130    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.154 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41415, routed)       1.672     7.826    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y8             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     7.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.097     7.293    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y35
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     7.399 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y35
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     7.474 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y35
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT2[26])
                                                      0.124     7.598 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT2[26]
                         net (fo=1, routed)           0.013     7.611    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT2[26]
    BITSLICE_RX_TX_X0Y229
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.258     7.353    
                         clock uncertainty           -0.170     7.183    
    BITSLICE_RX_TX_X0Y229
                         RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[5])
                                                     -0.054     7.129    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          7.129    
                         arrival time                          -6.348    
  -------------------------------------------------------------------
                         slack                                  0.781    

Slack (MET) :             0.793ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[0].u_ddr_mc_wr_byte/genBit[7].u_ddr_mc_wr_bit/dReg_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[7]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[1]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.582ns  (logic 0.079ns (4.994%)  route 1.503ns (95.006%))
  Logic Levels:           0  
  Clock Path Skew:        -0.436ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.628ns = ( 7.629 - 3.001 ) 
    Source Clock Delay      (SCD):    4.806ns
    Clock Pessimism Removal (CPR):    -0.258ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      2.044ns (routing 0.788ns, distribution 1.256ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.044     4.806    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[0].u_ddr_mc_wr_byte/genBit[7].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X84Y282        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[0].u_ddr_mc_wr_byte/genBit[7].u_ddr_mc_wr_bit/dReg_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X84Y282        FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.079     4.885 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[0].u_ddr_mc_wr_byte/genBit[7].u_ddr_mc_wr_bit/dReg_reg[7]/Q
                         net (fo=1, routed)           1.503     6.388    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/ch0_mcal_DQOut[7]
    BITSLICE_RX_TX_X0Y236
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[7]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      3.001     3.001 f  
    J19                                               0.000     3.001 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     5.285    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.915 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     6.130    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.154 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41415, routed)       1.672     7.826    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y8             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     7.196 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.099     7.295    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y36
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.117     7.412 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y36
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     7.487 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y36
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT2[26])
                                                      0.129     7.616 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT2[26]
                         net (fo=1, routed)           0.013     7.629    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT2[26]
    BITSLICE_RX_TX_X0Y236
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.258     7.371    
                         clock uncertainty           -0.170     7.201    
    BITSLICE_RX_TX_X0Y236
                         RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[7])
                                                     -0.020     7.181    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          7.181    
                         arrival time                          -6.388    
  -------------------------------------------------------------------
                         slack                                  0.793    

Slack (MET) :             0.794ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_upp_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[0]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[1]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.231ns  (logic 0.078ns (6.338%)  route 1.153ns (93.662%))
  Logic Levels:           0  
  Clock Path Skew:        -0.648ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.478ns = ( 7.479 - 3.001 ) 
    Source Clock Delay      (SCD):    4.806ns
    Clock Pessimism Removal (CPR):    -0.320ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      2.044ns (routing 0.788ns, distribution 1.256ns)
  Clock Net Delay (Destination): 1.672ns (routing 0.716ns, distribution 0.956ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.044     4.806    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/dReg_reg[10]
    SLICE_X94Y304        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_upp_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y304        FDRE (Prop_GFF_SLICEM_C_Q)
                                                      0.078     4.884 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_upp_reg[0]/Q
                         net (fo=8, routed)           1.153     6.037    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_t_b_upp[0]
    BITSLICE_CONTROL_X0Y33
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[0]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     5.285    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     6.130    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.154 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.672     7.826    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y8             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     7.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.102     7.298    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y33
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     7.404 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y33
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     7.479 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
                         clock pessimism             -0.320     7.159    
                         clock uncertainty           -0.170     6.989    
    BITSLICE_CONTROL_X0Y33
                         BITSLICE_CONTROL (Setup_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TBYTE_IN[0])
                                                     -0.158     6.831    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                          6.831    
                         arrival time                          -6.037    
  -------------------------------------------------------------------
                         slack                                  0.794    

Slack (MET) :             0.795ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_low_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[1]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[1]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.333ns  (logic 0.079ns (5.927%)  route 1.254ns (94.073%))
  Logic Levels:           0  
  Clock Path Skew:        -0.559ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.486ns = ( 7.487 - 3.001 ) 
    Source Clock Delay      (SCD):    4.787ns
    Clock Pessimism Removal (CPR):    -0.258ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      2.025ns (routing 0.788ns, distribution 1.237ns)
  Clock Net Delay (Destination): 1.672ns (routing 0.716ns, distribution 0.956ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.025     4.787    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/dReg_reg[10]
    SLICE_X81Y287        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_low_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y287        FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.079     4.866 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_low_reg[1]/Q
                         net (fo=8, routed)           1.254     6.120    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_t_b_low[1]
    BITSLICE_CONTROL_X0Y36
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[1]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      3.001     3.001 f  
    J19                                               0.000     3.001 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     5.285    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.915 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     6.130    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.154 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.672     7.826    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y8             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     7.196 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.099     7.295    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y36
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.117     7.412 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y36
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     7.487 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
                         clock pessimism             -0.258     7.229    
                         clock uncertainty           -0.170     7.059    
    BITSLICE_CONTROL_X0Y36
                         BITSLICE_CONTROL (Setup_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TBYTE_IN[1])
                                                     -0.144     6.915    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                          6.915    
                         arrival time                          -6.120    
  -------------------------------------------------------------------
                         slack                                  0.795    

Slack (MET) :             0.806ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[0].u_ddr_mc_wr_byte/genBit[2].u_ddr_mc_wr_bit/dReg_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[3]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[1]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.626ns  (logic 0.079ns (4.859%)  route 1.547ns (95.141%))
  Logic Levels:           0  
  Clock Path Skew:        -0.387ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.632ns = ( 7.633 - 3.001 ) 
    Source Clock Delay      (SCD):    4.762ns
    Clock Pessimism Removal (CPR):    -0.258ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      2.000ns (routing 0.788ns, distribution 1.212ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.000     4.762    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[0].u_ddr_mc_wr_byte/genBit[2].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X85Y271        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[0].u_ddr_mc_wr_byte/genBit[2].u_ddr_mc_wr_bit/dReg_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y271        FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.079     4.841 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[0].u_ddr_mc_wr_byte/genBit[2].u_ddr_mc_wr_bit/dReg_reg[3]/Q
                         net (fo=1, routed)           1.547     6.388    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/ch0_mcal_DQOut[3]
    BITSLICE_RX_TX_X0Y239
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[3]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      3.001     3.001 f  
    J19                                               0.000     3.001 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     5.285    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.915 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     6.130    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.154 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41415, routed)       1.672     7.826    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y8             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     7.196 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.099     7.295    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y36
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.117     7.412 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y36
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     7.487 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y36
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT5[26])
                                                      0.131     7.618 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT5[26]
                         net (fo=1, routed)           0.015     7.633    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT5[26]
    BITSLICE_RX_TX_X0Y239
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.258     7.375    
                         clock uncertainty           -0.170     7.205    
    BITSLICE_RX_TX_X0Y239
                         RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[3])
                                                     -0.011     7.194    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          7.194    
                         arrival time                          -6.388    
  -------------------------------------------------------------------
                         slack                                  0.806    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.536ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[1].u_ddr_mc_rd_en_low/rdEn_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[0]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[1]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.285ns  (logic 0.059ns (20.702%)  route 0.226ns (79.298%))
  Logic Levels:           0  
  Clock Path Skew:        -0.688ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.023ns
    Source Clock Delay      (SCD):    4.968ns
    Clock Pessimism Removal (CPR):    -0.258ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.815ns (routing 0.716ns, distribution 1.099ns)
  Clock Net Delay (Destination): 1.859ns (routing 0.788ns, distribution 1.071ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.129    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.815     4.968    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[1].u_ddr_mc_rd_en_low/rsMask_reg[7][9]_0
    SLICE_X81Y286        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[1].u_ddr_mc_rd_en_low/rdEn_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y286        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.059     5.027 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[1].u_ddr_mc_rd_en_low/rdEn_reg[0]/Q
                         net (fo=1, routed)           0.226     5.253    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_rden_low[0]
    BITSLICE_CONTROL_X0Y38
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[0]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      0.000     0.000 f  
    J19                                               0.000     0.000 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.859     4.621    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y8             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.563 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.148     3.711    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y38
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_RX_DIV2_CLK_Q)
                                                      0.193     3.904 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y38
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_RX_DIV2_CLK_Q_RX_DIV4_CLK_Q)
                                                      0.119     4.023 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q
                         clock pessimism              0.258     4.281    
                         clock uncertainty            0.170     4.451    
    BITSLICE_CONTROL_X0Y38
                         BITSLICE_CONTROL (Hold_CONTROL_BITSLICE_CONTROL_RX_DIV4_CLK_Q_PHY_RDEN[0])
                                                      0.267     4.718    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                         -4.718    
                         arrival time                           5.253    
  -------------------------------------------------------------------
                         slack                                  0.536    

Slack (MET) :             0.561ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[3].u_ddr_mc_wr_byte/genBit[7].u_ddr_mc_wr_bit/dReg_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[5]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[1]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.403ns  (logic 0.057ns (14.144%)  route 0.346ns (85.856%))
  Logic Levels:           0  
  Clock Path Skew:        -0.401ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.201ns
    Source Clock Delay      (SCD):    4.926ns
    Clock Pessimism Removal (CPR):    -0.324ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.773ns (routing 0.716ns, distribution 1.057ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.129    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.773     4.926    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[3].u_ddr_mc_wr_byte/genBit[7].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X82Y238        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[3].u_ddr_mc_wr_byte/genBit[7].u_ddr_mc_wr_bit/dReg_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y238        FDRE (Prop_FFF_SLICEM_C_Q)
                                                      0.057     4.983 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[3].u_ddr_mc_wr_byte/genBit[7].u_ddr_mc_wr_bit/dReg_reg[5]/Q
                         net (fo=1, routed)           0.346     5.329    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/ch0_mcal_DQOut[5]
    BITSLICE_RX_TX_X0Y210
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[5]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      0.000     0.000 f  
    J19                                               0.000     0.000 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41415, routed)       1.859     4.621    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y8             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.563 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.147     3.710    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y32
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     3.887 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y32
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.996 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y32
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT2[26])
                                                      0.187     4.183 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT2[26]
                         net (fo=1, routed)           0.018     4.201    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT2[26]
    BITSLICE_RX_TX_X0Y210
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.324     4.525    
                         clock uncertainty            0.170     4.695    
    BITSLICE_RX_TX_X0Y210
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[5])
                                                      0.072     4.767    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.767    
                         arrival time                           5.329    
  -------------------------------------------------------------------
                         slack                                  0.561    

Slack (MET) :             0.590ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[1].u_ddr_mc_rd_en_low/rdEn_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[3]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[1]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.339ns  (logic 0.059ns (17.404%)  route 0.280ns (82.596%))
  Logic Levels:           0  
  Clock Path Skew:        -0.689ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.023ns
    Source Clock Delay      (SCD):    4.969ns
    Clock Pessimism Removal (CPR):    -0.258ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.816ns (routing 0.716ns, distribution 1.100ns)
  Clock Net Delay (Destination): 1.859ns (routing 0.788ns, distribution 1.071ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.129    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.816     4.969    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[1].u_ddr_mc_rd_en_low/rsMask_reg[7][9]_0
    SLICE_X84Y291        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[1].u_ddr_mc_rd_en_low/rdEn_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X84Y291        FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.059     5.028 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[1].u_ddr_mc_rd_en_low/rdEn_reg[3]/Q
                         net (fo=1, routed)           0.280     5.308    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_rden_low[3]
    BITSLICE_CONTROL_X0Y38
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[3]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      0.000     0.000 f  
    J19                                               0.000     0.000 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.859     4.621    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y8             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.563 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.148     3.711    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y38
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_RX_DIV2_CLK_Q)
                                                      0.193     3.904 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y38
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_RX_DIV2_CLK_Q_RX_DIV4_CLK_Q)
                                                      0.119     4.023 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q
                         clock pessimism              0.258     4.281    
                         clock uncertainty            0.170     4.451    
    BITSLICE_CONTROL_X0Y38
                         BITSLICE_CONTROL (Hold_CONTROL_BITSLICE_CONTROL_RX_DIV4_CLK_Q_PHY_RDEN[3])
                                                      0.268     4.719    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                         -4.719    
                         arrival time                           5.308    
  -------------------------------------------------------------------
                         slack                                  0.590    

Slack (MET) :             0.593ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[0].u_ddr_mc_rd_en_low/rdEn_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[3]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[1]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.336ns  (logic 0.058ns (17.262%)  route 0.278ns (82.738%))
  Logic Levels:           0  
  Clock Path Skew:        -0.695ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.016ns
    Source Clock Delay      (SCD):    4.969ns
    Clock Pessimism Removal (CPR):    -0.258ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.816ns (routing 0.716ns, distribution 1.100ns)
  Clock Net Delay (Destination): 1.859ns (routing 0.788ns, distribution 1.071ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.129    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.816     4.969    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[0].u_ddr_mc_rd_en_low/rsMask_reg[7][9]_0
    SLICE_X83Y281        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[0].u_ddr_mc_rd_en_low/rdEn_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y281        FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.058     5.027 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[0].u_ddr_mc_rd_en_low/rdEn_reg[3]/Q
                         net (fo=1, routed)           0.278     5.305    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_rden_low[3]
    BITSLICE_CONTROL_X0Y36
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[3]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      0.000     0.000 f  
    J19                                               0.000     0.000 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.859     4.621    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y8             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.563 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.141     3.704    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y36
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_RX_DIV2_CLK_Q)
                                                      0.193     3.897 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y36
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_RX_DIV2_CLK_Q_RX_DIV4_CLK_Q)
                                                      0.119     4.016 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q
                         clock pessimism              0.258     4.274    
                         clock uncertainty            0.170     4.444    
    BITSLICE_CONTROL_X0Y36
                         BITSLICE_CONTROL (Hold_CONTROL_BITSLICE_CONTROL_RX_DIV4_CLK_Q_PHY_RDEN[3])
                                                      0.268     4.712    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                         -4.712    
                         arrival time                           5.305    
  -------------------------------------------------------------------
                         slack                                  0.593    

Slack (MET) :             0.596ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[3].u_ddr_mc_wr_byte/genBit[7].u_ddr_mc_wr_bit/dReg_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[1]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[1]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.410ns  (logic 0.058ns (14.146%)  route 0.352ns (85.854%))
  Logic Levels:           0  
  Clock Path Skew:        -0.402ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.201ns
    Source Clock Delay      (SCD):    4.927ns
    Clock Pessimism Removal (CPR):    -0.324ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.774ns (routing 0.716ns, distribution 1.058ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.129    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.774     4.927    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[3].u_ddr_mc_wr_byte/genBit[7].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X82Y238        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[3].u_ddr_mc_wr_byte/genBit[7].u_ddr_mc_wr_bit/dReg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y238        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.058     4.985 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[3].u_ddr_mc_wr_byte/genBit[7].u_ddr_mc_wr_bit/dReg_reg[1]/Q
                         net (fo=1, routed)           0.352     5.337    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/ch0_mcal_DQOut[1]
    BITSLICE_RX_TX_X0Y210
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[1]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      0.000     0.000 f  
    J19                                               0.000     0.000 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41415, routed)       1.859     4.621    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y8             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.563 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.147     3.710    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y32
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     3.887 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y32
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.996 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y32
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT2[26])
                                                      0.187     4.183 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT2[26]
                         net (fo=1, routed)           0.018     4.201    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT2[26]
    BITSLICE_RX_TX_X0Y210
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.324     4.525    
                         clock uncertainty            0.170     4.695    
    BITSLICE_RX_TX_X0Y210
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[1])
                                                      0.045     4.740    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.740    
                         arrival time                           5.337    
  -------------------------------------------------------------------
                         slack                                  0.596    

Slack (MET) :             0.608ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/genBit[7].u_ddr_mc_wr_bit/dReg_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[6]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[1]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.318ns  (logic 0.058ns (18.239%)  route 0.260ns (81.761%))
  Logic Levels:           0  
  Clock Path Skew:        -0.533ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.163ns
    Source Clock Delay      (SCD):    4.954ns
    Clock Pessimism Removal (CPR):    -0.258ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.801ns (routing 0.716ns, distribution 1.085ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.129    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.801     4.954    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/genBit[7].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X82Y267        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/genBit[7].u_ddr_mc_wr_bit/dReg_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y267        FDRE (Prop_GFF_SLICEM_C_Q)
                                                      0.058     5.012 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/genBit[7].u_ddr_mc_wr_bit/dReg_reg[6]/Q
                         net (fo=1, routed)           0.260     5.272    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/ch0_mcal_DQOut[6]
    BITSLICE_RX_TX_X0Y231
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[6]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41415, routed)       1.859     4.621    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y8             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.563 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.138     3.701    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y35
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.151     3.852 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y35
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.961 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y35
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT4[26])
                                                      0.180     4.141 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT4[26]
                         net (fo=1, routed)           0.022     4.163    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT4[26]
    BITSLICE_RX_TX_X0Y231
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.258     4.421    
                         clock uncertainty            0.170     4.591    
    BITSLICE_RX_TX_X0Y231
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[6])
                                                      0.073     4.664    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.664    
                         arrival time                           5.272    
  -------------------------------------------------------------------
                         slack                                  0.608    

Slack (MET) :             0.617ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/genBit[3].u_ddr_mc_wr_bit/dReg_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[6]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[1]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.320ns  (logic 0.058ns (18.125%)  route 0.262ns (81.875%))
  Logic Levels:           0  
  Clock Path Skew:        -0.531ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.179ns
    Source Clock Delay      (SCD):    4.968ns
    Clock Pessimism Removal (CPR):    -0.258ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.815ns (routing 0.716ns, distribution 1.099ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.129    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.815     4.968    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/genBit[3].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X81Y297        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/genBit[3].u_ddr_mc_wr_bit/dReg_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y297        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.058     5.026 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/genBit[3].u_ddr_mc_wr_bit/dReg_reg[6]/Q
                         net (fo=1, routed)           0.262     5.288    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/ch0_mcal_DQOut[6]
    BITSLICE_RX_TX_X0Y258
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[6]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      0.000     0.000 f  
    J19                                               0.000     0.000 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41415, routed)       1.859     4.621    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y8             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.563 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.150     3.713    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y39
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.151     3.864 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y39
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.973 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y39
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT5[26])
                                                      0.182     4.155 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT5[26]
                         net (fo=1, routed)           0.024     4.179    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT5[26]
    BITSLICE_RX_TX_X0Y258
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.258     4.437    
                         clock uncertainty            0.170     4.607    
    BITSLICE_RX_TX_X0Y258
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[6])
                                                      0.064     4.671    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.671    
                         arrival time                           5.288    
  -------------------------------------------------------------------
                         slack                                  0.617    

Slack (MET) :             0.617ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[3].u_ddr_mc_wr_byte/u_ddr_mc_wr_dm/dReg_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[5]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[1]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.472ns  (logic 0.058ns (12.288%)  route 0.414ns (87.712%))
  Logic Levels:           0  
  Clock Path Skew:        -0.382ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.201ns
    Source Clock Delay      (SCD):    4.907ns
    Clock Pessimism Removal (CPR):    -0.324ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.754ns (routing 0.716ns, distribution 1.038ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.129    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.754     4.907    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[3].u_ddr_mc_wr_byte/u_ddr_mc_wr_dm/dReg_reg[10]_0
    SLICE_X89Y239        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[3].u_ddr_mc_wr_byte/u_ddr_mc_wr_dm/dReg_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y239        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.058     4.965 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[3].u_ddr_mc_wr_byte/u_ddr_mc_wr_dm/dReg_reg[5]/Q
                         net (fo=1, routed)           0.414     5.379    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/clb2phy_wr_dq0[5]
    BITSLICE_RX_TX_X0Y208
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[5]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      0.000     0.000 f  
    J19                                               0.000     0.000 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41415, routed)       1.859     4.621    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y8             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.563 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.147     3.710    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y32
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     3.887 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y32
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.996 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y32
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT0[26])
                                                      0.162     4.158 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT0[26]
                         net (fo=1, routed)           0.043     4.201    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT0[26]
    BITSLICE_RX_TX_X0Y208
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.324     4.525    
                         clock uncertainty            0.170     4.695    
    BITSLICE_RX_TX_X0Y208
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[5])
                                                      0.066     4.761    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.761    
                         arrival time                           5.379    
  -------------------------------------------------------------------
                         slack                                  0.617    

Slack (MET) :             0.623ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/genBit[0].u_ddr_mc_wr_bit/dReg_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[7]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[1]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.337ns  (logic 0.058ns (17.211%)  route 0.279ns (82.789%))
  Logic Levels:           0  
  Clock Path Skew:        -0.500ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.213ns
    Source Clock Delay      (SCD):    4.970ns
    Clock Pessimism Removal (CPR):    -0.258ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.817ns (routing 0.716ns, distribution 1.101ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.129    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.817     4.970    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/genBit[0].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X81Y290        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/genBit[0].u_ddr_mc_wr_bit/dReg_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y290        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.058     5.028 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/genBit[0].u_ddr_mc_wr_bit/dReg_reg[7]/Q
                         net (fo=1, routed)           0.279     5.307    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/ch0_mcal_DQOut[7]
    BITSLICE_RX_TX_X0Y252
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[7]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41415, routed)       1.859     4.621    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y8             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.563 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.148     3.711    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y38
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     3.888 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y38
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.997 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y38
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT5[26])
                                                      0.192     4.189 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT5[26]
                         net (fo=1, routed)           0.024     4.213    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT5[26]
    BITSLICE_RX_TX_X0Y252
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.258     4.471    
                         clock uncertainty            0.170     4.641    
    BITSLICE_RX_TX_X0Y252
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[7])
                                                      0.044     4.685    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.685    
                         arrival time                           5.307    
  -------------------------------------------------------------------
                         slack                                  0.623    

Slack (MET) :             0.624ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/genBit[7].u_ddr_mc_wr_bit/dReg_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[3]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[1]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.345ns  (logic 0.057ns (16.522%)  route 0.288ns (83.478%))
  Logic Levels:           0  
  Clock Path Skew:        -0.502ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.205ns
    Source Clock Delay      (SCD):    4.965ns
    Clock Pessimism Removal (CPR):    -0.258ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.812ns (routing 0.716ns, distribution 1.096ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.129    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.812     4.965    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/genBit[7].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X82Y287        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/genBit[7].u_ddr_mc_wr_bit/dReg_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y287        FDRE (Prop_FFF_SLICEM_C_Q)
                                                      0.057     5.022 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/genBit[7].u_ddr_mc_wr_bit/dReg_reg[3]/Q
                         net (fo=1, routed)           0.288     5.310    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/ch0_mcal_DQOut[3]
    BITSLICE_RX_TX_X0Y250
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[3]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41415, routed)       1.859     4.621    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y8             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.563 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.148     3.711    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y38
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     3.888 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y38
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.997 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y38
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT3[26])
                                                      0.187     4.184 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT3[26]
                         net (fo=1, routed)           0.021     4.205    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT3[26]
    BITSLICE_RX_TX_X0Y250
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.258     4.463    
                         clock uncertainty            0.170     4.633    
    BITSLICE_RX_TX_X0Y250
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[3])
                                                      0.053     4.686    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.686    
                         arrival time                           5.310    
  -------------------------------------------------------------------
                         slack                                  0.624    





---------------------------------------------------------------------------------------------------
From Clock:  mmcm_clkout0
  To Clock:  pll_clk[2]_DIV

Setup :            0  Failing Endpoints,  Worst Slack        0.688ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.569ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.688ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2phy_t_b_addr_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[3]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[2]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.446ns  (logic 0.079ns (5.463%)  route 1.367ns (94.537%))
  Logic Levels:           0  
  Clock Path Skew:        -0.604ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.483ns = ( 7.484 - 3.001 ) 
    Source Clock Delay      (SCD):    4.834ns
    Clock Pessimism Removal (CPR):    -0.253ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      2.072ns (routing 0.788ns, distribution 1.284ns)
  Clock Net Delay (Destination): 1.688ns (routing 0.716ns, distribution 0.972ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.072     4.834    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/div_clk
    SLICE_X81Y356        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2phy_t_b_addr_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y356        FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.079     4.913 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2phy_t_b_addr_reg[3]/Q
                         net (fo=6, routed)           1.367     6.280    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/clb2phy_t_b_low[3]
    BITSLICE_CONTROL_X0Y43
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[3]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     5.285    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     6.130    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.154 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.688     7.842    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y11            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     7.212 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.091     7.303    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y43
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     7.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y43
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     7.484 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
                         clock pessimism             -0.253     7.231    
                         clock uncertainty           -0.170     7.061    
    BITSLICE_CONTROL_X0Y43
                         BITSLICE_CONTROL (Setup_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TBYTE_IN[3])
                                                     -0.093     6.968    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                          6.968    
                         arrival time                          -6.280    
  -------------------------------------------------------------------
                         slack                                  0.688    

Slack (MET) :             0.694ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2phy_t_b_addr_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[3]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[2]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.391ns  (logic 0.079ns (5.679%)  route 1.312ns (94.321%))
  Logic Levels:           0  
  Clock Path Skew:        -0.590ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.497ns = ( 7.498 - 3.001 ) 
    Source Clock Delay      (SCD):    4.834ns
    Clock Pessimism Removal (CPR):    -0.253ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      2.072ns (routing 0.788ns, distribution 1.284ns)
  Clock Net Delay (Destination): 1.688ns (routing 0.716ns, distribution 0.972ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.072     4.834    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/div_clk
    SLICE_X81Y356        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2phy_t_b_addr_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y356        FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.079     4.913 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2phy_t_b_addr_reg[3]/Q
                         net (fo=6, routed)           1.312     6.225    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/clb2phy_t_b_low[3]
    BITSLICE_CONTROL_X0Y42
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[3]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     5.285    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     6.130    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.154 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.688     7.842    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y11            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     7.212 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.094     7.306    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y42
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.117     7.423 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y42
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     7.498 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
                         clock pessimism             -0.253     7.245    
                         clock uncertainty           -0.170     7.075    
    BITSLICE_CONTROL_X0Y42
                         BITSLICE_CONTROL (Setup_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TBYTE_IN[3])
                                                     -0.156     6.919    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                          6.919    
                         arrival time                          -6.225    
  -------------------------------------------------------------------
                         slack                                  0.694    

Slack (MET) :             0.742ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ACT_n_dly_reg[0][6]/C
                            (rising edge-triggered cell FDSE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[6]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[2]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.598ns  (logic 0.080ns (5.006%)  route 1.518ns (94.994%))
  Logic Levels:           0  
  Clock Path Skew:        -0.439ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.641ns = ( 7.642 - 3.001 ) 
    Source Clock Delay      (SCD):    4.827ns
    Clock Pessimism Removal (CPR):    -0.253ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      2.065ns (routing 0.788ns, distribution 1.277ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.065     4.827    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X84Y321        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ACT_n_dly_reg[0][6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X84Y321        FDSE (Prop_CFF2_SLICEL_C_Q)
                                                      0.080     4.907 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ACT_n_dly_reg[0][6]/Q
                         net (fo=1, routed)           1.518     6.425    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/mcal_ACT_n[6]
    BITSLICE_RX_TX_X0Y302
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[6]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      3.001     3.001 f  
    J19                                               0.000     3.001 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     5.285    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.915 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     6.130    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.154 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41415, routed)       1.688     7.842    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y11            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     7.212 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.098     7.310    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y46
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.117     7.427 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y46
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     7.502 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y46
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT3[26])
                                                      0.128     7.630 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT3[26]
                         net (fo=1, routed)           0.012     7.642    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT3[26]
    BITSLICE_RX_TX_X0Y302
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.253     7.389    
                         clock uncertainty           -0.170     7.219    
    BITSLICE_RX_TX_X0Y302
                         RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[6])
                                                     -0.052     7.167    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          7.167    
                         arrival time                          -6.425    
  -------------------------------------------------------------------
                         slack                                  0.742    

Slack (MET) :             0.746ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_BA_dly_reg[0][15]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[7]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[2]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.617ns  (logic 0.078ns (4.824%)  route 1.539ns (95.176%))
  Logic Levels:           0  
  Clock Path Skew:        -0.417ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.623ns = ( 7.624 - 3.001 ) 
    Source Clock Delay      (SCD):    4.787ns
    Clock Pessimism Removal (CPR):    -0.253ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      2.025ns (routing 0.788ns, distribution 1.237ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.025     4.787    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X90Y321        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_BA_dly_reg[0][15]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X90Y321        FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.078     4.865 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_BA_dly_reg[0][15]/Q
                         net (fo=1, routed)           1.539     6.404    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/clb2phy_wr_dq6[7]
    BITSLICE_RX_TX_X0Y279
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[7]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     5.285    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     6.130    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.154 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41415, routed)       1.688     7.842    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y11            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     7.212 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.091     7.303    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y43
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     7.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y43
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     7.484 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y43
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT0[26])
                                                      0.126     7.610 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT0[26]
                         net (fo=1, routed)           0.014     7.624    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT0[26]
    BITSLICE_RX_TX_X0Y279
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.253     7.371    
                         clock uncertainty           -0.170     7.201    
    BITSLICE_RX_TX_X0Y279
                         RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[7])
                                                     -0.051     7.150    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          7.150    
                         arrival time                          -6.404    
  -------------------------------------------------------------------
                         slack                                  0.746    

Slack (MET) :             0.798ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_CS_n_dly_reg[0][2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[2]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[2]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.594ns  (logic 0.078ns (4.893%)  route 1.516ns (95.107%))
  Logic Levels:           0  
  Clock Path Skew:        -0.418ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.628ns = ( 7.629 - 3.001 ) 
    Source Clock Delay      (SCD):    4.793ns
    Clock Pessimism Removal (CPR):    -0.253ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      2.031ns (routing 0.788ns, distribution 1.243ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.031     4.793    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X86Y327        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_CS_n_dly_reg[0][2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X86Y327        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     4.871 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_CS_n_dly_reg[0][2]/Q
                         net (fo=1, routed)           1.516     6.387    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/mcal_CS_n[2]
    BITSLICE_RX_TX_X0Y307
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[2]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     5.285    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     6.130    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.154 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41415, routed)       1.688     7.842    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y11            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     7.212 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.099     7.311    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y47
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     7.417 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y47
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     7.492 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y47
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT2[26])
                                                      0.124     7.616 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT2[26]
                         net (fo=1, routed)           0.013     7.629    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT2[26]
    BITSLICE_RX_TX_X0Y307
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.253     7.376    
                         clock uncertainty           -0.170     7.206    
    BITSLICE_RX_TX_X0Y307
                         RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[2])
                                                     -0.021     7.185    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          7.185    
                         arrival time                          -6.387    
  -------------------------------------------------------------------
                         slack                                  0.798    

Slack (MET) :             0.821ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][118]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[6]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[2]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.547ns  (logic 0.078ns (5.042%)  route 1.469ns (94.958%))
  Logic Levels:           0  
  Clock Path Skew:        -0.413ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.631ns = ( 7.632 - 3.001 ) 
    Source Clock Delay      (SCD):    4.791ns
    Clock Pessimism Removal (CPR):    -0.253ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      2.029ns (routing 0.788ns, distribution 1.241ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.029     4.791    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X82Y332        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][118]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y332        FDRE (Prop_CFF_SLICEM_C_Q)
                                                      0.078     4.869 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][118]/Q
                         net (fo=1, routed)           1.469     6.338    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/mcal_ADR[6]
    BITSLICE_RX_TX_X0Y306
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[6]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     5.285    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     6.130    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.154 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41415, routed)       1.688     7.842    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y11            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     7.212 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.099     7.311    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y47
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     7.417 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y47
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     7.492 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y47
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT1[26])
                                                      0.125     7.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT1[26]
                         net (fo=1, routed)           0.015     7.632    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT1[26]
    BITSLICE_RX_TX_X0Y306
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.253     7.379    
                         clock uncertainty           -0.170     7.209    
    BITSLICE_RX_TX_X0Y306
                         RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[6])
                                                     -0.050     7.159    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          7.159    
                         arrival time                          -6.338    
  -------------------------------------------------------------------
                         slack                                  0.821    

Slack (MET) :             0.853ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2phy_t_b_addr_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[3]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[2]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.231ns  (logic 0.079ns (6.417%)  route 1.152ns (93.583%))
  Logic Levels:           0  
  Clock Path Skew:        -0.591ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.496ns = ( 7.497 - 3.001 ) 
    Source Clock Delay      (SCD):    4.834ns
    Clock Pessimism Removal (CPR):    -0.253ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      2.072ns (routing 0.788ns, distribution 1.284ns)
  Clock Net Delay (Destination): 1.688ns (routing 0.716ns, distribution 0.972ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.072     4.834    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/div_clk
    SLICE_X81Y356        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2phy_t_b_addr_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y356        FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.079     4.913 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2phy_t_b_addr_reg[3]/Q
                         net (fo=6, routed)           1.152     6.065    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/clb2phy_t_b_low[3]
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[3]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     5.285    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     6.130    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.154 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.688     7.842    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y11            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     7.212 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.093     7.305    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.117     7.422 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     7.497 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
                         clock pessimism             -0.253     7.244    
                         clock uncertainty           -0.170     7.074    
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Setup_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TBYTE_IN[3])
                                                     -0.156     6.918    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                          6.918    
                         arrival time                          -6.065    
  -------------------------------------------------------------------
                         slack                                  0.853    

Slack (MET) :             0.871ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][39]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[7]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[2]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.498ns  (logic 0.080ns (5.340%)  route 1.418ns (94.660%))
  Logic Levels:           0  
  Clock Path Skew:        -0.456ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.622ns = ( 7.623 - 3.001 ) 
    Source Clock Delay      (SCD):    4.825ns
    Clock Pessimism Removal (CPR):    -0.253ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      2.063ns (routing 0.788ns, distribution 1.275ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.063     4.825    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X81Y341        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][39]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y341        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.080     4.905 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][39]/Q
                         net (fo=1, routed)           1.418     6.323    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/mcal_ADR[7]
    BITSLICE_RX_TX_X0Y295
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[7]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     5.285    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     6.130    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.154 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41415, routed)       1.688     7.842    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y11            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     7.212 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.096     7.308    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y45
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     7.414 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y45
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     7.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y45
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT3[26])
                                                      0.122     7.611 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT3[26]
                         net (fo=1, routed)           0.012     7.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT3[26]
    BITSLICE_RX_TX_X0Y295
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.253     7.370    
                         clock uncertainty           -0.170     7.200    
    BITSLICE_RX_TX_X0Y295
                         RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[7])
                                                     -0.006     7.194    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          7.194    
                         arrival time                          -6.323    
  -------------------------------------------------------------------
                         slack                                  0.871    

Slack (MET) :             0.879ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ACT_n_dly_reg[0][7]/C
                            (rising edge-triggered cell FDSE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[7]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[2]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.440ns  (logic 0.079ns (5.486%)  route 1.361ns (94.514%))
  Logic Levels:           0  
  Clock Path Skew:        -0.458ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.641ns = ( 7.642 - 3.001 ) 
    Source Clock Delay      (SCD):    4.788ns
    Clock Pessimism Removal (CPR):    -0.311ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      2.026ns (routing 0.788ns, distribution 1.238ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.026     4.788    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X88Y250        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ACT_n_dly_reg[0][7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y250        FDSE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     4.867 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ACT_n_dly_reg[0][7]/Q
                         net (fo=1, routed)           1.361     6.228    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/mcal_ACT_n[7]
    BITSLICE_RX_TX_X0Y302
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[7]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      3.001     3.001 f  
    J19                                               0.000     3.001 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     5.285    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.915 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     6.130    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.154 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41415, routed)       1.688     7.842    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y11            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     7.212 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.098     7.310    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y46
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.117     7.427 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y46
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     7.502 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y46
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT3[26])
                                                      0.128     7.630 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT3[26]
                         net (fo=1, routed)           0.012     7.642    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT3[26]
    BITSLICE_RX_TX_X0Y302
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.311     7.330    
                         clock uncertainty           -0.170     7.160    
    BITSLICE_RX_TX_X0Y302
                         RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[7])
                                                     -0.053     7.107    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          7.107    
                         arrival time                          -6.228    
  -------------------------------------------------------------------
                         slack                                  0.879    

Slack (MET) :             0.891ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2phy_t_b_addr_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[3]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[2]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.248ns  (logic 0.079ns (6.332%)  route 1.169ns (93.668%))
  Logic Levels:           0  
  Clock Path Skew:        -0.599ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.488ns = ( 7.489 - 3.001 ) 
    Source Clock Delay      (SCD):    4.834ns
    Clock Pessimism Removal (CPR):    -0.253ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      2.072ns (routing 0.788ns, distribution 1.284ns)
  Clock Net Delay (Destination): 1.688ns (routing 0.716ns, distribution 0.972ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.072     4.834    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/div_clk
    SLICE_X81Y356        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2phy_t_b_addr_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y356        FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.079     4.913 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2phy_t_b_addr_reg[3]/Q
                         net (fo=6, routed)           1.169     6.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/clb2phy_t_b_low[3]
    BITSLICE_CONTROL_X0Y45
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[3]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     5.285    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     6.130    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.154 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.688     7.842    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y11            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     7.212 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.096     7.308    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y45
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     7.414 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y45
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     7.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
                         clock pessimism             -0.253     7.236    
                         clock uncertainty           -0.170     7.066    
    BITSLICE_CONTROL_X0Y45
                         BITSLICE_CONTROL (Setup_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TBYTE_IN[3])
                                                     -0.093     6.973    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                          6.973    
                         arrival time                          -6.081    
  -------------------------------------------------------------------
                         slack                                  0.891    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.569ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][62]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[6]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[2]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.310ns  (logic 0.060ns (19.335%)  route 0.250ns (80.665%))
  Logic Levels:           0  
  Clock Path Skew:        -0.514ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.206ns
    Source Clock Delay      (SCD):    4.973ns
    Clock Pessimism Removal (CPR):    -0.253ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.820ns (routing 0.716ns, distribution 1.104ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.129    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.820     4.973    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X81Y338        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][62]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y338        FDRE (Prop_BFF2_SLICEL_C_Q)
                                                      0.060     5.033 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][62]/Q
                         net (fo=2, routed)           0.250     5.283    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/clb2phy_wr_dq6[6]
    BITSLICE_RX_TX_X0Y292
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[6]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41415, routed)       1.880     4.642    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y11            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.584 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.137     3.721    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y45
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.151     3.872 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y45
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.981 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y45
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT0[26])
                                                      0.182     4.163 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT0[26]
                         net (fo=1, routed)           0.043     4.206    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT0[26]
    BITSLICE_RX_TX_X0Y292
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.253     4.459    
                         clock uncertainty            0.170     4.629    
    BITSLICE_RX_TX_X0Y292
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[6])
                                                      0.085     4.714    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.714    
                         arrival time                           5.283    
  -------------------------------------------------------------------
                         slack                                  0.569    

Slack (MET) :             0.586ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][60]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[3]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[2]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.304ns  (logic 0.059ns (19.381%)  route 0.245ns (80.619%))
  Logic Levels:           0  
  Clock Path Skew:        -0.514ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.206ns
    Source Clock Delay      (SCD):    4.973ns
    Clock Pessimism Removal (CPR):    -0.253ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.820ns (routing 0.716ns, distribution 1.104ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.129    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.820     4.973    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X81Y338        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][60]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y338        FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.059     5.032 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][60]/Q
                         net (fo=2, routed)           0.245     5.277    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/clb2phy_wr_dq6[3]
    BITSLICE_RX_TX_X0Y292
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[3]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41415, routed)       1.880     4.642    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y11            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.584 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.137     3.721    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y45
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.151     3.872 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y45
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.981 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y45
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT0[26])
                                                      0.182     4.163 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT0[26]
                         net (fo=1, routed)           0.043     4.206    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT0[26]
    BITSLICE_RX_TX_X0Y292
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.253     4.459    
                         clock uncertainty            0.170     4.629    
    BITSLICE_RX_TX_X0Y292
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[3])
                                                      0.062     4.691    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.691    
                         arrival time                           5.277    
  -------------------------------------------------------------------
                         slack                                  0.586    

Slack (MET) :             0.590ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][62]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[5]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[2]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.315ns  (logic 0.060ns (19.029%)  route 0.255ns (80.971%))
  Logic Levels:           0  
  Clock Path Skew:        -0.514ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.206ns
    Source Clock Delay      (SCD):    4.973ns
    Clock Pessimism Removal (CPR):    -0.253ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.820ns (routing 0.716ns, distribution 1.104ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.129    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.820     4.973    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X81Y338        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][62]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y338        FDRE (Prop_BFF2_SLICEL_C_Q)
                                                      0.060     5.033 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][62]/Q
                         net (fo=2, routed)           0.255     5.288    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/clb2phy_wr_dq6[5]
    BITSLICE_RX_TX_X0Y292
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[5]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41415, routed)       1.880     4.642    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y11            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.584 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.137     3.721    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y45
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.151     3.872 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y45
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.981 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y45
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT0[26])
                                                      0.182     4.163 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT0[26]
                         net (fo=1, routed)           0.043     4.206    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT0[26]
    BITSLICE_RX_TX_X0Y292
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.253     4.459    
                         clock uncertainty            0.170     4.629    
    BITSLICE_RX_TX_X0Y292
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[5])
                                                      0.069     4.698    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.698    
                         arrival time                           5.288    
  -------------------------------------------------------------------
                         slack                                  0.590    

Slack (MET) :             0.593ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][95]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[7]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[2]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.318ns  (logic 0.059ns (18.553%)  route 0.259ns (81.447%))
  Logic Levels:           0  
  Clock Path Skew:        -0.511ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.207ns
    Source Clock Delay      (SCD):    4.970ns
    Clock Pessimism Removal (CPR):    -0.253ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.817ns (routing 0.716ns, distribution 1.101ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.129    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.817     4.970    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X81Y333        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][95]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y333        FDRE (Prop_CFF2_SLICEL_C_Q)
                                                      0.059     5.029 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][95]/Q
                         net (fo=1, routed)           0.259     5.288    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/mcal_ADR[7]
    BITSLICE_RX_TX_X0Y288
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[7]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41415, routed)       1.880     4.642    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y11            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.584 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.132     3.716    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     3.893 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     4.002 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT2[26])
                                                      0.187     4.189 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT2[26]
                         net (fo=1, routed)           0.018     4.207    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT2[26]
    BITSLICE_RX_TX_X0Y288
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.253     4.460    
                         clock uncertainty            0.170     4.630    
    BITSLICE_RX_TX_X0Y288
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[7])
                                                      0.066     4.696    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.696    
                         arrival time                           5.288    
  -------------------------------------------------------------------
                         slack                                  0.593    

Slack (MET) :             0.593ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][68]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[3]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[2]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.332ns  (logic 0.059ns (17.748%)  route 0.273ns (82.252%))
  Logic Levels:           0  
  Clock Path Skew:        -0.504ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.218ns
    Source Clock Delay      (SCD):    4.974ns
    Clock Pessimism Removal (CPR):    -0.253ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.821ns (routing 0.716ns, distribution 1.105ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.129    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.821     4.974    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X81Y336        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][68]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y336        FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.059     5.033 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][68]/Q
                         net (fo=2, routed)           0.273     5.307    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/mcal_ADR[3]
    BITSLICE_RX_TX_X0Y291
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[3]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41415, routed)       1.880     4.642    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y11            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.584 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.132     3.716    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     3.893 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     4.002 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT5[26])
                                                      0.192     4.194 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT5[26]
                         net (fo=1, routed)           0.024     4.218    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT5[26]
    BITSLICE_RX_TX_X0Y291
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.253     4.471    
                         clock uncertainty            0.170     4.641    
    BITSLICE_RX_TX_X0Y291
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[3])
                                                      0.073     4.714    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.714    
                         arrival time                           5.307    
  -------------------------------------------------------------------
                         slack                                  0.593    

Slack (MET) :             0.594ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][92]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[3]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[2]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.305ns  (logic 0.059ns (19.317%)  route 0.246ns (80.683%))
  Logic Levels:           0  
  Clock Path Skew:        -0.513ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.207ns
    Source Clock Delay      (SCD):    4.972ns
    Clock Pessimism Removal (CPR):    -0.253ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.819ns (routing 0.716ns, distribution 1.103ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.129    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.819     4.972    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X81Y333        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][92]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y333        FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.059     5.031 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][92]/Q
                         net (fo=2, routed)           0.246     5.278    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/mcal_ADR[3]
    BITSLICE_RX_TX_X0Y288
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[3]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41415, routed)       1.880     4.642    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y11            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.584 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.132     3.716    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     3.893 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     4.002 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT2[26])
                                                      0.187     4.189 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT2[26]
                         net (fo=1, routed)           0.018     4.207    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT2[26]
    BITSLICE_RX_TX_X0Y288
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.253     4.460    
                         clock uncertainty            0.170     4.630    
    BITSLICE_RX_TX_X0Y288
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[3])
                                                      0.054     4.684    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.684    
                         arrival time                           5.278    
  -------------------------------------------------------------------
                         slack                                  0.594    

Slack (MET) :             0.602ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][70]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[5]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[2]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.342ns  (logic 0.060ns (17.536%)  route 0.282ns (82.464%))
  Logic Levels:           0  
  Clock Path Skew:        -0.504ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.218ns
    Source Clock Delay      (SCD):    4.974ns
    Clock Pessimism Removal (CPR):    -0.253ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.821ns (routing 0.716ns, distribution 1.105ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.129    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.821     4.974    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X81Y336        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][70]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y336        FDRE (Prop_BFF2_SLICEL_C_Q)
                                                      0.060     5.034 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][70]/Q
                         net (fo=2, routed)           0.282     5.316    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/mcal_ADR[5]
    BITSLICE_RX_TX_X0Y291
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[5]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41415, routed)       1.880     4.642    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y11            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.584 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.132     3.716    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     3.893 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     4.002 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT5[26])
                                                      0.192     4.194 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT5[26]
                         net (fo=1, routed)           0.024     4.218    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT5[26]
    BITSLICE_RX_TX_X0Y291
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.253     4.471    
                         clock uncertainty            0.170     4.641    
    BITSLICE_RX_TX_X0Y291
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[5])
                                                      0.074     4.715    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.715    
                         arrival time                           5.316    
  -------------------------------------------------------------------
                         slack                                  0.602    

Slack (MET) :             0.602ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][70]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[6]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[2]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.311ns  (logic 0.060ns (19.284%)  route 0.251ns (80.716%))
  Logic Levels:           0  
  Clock Path Skew:        -0.504ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.218ns
    Source Clock Delay      (SCD):    4.974ns
    Clock Pessimism Removal (CPR):    -0.253ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.821ns (routing 0.716ns, distribution 1.105ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.129    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.821     4.974    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X81Y336        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][70]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y336        FDRE (Prop_BFF2_SLICEL_C_Q)
                                                      0.060     5.034 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][70]/Q
                         net (fo=2, routed)           0.251     5.285    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/mcal_ADR[6]
    BITSLICE_RX_TX_X0Y291
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[6]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41415, routed)       1.880     4.642    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y11            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.584 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.132     3.716    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     3.893 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     4.002 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT5[26])
                                                      0.192     4.194 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT5[26]
                         net (fo=1, routed)           0.024     4.218    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT5[26]
    BITSLICE_RX_TX_X0Y291
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.253     4.471    
                         clock uncertainty            0.170     4.641    
    BITSLICE_RX_TX_X0Y291
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[6])
                                                      0.043     4.684    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.684    
                         arrival time                           5.285    
  -------------------------------------------------------------------
                         slack                                  0.602    

Slack (MET) :             0.603ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][71]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[7]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[2]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.311ns  (logic 0.059ns (18.971%)  route 0.252ns (81.029%))
  Logic Levels:           0  
  Clock Path Skew:        -0.506ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.218ns
    Source Clock Delay      (SCD):    4.976ns
    Clock Pessimism Removal (CPR):    -0.253ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.823ns (routing 0.716ns, distribution 1.107ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.129    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.823     4.976    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X81Y336        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][71]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y336        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.059     5.035 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][71]/Q
                         net (fo=1, routed)           0.252     5.287    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/mcal_ADR[7]
    BITSLICE_RX_TX_X0Y291
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[7]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41415, routed)       1.880     4.642    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y11            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.584 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.132     3.716    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     3.893 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     4.002 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT5[26])
                                                      0.192     4.194 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT5[26]
                         net (fo=1, routed)           0.024     4.218    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT5[26]
    BITSLICE_RX_TX_X0Y291
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.253     4.471    
                         clock uncertainty            0.170     4.641    
    BITSLICE_RX_TX_X0Y291
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[7])
                                                      0.044     4.685    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.685    
                         arrival time                           5.287    
  -------------------------------------------------------------------
                         slack                                  0.603    

Slack (MET) :             0.604ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][92]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[4]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[2]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.312ns  (logic 0.059ns (18.885%)  route 0.253ns (81.116%))
  Logic Levels:           0  
  Clock Path Skew:        -0.513ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.207ns
    Source Clock Delay      (SCD):    4.972ns
    Clock Pessimism Removal (CPR):    -0.253ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.819ns (routing 0.716ns, distribution 1.103ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.129    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.819     4.972    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X81Y333        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][92]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y333        FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.059     5.031 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][92]/Q
                         net (fo=2, routed)           0.253     5.285    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/mcal_ADR[4]
    BITSLICE_RX_TX_X0Y288
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[4]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41415, routed)       1.880     4.642    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y11            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.584 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.132     3.716    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     3.893 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     4.002 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT2[26])
                                                      0.187     4.189 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT2[26]
                         net (fo=1, routed)           0.018     4.207    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT2[26]
    BITSLICE_RX_TX_X0Y288
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.253     4.460    
                         clock uncertainty            0.170     4.630    
    BITSLICE_RX_TX_X0Y288
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[4])
                                                      0.051     4.681    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.681    
                         arrival time                           5.285    
  -------------------------------------------------------------------
                         slack                                  0.604    





---------------------------------------------------------------------------------------------------
From Clock:  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  To Clock:  mmcm_clkout5

Setup :            0  Failing Endpoints,  Worst Slack       49.663ns,  Total Violation        0.000ns
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             49.663ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[1]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            50.000ns  (MaxDelay Path 50.000ns)
  Data Path Delay:        0.362ns  (logic 0.080ns (22.099%)  route 0.282ns (77.901%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 50.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X109Y339                                    0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[1]/C
    SLICE_X109Y339       FDCE (Prop_DFF2_SLICEM_C_Q)
                                                      0.080     0.080 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[1]/Q
                         net (fo=1, routed)           0.282     0.362    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q[1]
    SLICE_X109Y339       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   50.000    50.000    
    SLICE_X109Y339       FDCE (Setup_GFF2_SLICEM_C_D)
                                                      0.025    50.025    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[1]
  -------------------------------------------------------------------
                         required time                         50.025    
                         arrival time                          -0.362    
  -------------------------------------------------------------------
                         slack                                 49.663    

Slack (MET) :             49.699ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[2]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            50.000ns  (MaxDelay Path 50.000ns)
  Data Path Delay:        0.326ns  (logic 0.078ns (23.926%)  route 0.248ns (76.074%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 50.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X109Y339                                    0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[2]/C
    SLICE_X109Y339       FDCE (Prop_CFF_SLICEM_C_Q)
                                                      0.078     0.078 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[2]/Q
                         net (fo=1, routed)           0.248     0.326    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q[2]
    SLICE_X109Y338       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   50.000    50.000    
    SLICE_X109Y338       FDCE (Setup_FFF2_SLICEM_C_D)
                                                      0.025    50.025    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[2]
  -------------------------------------------------------------------
                         required time                         50.025    
                         arrival time                          -0.326    
  -------------------------------------------------------------------
                         slack                                 49.699    

Slack (MET) :             49.717ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[0]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            50.000ns  (MaxDelay Path 50.000ns)
  Data Path Delay:        0.308ns  (logic 0.079ns (25.649%)  route 0.229ns (74.351%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 50.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X111Y345                                    0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[0]/C
    SLICE_X111Y345       FDCE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     0.079 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[0]/Q
                         net (fo=1, routed)           0.229     0.308    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q[0]
    SLICE_X112Y346       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   50.000    50.000    
    SLICE_X112Y346       FDCE (Setup_DFF2_SLICEM_C_D)
                                                      0.025    50.025    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         50.025    
                         arrival time                          -0.308    
  -------------------------------------------------------------------
                         slack                                 49.717    

Slack (MET) :             49.721ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[3]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            50.000ns  (MaxDelay Path 50.000ns)
  Data Path Delay:        0.304ns  (logic 0.077ns (25.329%)  route 0.227ns (74.671%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 50.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X109Y339                                    0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[3]/C
    SLICE_X109Y339       FDCE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     0.077 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[3]/Q
                         net (fo=1, routed)           0.227     0.304    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q[3]
    SLICE_X109Y336       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   50.000    50.000    
    SLICE_X109Y336       FDCE (Setup_DFF2_SLICEM_C_D)
                                                      0.025    50.025    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[3]
  -------------------------------------------------------------------
                         required time                         50.025    
                         arrival time                          -0.304    
  -------------------------------------------------------------------
                         slack                                 49.721    

Slack (MET) :             49.729ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[1]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            50.000ns  (MaxDelay Path 50.000ns)
  Data Path Delay:        0.296ns  (logic 0.081ns (27.365%)  route 0.215ns (72.635%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 50.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X111Y345                                    0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[1]/C
    SLICE_X111Y345       FDCE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     0.081 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[1]/Q
                         net (fo=1, routed)           0.215     0.296    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q[1]
    SLICE_X112Y346       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   50.000    50.000    
    SLICE_X112Y346       FDCE (Setup_FFF2_SLICEM_C_D)
                                                      0.025    50.025    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[1]
  -------------------------------------------------------------------
                         required time                         50.025    
                         arrival time                          -0.296    
  -------------------------------------------------------------------
                         slack                                 49.729    

Slack (MET) :             49.729ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[2]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            50.000ns  (MaxDelay Path 50.000ns)
  Data Path Delay:        0.296ns  (logic 0.081ns (27.365%)  route 0.215ns (72.635%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 50.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X111Y345                                    0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[2]/C
    SLICE_X111Y345       FDCE (Prop_AFF2_SLICEL_C_Q)
                                                      0.081     0.081 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[2]/Q
                         net (fo=1, routed)           0.215     0.296    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q[2]
    SLICE_X111Y345       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   50.000    50.000    
    SLICE_X111Y345       FDCE (Setup_HFF2_SLICEL_C_D)
                                                      0.025    50.025    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[2]
  -------------------------------------------------------------------
                         required time                         50.025    
                         arrival time                          -0.296    
  -------------------------------------------------------------------
                         slack                                 49.729    

Slack (MET) :             49.741ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[3]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            50.000ns  (MaxDelay Path 50.000ns)
  Data Path Delay:        0.284ns  (logic 0.079ns (27.817%)  route 0.205ns (72.183%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 50.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X111Y345                                    0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[3]/C
    SLICE_X111Y345       FDCE (Prop_BFF_SLICEL_C_Q)
                                                      0.079     0.079 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[3]/Q
                         net (fo=1, routed)           0.205     0.284    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q[3]
    SLICE_X111Y345       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   50.000    50.000    
    SLICE_X111Y345       FDCE (Setup_GFF2_SLICEL_C_D)
                                                      0.025    50.025    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[3]
  -------------------------------------------------------------------
                         required time                         50.025    
                         arrival time                          -0.284    
  -------------------------------------------------------------------
                         slack                                 49.741    

Slack (MET) :             49.778ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            50.000ns  (MaxDelay Path 50.000ns)
  Data Path Delay:        0.247ns  (logic 0.078ns (31.579%)  route 0.169ns (68.421%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 50.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X109Y339                                    0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[0]/C
    SLICE_X109Y339       FDCE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     0.078 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[0]/Q
                         net (fo=1, routed)           0.169     0.247    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q[0]
    SLICE_X109Y338       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   50.000    50.000    
    SLICE_X109Y338       FDCE (Setup_GFF2_SLICEM_C_D)
                                                      0.025    50.025    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         50.025    
                         arrival time                          -0.247    
  -------------------------------------------------------------------
                         slack                                 49.778    





---------------------------------------------------------------------------------------------------
From Clock:  mmcm_clkout0
  To Clock:  mmcm_clkout5

Setup :            0  Failing Endpoints,  Worst Slack       11.320ns,  Total Violation        0.000ns
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             11.320ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[3].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.000ns  (MaxDelay Path 12.000ns)
  Data Path Delay:        0.705ns  (logic 0.081ns (11.489%)  route 0.624ns (88.511%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y328                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[3]/C
    SLICE_X92Y328        FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.081     0.081 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[3]/Q
                         net (fo=1, routed)           0.624     0.705    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[3]
    SLICE_X92Y328        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[3].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.000    12.000    
    SLICE_X92Y328        FDRE (Setup_DFF2_SLICEL_C_D)
                                                      0.025    12.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[3].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         12.025    
                         arrival time                          -0.705    
  -------------------------------------------------------------------
                         slack                                 11.320    

Slack (MET) :             11.435ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[4].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.000ns  (MaxDelay Path 12.000ns)
  Data Path Delay:        0.590ns  (logic 0.081ns (13.729%)  route 0.509ns (86.271%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y328                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[4]/C
    SLICE_X92Y328        FDRE (Prop_FFF2_SLICEL_C_Q)
                                                      0.081     0.081 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[4]/Q
                         net (fo=1, routed)           0.509     0.590    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[4]
    SLICE_X92Y328        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[4].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.000    12.000    
    SLICE_X92Y328        FDRE (Setup_CFF2_SLICEL_C_D)
                                                      0.025    12.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[4].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         12.025    
                         arrival time                          -0.590    
  -------------------------------------------------------------------
                         slack                                 11.435    

Slack (MET) :             11.642ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[7].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.000ns  (MaxDelay Path 12.000ns)
  Data Path Delay:        0.383ns  (logic 0.081ns (21.149%)  route 0.302ns (78.851%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y328                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[7]/C
    SLICE_X92Y328        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.081     0.081 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[7]/Q
                         net (fo=1, routed)           0.302     0.383    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[7]
    SLICE_X95Y328        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[7].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.000    12.000    
    SLICE_X95Y328        FDRE (Setup_BFF2_SLICEL_C_D)
                                                      0.025    12.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[7].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         12.025    
                         arrival time                          -0.383    
  -------------------------------------------------------------------
                         slack                                 11.642    

Slack (MET) :             11.651ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[5].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.000ns  (MaxDelay Path 12.000ns)
  Data Path Delay:        0.374ns  (logic 0.079ns (21.123%)  route 0.295ns (78.877%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y323                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[5]/C
    SLICE_X93Y323        FDRE (Prop_GFF2_SLICEM_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[5]/Q
                         net (fo=1, routed)           0.295     0.374    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[5]
    SLICE_X93Y323        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[5].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.000    12.000    
    SLICE_X93Y323        FDRE (Setup_DFF2_SLICEM_C_D)
                                                      0.025    12.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[5].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         12.025    
                         arrival time                          -0.374    
  -------------------------------------------------------------------
                         slack                                 11.651    

Slack (MET) :             11.680ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[6].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.000ns  (MaxDelay Path 12.000ns)
  Data Path Delay:        0.345ns  (logic 0.079ns (22.899%)  route 0.266ns (77.101%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y323                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[6]/C
    SLICE_X93Y323        FDRE (Prop_FFF2_SLICEM_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[6]/Q
                         net (fo=1, routed)           0.266     0.345    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[6]
    SLICE_X95Y325        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[6].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.000    12.000    
    SLICE_X95Y325        FDRE (Setup_BFF2_SLICEL_C_D)
                                                      0.025    12.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[6].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         12.025    
                         arrival time                          -0.345    
  -------------------------------------------------------------------
                         slack                                 11.680    

Slack (MET) :             11.690ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[0].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.000ns  (MaxDelay Path 12.000ns)
  Data Path Delay:        0.335ns  (logic 0.078ns (23.284%)  route 0.257ns (76.716%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y323                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[0]/C
    SLICE_X93Y323        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.078     0.078 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[0]/Q
                         net (fo=1, routed)           0.257     0.335    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[0]
    SLICE_X93Y322        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[0].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.000    12.000    
    SLICE_X93Y322        FDRE (Setup_HFF2_SLICEM_C_D)
                                                      0.025    12.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[0].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         12.025    
                         arrival time                          -0.335    
  -------------------------------------------------------------------
                         slack                                 11.690    

Slack (MET) :             11.707ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_rdy_lvl_fclk_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_sync/SYNC[0].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.000ns  (MaxDelay Path 12.000ns)
  Data Path Delay:        0.318ns  (logic 0.078ns (24.526%)  route 0.240ns (75.474%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y324                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_rdy_lvl_fclk_reg/C
    SLICE_X93Y324        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.078     0.078 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_rdy_lvl_fclk_reg/Q
                         net (fo=2, routed)           0.240     0.318    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_sync/D[0]
    SLICE_X94Y323        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_sync/SYNC[0].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.000    12.000    
    SLICE_X94Y323        FDRE (Setup_DFF2_SLICEM_C_D)
                                                      0.025    12.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_sync/SYNC[0].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         12.025    
                         arrival time                          -0.318    
  -------------------------------------------------------------------
                         slack                                 11.707    

Slack (MET) :             11.719ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[8]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[8].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.000ns  (MaxDelay Path 12.000ns)
  Data Path Delay:        0.306ns  (logic 0.079ns (25.817%)  route 0.227ns (74.183%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y323                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[8]/C
    SLICE_X93Y323        FDRE (Prop_EFF2_SLICEM_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[8]/Q
                         net (fo=1, routed)           0.227     0.306    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[8]
    SLICE_X93Y323        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[8].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.000    12.000    
    SLICE_X93Y323        FDRE (Setup_CFF2_SLICEM_C_D)
                                                      0.025    12.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[8].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         12.025    
                         arrival time                          -0.306    
  -------------------------------------------------------------------
                         slack                                 11.719    

Slack (MET) :             11.721ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[2].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.000ns  (MaxDelay Path 12.000ns)
  Data Path Delay:        0.304ns  (logic 0.080ns (26.316%)  route 0.224ns (73.684%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y328                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[2]/C
    SLICE_X92Y328        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.080     0.080 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[2]/Q
                         net (fo=1, routed)           0.224     0.304    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[2]
    SLICE_X95Y328        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[2].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.000    12.000    
    SLICE_X95Y328        FDRE (Setup_CFF2_SLICEL_C_D)
                                                      0.025    12.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[2].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         12.025    
                         arrival time                          -0.304    
  -------------------------------------------------------------------
                         slack                                 11.721    

Slack (MET) :             11.787ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[1].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.000ns  (MaxDelay Path 12.000ns)
  Data Path Delay:        0.238ns  (logic 0.079ns (33.193%)  route 0.159ns (66.807%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y321                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[1]/C
    SLICE_X92Y321        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[1]/Q
                         net (fo=1, routed)           0.159     0.238    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[1]
    SLICE_X93Y321        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[1].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.000    12.000    
    SLICE_X93Y321        FDRE (Setup_HFF2_SLICEM_C_D)
                                                      0.025    12.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[1].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         12.025    
                         arrival time                          -0.238    
  -------------------------------------------------------------------
                         slack                                 11.787    





---------------------------------------------------------------------------------------------------
From Clock:  mmcm_clkout0
  To Clock:  mmcm_clkout6

Setup :            0  Failing Endpoints,  Worst Slack        0.820ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.456ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.820ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/sample_gts_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/sample_gts_riu_reg/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (mmcm_clkout6 rise@6.001ns - mmcm_clkout0 rise@3.001ns)
  Data Path Delay:        1.767ns  (logic 0.149ns (8.432%)  route 1.618ns (91.568%))
  Logic Levels:           1  (LUT1=1)
  Clock Path Skew:        -0.250ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.984ns = ( 10.985 - 6.001 ) 
    Source Clock Delay      (SCD):    4.809ns = ( 7.809 - 3.001 ) 
    Clock Pessimism Removal (CPR):    -0.425ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      2.047ns (routing 0.788ns, distribution 1.259ns)
  Clock Net Delay (Destination): 1.819ns (routing 0.726ns, distribution 1.093ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     3.101    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     3.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     3.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     4.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     4.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     5.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     5.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     5.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     5.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.047     7.809    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X85Y301        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/sample_gts_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y301        FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.079     7.888 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/sample_gts_reg/Q
                         net (fo=1, routed)           0.750     8.638    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/sample_gts
    SLICE_X75Y298        LUT1 (Prop_A5LUT_SLICEM_I0_O)
                                                      0.070     8.708 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/sample_gts_hold_fix/O
                         net (fo=1, routed)           0.868     9.576    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/sample_gts_hold_fix_1_alias
    SLICE_X85Y298        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/sample_gts_riu_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      6.001     6.001 r  
    J19                                               0.000     6.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     6.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     6.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     6.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     6.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     6.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     8.285    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     8.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.227     9.142    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     9.166 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.819    10.985    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X85Y298        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/sample_gts_riu_reg/C
                         clock pessimism             -0.425    10.560    
                         clock uncertainty           -0.188    10.372    
    SLICE_X85Y298        FDRE (Setup_AFF_SLICEL_C_D)
                                                      0.025    10.397    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/sample_gts_riu_reg
  -------------------------------------------------------------------
                         required time                         10.397    
                         arrival time                          -9.576    
  -------------------------------------------------------------------
                         slack                                  0.820    

Slack (MET) :             4.516ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[10]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[10].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (MaxDelay Path 5.000ns)
  Data Path Delay:        0.509ns  (logic 0.079ns (15.521%)  route 0.430ns (84.479%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 5.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y334                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[10]/C
    SLICE_X91Y334        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[10]/Q
                         net (fo=1, routed)           0.430     0.509    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[10]
    SLICE_X87Y334        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[10].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    5.000     5.000    
    SLICE_X87Y334        FDRE (Setup_HFF2_SLICEM_C_D)
                                                      0.025     5.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[10].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          5.025    
                         arrival time                          -0.509    
  -------------------------------------------------------------------
                         slack                                  4.516    

Slack (MET) :             4.521ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[3].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (MaxDelay Path 5.000ns)
  Data Path Delay:        0.504ns  (logic 0.081ns (16.071%)  route 0.423ns (83.929%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 5.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y297                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[3]/C
    SLICE_X88Y297        FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.081     0.081 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[3]/Q
                         net (fo=1, routed)           0.423     0.504    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[3]
    SLICE_X86Y307        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[3].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    5.000     5.000    
    SLICE_X86Y307        FDRE (Setup_DFF2_SLICEM_C_D)
                                                      0.025     5.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[3].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          5.025    
                         arrival time                          -0.504    
  -------------------------------------------------------------------
                         slack                                  4.521    

Slack (MET) :             4.544ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[22]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[22].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (MaxDelay Path 5.000ns)
  Data Path Delay:        0.481ns  (logic 0.078ns (16.216%)  route 0.403ns (83.784%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 5.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y309                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[22]/C
    SLICE_X93Y309        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.078     0.078 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[22]/Q
                         net (fo=1, routed)           0.403     0.481    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[22]
    SLICE_X91Y309        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[22].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    5.000     5.000    
    SLICE_X91Y309        FDRE (Setup_HFF2_SLICEL_C_D)
                                                      0.025     5.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[22].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          5.025    
                         arrival time                          -0.481    
  -------------------------------------------------------------------
                         slack                                  4.544    

Slack (MET) :             4.562ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[27]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[27].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (MaxDelay Path 5.000ns)
  Data Path Delay:        0.463ns  (logic 0.077ns (16.631%)  route 0.386ns (83.369%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 5.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X90Y298                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[27]/C
    SLICE_X90Y298        FDRE (Prop_CFF2_SLICEM_C_Q)
                                                      0.077     0.077 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[27]/Q
                         net (fo=1, routed)           0.386     0.463    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[27]
    SLICE_X86Y301        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[27].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    5.000     5.000    
    SLICE_X86Y301        FDRE (Setup_DFF2_SLICEM_C_D)
                                                      0.025     5.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[27].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          5.025    
                         arrival time                          -0.463    
  -------------------------------------------------------------------
                         slack                                  4.562    

Slack (MET) :             4.581ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[5].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (MaxDelay Path 5.000ns)
  Data Path Delay:        0.444ns  (logic 0.079ns (17.793%)  route 0.365ns (82.207%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 5.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y300                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[5]/C
    SLICE_X88Y300        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[5]/Q
                         net (fo=1, routed)           0.365     0.444    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[5]
    SLICE_X87Y302        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[5].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    5.000     5.000    
    SLICE_X87Y302        FDRE (Setup_GFF2_SLICEM_C_D)
                                                      0.025     5.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[5].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          5.025    
                         arrival time                          -0.444    
  -------------------------------------------------------------------
                         slack                                  4.581    

Slack (MET) :             4.606ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[26]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[26].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (MaxDelay Path 5.000ns)
  Data Path Delay:        0.419ns  (logic 0.080ns (19.093%)  route 0.339ns (80.907%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 5.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X90Y298                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[26]/C
    SLICE_X90Y298        FDRE (Prop_DFF2_SLICEM_C_Q)
                                                      0.080     0.080 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[26]/Q
                         net (fo=1, routed)           0.339     0.419    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[26]
    SLICE_X87Y302        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[26].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    5.000     5.000    
    SLICE_X87Y302        FDRE (Setup_HFF2_SLICEM_C_D)
                                                      0.025     5.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[26].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          5.025    
                         arrival time                          -0.419    
  -------------------------------------------------------------------
                         slack                                  4.606    

Slack (MET) :             4.611ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[9]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[9].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (MaxDelay Path 5.000ns)
  Data Path Delay:        0.414ns  (logic 0.077ns (18.599%)  route 0.337ns (81.401%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 5.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y345                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[9]/C
    SLICE_X89Y345        FDRE (Prop_CFF2_SLICEM_C_Q)
                                                      0.077     0.077 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[9]/Q
                         net (fo=1, routed)           0.337     0.414    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[9]
    SLICE_X91Y345        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[9].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    5.000     5.000    
    SLICE_X91Y345        FDRE (Setup_CFF2_SLICEL_C_D)
                                                      0.025     5.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[9].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          5.025    
                         arrival time                          -0.414    
  -------------------------------------------------------------------
                         slack                                  4.611    

Slack (MET) :             4.623ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[24]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[24].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (MaxDelay Path 5.000ns)
  Data Path Delay:        0.402ns  (logic 0.079ns (19.652%)  route 0.323ns (80.348%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 5.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y299                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[24]/C
    SLICE_X88Y299        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[24]/Q
                         net (fo=1, routed)           0.323     0.402    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[24]
    SLICE_X89Y303        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[24].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    5.000     5.000    
    SLICE_X89Y303        FDRE (Setup_HFF2_SLICEM_C_D)
                                                      0.025     5.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[24].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          5.025    
                         arrival time                          -0.402    
  -------------------------------------------------------------------
                         slack                                  4.623    

Slack (MET) :             4.627ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[18]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[18].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (MaxDelay Path 5.000ns)
  Data Path Delay:        0.398ns  (logic 0.080ns (20.101%)  route 0.318ns (79.899%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 5.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X90Y348                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[18]/C
    SLICE_X90Y348        FDRE (Prop_AFF2_SLICEM_C_Q)
                                                      0.080     0.080 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[18]/Q
                         net (fo=1, routed)           0.318     0.398    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[18]
    SLICE_X90Y348        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[18].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    5.000     5.000    
    SLICE_X90Y348        FDRE (Setup_GFF2_SLICEM_C_D)
                                                      0.025     5.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[18].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          5.025    
                         arrival time                          -0.398    
  -------------------------------------------------------------------
                         slack                                  4.627    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.456ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/sample_gts_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/sample_gts_riu_reg/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout6 rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.857ns  (logic 0.060ns (7.001%)  route 0.797ns (92.999%))
  Logic Levels:           1  (LUT1=1)
  Clock Path Skew:        0.166ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.893ns
    Source Clock Delay      (SCD):    2.983ns
    Clock Pessimism Removal (CPR):    -0.256ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.130ns (routing 0.435ns, distribution 0.695ns)
  Clock Net Delay (Destination): 1.263ns (routing 0.492ns, distribution 0.771ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.836    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.853 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.130     2.983    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X85Y301        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/sample_gts_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y301        FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.039     3.022 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/sample_gts_reg/Q
                         net (fo=1, routed)           0.387     3.409    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/sample_gts
    SLICE_X75Y298        LUT1 (Prop_A5LUT_SLICEM_I0_O)
                                                      0.021     3.430 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/sample_gts_hold_fix/O
                         net (fo=1, routed)           0.410     3.840    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/sample_gts_hold_fix_1_alias
    SLICE_X85Y298        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/sample_gts_riu_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     1.611    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.630 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.263     2.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X85Y298        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/sample_gts_riu_reg/C
                         clock pessimism              0.256     3.149    
                         clock uncertainty            0.188     3.337    
    SLICE_X85Y298        FDRE (Hold_AFF_SLICEL_C_D)
                                                      0.046     3.383    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/sample_gts_riu_reg
  -------------------------------------------------------------------
                         required time                         -3.383    
                         arrival time                           3.840    
  -------------------------------------------------------------------
                         slack                                  0.456    





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  clk_out1_d_1_clk_adc0_x2_0
  To Clock:  clk_out1_d_1_clk_adc0_x2_0

Setup :            0  Failing Endpoints,  Worst Slack        0.858ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.126ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.858ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_40/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[1]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            1.953ns  (clk_out1_d_1_clk_adc0_x2_0 rise@1.953ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        1.003ns  (logic 0.081ns (8.074%)  route 0.922ns (91.926%))
  Logic Levels:           0  
  Clock Path Skew:        0.026ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.516ns = ( 7.469 - 1.953 ) 
    Source Clock Delay      (SCD):    5.302ns
    Clock Pessimism Removal (CPR):    -0.188ns
  Clock Uncertainty:      0.051ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.074ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.034ns (routing 0.858ns, distribution 1.176ns)
  Clock Net Delay (Destination): 1.920ns (routing 0.782ns, distribution 1.138ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.595     3.122    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.995 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.240    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.268 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       2.034     5.302    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
    SLICE_X59Y144        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_40/C
  -------------------------------------------------------------------    -------------------
    SLICE_X59Y144        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.081     5.383 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_40/Q
                         net (fo=83, routed)          0.922     6.305    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/peripheral_aresetn[0]_repN_40_alias
    SLICE_X71Y127        FDCE                                         f  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      1.953     1.953 r  
    HSADC_X0Y0           HSADC                        0.000     1.953 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     2.075 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     2.225    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.339 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.341     4.680    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.310 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.525    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.549 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.920     7.469    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/s00_axis_aclk
    SLICE_X71Y127        FDCE                                         r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[1]/C
                         clock pessimism             -0.188     7.280    
                         clock uncertainty           -0.051     7.229    
    SLICE_X71Y127        FDCE (Recov_AFF_SLICEL_C_CLR)
                                                     -0.066     7.163    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[1]
  -------------------------------------------------------------------
                         required time                          7.163    
                         arrival time                          -6.305    
  -------------------------------------------------------------------
                         slack                                  0.858    

Slack (MET) :             0.877ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_12/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[0]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            1.953ns  (clk_out1_d_1_clk_adc0_x2_0 rise@1.953ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.917ns  (logic 0.079ns (8.615%)  route 0.838ns (91.385%))
  Logic Levels:           0  
  Clock Path Skew:        -0.041ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.518ns = ( 7.471 - 1.953 ) 
    Source Clock Delay      (SCD):    5.375ns
    Clock Pessimism Removal (CPR):    -0.184ns
  Clock Uncertainty:      0.051ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.074ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.107ns (routing 0.858ns, distribution 1.249ns)
  Clock Net Delay (Destination): 1.922ns (routing 0.782ns, distribution 1.140ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.595     3.122    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.995 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.240    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.268 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       2.107     5.375    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
    SLICE_X65Y142        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_12/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y142        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     5.454 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_12/Q
                         net (fo=154, routed)         0.838     6.292    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/peripheral_aresetn[0]_repN_12_alias
    SLICE_X71Y127        FDCE                                         f  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      1.953     1.953 r  
    HSADC_X0Y0           HSADC                        0.000     1.953 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     2.075 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     2.225    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.339 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.341     4.680    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.310 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.525    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.549 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.922     7.471    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/s00_axis_aclk
    SLICE_X71Y127        FDCE                                         r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[0]/C
                         clock pessimism             -0.184     7.287    
                         clock uncertainty           -0.051     7.236    
    SLICE_X71Y127        FDCE (Recov_EFF_SLICEL_C_CLR)
                                                     -0.066     7.170    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          7.170    
                         arrival time                          -6.292    
  -------------------------------------------------------------------
                         slack                                  0.877    

Slack (MET) :             1.363ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_32/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[1]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            1.953ns  (clk_out1_d_1_clk_adc0_x2_0 rise@1.953ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.481ns  (logic 0.079ns (16.440%)  route 0.402ns (83.560%))
  Logic Levels:           0  
  Clock Path Skew:        0.008ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.513ns = ( 7.466 - 1.953 ) 
    Source Clock Delay      (SCD):    5.317ns
    Clock Pessimism Removal (CPR):    -0.188ns
  Clock Uncertainty:      0.051ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.074ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.049ns (routing 0.858ns, distribution 1.191ns)
  Clock Net Delay (Destination): 1.917ns (routing 0.782ns, distribution 1.135ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.595     3.122    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.995 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.240    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.268 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       2.049     5.317    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
    SLICE_X59Y127        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_32/C
  -------------------------------------------------------------------    -------------------
    SLICE_X59Y127        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     5.396 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_32/Q
                         net (fo=19, routed)          0.402     5.797    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/peripheral_aresetn[0]_repN_32_alias
    SLICE_X68Y123        FDCE                                         f  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      1.953     1.953 r  
    HSADC_X0Y0           HSADC                        0.000     1.953 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     2.075 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     2.225    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.339 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.341     4.680    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.310 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.525    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.549 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.917     7.466    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/s00_axis_aclk
    SLICE_X68Y123        FDCE                                         r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[1]/C
                         clock pessimism             -0.188     7.278    
                         clock uncertainty           -0.051     7.226    
    SLICE_X68Y123        FDCE (Recov_EFF_SLICEL_C_CLR)
                                                     -0.066     7.160    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[1]
  -------------------------------------------------------------------
                         required time                          7.160    
                         arrival time                          -5.797    
  -------------------------------------------------------------------
                         slack                                  1.363    

Slack (MET) :             1.414ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_16/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[0]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            1.953ns  (clk_out1_d_1_clk_adc0_x2_0 rise@1.953ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.383ns  (logic 0.079ns (20.643%)  route 0.304ns (79.357%))
  Logic Levels:           0  
  Clock Path Skew:        -0.039ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.511ns = ( 7.464 - 1.953 ) 
    Source Clock Delay      (SCD):    5.417ns
    Clock Pessimism Removal (CPR):    -0.133ns
  Clock Uncertainty:      0.051ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.074ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.149ns (routing 0.858ns, distribution 1.291ns)
  Clock Net Delay (Destination): 1.915ns (routing 0.782ns, distribution 1.133ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.595     3.122    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.995 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.240    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.268 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       2.149     5.417    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
    SLICE_X67Y126        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_16/C
  -------------------------------------------------------------------    -------------------
    SLICE_X67Y126        FDRE (Prop_EFF2_SLICEM_C_Q)
                                                      0.079     5.496 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_16/Q
                         net (fo=143, routed)         0.304     5.799    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/peripheral_aresetn[0]_repN_16_alias
    SLICE_X68Y123        FDCE                                         f  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      1.953     1.953 r  
    HSADC_X0Y0           HSADC                        0.000     1.953 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     2.075 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     2.225    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.339 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.341     4.680    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.310 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.525    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.549 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.915     7.464    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/s00_axis_aclk
    SLICE_X68Y123        FDCE                                         r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[0]/C
                         clock pessimism             -0.133     7.331    
                         clock uncertainty           -0.051     7.280    
    SLICE_X68Y123        FDCE (Recov_DFF2_SLICEL_C_CLR)
                                                     -0.066     7.214    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          7.214    
                         arrival time                          -5.799    
  -------------------------------------------------------------------
                         slack                                  1.414    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.126ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_32/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[1]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.301ns  (logic 0.059ns (19.576%)  route 0.242ns (80.424%))
  Logic Levels:           0  
  Clock Path Skew:        0.208ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.435ns
    Source Clock Delay      (SCD):    5.416ns
    Clock Pessimism Removal (CPR):    -0.188ns
  Clock Net Delay (Source):      1.820ns (routing 0.782ns, distribution 1.038ns)
  Clock Net Delay (Destination): 2.167ns (routing 0.858ns, distribution 1.309ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.341     2.727    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.357 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.572    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.596 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.820     5.416    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
    SLICE_X59Y127        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_32/C
  -------------------------------------------------------------------    -------------------
    SLICE_X59Y127        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.059     5.475 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_32/Q
                         net (fo=19, routed)          0.242     5.717    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/peripheral_aresetn[0]_repN_32_alias
    SLICE_X68Y123        FDCE                                         f  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.595     3.122    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.995 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.240    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.268 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       2.167     5.435    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/s00_axis_aclk
    SLICE_X68Y123        FDCE                                         r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[1]/C
                         clock pessimism              0.188     5.623    
    SLICE_X68Y123        FDCE (Remov_EFF_SLICEL_C_CLR)
                                                     -0.032     5.591    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[1]
  -------------------------------------------------------------------
                         required time                         -5.591    
                         arrival time                           5.717    
  -------------------------------------------------------------------
                         slack                                  0.126    

Slack (MET) :             0.171ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_16/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[0]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.174ns  (logic 0.039ns (22.394%)  route 0.135ns (77.606%))
  Logic Levels:           0  
  Clock Path Skew:        0.023ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.148ns
    Source Clock Delay      (SCD):    3.247ns
    Clock Pessimism Removal (CPR):    -0.123ns
  Clock Net Delay (Source):      1.176ns (routing 0.470ns, distribution 0.706ns)
  Clock Net Delay (Destination): 1.323ns (routing 0.521ns, distribution 0.802ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.415     1.678    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.908 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.054    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.071 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.176     3.247    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
    SLICE_X67Y126        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_16/C
  -------------------------------------------------------------------    -------------------
    SLICE_X67Y126        FDRE (Prop_EFF2_SLICEM_C_Q)
                                                      0.039     3.286 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_16/Q
                         net (fo=143, routed)         0.135     3.421    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/peripheral_aresetn[0]_repN_16_alias
    SLICE_X68Y123        FDCE                                         f  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.583     1.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.640 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.806    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.825 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.323     3.148    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/s00_axis_aclk
    SLICE_X68Y123        FDCE                                         r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[0]/C
                         clock pessimism              0.123     3.270    
    SLICE_X68Y123        FDCE (Remov_DFF2_SLICEL_C_CLR)
                                                     -0.020     3.250    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         -3.250    
                         arrival time                           3.421    
  -------------------------------------------------------------------
                         slack                                  0.171    

Slack (MET) :             0.387ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_12/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[0]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.444ns  (logic 0.039ns (8.785%)  route 0.405ns (91.215%))
  Logic Levels:           0  
  Clock Path Skew:        0.077ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.155ns
    Source Clock Delay      (SCD):    3.230ns
    Clock Pessimism Removal (CPR):    -0.152ns
  Clock Net Delay (Source):      1.159ns (routing 0.470ns, distribution 0.689ns)
  Clock Net Delay (Destination): 1.330ns (routing 0.521ns, distribution 0.809ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.415     1.678    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.908 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.054    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.071 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.159     3.230    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
    SLICE_X65Y142        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_12/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y142        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     3.269 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_12/Q
                         net (fo=154, routed)         0.405     3.673    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/peripheral_aresetn[0]_repN_12_alias
    SLICE_X71Y127        FDCE                                         f  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.583     1.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.640 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.806    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.825 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.330     3.155    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/s00_axis_aclk
    SLICE_X71Y127        FDCE                                         r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[0]/C
                         clock pessimism              0.152     3.307    
    SLICE_X71Y127        FDCE (Remov_EFF_SLICEL_C_CLR)
                                                     -0.020     3.287    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         -3.287    
                         arrival time                           3.673    
  -------------------------------------------------------------------
                         slack                                  0.387    

Slack (MET) :             0.406ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_40/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[1]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.505ns  (logic 0.040ns (7.928%)  route 0.465ns (92.072%))
  Logic Levels:           0  
  Clock Path Skew:        0.119ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.151ns
    Source Clock Delay      (SCD):    3.186ns
    Clock Pessimism Removal (CPR):    -0.154ns
  Clock Net Delay (Source):      1.115ns (routing 0.470ns, distribution 0.645ns)
  Clock Net Delay (Destination): 1.326ns (routing 0.521ns, distribution 0.805ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.415     1.678    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.908 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.054    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.071 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.115     3.186    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
    SLICE_X59Y144        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_40/C
  -------------------------------------------------------------------    -------------------
    SLICE_X59Y144        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.040     3.226 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_40/Q
                         net (fo=83, routed)          0.465     3.691    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/peripheral_aresetn[0]_repN_40_alias
    SLICE_X71Y127        FDCE                                         f  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.583     1.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.640 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.806    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.825 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.326     3.151    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/s00_axis_aclk
    SLICE_X71Y127        FDCE                                         r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[1]/C
                         clock pessimism              0.154     3.305    
    SLICE_X71Y127        FDCE (Remov_AFF_SLICEL_C_CLR)
                                                     -0.020     3.285    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[1]
  -------------------------------------------------------------------
                         required time                         -3.285    
                         arrival time                           3.691    
  -------------------------------------------------------------------
                         slack                                  0.406    





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  clk_out1_d_1_clk_core_0
  To Clock:  clk_out1_d_1_clk_core_0

Setup :            0  Failing Endpoints,  Worst Slack        2.764ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.115ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             2.764ns  (required time - arrival time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_6/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.div_quotient_r_reg[27]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            5.208ns  (clk_out1_d_1_clk_core_0 rise@5.208ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        2.225ns  (logic 0.079ns (3.551%)  route 2.146ns (96.449%))
  Logic Levels:           0  
  Clock Path Skew:        -0.097ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.784ns = ( 10.992 - 5.208 ) 
    Source Clock Delay      (SCD):    5.662ns
    Clock Pessimism Removal (CPR):    -0.219ns
  Clock Uncertainty:      0.056ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.087ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.024ns (routing 0.920ns, distribution 1.104ns)
  Clock Net Delay (Destination): 1.845ns (routing 0.838ns, distribution 1.007ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.819     3.492    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.365 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.610    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.638 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        2.024     5.662    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X15Y347        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_6/C
  -------------------------------------------------------------------    -------------------
    SLICE_X15Y347        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     5.741 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_6/Q
                         net (fo=170, routed)         2.146     7.887    d_1_i/qick_processor_0/inst/QPROC/peripheral_aresetn[0]_repN_6_alias
    SLICE_X18Y360        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.div_quotient_r_reg[27]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.208     5.208 r  
    HSDAC_X0Y0           HSDAC                        0.000     5.208 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     5.489 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     5.615    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     5.729 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.549     8.278    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     8.908 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     9.123    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     9.147 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.845    10.992    d_1_i/qick_processor_0/inst/QPROC/c_clk_i
    SLICE_X18Y360        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.div_quotient_r_reg[27]/C
                         clock pessimism             -0.219    10.773    
                         clock uncertainty           -0.056    10.717    
    SLICE_X18Y360        FDCE (Recov_AFF_SLICEM_C_CLR)
                                                     -0.066    10.651    d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.div_quotient_r_reg[27]
  -------------------------------------------------------------------
                         required time                         10.651    
                         arrival time                          -7.887    
  -------------------------------------------------------------------
                         slack                                  2.764    

Slack (MET) :             2.764ns  (required time - arrival time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_6/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.div_quotient_r_reg[2]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            5.208ns  (clk_out1_d_1_clk_core_0 rise@5.208ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        2.225ns  (logic 0.079ns (3.551%)  route 2.146ns (96.449%))
  Logic Levels:           0  
  Clock Path Skew:        -0.097ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.784ns = ( 10.992 - 5.208 ) 
    Source Clock Delay      (SCD):    5.662ns
    Clock Pessimism Removal (CPR):    -0.219ns
  Clock Uncertainty:      0.056ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.087ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.024ns (routing 0.920ns, distribution 1.104ns)
  Clock Net Delay (Destination): 1.845ns (routing 0.838ns, distribution 1.007ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.819     3.492    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.365 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.610    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.638 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        2.024     5.662    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X15Y347        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_6/C
  -------------------------------------------------------------------    -------------------
    SLICE_X15Y347        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     5.741 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_6/Q
                         net (fo=170, routed)         2.146     7.887    d_1_i/qick_processor_0/inst/QPROC/peripheral_aresetn[0]_repN_6_alias
    SLICE_X18Y360        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.div_quotient_r_reg[2]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.208     5.208 r  
    HSDAC_X0Y0           HSDAC                        0.000     5.208 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     5.489 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     5.615    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     5.729 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.549     8.278    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     8.908 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     9.123    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     9.147 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.845    10.992    d_1_i/qick_processor_0/inst/QPROC/c_clk_i
    SLICE_X18Y360        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.div_quotient_r_reg[2]/C
                         clock pessimism             -0.219    10.773    
                         clock uncertainty           -0.056    10.717    
    SLICE_X18Y360        FDCE (Recov_AFF2_SLICEM_C_CLR)
                                                     -0.066    10.651    d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.div_quotient_r_reg[2]
  -------------------------------------------------------------------
                         required time                         10.651    
                         arrival time                          -7.887    
  -------------------------------------------------------------------
                         slack                                  2.764    

Slack (MET) :             2.764ns  (required time - arrival time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_6/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.div_quotient_r_reg[30]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            5.208ns  (clk_out1_d_1_clk_core_0 rise@5.208ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        2.225ns  (logic 0.079ns (3.551%)  route 2.146ns (96.449%))
  Logic Levels:           0  
  Clock Path Skew:        -0.097ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.784ns = ( 10.992 - 5.208 ) 
    Source Clock Delay      (SCD):    5.662ns
    Clock Pessimism Removal (CPR):    -0.219ns
  Clock Uncertainty:      0.056ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.087ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.024ns (routing 0.920ns, distribution 1.104ns)
  Clock Net Delay (Destination): 1.845ns (routing 0.838ns, distribution 1.007ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.819     3.492    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.365 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.610    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.638 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        2.024     5.662    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X15Y347        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_6/C
  -------------------------------------------------------------------    -------------------
    SLICE_X15Y347        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     5.741 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_6/Q
                         net (fo=170, routed)         2.146     7.887    d_1_i/qick_processor_0/inst/QPROC/peripheral_aresetn[0]_repN_6_alias
    SLICE_X18Y360        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.div_quotient_r_reg[30]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.208     5.208 r  
    HSDAC_X0Y0           HSDAC                        0.000     5.208 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     5.489 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     5.615    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     5.729 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.549     8.278    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     8.908 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     9.123    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     9.147 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.845    10.992    d_1_i/qick_processor_0/inst/QPROC/c_clk_i
    SLICE_X18Y360        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.div_quotient_r_reg[30]/C
                         clock pessimism             -0.219    10.773    
                         clock uncertainty           -0.056    10.717    
    SLICE_X18Y360        FDCE (Recov_BFF_SLICEM_C_CLR)
                                                     -0.066    10.651    d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.div_quotient_r_reg[30]
  -------------------------------------------------------------------
                         required time                         10.651    
                         arrival time                          -7.887    
  -------------------------------------------------------------------
                         slack                                  2.764    

Slack (MET) :             2.764ns  (required time - arrival time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_6/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.div_quotient_r_reg[31]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            5.208ns  (clk_out1_d_1_clk_core_0 rise@5.208ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        2.225ns  (logic 0.079ns (3.551%)  route 2.146ns (96.449%))
  Logic Levels:           0  
  Clock Path Skew:        -0.097ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.784ns = ( 10.992 - 5.208 ) 
    Source Clock Delay      (SCD):    5.662ns
    Clock Pessimism Removal (CPR):    -0.219ns
  Clock Uncertainty:      0.056ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.087ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.024ns (routing 0.920ns, distribution 1.104ns)
  Clock Net Delay (Destination): 1.845ns (routing 0.838ns, distribution 1.007ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.819     3.492    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.365 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.610    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.638 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        2.024     5.662    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X15Y347        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_6/C
  -------------------------------------------------------------------    -------------------
    SLICE_X15Y347        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     5.741 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_6/Q
                         net (fo=170, routed)         2.146     7.887    d_1_i/qick_processor_0/inst/QPROC/peripheral_aresetn[0]_repN_6_alias
    SLICE_X18Y360        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.div_quotient_r_reg[31]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.208     5.208 r  
    HSDAC_X0Y0           HSDAC                        0.000     5.208 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     5.489 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     5.615    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     5.729 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.549     8.278    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     8.908 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     9.123    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     9.147 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.845    10.992    d_1_i/qick_processor_0/inst/QPROC/c_clk_i
    SLICE_X18Y360        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.div_quotient_r_reg[31]/C
                         clock pessimism             -0.219    10.773    
                         clock uncertainty           -0.056    10.717    
    SLICE_X18Y360        FDCE (Recov_BFF2_SLICEM_C_CLR)
                                                     -0.066    10.651    d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.div_quotient_r_reg[31]
  -------------------------------------------------------------------
                         required time                         10.651    
                         arrival time                          -7.887    
  -------------------------------------------------------------------
                         slack                                  2.764    

Slack (MET) :             2.764ns  (required time - arrival time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_6/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.div_quotient_r_reg[3]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            5.208ns  (clk_out1_d_1_clk_core_0 rise@5.208ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        2.225ns  (logic 0.079ns (3.551%)  route 2.146ns (96.449%))
  Logic Levels:           0  
  Clock Path Skew:        -0.097ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.784ns = ( 10.992 - 5.208 ) 
    Source Clock Delay      (SCD):    5.662ns
    Clock Pessimism Removal (CPR):    -0.219ns
  Clock Uncertainty:      0.056ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.087ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.024ns (routing 0.920ns, distribution 1.104ns)
  Clock Net Delay (Destination): 1.845ns (routing 0.838ns, distribution 1.007ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.819     3.492    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.365 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.610    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.638 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        2.024     5.662    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X15Y347        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_6/C
  -------------------------------------------------------------------    -------------------
    SLICE_X15Y347        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     5.741 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_6/Q
                         net (fo=170, routed)         2.146     7.887    d_1_i/qick_processor_0/inst/QPROC/peripheral_aresetn[0]_repN_6_alias
    SLICE_X18Y360        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.div_quotient_r_reg[3]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.208     5.208 r  
    HSDAC_X0Y0           HSDAC                        0.000     5.208 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     5.489 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     5.615    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     5.729 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.549     8.278    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     8.908 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     9.123    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     9.147 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.845    10.992    d_1_i/qick_processor_0/inst/QPROC/c_clk_i
    SLICE_X18Y360        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.div_quotient_r_reg[3]/C
                         clock pessimism             -0.219    10.773    
                         clock uncertainty           -0.056    10.717    
    SLICE_X18Y360        FDCE (Recov_CFF_SLICEM_C_CLR)
                                                     -0.066    10.651    d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.div_quotient_r_reg[3]
  -------------------------------------------------------------------
                         required time                         10.651    
                         arrival time                          -7.887    
  -------------------------------------------------------------------
                         slack                                  2.764    

Slack (MET) :             2.764ns  (required time - arrival time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_6/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.div_quotient_r_reg[4]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            5.208ns  (clk_out1_d_1_clk_core_0 rise@5.208ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        2.225ns  (logic 0.079ns (3.551%)  route 2.146ns (96.449%))
  Logic Levels:           0  
  Clock Path Skew:        -0.097ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.784ns = ( 10.992 - 5.208 ) 
    Source Clock Delay      (SCD):    5.662ns
    Clock Pessimism Removal (CPR):    -0.219ns
  Clock Uncertainty:      0.056ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.087ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.024ns (routing 0.920ns, distribution 1.104ns)
  Clock Net Delay (Destination): 1.845ns (routing 0.838ns, distribution 1.007ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.819     3.492    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.365 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.610    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.638 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        2.024     5.662    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X15Y347        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_6/C
  -------------------------------------------------------------------    -------------------
    SLICE_X15Y347        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     5.741 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_6/Q
                         net (fo=170, routed)         2.146     7.887    d_1_i/qick_processor_0/inst/QPROC/peripheral_aresetn[0]_repN_6_alias
    SLICE_X18Y360        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.div_quotient_r_reg[4]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.208     5.208 r  
    HSDAC_X0Y0           HSDAC                        0.000     5.208 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     5.489 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     5.615    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     5.729 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.549     8.278    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     8.908 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     9.123    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     9.147 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.845    10.992    d_1_i/qick_processor_0/inst/QPROC/c_clk_i
    SLICE_X18Y360        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.div_quotient_r_reg[4]/C
                         clock pessimism             -0.219    10.773    
                         clock uncertainty           -0.056    10.717    
    SLICE_X18Y360        FDCE (Recov_CFF2_SLICEM_C_CLR)
                                                     -0.066    10.651    d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.div_quotient_r_reg[4]
  -------------------------------------------------------------------
                         required time                         10.651    
                         arrival time                          -7.887    
  -------------------------------------------------------------------
                         slack                                  2.764    

Slack (MET) :             2.764ns  (required time - arrival time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_6/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.div_quotient_r_reg[6]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            5.208ns  (clk_out1_d_1_clk_core_0 rise@5.208ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        2.225ns  (logic 0.079ns (3.551%)  route 2.146ns (96.449%))
  Logic Levels:           0  
  Clock Path Skew:        -0.097ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.784ns = ( 10.992 - 5.208 ) 
    Source Clock Delay      (SCD):    5.662ns
    Clock Pessimism Removal (CPR):    -0.219ns
  Clock Uncertainty:      0.056ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.087ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.024ns (routing 0.920ns, distribution 1.104ns)
  Clock Net Delay (Destination): 1.845ns (routing 0.838ns, distribution 1.007ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.819     3.492    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.365 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.610    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.638 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        2.024     5.662    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X15Y347        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_6/C
  -------------------------------------------------------------------    -------------------
    SLICE_X15Y347        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     5.741 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_6/Q
                         net (fo=170, routed)         2.146     7.887    d_1_i/qick_processor_0/inst/QPROC/peripheral_aresetn[0]_repN_6_alias
    SLICE_X18Y360        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.div_quotient_r_reg[6]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.208     5.208 r  
    HSDAC_X0Y0           HSDAC                        0.000     5.208 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     5.489 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     5.615    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     5.729 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.549     8.278    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     8.908 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     9.123    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     9.147 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.845    10.992    d_1_i/qick_processor_0/inst/QPROC/c_clk_i
    SLICE_X18Y360        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.div_quotient_r_reg[6]/C
                         clock pessimism             -0.219    10.773    
                         clock uncertainty           -0.056    10.717    
    SLICE_X18Y360        FDCE (Recov_DFF_SLICEM_C_CLR)
                                                     -0.066    10.651    d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.div_quotient_r_reg[6]
  -------------------------------------------------------------------
                         required time                         10.651    
                         arrival time                          -7.887    
  -------------------------------------------------------------------
                         slack                                  2.764    

Slack (MET) :             2.809ns  (required time - arrival time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_14/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/wreg_32_dt_reg[2][11]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            5.208ns  (clk_out1_d_1_clk_core_0 rise@5.208ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        2.099ns  (logic 0.081ns (3.859%)  route 2.018ns (96.141%))
  Logic Levels:           0  
  Clock Path Skew:        -0.178ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.667ns = ( 10.875 - 5.208 ) 
    Source Clock Delay      (SCD):    5.683ns
    Clock Pessimism Removal (CPR):    -0.162ns
  Clock Uncertainty:      0.056ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.087ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.045ns (routing 0.920ns, distribution 1.125ns)
  Clock Net Delay (Destination): 1.728ns (routing 0.838ns, distribution 0.890ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.819     3.492    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.365 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.610    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.638 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        2.045     5.683    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X38Y386        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_14/C
  -------------------------------------------------------------------    -------------------
    SLICE_X38Y386        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.081     5.764 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_14/Q
                         net (fo=166, routed)         2.018     7.782    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/peripheral_aresetn[0]_repN_14_alias
    SLICE_X33Y383        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/wreg_32_dt_reg[2][11]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.208     5.208 r  
    HSDAC_X0Y0           HSDAC                        0.000     5.208 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     5.489 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     5.615    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     5.729 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.549     8.278    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     8.908 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     9.123    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     9.147 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.728    10.875    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/c_clk_i
    SLICE_X33Y383        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/wreg_32_dt_reg[2][11]/C
                         clock pessimism             -0.162    10.713    
                         clock uncertainty           -0.056    10.657    
    SLICE_X33Y383        FDCE (Recov_DFF_SLICEL_C_CLR)
                                                     -0.066    10.591    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/wreg_32_dt_reg[2][11]
  -------------------------------------------------------------------
                         required time                         10.591    
                         arrival time                          -7.782    
  -------------------------------------------------------------------
                         slack                                  2.809    

Slack (MET) :             2.809ns  (required time - arrival time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_14/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/wreg_32_dt_reg[2][15]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            5.208ns  (clk_out1_d_1_clk_core_0 rise@5.208ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        2.099ns  (logic 0.081ns (3.859%)  route 2.018ns (96.141%))
  Logic Levels:           0  
  Clock Path Skew:        -0.178ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.667ns = ( 10.875 - 5.208 ) 
    Source Clock Delay      (SCD):    5.683ns
    Clock Pessimism Removal (CPR):    -0.162ns
  Clock Uncertainty:      0.056ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.087ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.045ns (routing 0.920ns, distribution 1.125ns)
  Clock Net Delay (Destination): 1.728ns (routing 0.838ns, distribution 0.890ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.819     3.492    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.365 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.610    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.638 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        2.045     5.683    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X38Y386        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_14/C
  -------------------------------------------------------------------    -------------------
    SLICE_X38Y386        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.081     5.764 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_14/Q
                         net (fo=166, routed)         2.018     7.782    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/peripheral_aresetn[0]_repN_14_alias
    SLICE_X33Y383        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/wreg_32_dt_reg[2][15]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.208     5.208 r  
    HSDAC_X0Y0           HSDAC                        0.000     5.208 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     5.489 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     5.615    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     5.729 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.549     8.278    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     8.908 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     9.123    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     9.147 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.728    10.875    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/c_clk_i
    SLICE_X33Y383        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/wreg_32_dt_reg[2][15]/C
                         clock pessimism             -0.162    10.713    
                         clock uncertainty           -0.056    10.657    
    SLICE_X33Y383        FDCE (Recov_CFF_SLICEL_C_CLR)
                                                     -0.066    10.591    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/wreg_32_dt_reg[2][15]
  -------------------------------------------------------------------
                         required time                         10.591    
                         arrival time                          -7.782    
  -------------------------------------------------------------------
                         slack                                  2.809    

Slack (MET) :             2.809ns  (required time - arrival time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_14/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/wreg_32_dt_reg[2][9]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            5.208ns  (clk_out1_d_1_clk_core_0 rise@5.208ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        2.099ns  (logic 0.081ns (3.859%)  route 2.018ns (96.141%))
  Logic Levels:           0  
  Clock Path Skew:        -0.178ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.667ns = ( 10.875 - 5.208 ) 
    Source Clock Delay      (SCD):    5.683ns
    Clock Pessimism Removal (CPR):    -0.162ns
  Clock Uncertainty:      0.056ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.087ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.045ns (routing 0.920ns, distribution 1.125ns)
  Clock Net Delay (Destination): 1.728ns (routing 0.838ns, distribution 0.890ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.819     3.492    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.365 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.610    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.638 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        2.045     5.683    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X38Y386        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_14/C
  -------------------------------------------------------------------    -------------------
    SLICE_X38Y386        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.081     5.764 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_14/Q
                         net (fo=166, routed)         2.018     7.782    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/peripheral_aresetn[0]_repN_14_alias
    SLICE_X33Y383        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/wreg_32_dt_reg[2][9]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.208     5.208 r  
    HSDAC_X0Y0           HSDAC                        0.000     5.208 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     5.489 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     5.615    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     5.729 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.549     8.278    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     8.908 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     9.123    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     9.147 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.728    10.875    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/c_clk_i
    SLICE_X33Y383        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/wreg_32_dt_reg[2][9]/C
                         clock pessimism             -0.162    10.713    
                         clock uncertainty           -0.056    10.657    
    SLICE_X33Y383        FDCE (Recov_BFF_SLICEL_C_CLR)
                                                     -0.066    10.591    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/wreg_32_dt_reg[2][9]
  -------------------------------------------------------------------
                         required time                         10.591    
                         arrival time                          -7.782    
  -------------------------------------------------------------------
                         slack                                  2.809    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.115ns  (arrival time - required time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_4/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/sreg_dt_reg[0][29]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.173ns  (logic 0.038ns (21.942%)  route 0.135ns (78.058%))
  Logic Levels:           0  
  Clock Path Skew:        0.078ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.297ns
    Source Clock Delay      (SCD):    3.370ns
    Clock Pessimism Removal (CPR):    -0.150ns
  Clock Net Delay (Source):      1.089ns (routing 0.503ns, distribution 0.586ns)
  Clock Net Delay (Destination): 1.251ns (routing 0.553ns, distribution 0.698ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       1.539     1.888    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     2.118 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.264    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.281 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.089     3.370    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X24Y379        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_4/C
  -------------------------------------------------------------------    -------------------
    SLICE_X24Y379        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     3.408 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_4/Q
                         net (fo=237, routed)         0.135     3.543    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/peripheral_aresetn[0]_repN_4_alias
    SLICE_X20Y379        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/sreg_dt_reg[0][29]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       1.708     2.156    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.861 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     2.027    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     2.046 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.251     3.297    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/c_clk_i
    SLICE_X20Y379        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/sreg_dt_reg[0][29]/C
                         clock pessimism              0.150     3.447    
    SLICE_X20Y379        FDCE (Remov_AFF_SLICEM_C_CLR)
                                                     -0.020     3.427    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/sreg_dt_reg[0][29]
  -------------------------------------------------------------------
                         required time                         -3.427    
                         arrival time                           3.543    
  -------------------------------------------------------------------
                         slack                                  0.115    

Slack (MET) :             0.119ns  (arrival time - required time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_10/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/clr_fifo_ack_reg/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.160ns  (logic 0.039ns (24.319%)  route 0.121ns (75.681%))
  Logic Levels:           0  
  Clock Path Skew:        0.061ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.302ns
    Source Clock Delay      (SCD):    3.393ns
    Clock Pessimism Removal (CPR):    -0.151ns
  Clock Net Delay (Source):      1.112ns (routing 0.503ns, distribution 0.609ns)
  Clock Net Delay (Destination): 1.256ns (routing 0.553ns, distribution 0.703ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       1.539     1.888    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     2.118 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.264    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.281 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.112     3.393    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X15Y347        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_10/C
  -------------------------------------------------------------------    -------------------
    SLICE_X15Y347        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.039     3.432 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_10/Q
                         net (fo=147, routed)         0.121     3.553    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/peripheral_aresetn[0]_repN_10_alias
    SLICE_X14Y347        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/clr_fifo_ack_reg/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       1.708     2.156    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.861 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     2.027    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     2.046 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.256     3.302    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/c_clk_i
    SLICE_X14Y347        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/clr_fifo_ack_reg/C
                         clock pessimism              0.151     3.454    
    SLICE_X14Y347        FDCE (Remov_HFF_SLICEL_C_CLR)
                                                     -0.020     3.434    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/clr_fifo_ack_reg
  -------------------------------------------------------------------
                         required time                         -3.434    
                         arrival time                           3.553    
  -------------------------------------------------------------------
                         slack                                  0.119    

Slack (MET) :             0.119ns  (arrival time - required time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_10/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/clr_fifo_req_reg/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.160ns  (logic 0.039ns (24.319%)  route 0.121ns (75.681%))
  Logic Levels:           0  
  Clock Path Skew:        0.061ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.302ns
    Source Clock Delay      (SCD):    3.393ns
    Clock Pessimism Removal (CPR):    -0.151ns
  Clock Net Delay (Source):      1.112ns (routing 0.503ns, distribution 0.609ns)
  Clock Net Delay (Destination): 1.256ns (routing 0.553ns, distribution 0.703ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       1.539     1.888    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     2.118 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.264    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.281 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.112     3.393    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X15Y347        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_10/C
  -------------------------------------------------------------------    -------------------
    SLICE_X15Y347        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.039     3.432 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_10/Q
                         net (fo=147, routed)         0.121     3.553    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/peripheral_aresetn[0]_repN_10_alias
    SLICE_X14Y347        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/clr_fifo_req_reg/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       1.708     2.156    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.861 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     2.027    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     2.046 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.256     3.302    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/c_clk_i
    SLICE_X14Y347        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/clr_fifo_req_reg/C
                         clock pessimism              0.151     3.454    
    SLICE_X14Y347        FDCE (Remov_EFF_SLICEL_C_CLR)
                                                     -0.020     3.434    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/clr_fifo_req_reg
  -------------------------------------------------------------------
                         required time                         -3.434    
                         arrival time                           3.553    
  -------------------------------------------------------------------
                         slack                                  0.119    

Slack (MET) :             0.119ns  (arrival time - required time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_10/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/gcc_wr_ptr/clear_cdc_reg/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.160ns  (logic 0.039ns (24.319%)  route 0.121ns (75.681%))
  Logic Levels:           0  
  Clock Path Skew:        0.061ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.302ns
    Source Clock Delay      (SCD):    3.393ns
    Clock Pessimism Removal (CPR):    -0.151ns
  Clock Net Delay (Source):      1.112ns (routing 0.503ns, distribution 0.609ns)
  Clock Net Delay (Destination): 1.256ns (routing 0.553ns, distribution 0.703ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       1.539     1.888    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     2.118 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.264    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.281 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.112     3.393    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X15Y347        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_10/C
  -------------------------------------------------------------------    -------------------
    SLICE_X15Y347        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.039     3.432 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_10/Q
                         net (fo=147, routed)         0.121     3.553    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/gcc_wr_ptr/peripheral_aresetn[0]_repN_10_alias
    SLICE_X14Y347        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/gcc_wr_ptr/clear_cdc_reg/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       1.708     2.156    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.861 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     2.027    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     2.046 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.256     3.302    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X14Y347        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/gcc_wr_ptr/clear_cdc_reg/C
                         clock pessimism              0.151     3.454    
    SLICE_X14Y347        FDCE (Remov_HFF2_SLICEL_C_CLR)
                                                     -0.020     3.434    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/gcc_wr_ptr/clear_cdc_reg
  -------------------------------------------------------------------
                         required time                         -3.434    
                         arrival time                           3.553    
  -------------------------------------------------------------------
                         slack                                  0.119    

Slack (MET) :             0.119ns  (arrival time - required time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_10/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/gcc_wr_ptr/clear_r_reg/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.160ns  (logic 0.039ns (24.319%)  route 0.121ns (75.681%))
  Logic Levels:           0  
  Clock Path Skew:        0.061ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.302ns
    Source Clock Delay      (SCD):    3.393ns
    Clock Pessimism Removal (CPR):    -0.151ns
  Clock Net Delay (Source):      1.112ns (routing 0.503ns, distribution 0.609ns)
  Clock Net Delay (Destination): 1.256ns (routing 0.553ns, distribution 0.703ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       1.539     1.888    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     2.118 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.264    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.281 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.112     3.393    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X15Y347        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_10/C
  -------------------------------------------------------------------    -------------------
    SLICE_X15Y347        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.039     3.432 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_10/Q
                         net (fo=147, routed)         0.121     3.553    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/gcc_wr_ptr/peripheral_aresetn[0]_repN_10_alias
    SLICE_X14Y347        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/gcc_wr_ptr/clear_r_reg/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       1.708     2.156    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.861 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     2.027    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     2.046 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.256     3.302    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X14Y347        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/gcc_wr_ptr/clear_r_reg/C
                         clock pessimism              0.151     3.454    
    SLICE_X14Y347        FDCE (Remov_EFF2_SLICEL_C_CLR)
                                                     -0.020     3.434    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/gcc_wr_ptr/clear_r_reg
  -------------------------------------------------------------------
                         required time                         -3.434    
                         arrival time                           3.553    
  -------------------------------------------------------------------
                         slack                                  0.119    

Slack (MET) :             0.120ns  (arrival time - required time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_10/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[3]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.160ns  (logic 0.039ns (24.440%)  route 0.121ns (75.560%))
  Logic Levels:           0  
  Clock Path Skew:        0.060ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.301ns
    Source Clock Delay      (SCD):    3.393ns
    Clock Pessimism Removal (CPR):    -0.151ns
  Clock Net Delay (Source):      1.112ns (routing 0.503ns, distribution 0.609ns)
  Clock Net Delay (Destination): 1.255ns (routing 0.553ns, distribution 0.702ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       1.539     1.888    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     2.118 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.264    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.281 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.112     3.393    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X15Y347        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_10/C
  -------------------------------------------------------------------    -------------------
    SLICE_X15Y347        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.039     3.432 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_10/Q
                         net (fo=147, routed)         0.121     3.552    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/gcc_wr_ptr/peripheral_aresetn[0]_repN_10_alias
    SLICE_X12Y347        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[3]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       1.708     2.156    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.861 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     2.027    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     2.046 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.255     3.301    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X12Y347        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[3]/C
                         clock pessimism              0.151     3.452    
    SLICE_X12Y347        FDCE (Remov_HFF_SLICEL_C_CLR)
                                                     -0.020     3.432    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[3]
  -------------------------------------------------------------------
                         required time                         -3.432    
                         arrival time                           3.552    
  -------------------------------------------------------------------
                         slack                                  0.120    

Slack (MET) :             0.120ns  (arrival time - required time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_10/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[5]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.160ns  (logic 0.039ns (24.440%)  route 0.121ns (75.560%))
  Logic Levels:           0  
  Clock Path Skew:        0.060ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.301ns
    Source Clock Delay      (SCD):    3.393ns
    Clock Pessimism Removal (CPR):    -0.151ns
  Clock Net Delay (Source):      1.112ns (routing 0.503ns, distribution 0.609ns)
  Clock Net Delay (Destination): 1.255ns (routing 0.553ns, distribution 0.702ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       1.539     1.888    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     2.118 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.264    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.281 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.112     3.393    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X15Y347        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_10/C
  -------------------------------------------------------------------    -------------------
    SLICE_X15Y347        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.039     3.432 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_10/Q
                         net (fo=147, routed)         0.121     3.552    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/gcc_wr_ptr/peripheral_aresetn[0]_repN_10_alias
    SLICE_X12Y347        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[5]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       1.708     2.156    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.861 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     2.027    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     2.046 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.255     3.301    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X12Y347        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[5]/C
                         clock pessimism              0.151     3.452    
    SLICE_X12Y347        FDCE (Remov_GFF_SLICEL_C_CLR)
                                                     -0.020     3.432    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[5]
  -------------------------------------------------------------------
                         required time                         -3.432    
                         arrival time                           3.552    
  -------------------------------------------------------------------
                         slack                                  0.120    

Slack (MET) :             0.120ns  (arrival time - required time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_10/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[5]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.160ns  (logic 0.039ns (24.440%)  route 0.121ns (75.560%))
  Logic Levels:           0  
  Clock Path Skew:        0.060ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.301ns
    Source Clock Delay      (SCD):    3.393ns
    Clock Pessimism Removal (CPR):    -0.151ns
  Clock Net Delay (Source):      1.112ns (routing 0.503ns, distribution 0.609ns)
  Clock Net Delay (Destination): 1.255ns (routing 0.553ns, distribution 0.702ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       1.539     1.888    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     2.118 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.264    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.281 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.112     3.393    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X15Y347        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_10/C
  -------------------------------------------------------------------    -------------------
    SLICE_X15Y347        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.039     3.432 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_10/Q
                         net (fo=147, routed)         0.121     3.552    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/gcc_wr_ptr/peripheral_aresetn[0]_repN_10_alias
    SLICE_X12Y347        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[5]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       1.708     2.156    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.861 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     2.027    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     2.046 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.255     3.301    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X12Y347        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[5]/C
                         clock pessimism              0.151     3.452    
    SLICE_X12Y347        FDCE (Remov_FFF_SLICEL_C_CLR)
                                                     -0.020     3.432    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[5]
  -------------------------------------------------------------------
                         required time                         -3.432    
                         arrival time                           3.552    
  -------------------------------------------------------------------
                         slack                                  0.120    

Slack (MET) :             0.121ns  (arrival time - required time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.div_remainder_r_reg[0]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.193ns  (logic 0.038ns (19.738%)  route 0.155ns (80.262%))
  Logic Levels:           0  
  Clock Path Skew:        0.092ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.273ns
    Source Clock Delay      (SCD):    3.335ns
    Clock Pessimism Removal (CPR):    -0.153ns
  Clock Net Delay (Source):      1.054ns (routing 0.503ns, distribution 0.551ns)
  Clock Net Delay (Destination): 1.227ns (routing 0.553ns, distribution 0.674ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       1.539     1.888    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     2.118 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.264    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.281 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.054     3.335    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X23Y349        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X23Y349        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     3.373 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/Q
                         net (fo=200, routed)         0.155     3.528    d_1_i/qick_processor_0/inst/QPROC/peripheral_aresetn[0]_repN_alias
    SLICE_X20Y353        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.div_remainder_r_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       1.708     2.156    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.861 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     2.027    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     2.046 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.227     3.273    d_1_i/qick_processor_0/inst/QPROC/c_clk_i
    SLICE_X20Y353        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.div_remainder_r_reg[0]/C
                         clock pessimism              0.153     3.427    
    SLICE_X20Y353        FDCE (Remov_EFF_SLICEM_C_CLR)
                                                     -0.020     3.407    d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.div_remainder_r_reg[0]
  -------------------------------------------------------------------
                         required time                         -3.407    
                         arrival time                           3.528    
  -------------------------------------------------------------------
                         slack                                  0.121    

Slack (MET) :             0.121ns  (arrival time - required time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.div_remainder_r_reg[1]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.193ns  (logic 0.038ns (19.738%)  route 0.155ns (80.262%))
  Logic Levels:           0  
  Clock Path Skew:        0.092ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.273ns
    Source Clock Delay      (SCD):    3.335ns
    Clock Pessimism Removal (CPR):    -0.153ns
  Clock Net Delay (Source):      1.054ns (routing 0.503ns, distribution 0.551ns)
  Clock Net Delay (Destination): 1.227ns (routing 0.553ns, distribution 0.674ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       1.539     1.888    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     2.118 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.264    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.281 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.054     3.335    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X23Y349        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X23Y349        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     3.373 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/Q
                         net (fo=200, routed)         0.155     3.528    d_1_i/qick_processor_0/inst/QPROC/peripheral_aresetn[0]_repN_alias
    SLICE_X20Y353        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.div_remainder_r_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       1.708     2.156    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.861 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     2.027    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     2.046 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.227     3.273    d_1_i/qick_processor_0/inst/QPROC/c_clk_i
    SLICE_X20Y353        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.div_remainder_r_reg[1]/C
                         clock pessimism              0.153     3.427    
    SLICE_X20Y353        FDCE (Remov_EFF2_SLICEM_C_CLR)
                                                     -0.020     3.407    d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.div_remainder_r_reg[1]
  -------------------------------------------------------------------
                         required time                         -3.407    
                         arrival time                           3.528    
  -------------------------------------------------------------------
                         slack                                  0.121    





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  clk_pl_0
  To Clock:  clk_pl_0

Setup :            0  Failing Endpoints,  Worst Slack        6.406ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.154ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             6.406ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][15]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        3.229ns  (logic 0.104ns (3.221%)  route 3.125ns (96.779%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.169ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.137ns = ( 12.137 - 10.000 ) 
    Source Clock Delay      (SCD):    2.414ns
    Clock Pessimism Removal (CPR):    0.108ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.188ns (routing 0.662ns, distribution 1.526ns)
  Clock Net Delay (Destination): 1.955ns (routing 0.598ns, distribution 1.357ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.188     2.414    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X70Y110        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X70Y110        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     2.490 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.272     3.762    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y68         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.790 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=14838, routed)       1.853     5.643    d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL_n_1
    SLICE_X31Y361        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][15]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.955    12.137    d_1_i/qick_processor_0/inst/QPROC/ps_clk_i
    SLICE_X31Y361        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][15]/C
                         clock pessimism              0.108    12.245    
                         clock uncertainty           -0.130    12.116    
    SLICE_X31Y361        FDCE (Recov_DFF_SLICEM_C_CLR)
                                                     -0.066    12.050    d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][15]
  -------------------------------------------------------------------
                         required time                         12.050    
                         arrival time                          -5.643    
  -------------------------------------------------------------------
                         slack                                  6.406    

Slack (MET) :             6.408ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][23]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        3.211ns  (logic 0.104ns (3.239%)  route 3.107ns (96.761%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.185ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.121ns = ( 12.121 - 10.000 ) 
    Source Clock Delay      (SCD):    2.414ns
    Clock Pessimism Removal (CPR):    0.108ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.188ns (routing 0.662ns, distribution 1.526ns)
  Clock Net Delay (Destination): 1.939ns (routing 0.598ns, distribution 1.341ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.188     2.414    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X70Y110        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X70Y110        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     2.490 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.272     3.762    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y68         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.790 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=14838, routed)       1.835     5.625    d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL_n_1
    SLICE_X35Y360        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][23]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.939    12.121    d_1_i/qick_processor_0/inst/QPROC/ps_clk_i
    SLICE_X35Y360        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][23]/C
                         clock pessimism              0.108    12.229    
                         clock uncertainty           -0.130    12.100    
    SLICE_X35Y360        FDCE (Recov_DFF_SLICEM_C_CLR)
                                                     -0.066    12.034    d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][23]
  -------------------------------------------------------------------
                         required time                         12.034    
                         arrival time                          -5.625    
  -------------------------------------------------------------------
                         slack                                  6.408    

Slack (MET) :             6.414ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][13]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        3.214ns  (logic 0.104ns (3.236%)  route 3.110ns (96.764%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.176ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.130ns = ( 12.130 - 10.000 ) 
    Source Clock Delay      (SCD):    2.414ns
    Clock Pessimism Removal (CPR):    0.108ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.188ns (routing 0.662ns, distribution 1.526ns)
  Clock Net Delay (Destination): 1.948ns (routing 0.598ns, distribution 1.350ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.188     2.414    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X70Y110        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X70Y110        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     2.490 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.272     3.762    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y68         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.790 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=14838, routed)       1.838     5.628    d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL_n_1
    SLICE_X32Y361        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][13]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.948    12.130    d_1_i/qick_processor_0/inst/QPROC/ps_clk_i
    SLICE_X32Y361        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][13]/C
                         clock pessimism              0.108    12.238    
                         clock uncertainty           -0.130    12.109    
    SLICE_X32Y361        FDCE (Recov_DFF_SLICEL_C_CLR)
                                                     -0.066    12.043    d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][13]
  -------------------------------------------------------------------
                         required time                         12.043    
                         arrival time                          -5.628    
  -------------------------------------------------------------------
                         slack                                  6.414    

Slack (MET) :             6.414ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][18]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        3.200ns  (logic 0.104ns (3.250%)  route 3.096ns (96.750%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.190ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.117ns = ( 12.117 - 10.000 ) 
    Source Clock Delay      (SCD):    2.414ns
    Clock Pessimism Removal (CPR):    0.108ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.188ns (routing 0.662ns, distribution 1.526ns)
  Clock Net Delay (Destination): 1.935ns (routing 0.598ns, distribution 1.337ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.188     2.414    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X70Y110        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X70Y110        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     2.490 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.272     3.762    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y68         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.790 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=14838, routed)       1.824     5.614    d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL_n_1
    SLICE_X35Y361        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][18]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.935    12.117    d_1_i/qick_processor_0/inst/QPROC/ps_clk_i
    SLICE_X35Y361        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][18]/C
                         clock pessimism              0.108    12.225    
                         clock uncertainty           -0.130    12.095    
    SLICE_X35Y361        FDCE (Recov_DFF_SLICEM_C_CLR)
                                                     -0.066    12.029    d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][18]
  -------------------------------------------------------------------
                         required time                         12.029    
                         arrival time                          -5.614    
  -------------------------------------------------------------------
                         slack                                  6.414    

Slack (MET) :             6.416ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][22]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        3.196ns  (logic 0.104ns (3.254%)  route 3.092ns (96.746%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.192ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.114ns = ( 12.114 - 10.000 ) 
    Source Clock Delay      (SCD):    2.414ns
    Clock Pessimism Removal (CPR):    0.108ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.188ns (routing 0.662ns, distribution 1.526ns)
  Clock Net Delay (Destination): 1.932ns (routing 0.598ns, distribution 1.334ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.188     2.414    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X70Y110        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X70Y110        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     2.490 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.272     3.762    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y68         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.790 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=14838, routed)       1.820     5.610    d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL_n_1
    SLICE_X36Y360        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][22]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.932    12.114    d_1_i/qick_processor_0/inst/QPROC/ps_clk_i
    SLICE_X36Y360        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][22]/C
                         clock pessimism              0.108    12.222    
                         clock uncertainty           -0.130    12.093    
    SLICE_X36Y360        FDCE (Recov_DFF_SLICEL_C_CLR)
                                                     -0.066    12.027    d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][22]
  -------------------------------------------------------------------
                         required time                         12.027    
                         arrival time                          -5.610    
  -------------------------------------------------------------------
                         slack                                  6.416    

Slack (MET) :             6.416ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[0][23]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        3.197ns  (logic 0.104ns (3.253%)  route 3.093ns (96.747%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.191ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.116ns = ( 12.116 - 10.000 ) 
    Source Clock Delay      (SCD):    2.414ns
    Clock Pessimism Removal (CPR):    0.108ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.188ns (routing 0.662ns, distribution 1.526ns)
  Clock Net Delay (Destination): 1.934ns (routing 0.598ns, distribution 1.336ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.188     2.414    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X70Y110        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X70Y110        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     2.490 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.272     3.762    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y68         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.790 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=14838, routed)       1.821     5.611    d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL_n_1
    SLICE_X35Y361        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[0][23]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.934    12.116    d_1_i/qick_processor_0/inst/QPROC/ps_clk_i
    SLICE_X35Y361        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[0][23]/C
                         clock pessimism              0.108    12.224    
                         clock uncertainty           -0.130    12.094    
    SLICE_X35Y361        FDCE (Recov_HFF_SLICEM_C_CLR)
                                                     -0.066    12.028    d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[0][23]
  -------------------------------------------------------------------
                         required time                         12.028    
                         arrival time                          -5.611    
  -------------------------------------------------------------------
                         slack                                  6.416    

Slack (MET) :             6.420ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][17]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        3.185ns  (logic 0.104ns (3.265%)  route 3.081ns (96.735%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.200ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.107ns = ( 12.107 - 10.000 ) 
    Source Clock Delay      (SCD):    2.414ns
    Clock Pessimism Removal (CPR):    0.108ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.188ns (routing 0.662ns, distribution 1.526ns)
  Clock Net Delay (Destination): 1.925ns (routing 0.598ns, distribution 1.327ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.188     2.414    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X70Y110        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X70Y110        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     2.490 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.272     3.762    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y68         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.790 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=14838, routed)       1.809     5.599    d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL_n_1
    SLICE_X37Y366        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][17]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.925    12.107    d_1_i/qick_processor_0/inst/QPROC/ps_clk_i
    SLICE_X37Y366        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][17]/C
                         clock pessimism              0.108    12.215    
                         clock uncertainty           -0.130    12.085    
    SLICE_X37Y366        FDCE (Recov_DFF_SLICEM_C_CLR)
                                                     -0.066    12.019    d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][17]
  -------------------------------------------------------------------
                         required time                         12.019    
                         arrival time                          -5.599    
  -------------------------------------------------------------------
                         slack                                  6.420    

Slack (MET) :             6.421ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][27]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        3.220ns  (logic 0.104ns (3.230%)  route 3.116ns (96.770%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.164ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.143ns = ( 12.143 - 10.000 ) 
    Source Clock Delay      (SCD):    2.414ns
    Clock Pessimism Removal (CPR):    0.108ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.188ns (routing 0.662ns, distribution 1.526ns)
  Clock Net Delay (Destination): 1.961ns (routing 0.598ns, distribution 1.363ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.188     2.414    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X70Y110        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X70Y110        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     2.490 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.272     3.762    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y68         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.790 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=14838, routed)       1.844     5.634    d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL_n_1
    SLICE_X24Y362        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][27]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.961    12.143    d_1_i/qick_processor_0/inst/QPROC/ps_clk_i
    SLICE_X24Y362        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][27]/C
                         clock pessimism              0.108    12.251    
                         clock uncertainty           -0.130    12.121    
    SLICE_X24Y362        FDCE (Recov_DFF_SLICEM_C_CLR)
                                                     -0.066    12.055    d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][27]
  -------------------------------------------------------------------
                         required time                         12.055    
                         arrival time                          -5.634    
  -------------------------------------------------------------------
                         slack                                  6.421    

Slack (MET) :             6.421ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][6]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        3.219ns  (logic 0.104ns (3.231%)  route 3.115ns (96.769%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.165ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.142ns = ( 12.142 - 10.000 ) 
    Source Clock Delay      (SCD):    2.414ns
    Clock Pessimism Removal (CPR):    0.108ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.188ns (routing 0.662ns, distribution 1.526ns)
  Clock Net Delay (Destination): 1.960ns (routing 0.598ns, distribution 1.362ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.188     2.414    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X70Y110        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X70Y110        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     2.490 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.272     3.762    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y68         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.790 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=14838, routed)       1.843     5.633    d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL_n_1
    SLICE_X24Y365        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][6]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.960    12.142    d_1_i/qick_processor_0/inst/QPROC/ps_clk_i
    SLICE_X24Y365        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][6]/C
                         clock pessimism              0.108    12.250    
                         clock uncertainty           -0.130    12.120    
    SLICE_X24Y365        FDCE (Recov_DFF_SLICEM_C_CLR)
                                                     -0.066    12.054    d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][6]
  -------------------------------------------------------------------
                         required time                         12.054    
                         arrival time                          -5.633    
  -------------------------------------------------------------------
                         slack                                  6.421    

Slack (MET) :             6.421ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][8]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        3.219ns  (logic 0.104ns (3.231%)  route 3.115ns (96.769%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.165ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.142ns = ( 12.142 - 10.000 ) 
    Source Clock Delay      (SCD):    2.414ns
    Clock Pessimism Removal (CPR):    0.108ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.188ns (routing 0.662ns, distribution 1.526ns)
  Clock Net Delay (Destination): 1.960ns (routing 0.598ns, distribution 1.362ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.188     2.414    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X70Y110        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X70Y110        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     2.490 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.272     3.762    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y68         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.790 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=14838, routed)       1.843     5.633    d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL_n_1
    SLICE_X24Y365        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][8]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.960    12.142    d_1_i/qick_processor_0/inst/QPROC/ps_clk_i
    SLICE_X24Y365        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][8]/C
                         clock pessimism              0.108    12.250    
                         clock uncertainty           -0.130    12.120    
    SLICE_X24Y365        FDCE (Recov_CFF_SLICEM_C_CLR)
                                                     -0.066    12.054    d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][8]
  -------------------------------------------------------------------
                         required time                         12.054    
                         arrival time                          -5.633    
  -------------------------------------------------------------------
                         slack                                  6.421    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.154ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[1]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.188ns  (logic 0.053ns (28.242%)  route 0.135ns (71.758%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.054ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.592ns
    Source Clock Delay      (SCD):    1.399ns
    Clock Pessimism Removal (CPR):    0.140ns
  Clock Net Delay (Source):      1.279ns (routing 0.358ns, distribution 0.921ns)
  Clock Net Delay (Destination): 1.445ns (routing 0.404ns, distribution 1.041ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.279     1.399    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
    SLICE_X85Y41         FDRE                                         r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y41         FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     1.438 f  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/Q
                         net (fo=3, routed)           0.029     1.466    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[0]
    SLICE_X85Y41         LUT3 (Prop_G6LUT_SLICEL_I1_O)
                                                      0.014     1.480 f  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                         net (fo=32, routed)          0.106     1.586    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0]
    SLICE_X86Y41         FDCE                                         f  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[1]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.445     1.592    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/clk
    SLICE_X86Y41         FDCE                                         r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[1]/C
                         clock pessimism             -0.140     1.452    
    SLICE_X86Y41         FDCE (Remov_AFF_SLICEM_C_CLR)
                                                     -0.020     1.432    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[1]
  -------------------------------------------------------------------
                         required time                         -1.432    
                         arrival time                           1.586    
  -------------------------------------------------------------------
                         slack                                  0.154    

Slack (MET) :             0.154ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[2]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.188ns  (logic 0.053ns (28.242%)  route 0.135ns (71.758%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.054ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.592ns
    Source Clock Delay      (SCD):    1.399ns
    Clock Pessimism Removal (CPR):    0.140ns
  Clock Net Delay (Source):      1.279ns (routing 0.358ns, distribution 0.921ns)
  Clock Net Delay (Destination): 1.445ns (routing 0.404ns, distribution 1.041ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.279     1.399    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
    SLICE_X85Y41         FDRE                                         r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y41         FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     1.438 f  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/Q
                         net (fo=3, routed)           0.029     1.466    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[0]
    SLICE_X85Y41         LUT3 (Prop_G6LUT_SLICEL_I1_O)
                                                      0.014     1.480 f  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                         net (fo=32, routed)          0.106     1.586    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0]
    SLICE_X86Y41         FDCE                                         f  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[2]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.445     1.592    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/clk
    SLICE_X86Y41         FDCE                                         r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[2]/C
                         clock pessimism             -0.140     1.452    
    SLICE_X86Y41         FDCE (Remov_BFF2_SLICEM_C_CLR)
                                                     -0.020     1.432    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[2]
  -------------------------------------------------------------------
                         required time                         -1.432    
                         arrival time                           1.586    
  -------------------------------------------------------------------
                         slack                                  0.154    

Slack (MET) :             0.154ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[3]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.188ns  (logic 0.053ns (28.242%)  route 0.135ns (71.758%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.054ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.592ns
    Source Clock Delay      (SCD):    1.399ns
    Clock Pessimism Removal (CPR):    0.140ns
  Clock Net Delay (Source):      1.279ns (routing 0.358ns, distribution 0.921ns)
  Clock Net Delay (Destination): 1.445ns (routing 0.404ns, distribution 1.041ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.279     1.399    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
    SLICE_X85Y41         FDRE                                         r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y41         FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     1.438 f  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/Q
                         net (fo=3, routed)           0.029     1.466    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[0]
    SLICE_X85Y41         LUT3 (Prop_G6LUT_SLICEL_I1_O)
                                                      0.014     1.480 f  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                         net (fo=32, routed)          0.106     1.586    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0]
    SLICE_X86Y41         FDCE                                         f  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[3]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.445     1.592    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/clk
    SLICE_X86Y41         FDCE                                         r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[3]/C
                         clock pessimism             -0.140     1.452    
    SLICE_X86Y41         FDCE (Remov_CFF_SLICEM_C_CLR)
                                                     -0.020     1.432    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[3]
  -------------------------------------------------------------------
                         required time                         -1.432    
                         arrival time                           1.586    
  -------------------------------------------------------------------
                         slack                                  0.154    

Slack (MET) :             0.154ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[4]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.188ns  (logic 0.053ns (28.242%)  route 0.135ns (71.758%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.054ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.592ns
    Source Clock Delay      (SCD):    1.399ns
    Clock Pessimism Removal (CPR):    0.140ns
  Clock Net Delay (Source):      1.279ns (routing 0.358ns, distribution 0.921ns)
  Clock Net Delay (Destination): 1.445ns (routing 0.404ns, distribution 1.041ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.279     1.399    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
    SLICE_X85Y41         FDRE                                         r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y41         FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     1.438 f  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/Q
                         net (fo=3, routed)           0.029     1.466    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[0]
    SLICE_X85Y41         LUT3 (Prop_G6LUT_SLICEL_I1_O)
                                                      0.014     1.480 f  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                         net (fo=32, routed)          0.106     1.586    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0]
    SLICE_X86Y41         FDCE                                         f  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[4]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.445     1.592    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/clk
    SLICE_X86Y41         FDCE                                         r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[4]/C
                         clock pessimism             -0.140     1.452    
    SLICE_X86Y41         FDCE (Remov_CFF2_SLICEM_C_CLR)
                                                     -0.020     1.432    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[4]
  -------------------------------------------------------------------
                         required time                         -1.432    
                         arrival time                           1.586    
  -------------------------------------------------------------------
                         slack                                  0.154    

Slack (MET) :             0.155ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[2]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.187ns  (logic 0.053ns (28.393%)  route 0.134ns (71.607%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.052ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.590ns
    Source Clock Delay      (SCD):    1.399ns
    Clock Pessimism Removal (CPR):    0.140ns
  Clock Net Delay (Source):      1.279ns (routing 0.358ns, distribution 0.921ns)
  Clock Net Delay (Destination): 1.443ns (routing 0.404ns, distribution 1.039ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.279     1.399    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
    SLICE_X85Y41         FDRE                                         r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y41         FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     1.438 f  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/Q
                         net (fo=3, routed)           0.029     1.466    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[0]
    SLICE_X85Y41         LUT3 (Prop_G6LUT_SLICEL_I1_O)
                                                      0.014     1.480 f  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                         net (fo=32, routed)          0.105     1.585    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0]
    SLICE_X86Y41         FDCE                                         f  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[2]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.443     1.590    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/clk
    SLICE_X86Y41         FDCE                                         r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[2]/C
                         clock pessimism             -0.140     1.450    
    SLICE_X86Y41         FDCE (Remov_EFF_SLICEM_C_CLR)
                                                     -0.020     1.430    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[2]
  -------------------------------------------------------------------
                         required time                         -1.430    
                         arrival time                           1.585    
  -------------------------------------------------------------------
                         slack                                  0.155    

Slack (MET) :             0.155ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[3]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.187ns  (logic 0.053ns (28.393%)  route 0.134ns (71.607%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.052ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.590ns
    Source Clock Delay      (SCD):    1.399ns
    Clock Pessimism Removal (CPR):    0.140ns
  Clock Net Delay (Source):      1.279ns (routing 0.358ns, distribution 0.921ns)
  Clock Net Delay (Destination): 1.443ns (routing 0.404ns, distribution 1.039ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.279     1.399    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
    SLICE_X85Y41         FDRE                                         r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y41         FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     1.438 f  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/Q
                         net (fo=3, routed)           0.029     1.466    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[0]
    SLICE_X85Y41         LUT3 (Prop_G6LUT_SLICEL_I1_O)
                                                      0.014     1.480 f  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                         net (fo=32, routed)          0.105     1.585    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0]
    SLICE_X86Y41         FDCE                                         f  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[3]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.443     1.590    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/clk
    SLICE_X86Y41         FDCE                                         r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[3]/C
                         clock pessimism             -0.140     1.450    
    SLICE_X86Y41         FDCE (Remov_EFF2_SLICEM_C_CLR)
                                                     -0.020     1.430    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[3]
  -------------------------------------------------------------------
                         required time                         -1.430    
                         arrival time                           1.585    
  -------------------------------------------------------------------
                         slack                                  0.155    

Slack (MET) :             0.155ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[4]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.187ns  (logic 0.053ns (28.393%)  route 0.134ns (71.607%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.052ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.590ns
    Source Clock Delay      (SCD):    1.399ns
    Clock Pessimism Removal (CPR):    0.140ns
  Clock Net Delay (Source):      1.279ns (routing 0.358ns, distribution 0.921ns)
  Clock Net Delay (Destination): 1.443ns (routing 0.404ns, distribution 1.039ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.279     1.399    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
    SLICE_X85Y41         FDRE                                         r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y41         FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     1.438 f  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/Q
                         net (fo=3, routed)           0.029     1.466    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[0]
    SLICE_X85Y41         LUT3 (Prop_G6LUT_SLICEL_I1_O)
                                                      0.014     1.480 f  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                         net (fo=32, routed)          0.105     1.585    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0]
    SLICE_X86Y41         FDCE                                         f  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[4]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.443     1.590    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/clk
    SLICE_X86Y41         FDCE                                         r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[4]/C
                         clock pessimism             -0.140     1.450    
    SLICE_X86Y41         FDCE (Remov_FFF_SLICEM_C_CLR)
                                                     -0.020     1.430    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[4]
  -------------------------------------------------------------------
                         required time                         -1.430    
                         arrival time                           1.585    
  -------------------------------------------------------------------
                         slack                                  0.155    

Slack (MET) :             0.155ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[1]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.187ns  (logic 0.053ns (28.393%)  route 0.134ns (71.607%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.052ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.590ns
    Source Clock Delay      (SCD):    1.399ns
    Clock Pessimism Removal (CPR):    0.140ns
  Clock Net Delay (Source):      1.279ns (routing 0.358ns, distribution 0.921ns)
  Clock Net Delay (Destination): 1.443ns (routing 0.404ns, distribution 1.039ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.279     1.399    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
    SLICE_X85Y41         FDRE                                         r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y41         FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     1.438 f  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/Q
                         net (fo=3, routed)           0.029     1.466    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[0]
    SLICE_X85Y41         LUT3 (Prop_G6LUT_SLICEL_I1_O)
                                                      0.014     1.480 f  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                         net (fo=32, routed)          0.105     1.585    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0]
    SLICE_X86Y41         FDCE                                         f  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[1]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.443     1.590    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/clk
    SLICE_X86Y41         FDCE                                         r  d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[1]/C
                         clock pessimism             -0.140     1.450    
    SLICE_X86Y41         FDCE (Remov_FFF2_SLICEM_C_CLR)
                                                     -0.020     1.430    d_1_i/ps8_0_axi_periph/i01_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[1]
  -------------------------------------------------------------------
                         required time                         -1.430    
                         arrival time                           1.585    
  -------------------------------------------------------------------
                         slack                                  0.155    

Slack (MET) :             0.161ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[1]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.158ns  (logic 0.053ns (33.583%)  route 0.105ns (66.417%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.016ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.607ns
    Source Clock Delay      (SCD):    1.413ns
    Clock Pessimism Removal (CPR):    0.178ns
  Clock Net Delay (Source):      1.293ns (routing 0.358ns, distribution 0.935ns)
  Clock Net Delay (Destination): 1.460ns (routing 0.404ns, distribution 1.056ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.293     1.413    d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
    SLICE_X91Y9          FDRE                                         r  d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y9          FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     1.452 f  d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/Q
                         net (fo=3, routed)           0.027     1.479    d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[0]
    SLICE_X91Y9          LUT3 (Prop_G6LUT_SLICEL_I1_O)
                                                      0.014     1.493 f  d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                         net (fo=32, routed)          0.078     1.571    d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[4]_1
    SLICE_X90Y9          FDCE                                         f  d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[1]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.460     1.607    d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/clk
    SLICE_X90Y9          FDCE                                         r  d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[1]/C
                         clock pessimism             -0.178     1.430    
    SLICE_X90Y9          FDCE (Remov_EFF_SLICEM_C_CLR)
                                                     -0.020     1.410    d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[1]
  -------------------------------------------------------------------
                         required time                         -1.410    
                         arrival time                           1.571    
  -------------------------------------------------------------------
                         slack                                  0.161    

Slack (MET) :             0.161ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[2]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.158ns  (logic 0.053ns (33.583%)  route 0.105ns (66.417%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.016ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.607ns
    Source Clock Delay      (SCD):    1.413ns
    Clock Pessimism Removal (CPR):    0.178ns
  Clock Net Delay (Source):      1.293ns (routing 0.358ns, distribution 0.935ns)
  Clock Net Delay (Destination): 1.460ns (routing 0.404ns, distribution 1.056ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.293     1.413    d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
    SLICE_X91Y9          FDRE                                         r  d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y9          FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     1.452 f  d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/Q
                         net (fo=3, routed)           0.027     1.479    d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[0]
    SLICE_X91Y9          LUT3 (Prop_G6LUT_SLICEL_I1_O)
                                                      0.014     1.493 f  d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                         net (fo=32, routed)          0.078     1.571    d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[4]_1
    SLICE_X90Y9          FDCE                                         f  d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[2]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.460     1.607    d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/clk
    SLICE_X90Y9          FDCE                                         r  d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[2]/C
                         clock pessimism             -0.178     1.430    
    SLICE_X90Y9          FDCE (Remov_EFF2_SLICEM_C_CLR)
                                                     -0.020     1.410    d_1_i/ps8_0_axi_periph/m26_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[2]
  -------------------------------------------------------------------
                         required time                         -1.410    
                         arrival time                           1.571    
  -------------------------------------------------------------------
                         slack                                  0.161    





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  To Clock:  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK

Setup :            0  Failing Endpoints,  Worst Slack       46.371ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.130ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             46.371ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[14]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            50.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        3.371ns  (logic 0.303ns (8.988%)  route 3.068ns (91.012%))
  Logic Levels:           2  (LUT4=1 LUT6=1)
  Clock Path Skew:        -0.156ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.445ns = ( 55.445 - 50.000 ) 
    Source Clock Delay      (SCD):    10.808ns
    Clock Pessimism Removal (CPR):    5.207ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.914ns (routing 1.680ns, distribution 1.234ns)
  Clock Net Delay (Destination): 2.603ns (routing 1.525ns, distribution 1.078ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.566     7.866    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.894 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.914    10.808    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X107Y113       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X107Y113       FDRE (Prop_EFF2_SLICEM_C_Q)
                                                      0.079    10.887 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[2]/Q
                         net (fo=1, routed)           0.153    11.040    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno[2]
    SLICE_X107Y113       LUT6 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.125    11.165 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1/O
                         net (fo=5, routed)           0.162    11.327    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1_n_0
    SLICE_X107Y114       LUT4 (Prop_G5LUT_SLICEM_I3_O)
                                                      0.099    11.426 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_sel[0]_INST_0/O
                         net (fo=11, routed)          2.753    14.179    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]_0
    SLICE_X113Y327       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[14]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.353    52.818    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    52.842 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.603    55.445    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
    SLICE_X113Y327       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[14]/C
                         clock pessimism              5.207    60.652    
                         clock uncertainty           -0.035    60.616    
    SLICE_X113Y327       FDCE (Recov_AFF_SLICEM_C_CLR)
                                                     -0.066    60.550    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[14]
  -------------------------------------------------------------------
                         required time                         60.550    
                         arrival time                         -14.179    
  -------------------------------------------------------------------
                         slack                                 46.371    

Slack (MET) :             46.371ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[15]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            50.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        3.371ns  (logic 0.303ns (8.988%)  route 3.068ns (91.012%))
  Logic Levels:           2  (LUT4=1 LUT6=1)
  Clock Path Skew:        -0.156ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.445ns = ( 55.445 - 50.000 ) 
    Source Clock Delay      (SCD):    10.808ns
    Clock Pessimism Removal (CPR):    5.207ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.914ns (routing 1.680ns, distribution 1.234ns)
  Clock Net Delay (Destination): 2.603ns (routing 1.525ns, distribution 1.078ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.566     7.866    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.894 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.914    10.808    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X107Y113       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X107Y113       FDRE (Prop_EFF2_SLICEM_C_Q)
                                                      0.079    10.887 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[2]/Q
                         net (fo=1, routed)           0.153    11.040    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno[2]
    SLICE_X107Y113       LUT6 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.125    11.165 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1/O
                         net (fo=5, routed)           0.162    11.327    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1_n_0
    SLICE_X107Y114       LUT4 (Prop_G5LUT_SLICEM_I3_O)
                                                      0.099    11.426 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_sel[0]_INST_0/O
                         net (fo=11, routed)          2.753    14.179    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]_0
    SLICE_X113Y327       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[15]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.353    52.818    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    52.842 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.603    55.445    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
    SLICE_X113Y327       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[15]/C
                         clock pessimism              5.207    60.652    
                         clock uncertainty           -0.035    60.616    
    SLICE_X113Y327       FDCE (Recov_AFF2_SLICEM_C_CLR)
                                                     -0.066    60.550    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[15]
  -------------------------------------------------------------------
                         required time                         60.550    
                         arrival time                         -14.179    
  -------------------------------------------------------------------
                         slack                                 46.371    

Slack (MET) :             46.373ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[10]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            50.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        3.368ns  (logic 0.303ns (8.996%)  route 3.065ns (91.004%))
  Logic Levels:           2  (LUT4=1 LUT6=1)
  Clock Path Skew:        -0.157ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.444ns = ( 55.444 - 50.000 ) 
    Source Clock Delay      (SCD):    10.808ns
    Clock Pessimism Removal (CPR):    5.207ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.914ns (routing 1.680ns, distribution 1.234ns)
  Clock Net Delay (Destination): 2.602ns (routing 1.525ns, distribution 1.077ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.566     7.866    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.894 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.914    10.808    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X107Y113       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X107Y113       FDRE (Prop_EFF2_SLICEM_C_Q)
                                                      0.079    10.887 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[2]/Q
                         net (fo=1, routed)           0.153    11.040    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno[2]
    SLICE_X107Y113       LUT6 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.125    11.165 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1/O
                         net (fo=5, routed)           0.162    11.327    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1_n_0
    SLICE_X107Y114       LUT4 (Prop_G5LUT_SLICEM_I3_O)
                                                      0.099    11.426 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_sel[0]_INST_0/O
                         net (fo=11, routed)          2.750    14.176    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]_0
    SLICE_X113Y327       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[10]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.353    52.818    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    52.842 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.602    55.444    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
    SLICE_X113Y327       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[10]/C
                         clock pessimism              5.207    60.651    
                         clock uncertainty           -0.035    60.615    
    SLICE_X113Y327       FDCE (Recov_EFF_SLICEM_C_CLR)
                                                     -0.066    60.549    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[10]
  -------------------------------------------------------------------
                         required time                         60.549    
                         arrival time                         -14.176    
  -------------------------------------------------------------------
                         slack                                 46.373    

Slack (MET) :             46.373ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[11]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            50.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        3.368ns  (logic 0.303ns (8.996%)  route 3.065ns (91.004%))
  Logic Levels:           2  (LUT4=1 LUT6=1)
  Clock Path Skew:        -0.157ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.444ns = ( 55.444 - 50.000 ) 
    Source Clock Delay      (SCD):    10.808ns
    Clock Pessimism Removal (CPR):    5.207ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.914ns (routing 1.680ns, distribution 1.234ns)
  Clock Net Delay (Destination): 2.602ns (routing 1.525ns, distribution 1.077ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.566     7.866    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.894 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.914    10.808    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X107Y113       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X107Y113       FDRE (Prop_EFF2_SLICEM_C_Q)
                                                      0.079    10.887 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[2]/Q
                         net (fo=1, routed)           0.153    11.040    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno[2]
    SLICE_X107Y113       LUT6 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.125    11.165 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1/O
                         net (fo=5, routed)           0.162    11.327    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1_n_0
    SLICE_X107Y114       LUT4 (Prop_G5LUT_SLICEM_I3_O)
                                                      0.099    11.426 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_sel[0]_INST_0/O
                         net (fo=11, routed)          2.750    14.176    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]_0
    SLICE_X113Y327       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[11]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.353    52.818    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    52.842 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.602    55.444    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
    SLICE_X113Y327       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[11]/C
                         clock pessimism              5.207    60.651    
                         clock uncertainty           -0.035    60.615    
    SLICE_X113Y327       FDCE (Recov_EFF2_SLICEM_C_CLR)
                                                     -0.066    60.549    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[11]
  -------------------------------------------------------------------
                         required time                         60.549    
                         arrival time                         -14.176    
  -------------------------------------------------------------------
                         slack                                 46.373    

Slack (MET) :             46.373ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[12]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            50.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        3.368ns  (logic 0.303ns (8.996%)  route 3.065ns (91.004%))
  Logic Levels:           2  (LUT4=1 LUT6=1)
  Clock Path Skew:        -0.157ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.444ns = ( 55.444 - 50.000 ) 
    Source Clock Delay      (SCD):    10.808ns
    Clock Pessimism Removal (CPR):    5.207ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.914ns (routing 1.680ns, distribution 1.234ns)
  Clock Net Delay (Destination): 2.602ns (routing 1.525ns, distribution 1.077ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.566     7.866    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.894 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.914    10.808    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X107Y113       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X107Y113       FDRE (Prop_EFF2_SLICEM_C_Q)
                                                      0.079    10.887 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[2]/Q
                         net (fo=1, routed)           0.153    11.040    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno[2]
    SLICE_X107Y113       LUT6 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.125    11.165 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1/O
                         net (fo=5, routed)           0.162    11.327    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1_n_0
    SLICE_X107Y114       LUT4 (Prop_G5LUT_SLICEM_I3_O)
                                                      0.099    11.426 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_sel[0]_INST_0/O
                         net (fo=11, routed)          2.750    14.176    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]_0
    SLICE_X113Y327       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[12]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.353    52.818    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    52.842 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.602    55.444    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
    SLICE_X113Y327       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[12]/C
                         clock pessimism              5.207    60.651    
                         clock uncertainty           -0.035    60.615    
    SLICE_X113Y327       FDCE (Recov_FFF_SLICEM_C_CLR)
                                                     -0.066    60.549    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[12]
  -------------------------------------------------------------------
                         required time                         60.549    
                         arrival time                         -14.176    
  -------------------------------------------------------------------
                         slack                                 46.373    

Slack (MET) :             46.373ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[13]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            50.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        3.368ns  (logic 0.303ns (8.996%)  route 3.065ns (91.004%))
  Logic Levels:           2  (LUT4=1 LUT6=1)
  Clock Path Skew:        -0.157ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.444ns = ( 55.444 - 50.000 ) 
    Source Clock Delay      (SCD):    10.808ns
    Clock Pessimism Removal (CPR):    5.207ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.914ns (routing 1.680ns, distribution 1.234ns)
  Clock Net Delay (Destination): 2.602ns (routing 1.525ns, distribution 1.077ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.566     7.866    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.894 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.914    10.808    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X107Y113       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X107Y113       FDRE (Prop_EFF2_SLICEM_C_Q)
                                                      0.079    10.887 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[2]/Q
                         net (fo=1, routed)           0.153    11.040    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno[2]
    SLICE_X107Y113       LUT6 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.125    11.165 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1/O
                         net (fo=5, routed)           0.162    11.327    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1_n_0
    SLICE_X107Y114       LUT4 (Prop_G5LUT_SLICEM_I3_O)
                                                      0.099    11.426 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_sel[0]_INST_0/O
                         net (fo=11, routed)          2.750    14.176    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]_0
    SLICE_X113Y327       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[13]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.353    52.818    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    52.842 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.602    55.444    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
    SLICE_X113Y327       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[13]/C
                         clock pessimism              5.207    60.651    
                         clock uncertainty           -0.035    60.615    
    SLICE_X113Y327       FDCE (Recov_FFF2_SLICEM_C_CLR)
                                                     -0.066    60.549    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[13]
  -------------------------------------------------------------------
                         required time                         60.549    
                         arrival time                         -14.176    
  -------------------------------------------------------------------
                         slack                                 46.373    

Slack (MET) :             46.373ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            50.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        3.368ns  (logic 0.303ns (8.996%)  route 3.065ns (91.004%))
  Logic Levels:           2  (LUT4=1 LUT6=1)
  Clock Path Skew:        -0.157ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.444ns = ( 55.444 - 50.000 ) 
    Source Clock Delay      (SCD):    10.808ns
    Clock Pessimism Removal (CPR):    5.207ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.914ns (routing 1.680ns, distribution 1.234ns)
  Clock Net Delay (Destination): 2.602ns (routing 1.525ns, distribution 1.077ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.566     7.866    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.894 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.914    10.808    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X107Y113       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X107Y113       FDRE (Prop_EFF2_SLICEM_C_Q)
                                                      0.079    10.887 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[2]/Q
                         net (fo=1, routed)           0.153    11.040    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno[2]
    SLICE_X107Y113       LUT6 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.125    11.165 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1/O
                         net (fo=5, routed)           0.162    11.327    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1_n_0
    SLICE_X107Y114       LUT4 (Prop_G5LUT_SLICEM_I3_O)
                                                      0.099    11.426 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_sel[0]_INST_0/O
                         net (fo=11, routed)          2.750    14.176    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]_0
    SLICE_X113Y327       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.353    52.818    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    52.842 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.602    55.444    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
    SLICE_X113Y327       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]/C
                         clock pessimism              5.207    60.651    
                         clock uncertainty           -0.035    60.615    
    SLICE_X113Y327       FDCE (Recov_GFF_SLICEM_C_CLR)
                                                     -0.066    60.549    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]
  -------------------------------------------------------------------
                         required time                         60.549    
                         arrival time                         -14.176    
  -------------------------------------------------------------------
                         slack                                 46.373    

Slack (MET) :             46.373ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[7]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            50.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        3.368ns  (logic 0.303ns (8.996%)  route 3.065ns (91.004%))
  Logic Levels:           2  (LUT4=1 LUT6=1)
  Clock Path Skew:        -0.157ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.444ns = ( 55.444 - 50.000 ) 
    Source Clock Delay      (SCD):    10.808ns
    Clock Pessimism Removal (CPR):    5.207ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.914ns (routing 1.680ns, distribution 1.234ns)
  Clock Net Delay (Destination): 2.602ns (routing 1.525ns, distribution 1.077ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.566     7.866    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.894 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.914    10.808    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X107Y113       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X107Y113       FDRE (Prop_EFF2_SLICEM_C_Q)
                                                      0.079    10.887 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[2]/Q
                         net (fo=1, routed)           0.153    11.040    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno[2]
    SLICE_X107Y113       LUT6 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.125    11.165 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1/O
                         net (fo=5, routed)           0.162    11.327    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1_n_0
    SLICE_X107Y114       LUT4 (Prop_G5LUT_SLICEM_I3_O)
                                                      0.099    11.426 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_sel[0]_INST_0/O
                         net (fo=11, routed)          2.750    14.176    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]_0
    SLICE_X113Y327       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[7]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.353    52.818    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    52.842 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.602    55.444    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
    SLICE_X113Y327       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[7]/C
                         clock pessimism              5.207    60.651    
                         clock uncertainty           -0.035    60.615    
    SLICE_X113Y327       FDCE (Recov_GFF2_SLICEM_C_CLR)
                                                     -0.066    60.549    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[7]
  -------------------------------------------------------------------
                         required time                         60.549    
                         arrival time                         -14.176    
  -------------------------------------------------------------------
                         slack                                 46.373    

Slack (MET) :             46.373ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[8]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            50.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        3.368ns  (logic 0.303ns (8.996%)  route 3.065ns (91.004%))
  Logic Levels:           2  (LUT4=1 LUT6=1)
  Clock Path Skew:        -0.157ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.444ns = ( 55.444 - 50.000 ) 
    Source Clock Delay      (SCD):    10.808ns
    Clock Pessimism Removal (CPR):    5.207ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.914ns (routing 1.680ns, distribution 1.234ns)
  Clock Net Delay (Destination): 2.602ns (routing 1.525ns, distribution 1.077ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.566     7.866    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.894 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.914    10.808    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X107Y113       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X107Y113       FDRE (Prop_EFF2_SLICEM_C_Q)
                                                      0.079    10.887 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[2]/Q
                         net (fo=1, routed)           0.153    11.040    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno[2]
    SLICE_X107Y113       LUT6 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.125    11.165 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1/O
                         net (fo=5, routed)           0.162    11.327    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1_n_0
    SLICE_X107Y114       LUT4 (Prop_G5LUT_SLICEM_I3_O)
                                                      0.099    11.426 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_sel[0]_INST_0/O
                         net (fo=11, routed)          2.750    14.176    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]_0
    SLICE_X113Y327       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[8]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.353    52.818    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    52.842 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.602    55.444    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
    SLICE_X113Y327       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[8]/C
                         clock pessimism              5.207    60.651    
                         clock uncertainty           -0.035    60.615    
    SLICE_X113Y327       FDCE (Recov_HFF_SLICEM_C_CLR)
                                                     -0.066    60.549    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[8]
  -------------------------------------------------------------------
                         required time                         60.549    
                         arrival time                         -14.176    
  -------------------------------------------------------------------
                         slack                                 46.373    

Slack (MET) :             46.373ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[9]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            50.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        3.368ns  (logic 0.303ns (8.996%)  route 3.065ns (91.004%))
  Logic Levels:           2  (LUT4=1 LUT6=1)
  Clock Path Skew:        -0.157ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.444ns = ( 55.444 - 50.000 ) 
    Source Clock Delay      (SCD):    10.808ns
    Clock Pessimism Removal (CPR):    5.207ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.914ns (routing 1.680ns, distribution 1.234ns)
  Clock Net Delay (Destination): 2.602ns (routing 1.525ns, distribution 1.077ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.566     7.866    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.894 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.914    10.808    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X107Y113       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X107Y113       FDRE (Prop_EFF2_SLICEM_C_Q)
                                                      0.079    10.887 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[2]/Q
                         net (fo=1, routed)           0.153    11.040    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno[2]
    SLICE_X107Y113       LUT6 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.125    11.165 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1/O
                         net (fo=5, routed)           0.162    11.327    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1_n_0
    SLICE_X107Y114       LUT4 (Prop_G5LUT_SLICEM_I3_O)
                                                      0.099    11.426 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_sel[0]_INST_0/O
                         net (fo=11, routed)          2.750    14.176    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]_0
    SLICE_X113Y327       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[9]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.353    52.818    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    52.842 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.602    55.444    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
    SLICE_X113Y327       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[9]/C
                         clock pessimism              5.207    60.651    
                         clock uncertainty           -0.035    60.615    
    SLICE_X113Y327       FDCE (Recov_HFF2_SLICEM_C_CLR)
                                                     -0.066    60.549    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[9]
  -------------------------------------------------------------------
                         required time                         60.549    
                         arrival time                         -14.176    
  -------------------------------------------------------------------
                         slack                                 46.373    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.130ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
                            (rising edge-triggered cell FDPE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_o_i_reg/PRE
                            (removal check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.142ns  (logic 0.039ns (27.531%)  route 0.103ns (72.469%))
  Logic Levels:           0  
  Clock Path Skew:        0.032ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.579ns
    Source Clock Delay      (SCD):    3.937ns
    Clock Pessimism Removal (CPR):    4.610ns
  Clock Net Delay (Source):      1.594ns (routing 0.916ns, distribution 0.678ns)
  Clock Net Delay (Destination): 1.810ns (routing 1.028ns, distribution 0.782ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.861     2.326    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.343 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.594     3.937    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
    SLICE_X111Y342       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X111Y342       FDPE (Prop_FFF_SLICEL_C_Q)
                                                      0.039     3.976 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/Q
                         net (fo=18, routed)          0.103     4.079    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/out[1]
    SLICE_X110Y343       FDPE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_o_i_reg/PRE
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.450     6.750    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.769 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.810     8.579    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/rd_clk
    SLICE_X110Y343       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_o_i_reg/C
                         clock pessimism             -4.610     3.969    
    SLICE_X110Y343       FDPE (Remov_DFF2_SLICEM_C_PRE)
                                                     -0.020     3.949    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_o_i_reg
  -------------------------------------------------------------------
                         required time                         -3.949    
                         arrival time                           4.079    
  -------------------------------------------------------------------
                         slack                                  0.130    

Slack (MET) :             0.130ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
                            (rising edge-triggered cell FDPE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg/CLR
                            (removal check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.142ns  (logic 0.039ns (27.531%)  route 0.103ns (72.469%))
  Logic Levels:           0  
  Clock Path Skew:        0.032ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.579ns
    Source Clock Delay      (SCD):    3.937ns
    Clock Pessimism Removal (CPR):    4.610ns
  Clock Net Delay (Source):      1.594ns (routing 0.916ns, distribution 0.678ns)
  Clock Net Delay (Destination): 1.810ns (routing 1.028ns, distribution 0.782ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.861     2.326    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.343 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.594     3.937    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
    SLICE_X111Y342       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X111Y342       FDPE (Prop_FFF_SLICEL_C_Q)
                                                      0.039     3.976 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/Q
                         net (fo=18, routed)          0.103     4.079    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/out[1]
    SLICE_X110Y343       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg/CLR
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.450     6.750    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.769 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.810     8.579    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/rd_clk
    SLICE_X110Y343       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg/C
                         clock pessimism             -4.610     3.969    
    SLICE_X110Y343       FDCE (Remov_CFF2_SLICEM_C_CLR)
                                                     -0.020     3.949    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg
  -------------------------------------------------------------------
                         required time                         -3.949    
                         arrival time                           4.079    
  -------------------------------------------------------------------
                         slack                                  0.130    

Slack (MET) :             0.135ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_wr_reg2_reg/C
                            (rising edge-triggered cell FDPE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg/PRE
                            (removal check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.137ns  (logic 0.039ns (28.467%)  route 0.098ns (71.533%))
  Logic Levels:           0  
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.564ns
    Source Clock Delay      (SCD):    3.932ns
    Clock Pessimism Removal (CPR):    4.610ns
  Clock Net Delay (Source):      1.589ns (routing 0.916ns, distribution 0.673ns)
  Clock Net Delay (Destination): 1.795ns (routing 1.028ns, distribution 0.767ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.861     2.326    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.343 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.589     3.932    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_clk
    SLICE_X110Y335       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_wr_reg2_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X110Y335       FDPE (Prop_EFF2_SLICEM_C_Q)
                                                      0.039     3.971 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_wr_reg2_reg/Q
                         net (fo=1, routed)           0.098     4.069    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.rst_wr_reg2
    SLICE_X110Y336       FDPE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg/PRE
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.450     6.750    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.769 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.795     8.564    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_clk
    SLICE_X110Y336       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg/C
                         clock pessimism             -4.610     3.954    
    SLICE_X110Y336       FDPE (Remov_HFF2_SLICEM_C_PRE)
                                                     -0.020     3.934    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg
  -------------------------------------------------------------------
                         required time                         -3.934    
                         arrival time                           4.069    
  -------------------------------------------------------------------
                         slack                                  0.135    

Slack (MET) :             0.138ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
                            (rising edge-triggered cell FDPE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[0]/PRE
                            (removal check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.143ns  (logic 0.039ns (27.284%)  route 0.104ns (72.716%))
  Logic Levels:           0  
  Clock Path Skew:        0.025ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.570ns
    Source Clock Delay      (SCD):    3.935ns
    Clock Pessimism Removal (CPR):    4.610ns
  Clock Net Delay (Source):      1.592ns (routing 0.916ns, distribution 0.676ns)
  Clock Net Delay (Destination): 1.801ns (routing 1.028ns, distribution 0.773ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.861     2.326    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.343 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.592     3.935    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_clk
    SLICE_X109Y340       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X109Y340       FDPE (Prop_EFF2_SLICEM_C_Q)
                                                      0.039     3.974 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/Q
                         net (fo=12, routed)          0.104     4.078    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0]_0[0]
    SLICE_X109Y342       FDPE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[0]/PRE
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.450     6.750    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.769 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.801     8.570    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/wr_clk
    SLICE_X109Y342       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[0]/C
                         clock pessimism             -4.610     3.960    
    SLICE_X109Y342       FDPE (Remov_AFF_SLICEM_C_PRE)
                                                     -0.020     3.940    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[0]
  -------------------------------------------------------------------
                         required time                         -3.940    
                         arrival time                           4.078    
  -------------------------------------------------------------------
                         slack                                  0.138    

Slack (MET) :             0.138ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
                            (rising edge-triggered cell FDPE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[1]/CLR
                            (removal check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.143ns  (logic 0.039ns (27.284%)  route 0.104ns (72.716%))
  Logic Levels:           0  
  Clock Path Skew:        0.025ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.570ns
    Source Clock Delay      (SCD):    3.935ns
    Clock Pessimism Removal (CPR):    4.610ns
  Clock Net Delay (Source):      1.592ns (routing 0.916ns, distribution 0.676ns)
  Clock Net Delay (Destination): 1.801ns (routing 1.028ns, distribution 0.773ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.861     2.326    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.343 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.592     3.935    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_clk
    SLICE_X109Y340       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X109Y340       FDPE (Prop_EFF2_SLICEM_C_Q)
                                                      0.039     3.974 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/Q
                         net (fo=12, routed)          0.104     4.078    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0]_0[0]
    SLICE_X109Y342       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[1]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.450     6.750    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.769 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.801     8.570    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/wr_clk
    SLICE_X109Y342       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[1]/C
                         clock pessimism             -4.610     3.960    
    SLICE_X109Y342       FDCE (Remov_AFF2_SLICEM_C_CLR)
                                                     -0.020     3.940    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[1]
  -------------------------------------------------------------------
                         required time                         -3.940    
                         arrival time                           4.078    
  -------------------------------------------------------------------
                         slack                                  0.138    

Slack (MET) :             0.138ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
                            (rising edge-triggered cell FDPE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[2]/CLR
                            (removal check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.143ns  (logic 0.039ns (27.284%)  route 0.104ns (72.716%))
  Logic Levels:           0  
  Clock Path Skew:        0.025ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.570ns
    Source Clock Delay      (SCD):    3.935ns
    Clock Pessimism Removal (CPR):    4.610ns
  Clock Net Delay (Source):      1.592ns (routing 0.916ns, distribution 0.676ns)
  Clock Net Delay (Destination): 1.801ns (routing 1.028ns, distribution 0.773ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.861     2.326    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.343 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.592     3.935    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_clk
    SLICE_X109Y340       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X109Y340       FDPE (Prop_EFF2_SLICEM_C_Q)
                                                      0.039     3.974 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/Q
                         net (fo=12, routed)          0.104     4.078    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0]_0[0]
    SLICE_X109Y342       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[2]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.450     6.750    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.769 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.801     8.570    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/wr_clk
    SLICE_X109Y342       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[2]/C
                         clock pessimism             -4.610     3.960    
    SLICE_X109Y342       FDCE (Remov_BFF_SLICEM_C_CLR)
                                                     -0.020     3.940    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[2]
  -------------------------------------------------------------------
                         required time                         -3.940    
                         arrival time                           4.078    
  -------------------------------------------------------------------
                         slack                                  0.138    

Slack (MET) :             0.138ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
                            (rising edge-triggered cell FDPE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[3]/CLR
                            (removal check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.143ns  (logic 0.039ns (27.284%)  route 0.104ns (72.716%))
  Logic Levels:           0  
  Clock Path Skew:        0.025ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.570ns
    Source Clock Delay      (SCD):    3.935ns
    Clock Pessimism Removal (CPR):    4.610ns
  Clock Net Delay (Source):      1.592ns (routing 0.916ns, distribution 0.676ns)
  Clock Net Delay (Destination): 1.801ns (routing 1.028ns, distribution 0.773ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.861     2.326    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.343 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.592     3.935    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_clk
    SLICE_X109Y340       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X109Y340       FDPE (Prop_EFF2_SLICEM_C_Q)
                                                      0.039     3.974 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/Q
                         net (fo=12, routed)          0.104     4.078    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0]_0[0]
    SLICE_X109Y342       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[3]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.450     6.750    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.769 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.801     8.570    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/wr_clk
    SLICE_X109Y342       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[3]/C
                         clock pessimism             -4.610     3.960    
    SLICE_X109Y342       FDCE (Remov_BFF2_SLICEM_C_CLR)
                                                     -0.020     3.940    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[3]
  -------------------------------------------------------------------
                         required time                         -3.940    
                         arrival time                           4.078    
  -------------------------------------------------------------------
                         slack                                  0.138    

Slack (MET) :             0.138ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
                            (rising edge-triggered cell FDPE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[0]/CLR
                            (removal check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.143ns  (logic 0.039ns (27.284%)  route 0.104ns (72.716%))
  Logic Levels:           0  
  Clock Path Skew:        0.025ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.570ns
    Source Clock Delay      (SCD):    3.935ns
    Clock Pessimism Removal (CPR):    4.610ns
  Clock Net Delay (Source):      1.592ns (routing 0.916ns, distribution 0.676ns)
  Clock Net Delay (Destination): 1.801ns (routing 1.028ns, distribution 0.773ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.861     2.326    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.343 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.592     3.935    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_clk
    SLICE_X109Y340       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X109Y340       FDPE (Prop_EFF2_SLICEM_C_Q)
                                                      0.039     3.974 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/Q
                         net (fo=12, routed)          0.104     4.078    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0]_0[0]
    SLICE_X109Y342       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[0]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.450     6.750    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.769 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.801     8.570    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/wr_clk
    SLICE_X109Y342       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[0]/C
                         clock pessimism             -4.610     3.960    
    SLICE_X109Y342       FDCE (Remov_CFF_SLICEM_C_CLR)
                                                     -0.020     3.940    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[0]
  -------------------------------------------------------------------
                         required time                         -3.940    
                         arrival time                           4.078    
  -------------------------------------------------------------------
                         slack                                  0.138    

Slack (MET) :             0.138ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
                            (rising edge-triggered cell FDPE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[1]/CLR
                            (removal check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.143ns  (logic 0.039ns (27.284%)  route 0.104ns (72.716%))
  Logic Levels:           0  
  Clock Path Skew:        0.025ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.570ns
    Source Clock Delay      (SCD):    3.935ns
    Clock Pessimism Removal (CPR):    4.610ns
  Clock Net Delay (Source):      1.592ns (routing 0.916ns, distribution 0.676ns)
  Clock Net Delay (Destination): 1.801ns (routing 1.028ns, distribution 0.773ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.861     2.326    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.343 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.592     3.935    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_clk
    SLICE_X109Y340       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X109Y340       FDPE (Prop_EFF2_SLICEM_C_Q)
                                                      0.039     3.974 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/Q
                         net (fo=12, routed)          0.104     4.078    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0]_0[0]
    SLICE_X109Y342       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[1]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.450     6.750    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.769 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.801     8.570    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/wr_clk
    SLICE_X109Y342       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[1]/C
                         clock pessimism             -4.610     3.960    
    SLICE_X109Y342       FDCE (Remov_CFF2_SLICEM_C_CLR)
                                                     -0.020     3.940    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[1]
  -------------------------------------------------------------------
                         required time                         -3.940    
                         arrival time                           4.078    
  -------------------------------------------------------------------
                         slack                                  0.138    

Slack (MET) :             0.138ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
                            (rising edge-triggered cell FDPE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[2]/CLR
                            (removal check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.143ns  (logic 0.039ns (27.284%)  route 0.104ns (72.716%))
  Logic Levels:           0  
  Clock Path Skew:        0.025ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.570ns
    Source Clock Delay      (SCD):    3.935ns
    Clock Pessimism Removal (CPR):    4.610ns
  Clock Net Delay (Source):      1.592ns (routing 0.916ns, distribution 0.676ns)
  Clock Net Delay (Destination): 1.801ns (routing 1.028ns, distribution 0.773ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.861     2.326    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.343 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.592     3.935    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_clk
    SLICE_X109Y340       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X109Y340       FDPE (Prop_EFF2_SLICEM_C_Q)
                                                      0.039     3.974 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/Q
                         net (fo=12, routed)          0.104     4.078    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0]_0[0]
    SLICE_X109Y342       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[2]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.450     6.750    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.769 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.801     8.570    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/wr_clk
    SLICE_X109Y342       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[2]/C
                         clock pessimism             -4.610     3.960    
    SLICE_X109Y342       FDCE (Remov_DFF_SLICEM_C_CLR)
                                                     -0.020     3.940    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[2]
  -------------------------------------------------------------------
                         required time                         -3.940    
                         arrival time                           4.078    
  -------------------------------------------------------------------
                         slack                                  0.138    





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  mmcm_clkout5
  To Clock:  mmcm_clkout5

Setup :            0  Failing Endpoints,  Worst Slack       10.598ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.137ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             10.598ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
                            (rising edge-triggered cell FDPE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[0]/CLR
                            (recovery check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        1.229ns  (logic 0.078ns (6.347%)  route 1.151ns (93.653%))
  Logic Levels:           0  
  Clock Path Skew:        -0.033ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.448ns = ( 16.450 - 12.002 ) 
    Source Clock Delay      (SCD):    4.233ns
    Clock Pessimism Removal (CPR):    -0.248ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.480ns (routing 0.539ns, distribution 0.941ns)
  Clock Net Delay (Destination): 1.303ns (routing 0.490ns, distribution 0.813ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.725    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.753 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.480     4.233    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
    SLICE_X109Y337       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X109Y337       FDPE (Prop_BFF_SLICEM_C_Q)
                                                      0.078     4.311 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/Q
                         net (fo=10, routed)          1.151     5.462    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/AR[0]
    SLICE_X109Y338       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[0]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369    14.286    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    15.123    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    15.147 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.303    16.450    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/rd_clk
    SLICE_X109Y338       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[0]/C
                         clock pessimism             -0.248    16.202    
                         clock uncertainty           -0.076    16.126    
    SLICE_X109Y338       FDCE (Recov_AFF_SLICEM_C_CLR)
                                                     -0.066    16.060    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[0]
  -------------------------------------------------------------------
                         required time                         16.060    
                         arrival time                          -5.462    
  -------------------------------------------------------------------
                         slack                                 10.598    

Slack (MET) :             10.598ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
                            (rising edge-triggered cell FDPE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[1]/CLR
                            (recovery check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        1.229ns  (logic 0.078ns (6.347%)  route 1.151ns (93.653%))
  Logic Levels:           0  
  Clock Path Skew:        -0.033ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.448ns = ( 16.450 - 12.002 ) 
    Source Clock Delay      (SCD):    4.233ns
    Clock Pessimism Removal (CPR):    -0.248ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.480ns (routing 0.539ns, distribution 0.941ns)
  Clock Net Delay (Destination): 1.303ns (routing 0.490ns, distribution 0.813ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.725    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.753 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.480     4.233    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
    SLICE_X109Y337       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X109Y337       FDPE (Prop_BFF_SLICEM_C_Q)
                                                      0.078     4.311 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/Q
                         net (fo=10, routed)          1.151     5.462    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/AR[0]
    SLICE_X109Y338       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[1]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369    14.286    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    15.123    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    15.147 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.303    16.450    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/rd_clk
    SLICE_X109Y338       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[1]/C
                         clock pessimism             -0.248    16.202    
                         clock uncertainty           -0.076    16.126    
    SLICE_X109Y338       FDCE (Recov_AFF2_SLICEM_C_CLR)
                                                     -0.066    16.060    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[1]
  -------------------------------------------------------------------
                         required time                         16.060    
                         arrival time                          -5.462    
  -------------------------------------------------------------------
                         slack                                 10.598    

Slack (MET) :             10.598ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
                            (rising edge-triggered cell FDPE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[2]/CLR
                            (recovery check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        1.229ns  (logic 0.078ns (6.347%)  route 1.151ns (93.653%))
  Logic Levels:           0  
  Clock Path Skew:        -0.033ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.448ns = ( 16.450 - 12.002 ) 
    Source Clock Delay      (SCD):    4.233ns
    Clock Pessimism Removal (CPR):    -0.248ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.480ns (routing 0.539ns, distribution 0.941ns)
  Clock Net Delay (Destination): 1.303ns (routing 0.490ns, distribution 0.813ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.725    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.753 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.480     4.233    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
    SLICE_X109Y337       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X109Y337       FDPE (Prop_BFF_SLICEM_C_Q)
                                                      0.078     4.311 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/Q
                         net (fo=10, routed)          1.151     5.462    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/AR[0]
    SLICE_X109Y338       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[2]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369    14.286    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    15.123    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    15.147 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.303    16.450    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/rd_clk
    SLICE_X109Y338       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[2]/C
                         clock pessimism             -0.248    16.202    
                         clock uncertainty           -0.076    16.126    
    SLICE_X109Y338       FDCE (Recov_BFF_SLICEM_C_CLR)
                                                     -0.066    16.060    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[2]
  -------------------------------------------------------------------
                         required time                         16.060    
                         arrival time                          -5.462    
  -------------------------------------------------------------------
                         slack                                 10.598    

Slack (MET) :             10.598ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
                            (rising edge-triggered cell FDPE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[3]/CLR
                            (recovery check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        1.229ns  (logic 0.078ns (6.347%)  route 1.151ns (93.653%))
  Logic Levels:           0  
  Clock Path Skew:        -0.033ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.448ns = ( 16.450 - 12.002 ) 
    Source Clock Delay      (SCD):    4.233ns
    Clock Pessimism Removal (CPR):    -0.248ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.480ns (routing 0.539ns, distribution 0.941ns)
  Clock Net Delay (Destination): 1.303ns (routing 0.490ns, distribution 0.813ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.725    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.753 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.480     4.233    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
    SLICE_X109Y337       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X109Y337       FDPE (Prop_BFF_SLICEM_C_Q)
                                                      0.078     4.311 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/Q
                         net (fo=10, routed)          1.151     5.462    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/AR[0]
    SLICE_X109Y338       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[3]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369    14.286    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    15.123    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    15.147 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.303    16.450    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/rd_clk
    SLICE_X109Y338       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[3]/C
                         clock pessimism             -0.248    16.202    
                         clock uncertainty           -0.076    16.126    
    SLICE_X109Y338       FDCE (Recov_BFF2_SLICEM_C_CLR)
                                                     -0.066    16.060    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[3]
  -------------------------------------------------------------------
                         required time                         16.060    
                         arrival time                          -5.462    
  -------------------------------------------------------------------
                         slack                                 10.598    

Slack (MET) :             10.598ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
                            (rising edge-triggered cell FDPE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[1]/CLR
                            (recovery check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        1.229ns  (logic 0.078ns (6.347%)  route 1.151ns (93.653%))
  Logic Levels:           0  
  Clock Path Skew:        -0.033ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.448ns = ( 16.450 - 12.002 ) 
    Source Clock Delay      (SCD):    4.233ns
    Clock Pessimism Removal (CPR):    -0.248ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.480ns (routing 0.539ns, distribution 0.941ns)
  Clock Net Delay (Destination): 1.303ns (routing 0.490ns, distribution 0.813ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.725    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.753 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.480     4.233    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
    SLICE_X109Y337       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X109Y337       FDPE (Prop_BFF_SLICEM_C_Q)
                                                      0.078     4.311 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/Q
                         net (fo=10, routed)          1.151     5.462    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/AR[0]
    SLICE_X109Y338       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[1]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369    14.286    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    15.123    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    15.147 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.303    16.450    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/rd_clk
    SLICE_X109Y338       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[1]/C
                         clock pessimism             -0.248    16.202    
                         clock uncertainty           -0.076    16.126    
    SLICE_X109Y338       FDCE (Recov_DFF_SLICEM_C_CLR)
                                                     -0.066    16.060    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[1]
  -------------------------------------------------------------------
                         required time                         16.060    
                         arrival time                          -5.462    
  -------------------------------------------------------------------
                         slack                                 10.598    

Slack (MET) :             10.598ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
                            (rising edge-triggered cell FDPE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[2]/CLR
                            (recovery check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        1.229ns  (logic 0.078ns (6.347%)  route 1.151ns (93.653%))
  Logic Levels:           0  
  Clock Path Skew:        -0.033ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.448ns = ( 16.450 - 12.002 ) 
    Source Clock Delay      (SCD):    4.233ns
    Clock Pessimism Removal (CPR):    -0.248ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.480ns (routing 0.539ns, distribution 0.941ns)
  Clock Net Delay (Destination): 1.303ns (routing 0.490ns, distribution 0.813ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.725    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.753 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.480     4.233    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
    SLICE_X109Y337       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X109Y337       FDPE (Prop_BFF_SLICEM_C_Q)
                                                      0.078     4.311 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/Q
                         net (fo=10, routed)          1.151     5.462    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/AR[0]
    SLICE_X109Y338       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[2]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369    14.286    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    15.123    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    15.147 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.303    16.450    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/rd_clk
    SLICE_X109Y338       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[2]/C
                         clock pessimism             -0.248    16.202    
                         clock uncertainty           -0.076    16.126    
    SLICE_X109Y338       FDCE (Recov_CFF_SLICEM_C_CLR)
                                                     -0.066    16.060    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[2]
  -------------------------------------------------------------------
                         required time                         16.060    
                         arrival time                          -5.462    
  -------------------------------------------------------------------
                         slack                                 10.598    

Slack (MET) :             10.598ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
                            (rising edge-triggered cell FDPE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[3]/CLR
                            (recovery check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        1.229ns  (logic 0.078ns (6.347%)  route 1.151ns (93.653%))
  Logic Levels:           0  
  Clock Path Skew:        -0.033ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.448ns = ( 16.450 - 12.002 ) 
    Source Clock Delay      (SCD):    4.233ns
    Clock Pessimism Removal (CPR):    -0.248ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.480ns (routing 0.539ns, distribution 0.941ns)
  Clock Net Delay (Destination): 1.303ns (routing 0.490ns, distribution 0.813ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.725    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.753 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.480     4.233    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
    SLICE_X109Y337       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X109Y337       FDPE (Prop_BFF_SLICEM_C_Q)
                                                      0.078     4.311 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/Q
                         net (fo=10, routed)          1.151     5.462    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/AR[0]
    SLICE_X109Y338       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[3]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369    14.286    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    15.123    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    15.147 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.303    16.450    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/rd_clk
    SLICE_X109Y338       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[3]/C
                         clock pessimism             -0.248    16.202    
                         clock uncertainty           -0.076    16.126    
    SLICE_X109Y338       FDCE (Recov_DFF2_SLICEM_C_CLR)
                                                     -0.066    16.060    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[3]
  -------------------------------------------------------------------
                         required time                         16.060    
                         arrival time                          -5.462    
  -------------------------------------------------------------------
                         slack                                 10.598    

Slack (MET) :             10.634ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[12]/CLR
                            (recovery check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        1.090ns  (logic 0.078ns (7.158%)  route 1.012ns (92.842%))
  Logic Levels:           0  
  Clock Path Skew:        -0.137ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.410ns = ( 16.412 - 12.002 ) 
    Source Clock Delay      (SCD):    4.247ns
    Clock Pessimism Removal (CPR):    -0.300ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.494ns (routing 0.539ns, distribution 0.955ns)
  Clock Net Delay (Destination): 1.265ns (routing 0.490ns, distribution 0.775ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.725    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.753 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.494     4.247    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X110Y338       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X110Y338       FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     4.325 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         1.012     5.336    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/out[0]
    SLICE_X107Y330       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[12]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369    14.286    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    15.123    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    15.147 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.265    16.412    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X107Y330       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[12]/C
                         clock pessimism             -0.300    16.112    
                         clock uncertainty           -0.076    16.037    
    SLICE_X107Y330       FDCE (Recov_HFF_SLICEM_C_CLR)
                                                     -0.066    15.971    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[12]
  -------------------------------------------------------------------
                         required time                         15.971    
                         arrival time                          -5.336    
  -------------------------------------------------------------------
                         slack                                 10.634    

Slack (MET) :             10.634ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[13]/CLR
                            (recovery check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        1.090ns  (logic 0.078ns (7.158%)  route 1.012ns (92.842%))
  Logic Levels:           0  
  Clock Path Skew:        -0.137ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.410ns = ( 16.412 - 12.002 ) 
    Source Clock Delay      (SCD):    4.247ns
    Clock Pessimism Removal (CPR):    -0.300ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.494ns (routing 0.539ns, distribution 0.955ns)
  Clock Net Delay (Destination): 1.265ns (routing 0.490ns, distribution 0.775ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.725    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.753 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.494     4.247    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X110Y338       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X110Y338       FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     4.325 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         1.012     5.336    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/out[0]
    SLICE_X107Y330       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[13]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369    14.286    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    15.123    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    15.147 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.265    16.412    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X107Y330       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[13]/C
                         clock pessimism             -0.300    16.112    
                         clock uncertainty           -0.076    16.037    
    SLICE_X107Y330       FDCE (Recov_HFF2_SLICEM_C_CLR)
                                                     -0.066    15.971    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[13]
  -------------------------------------------------------------------
                         required time                         15.971    
                         arrival time                          -5.336    
  -------------------------------------------------------------------
                         slack                                 10.634    

Slack (MET) :             10.666ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
                            (rising edge-triggered cell FDPE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i_reg/PRE
                            (recovery check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        1.169ns  (logic 0.078ns (6.672%)  route 1.091ns (93.328%))
  Logic Levels:           0  
  Clock Path Skew:        -0.026ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.445ns = ( 16.447 - 12.002 ) 
    Source Clock Delay      (SCD):    4.233ns
    Clock Pessimism Removal (CPR):    -0.238ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.480ns (routing 0.539ns, distribution 0.941ns)
  Clock Net Delay (Destination): 1.300ns (routing 0.490ns, distribution 0.810ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.725    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.753 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.480     4.233    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
    SLICE_X109Y337       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X109Y337       FDPE (Prop_BFF_SLICEM_C_Q)
                                                      0.078     4.311 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/Q
                         net (fo=10, routed)          1.091     5.402    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/AR[0]
    SLICE_X109Y337       FDPE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i_reg/PRE
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369    14.286    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    15.123    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    15.147 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.300    16.447    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/rd_clk
    SLICE_X109Y337       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i_reg/C
                         clock pessimism             -0.238    16.209    
                         clock uncertainty           -0.076    16.134    
    SLICE_X109Y337       FDPE (Recov_HFF2_SLICEM_C_PRE)
                                                     -0.066    16.068    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i_reg
  -------------------------------------------------------------------
                         required time                         16.068    
                         arrival time                          -5.402    
  -------------------------------------------------------------------
                         slack                                 10.666    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.137ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
                            (rising edge-triggered cell FDPE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0]/CLR
                            (removal check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.141ns  (logic 0.039ns (27.622%)  route 0.102ns (72.378%))
  Logic Levels:           0  
  Clock Path Skew:        0.024ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.552ns
    Source Clock Delay      (SCD):    2.671ns
    Clock Pessimism Removal (CPR):    -0.143ns
  Clock Net Delay (Source):      0.824ns (routing 0.299ns, distribution 0.525ns)
  Clock Net Delay (Destination): 0.940ns (routing 0.333ns, distribution 0.607ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.830    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.847 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.824     2.671    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_clk
    SLICE_X112Y348       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X112Y348       FDPE (Prop_EFF2_SLICEM_C_Q)
                                                      0.039     2.710 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/Q
                         net (fo=12, routed)          0.102     2.812    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0]_0[0]
    SLICE_X112Y347       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.593    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.612 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.940     2.552    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/wr_clk
    SLICE_X112Y347       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0]/C
                         clock pessimism              0.143     2.695    
    SLICE_X112Y347       FDCE (Remov_CFF2_SLICEM_C_CLR)
                                                     -0.020     2.675    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0]
  -------------------------------------------------------------------
                         required time                         -2.675    
                         arrival time                           2.812    
  -------------------------------------------------------------------
                         slack                                  0.137    

Slack (MET) :             0.137ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
                            (rising edge-triggered cell FDPE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[1]/PRE
                            (removal check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.141ns  (logic 0.039ns (27.622%)  route 0.102ns (72.378%))
  Logic Levels:           0  
  Clock Path Skew:        0.024ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.552ns
    Source Clock Delay      (SCD):    2.671ns
    Clock Pessimism Removal (CPR):    -0.143ns
  Clock Net Delay (Source):      0.824ns (routing 0.299ns, distribution 0.525ns)
  Clock Net Delay (Destination): 0.940ns (routing 0.333ns, distribution 0.607ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.830    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.847 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.824     2.671    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_clk
    SLICE_X112Y348       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X112Y348       FDPE (Prop_EFF2_SLICEM_C_Q)
                                                      0.039     2.710 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/Q
                         net (fo=12, routed)          0.102     2.812    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0]_0[0]
    SLICE_X112Y347       FDPE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[1]/PRE
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.593    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.612 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.940     2.552    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/wr_clk
    SLICE_X112Y347       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[1]/C
                         clock pessimism              0.143     2.695    
    SLICE_X112Y347       FDPE (Remov_BFF2_SLICEM_C_PRE)
                                                     -0.020     2.675    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[1]
  -------------------------------------------------------------------
                         required time                         -2.675    
                         arrival time                           2.812    
  -------------------------------------------------------------------
                         slack                                  0.137    

Slack (MET) :             0.137ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
                            (rising edge-triggered cell FDPE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[2]/CLR
                            (removal check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.141ns  (logic 0.039ns (27.622%)  route 0.102ns (72.378%))
  Logic Levels:           0  
  Clock Path Skew:        0.024ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.552ns
    Source Clock Delay      (SCD):    2.671ns
    Clock Pessimism Removal (CPR):    -0.143ns
  Clock Net Delay (Source):      0.824ns (routing 0.299ns, distribution 0.525ns)
  Clock Net Delay (Destination): 0.940ns (routing 0.333ns, distribution 0.607ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.830    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.847 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.824     2.671    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_clk
    SLICE_X112Y348       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X112Y348       FDPE (Prop_EFF2_SLICEM_C_Q)
                                                      0.039     2.710 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/Q
                         net (fo=12, routed)          0.102     2.812    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0]_0[0]
    SLICE_X112Y347       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[2]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.593    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.612 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.940     2.552    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/wr_clk
    SLICE_X112Y347       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[2]/C
                         clock pessimism              0.143     2.695    
    SLICE_X112Y347       FDCE (Remov_DFF_SLICEM_C_CLR)
                                                     -0.020     2.675    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[2]
  -------------------------------------------------------------------
                         required time                         -2.675    
                         arrival time                           2.812    
  -------------------------------------------------------------------
                         slack                                  0.137    

Slack (MET) :             0.137ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
                            (rising edge-triggered cell FDPE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[3]/CLR
                            (removal check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.141ns  (logic 0.039ns (27.622%)  route 0.102ns (72.378%))
  Logic Levels:           0  
  Clock Path Skew:        0.024ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.552ns
    Source Clock Delay      (SCD):    2.671ns
    Clock Pessimism Removal (CPR):    -0.143ns
  Clock Net Delay (Source):      0.824ns (routing 0.299ns, distribution 0.525ns)
  Clock Net Delay (Destination): 0.940ns (routing 0.333ns, distribution 0.607ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.830    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.847 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.824     2.671    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_clk
    SLICE_X112Y348       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X112Y348       FDPE (Prop_EFF2_SLICEM_C_Q)
                                                      0.039     2.710 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/Q
                         net (fo=12, routed)          0.102     2.812    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0]_0[0]
    SLICE_X112Y347       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[3]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.593    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.612 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.940     2.552    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/wr_clk
    SLICE_X112Y347       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[3]/C
                         clock pessimism              0.143     2.695    
    SLICE_X112Y347       FDCE (Remov_DFF2_SLICEM_C_CLR)
                                                     -0.020     2.675    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[3]
  -------------------------------------------------------------------
                         required time                         -2.675    
                         arrival time                           2.812    
  -------------------------------------------------------------------
                         slack                                  0.137    

Slack (MET) :             0.138ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
                            (rising edge-triggered cell FDPE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[0]/PRE
                            (removal check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.140ns  (logic 0.039ns (27.819%)  route 0.101ns (72.181%))
  Logic Levels:           0  
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.550ns
    Source Clock Delay      (SCD):    2.671ns
    Clock Pessimism Removal (CPR):    -0.143ns
  Clock Net Delay (Source):      0.824ns (routing 0.299ns, distribution 0.525ns)
  Clock Net Delay (Destination): 0.938ns (routing 0.333ns, distribution 0.605ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.830    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.847 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.824     2.671    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_clk
    SLICE_X112Y348       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X112Y348       FDPE (Prop_EFF2_SLICEM_C_Q)
                                                      0.039     2.710 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/Q
                         net (fo=12, routed)          0.101     2.811    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0]_0[0]
    SLICE_X112Y347       FDPE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[0]/PRE
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.593    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.612 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.938     2.550    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/wr_clk
    SLICE_X112Y347       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[0]/C
                         clock pessimism              0.143     2.693    
    SLICE_X112Y347       FDPE (Remov_EFF_SLICEM_C_PRE)
                                                     -0.020     2.673    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[0]
  -------------------------------------------------------------------
                         required time                         -2.673    
                         arrival time                           2.811    
  -------------------------------------------------------------------
                         slack                                  0.138    

Slack (MET) :             0.138ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
                            (rising edge-triggered cell FDPE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[1]/CLR
                            (removal check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.140ns  (logic 0.039ns (27.819%)  route 0.101ns (72.181%))
  Logic Levels:           0  
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.550ns
    Source Clock Delay      (SCD):    2.671ns
    Clock Pessimism Removal (CPR):    -0.143ns
  Clock Net Delay (Source):      0.824ns (routing 0.299ns, distribution 0.525ns)
  Clock Net Delay (Destination): 0.938ns (routing 0.333ns, distribution 0.605ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.830    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.847 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.824     2.671    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_clk
    SLICE_X112Y348       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X112Y348       FDPE (Prop_EFF2_SLICEM_C_Q)
                                                      0.039     2.710 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/Q
                         net (fo=12, routed)          0.101     2.811    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0]_0[0]
    SLICE_X112Y347       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[1]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.593    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.612 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.938     2.550    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/wr_clk
    SLICE_X112Y347       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[1]/C
                         clock pessimism              0.143     2.693    
    SLICE_X112Y347       FDCE (Remov_EFF2_SLICEM_C_CLR)
                                                     -0.020     2.673    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[1]
  -------------------------------------------------------------------
                         required time                         -2.673    
                         arrival time                           2.811    
  -------------------------------------------------------------------
                         slack                                  0.138    

Slack (MET) :             0.138ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
                            (rising edge-triggered cell FDPE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[2]/CLR
                            (removal check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.140ns  (logic 0.039ns (27.819%)  route 0.101ns (72.181%))
  Logic Levels:           0  
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.550ns
    Source Clock Delay      (SCD):    2.671ns
    Clock Pessimism Removal (CPR):    -0.143ns
  Clock Net Delay (Source):      0.824ns (routing 0.299ns, distribution 0.525ns)
  Clock Net Delay (Destination): 0.938ns (routing 0.333ns, distribution 0.605ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.830    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.847 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.824     2.671    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_clk
    SLICE_X112Y348       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X112Y348       FDPE (Prop_EFF2_SLICEM_C_Q)
                                                      0.039     2.710 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/Q
                         net (fo=12, routed)          0.101     2.811    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0]_0[0]
    SLICE_X112Y347       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[2]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.593    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.612 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.938     2.550    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/wr_clk
    SLICE_X112Y347       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[2]/C
                         clock pessimism              0.143     2.693    
    SLICE_X112Y347       FDCE (Remov_FFF_SLICEM_C_CLR)
                                                     -0.020     2.673    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[2]
  -------------------------------------------------------------------
                         required time                         -2.673    
                         arrival time                           2.811    
  -------------------------------------------------------------------
                         slack                                  0.138    

Slack (MET) :             0.138ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
                            (rising edge-triggered cell FDPE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[3]/CLR
                            (removal check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.140ns  (logic 0.039ns (27.819%)  route 0.101ns (72.181%))
  Logic Levels:           0  
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.550ns
    Source Clock Delay      (SCD):    2.671ns
    Clock Pessimism Removal (CPR):    -0.143ns
  Clock Net Delay (Source):      0.824ns (routing 0.299ns, distribution 0.525ns)
  Clock Net Delay (Destination): 0.938ns (routing 0.333ns, distribution 0.605ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.830    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.847 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.824     2.671    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_clk
    SLICE_X112Y348       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X112Y348       FDPE (Prop_EFF2_SLICEM_C_Q)
                                                      0.039     2.710 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/Q
                         net (fo=12, routed)          0.101     2.811    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0]_0[0]
    SLICE_X112Y347       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[3]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.593    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.612 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.938     2.550    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/wr_clk
    SLICE_X112Y347       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[3]/C
                         clock pessimism              0.143     2.693    
    SLICE_X112Y347       FDCE (Remov_FFF2_SLICEM_C_CLR)
                                                     -0.020     2.673    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[3]
  -------------------------------------------------------------------
                         required time                         -2.673    
                         arrival time                           2.811    
  -------------------------------------------------------------------
                         slack                                  0.138    

Slack (MET) :             0.138ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
                            (rising edge-triggered cell FDPE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[0]/CLR
                            (removal check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.140ns  (logic 0.039ns (27.819%)  route 0.101ns (72.181%))
  Logic Levels:           0  
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.550ns
    Source Clock Delay      (SCD):    2.671ns
    Clock Pessimism Removal (CPR):    -0.143ns
  Clock Net Delay (Source):      0.824ns (routing 0.299ns, distribution 0.525ns)
  Clock Net Delay (Destination): 0.938ns (routing 0.333ns, distribution 0.605ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.830    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.847 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.824     2.671    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_clk
    SLICE_X112Y348       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X112Y348       FDPE (Prop_EFF2_SLICEM_C_Q)
                                                      0.039     2.710 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/Q
                         net (fo=12, routed)          0.101     2.811    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0]_0[0]
    SLICE_X112Y347       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[0]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.593    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.612 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.938     2.550    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/wr_clk
    SLICE_X112Y347       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[0]/C
                         clock pessimism              0.143     2.693    
    SLICE_X112Y347       FDCE (Remov_GFF_SLICEM_C_CLR)
                                                     -0.020     2.673    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[0]
  -------------------------------------------------------------------
                         required time                         -2.673    
                         arrival time                           2.811    
  -------------------------------------------------------------------
                         slack                                  0.138    

Slack (MET) :             0.138ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
                            (rising edge-triggered cell FDPE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[1]/CLR
                            (removal check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.140ns  (logic 0.039ns (27.819%)  route 0.101ns (72.181%))
  Logic Levels:           0  
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.550ns
    Source Clock Delay      (SCD):    2.671ns
    Clock Pessimism Removal (CPR):    -0.143ns
  Clock Net Delay (Source):      0.824ns (routing 0.299ns, distribution 0.525ns)
  Clock Net Delay (Destination): 0.938ns (routing 0.333ns, distribution 0.605ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.830    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.847 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.824     2.671    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_clk
    SLICE_X112Y348       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X112Y348       FDPE (Prop_EFF2_SLICEM_C_Q)
                                                      0.039     2.710 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/Q
                         net (fo=12, routed)          0.101     2.811    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0]_0[0]
    SLICE_X112Y347       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[1]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.593    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.612 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.938     2.550    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/wr_clk
    SLICE_X112Y347       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[1]/C
                         clock pessimism              0.143     2.693    
    SLICE_X112Y347       FDCE (Remov_GFF2_SLICEM_C_CLR)
                                                     -0.020     2.673    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[1]
  -------------------------------------------------------------------
                         required time                         -2.673    
                         arrival time                           2.811    
  -------------------------------------------------------------------
                         slack                                  0.138    





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFDAC0_CLK
  To Clock:  

Max Delay             8 Endpoints
Min Delay             8 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[4]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            PMOD0_4_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        4.049ns  (logic 0.949ns (23.427%)  route 3.100ns (76.573%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.048ns (routing 1.381ns, distribution 1.667ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       3.048     3.721    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X12Y369        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X12Y369        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     3.800 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[4]/Q
                         net (fo=2, routed)           3.100     6.901    PMOD0_4_LS_OBUF
    J16                  OBUF (Prop_OUTBUF_HPIOB_S_I_O)
                                                      0.870     7.770 r  PMOD0_4_LS_OBUF_inst/O
                         net (fo=0)                   0.000     7.770    PMOD0_4_LS
    J16                                                               r  PMOD0_4_LS (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            PMOD0_2_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        3.927ns  (logic 0.945ns (24.061%)  route 2.982ns (75.939%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.016ns (routing 1.381ns, distribution 1.635ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       3.016     3.689    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X15Y374        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X15Y374        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     3.768 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[2]/Q
                         net (fo=2, routed)           2.982     6.750    PMOD0_2_LS_OBUF
    H16                  OBUF (Prop_OUTBUF_HPIOB_S_I_O)
                                                      0.866     7.616 r  PMOD0_2_LS_OBUF_inst/O
                         net (fo=0)                   0.000     7.616    PMOD0_2_LS
    H16                                                               r  PMOD0_2_LS (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            PMOD0_1_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        3.887ns  (logic 0.938ns (24.134%)  route 2.949ns (75.866%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.031ns (routing 1.381ns, distribution 1.650ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       3.031     3.704    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X15Y367        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X15Y367        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     3.783 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[1]/Q
                         net (fo=2, routed)           2.949     6.733    PMOD0_1_LS_OBUF
    M18                  OBUF (Prop_OUTBUF_HPIOB_SNGL_I_O)
                                                      0.859     7.592 r  PMOD0_1_LS_OBUF_inst/O
                         net (fo=0)                   0.000     7.592    PMOD0_1_LS
    M18                                                               r  PMOD0_1_LS (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[6]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            PMOD0_6_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        3.907ns  (logic 0.938ns (24.013%)  route 2.969ns (75.987%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.005ns (routing 1.381ns, distribution 1.624ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       3.005     3.678    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X15Y384        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X15Y384        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     3.757 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[6]/Q
                         net (fo=2, routed)           2.969     6.726    PMOD0_6_LS_OBUF
    H15                  OBUF (Prop_OUTBUF_HPIOB_S_I_O)
                                                      0.859     7.585 r  PMOD0_6_LS_OBUF_inst/O
                         net (fo=0)                   0.000     7.585    PMOD0_6_LS
    H15                                                               r  PMOD0_6_LS (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            PMOD0_3_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        3.881ns  (logic 0.944ns (24.321%)  route 2.937ns (75.679%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.998ns (routing 1.381ns, distribution 1.617ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       2.998     3.671    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X17Y396        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X17Y396        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     3.750 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[3]/Q
                         net (fo=2, routed)           2.937     6.687    PMOD0_3_LS_OBUF
    H17                  OBUF (Prop_OUTBUF_HPIOB_M_I_O)
                                                      0.865     7.552 r  PMOD0_3_LS_OBUF_inst/O
                         net (fo=0)                   0.000     7.552    PMOD0_3_LS
    H17                                                               r  PMOD0_3_LS (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[5]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            PMOD0_5_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        3.782ns  (logic 0.948ns (25.062%)  route 2.834ns (74.938%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.881ns (routing 1.381ns, distribution 1.500ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       2.881     3.554    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X36Y399        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X36Y399        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     3.633 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[5]/Q
                         net (fo=2, routed)           2.834     6.467    PMOD0_5_LS_OBUF
    K16                  OBUF (Prop_OUTBUF_HPIOB_M_I_O)
                                                      0.869     7.336 r  PMOD0_5_LS_OBUF_inst/O
                         net (fo=0)                   0.000     7.336    PMOD0_5_LS
    K16                                                               r  PMOD0_5_LS (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[7]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            PMOD0_7_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        3.742ns  (logic 0.938ns (25.069%)  route 2.804ns (74.931%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.903ns (routing 1.381ns, distribution 1.522ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       2.903     3.576    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X26Y395        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X26Y395        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     3.655 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[7]/Q
                         net (fo=2, routed)           2.804     6.459    PMOD0_7_LS_OBUF
    J15                  OBUF (Prop_OUTBUF_HPIOB_M_I_O)
                                                      0.859     7.318 r  PMOD0_7_LS_OBUF_inst/O
                         net (fo=0)                   0.000     7.318    PMOD0_7_LS
    J15                                                               r  PMOD0_7_LS (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            PMOD0_0_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        3.593ns  (logic 0.926ns (25.781%)  route 2.667ns (74.219%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.025ns (routing 1.381ns, distribution 1.644ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       3.025     3.698    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X15Y386        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X15Y386        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     3.777 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[0]/Q
                         net (fo=2, routed)           2.667     6.444    PMOD0_0_LS_OBUF
    C17                  OBUF (Prop_OUTBUF_HPIOB_M_I_O)
                                                      0.847     7.291 r  PMOD0_0_LS_OBUF_inst/O
                         net (fo=0)                   0.000     7.291    PMOD0_0_LS
    C17                                                               r  PMOD0_0_LS (OUT)
  -------------------------------------------------------------------    -------------------





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            PMOD0_0_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.705ns  (logic 0.460ns (26.986%)  route 1.245ns (73.014%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.653ns (routing 0.748ns, distribution 0.905ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       1.653     2.002    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X15Y386        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X15Y386        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     2.041 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[0]/Q
                         net (fo=2, routed)           1.245     3.286    PMOD0_0_LS_OBUF
    C17                  OBUF (Prop_OUTBUF_HPIOB_M_I_O)
                                                      0.421     3.707 r  PMOD0_0_LS_OBUF_inst/O
                         net (fo=0)                   0.000     3.707    PMOD0_0_LS
    C17                                                               r  PMOD0_0_LS (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[5]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            PMOD0_5_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.818ns  (logic 0.481ns (26.467%)  route 1.337ns (73.533%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.579ns (routing 0.748ns, distribution 0.831ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       1.579     1.928    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X36Y399        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X36Y399        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     1.967 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[5]/Q
                         net (fo=2, routed)           1.337     3.304    PMOD0_5_LS_OBUF
    K16                  OBUF (Prop_OUTBUF_HPIOB_M_I_O)
                                                      0.442     3.746 r  PMOD0_5_LS_OBUF_inst/O
                         net (fo=0)                   0.000     3.746    PMOD0_5_LS
    K16                                                               r  PMOD0_5_LS (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[7]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            PMOD0_7_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.824ns  (logic 0.472ns (25.852%)  route 1.353ns (74.148%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.592ns (routing 0.748ns, distribution 0.844ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       1.592     1.941    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X26Y395        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X26Y395        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     1.980 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[7]/Q
                         net (fo=2, routed)           1.353     3.333    PMOD0_7_LS_OBUF
    J15                  OBUF (Prop_OUTBUF_HPIOB_M_I_O)
                                                      0.433     3.765 r  PMOD0_7_LS_OBUF_inst/O
                         net (fo=0)                   0.000     3.765    PMOD0_7_LS
    J15                                                               r  PMOD0_7_LS (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            PMOD0_3_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.853ns  (logic 0.477ns (25.756%)  route 1.376ns (74.244%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.642ns (routing 0.748ns, distribution 0.894ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       1.642     1.991    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X17Y396        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X17Y396        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     2.030 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[3]/Q
                         net (fo=2, routed)           1.376     3.406    PMOD0_3_LS_OBUF
    H17                  OBUF (Prop_OUTBUF_HPIOB_M_I_O)
                                                      0.438     3.844 r  PMOD0_3_LS_OBUF_inst/O
                         net (fo=0)                   0.000     3.844    PMOD0_3_LS
    H17                                                               r  PMOD0_3_LS (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[6]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            PMOD0_6_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.882ns  (logic 0.472ns (25.060%)  route 1.411ns (74.940%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.647ns (routing 0.748ns, distribution 0.899ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       1.647     1.996    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X15Y384        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X15Y384        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     2.035 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[6]/Q
                         net (fo=2, routed)           1.411     3.446    PMOD0_6_LS_OBUF
    H15                  OBUF (Prop_OUTBUF_HPIOB_S_I_O)
                                                      0.433     3.878 r  PMOD0_6_LS_OBUF_inst/O
                         net (fo=0)                   0.000     3.878    PMOD0_6_LS
    H15                                                               r  PMOD0_6_LS (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            PMOD0_2_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.885ns  (logic 0.478ns (25.374%)  route 1.407ns (74.626%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.653ns (routing 0.748ns, distribution 0.905ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       1.653     2.002    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X15Y374        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X15Y374        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     2.041 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[2]/Q
                         net (fo=2, routed)           1.407     3.448    PMOD0_2_LS_OBUF
    H16                  OBUF (Prop_OUTBUF_HPIOB_S_I_O)
                                                      0.439     3.887 r  PMOD0_2_LS_OBUF_inst/O
                         net (fo=0)                   0.000     3.887    PMOD0_2_LS
    H16                                                               r  PMOD0_2_LS (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            PMOD0_1_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.884ns  (logic 0.472ns (25.040%)  route 1.412ns (74.960%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.659ns (routing 0.748ns, distribution 0.911ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       1.659     2.008    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X15Y367        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X15Y367        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     2.047 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[1]/Q
                         net (fo=2, routed)           1.412     3.459    PMOD0_1_LS_OBUF
    M18                  OBUF (Prop_OUTBUF_HPIOB_SNGL_I_O)
                                                      0.433     3.891 r  PMOD0_1_LS_OBUF_inst/O
                         net (fo=0)                   0.000     3.891    PMOD0_1_LS
    M18                                                               r  PMOD0_1_LS (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[4]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            PMOD0_4_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.943ns  (logic 0.482ns (24.803%)  route 1.461ns (75.197%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.668ns (routing 0.748ns, distribution 0.920ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       1.668     2.017    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X12Y369        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X12Y369        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     2.056 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[4]/Q
                         net (fo=2, routed)           1.461     3.517    PMOD0_4_LS_OBUF
    J16                  OBUF (Prop_OUTBUF_HPIOB_S_I_O)
                                                      0.443     3.960 r  PMOD0_4_LS_OBUF_inst/O
                         net (fo=0)                   0.000     3.960    PMOD0_4_LS
    J16                                                               r  PMOD0_4_LS (OUT)
  -------------------------------------------------------------------    -------------------





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  
  To Clock:  RFADC0_CLK

Max Delay             1 Endpoint
Min Delay             1 Endpoint
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                            (internal pin)
  Destination:            d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.053ns  (logic 0.088ns (4.287%)  route 1.965ns (95.713%))
  Logic Levels:           1  (LUT1=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.367ns (routing 1.383ns, distribution 0.984ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    PS8_X0Y0             PS8                          0.000     0.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                         net (fo=5, routed)           1.785     1.785    d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/ext_reset_in
    SLICE_X34Y301        LUT1 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.088     1.873 r  d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1/O
                         net (fo=1, routed)           0.180     2.053    d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/exr_d1
    SLICE_X34Y299        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=35, routed)          2.367     2.753    d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/slowest_sync_clk
    SLICE_X34Y299        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                            (internal pin)
  Destination:            d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.015ns  (logic 0.035ns (3.447%)  route 0.980ns (96.553%))
  Logic Levels:           1  (LUT1=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.633ns (routing 0.914ns, distribution 0.719ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    PS8_X0Y0             PS8                          0.000     0.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                         net (fo=5, routed)           0.914     0.914    d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/ext_reset_in
    SLICE_X34Y301        LUT1 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.035     0.949 r  d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1/O
                         net (fo=1, routed)           0.066     1.015    d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/exr_d1
    SLICE_X34Y299        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X2Y2 (CLOCK_ROOT)    net (fo=35, routed)          1.633     1.985    d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/slowest_sync_clk
    SLICE_X34Y299        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  
  To Clock:  RFDAC0_CLK

Max Delay             1 Endpoint
Min Delay             1 Endpoint
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                            (internal pin)
  Destination:            d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.817ns  (logic 0.066ns (3.633%)  route 1.751ns (96.367%))
  Logic Levels:           1  (LUT1=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.588ns (routing 1.256ns, distribution 1.332ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    PS8_X0Y0             PS8                          0.000     0.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                         net (fo=5, routed)           1.721     1.721    d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/ext_reset_in
    SLICE_X37Y302        LUT1 (Prop_D5LUT_SLICEM_I0_O)
                                                      0.066     1.787 r  d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1/O
                         net (fo=1, routed)           0.030     1.817    d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/exr_d1
    SLICE_X37Y302        FDRE                                         r  d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       2.588     3.109    d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/slowest_sync_clk
    SLICE_X37Y302        FDRE                                         r  d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                            (internal pin)
  Destination:            d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.916ns  (logic 0.024ns (2.619%)  route 0.892ns (97.381%))
  Logic Levels:           1  (LUT1=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.764ns (routing 0.827ns, distribution 0.937ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    PS8_X0Y0             PS8                          0.000     0.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                         net (fo=5, routed)           0.883     0.883    d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/ext_reset_in
    SLICE_X37Y302        LUT1 (Prop_D5LUT_SLICEM_I0_O)
                                                      0.024     0.907 r  d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1/O
                         net (fo=1, routed)           0.009     0.916    d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/exr_d1
    SLICE_X37Y302        FDRE                                         r  d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       1.764     2.212    d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/slowest_sync_clk
    SLICE_X37Y302        FDRE                                         r  d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFDAC0_CLK
  To Clock:  RFDAC0_CLK

Max Delay         30761 Endpoints
Min Delay         30761 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_6/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.828ns  (logic 0.228ns (4.723%)  route 4.600ns (95.277%))
  Logic Levels:           2  (BUFGCE=1 LUT1=1)
  Clock Path Skew:        -0.358ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.288ns
    Source Clock Delay      (SCD):    3.646ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.973ns (routing 1.381ns, distribution 1.592ns)
  Clock Net Delay (Destination): 2.767ns (routing 1.256ns, distribution 1.511ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       2.973     3.646    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X82Y270        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y270        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     3.722 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.422     4.144    d_1_i/rst_dac0/U0/peripheral_aresetn[0]
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     4.172 r  d_1_i/rst_dac0/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=29204, routed)       1.218     5.390    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/aresetn
    SLICE_X102Y257       LUT1 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.124     5.514 r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_xlnx_opt/O
                         net (fo=17, routed)          2.959     8.474    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_xlnx_opt_1
    SLICE_X89Y361        FDRE                                         r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_6/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       2.767     3.288    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X89Y361        FDRE                                         r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_6/C

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_9/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.748ns  (logic 0.228ns (4.802%)  route 4.520ns (95.198%))
  Logic Levels:           2  (BUFGCE=1 LUT1=1)
  Clock Path Skew:        -0.486ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.160ns
    Source Clock Delay      (SCD):    3.646ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.973ns (routing 1.381ns, distribution 1.592ns)
  Clock Net Delay (Destination): 2.639ns (routing 1.256ns, distribution 1.383ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       2.973     3.646    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X82Y270        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y270        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     3.722 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.422     4.144    d_1_i/rst_dac0/U0/peripheral_aresetn[0]
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     4.172 r  d_1_i/rst_dac0/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=29204, routed)       1.218     5.390    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/aresetn
    SLICE_X102Y257       LUT1 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.124     5.514 r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_xlnx_opt/O
                         net (fo=17, routed)          2.879     8.394    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_xlnx_opt_1
    SLICE_X80Y317        FDRE                                         r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_9/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       2.639     3.160    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X80Y317        FDRE                                         r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_9/C

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_7/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.448ns  (logic 0.226ns (5.081%)  route 4.222ns (94.919%))
  Logic Levels:           2  (BUFGCE=1 LUT1=1)
  Clock Path Skew:        -0.291ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.355ns
    Source Clock Delay      (SCD):    3.646ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.973ns (routing 1.381ns, distribution 1.592ns)
  Clock Net Delay (Destination): 2.834ns (routing 1.256ns, distribution 1.578ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       2.973     3.646    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X82Y270        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y270        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     3.722 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.422     4.144    d_1_i/rst_dac0/U0/peripheral_aresetn[0]
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     4.172 r  d_1_i/rst_dac0/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=29204, routed)       1.430     5.602    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/aresetn
    SLICE_X105Y169       LUT1 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.122     5.724 r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_xlnx_opt/O
                         net (fo=25, routed)          2.370     8.094    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_xlnx_opt_1
    SLICE_X117Y280       FDRE                                         r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_7/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       2.834     3.355    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X117Y280       FDRE                                         r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_7/C

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_10/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.377ns  (logic 0.226ns (5.164%)  route 4.151ns (94.836%))
  Logic Levels:           2  (BUFGCE=1 LUT1=1)
  Clock Path Skew:        -0.291ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.355ns
    Source Clock Delay      (SCD):    3.646ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.973ns (routing 1.381ns, distribution 1.592ns)
  Clock Net Delay (Destination): 2.834ns (routing 1.256ns, distribution 1.578ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       2.973     3.646    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X82Y270        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y270        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     3.722 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.422     4.144    d_1_i/rst_dac0/U0/peripheral_aresetn[0]
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     4.172 r  d_1_i/rst_dac0/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=29204, routed)       1.430     5.602    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/aresetn
    SLICE_X105Y169       LUT1 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.122     5.724 r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_xlnx_opt/O
                         net (fo=25, routed)          2.299     8.023    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_xlnx_opt_1
    SLICE_X114Y73        FDRE                                         r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_10/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       2.834     3.355    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X114Y73        FDRE                                         r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_10/C

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_5/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.327ns  (logic 0.193ns (4.460%)  route 4.134ns (95.540%))
  Logic Levels:           2  (BUFGCE=1 LUT1=1)
  Clock Path Skew:        -0.497ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.149ns
    Source Clock Delay      (SCD):    3.646ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.973ns (routing 1.381ns, distribution 1.592ns)
  Clock Net Delay (Destination): 2.628ns (routing 1.256ns, distribution 1.372ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       2.973     3.646    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X82Y270        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y270        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     3.722 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.422     4.144    d_1_i/rst_dac0/U0/peripheral_aresetn[0]
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     4.172 r  d_1_i/rst_dac0/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=29204, routed)       1.182     5.354    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/aresetn
    SLICE_X92Y199        LUT1 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.089     5.443 r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_xlnx_opt/O
                         net (fo=28, routed)          2.530     7.973    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_xlnx_opt_1
    SLICE_X79Y287        FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_5/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       2.628     3.149    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X79Y287        FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_5/C

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_9/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.228ns  (logic 0.226ns (5.346%)  route 4.002ns (94.654%))
  Logic Levels:           2  (BUFGCE=1 LUT1=1)
  Clock Path Skew:        -0.307ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.339ns
    Source Clock Delay      (SCD):    3.646ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.973ns (routing 1.381ns, distribution 1.592ns)
  Clock Net Delay (Destination): 2.818ns (routing 1.256ns, distribution 1.562ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       2.973     3.646    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X82Y270        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y270        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     3.722 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.422     4.144    d_1_i/rst_dac0/U0/peripheral_aresetn[0]
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     4.172 r  d_1_i/rst_dac0/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=29204, routed)       1.430     5.602    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/aresetn
    SLICE_X105Y169       LUT1 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.122     5.724 r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_xlnx_opt/O
                         net (fo=25, routed)          2.150     7.874    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_xlnx_opt_1
    SLICE_X113Y89        FDRE                                         r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_9/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       2.818     3.339    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X113Y89        FDRE                                         r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_9/C

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_8/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.198ns  (logic 0.226ns (5.384%)  route 3.972ns (94.616%))
  Logic Levels:           2  (BUFGCE=1 LUT1=1)
  Clock Path Skew:        -0.290ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.356ns
    Source Clock Delay      (SCD):    3.646ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.973ns (routing 1.381ns, distribution 1.592ns)
  Clock Net Delay (Destination): 2.835ns (routing 1.256ns, distribution 1.579ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       2.973     3.646    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X82Y270        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y270        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     3.722 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.422     4.144    d_1_i/rst_dac0/U0/peripheral_aresetn[0]
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     4.172 r  d_1_i/rst_dac0/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=29204, routed)       1.430     5.602    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/aresetn
    SLICE_X105Y169       LUT1 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.122     5.724 r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_xlnx_opt/O
                         net (fo=25, routed)          2.120     7.844    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_xlnx_opt_1
    SLICE_X115Y273       FDRE                                         r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_8/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       2.835     3.356    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X115Y273       FDRE                                         r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_8/C

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_3/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.072ns  (logic 0.265ns (6.508%)  route 3.807ns (93.492%))
  Logic Levels:           2  (BUFGCE=1 LUT1=1)
  Clock Path Skew:        -0.374ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.272ns
    Source Clock Delay      (SCD):    3.646ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.973ns (routing 1.381ns, distribution 1.592ns)
  Clock Net Delay (Destination): 2.751ns (routing 1.256ns, distribution 1.495ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       2.973     3.646    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X82Y270        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y270        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     3.722 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.422     4.144    d_1_i/rst_dac0/U0/peripheral_aresetn[0]
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     4.172 r  d_1_i/rst_dac0/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=29204, routed)       1.624     5.796    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/aresetn
    SLICE_X18Y232        LUT1 (Prop_H5LUT_SLICEM_I0_O)
                                                      0.161     5.957 r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_xlnx_opt/O
                         net (fo=15, routed)          1.761     7.718    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_xlnx_opt_1
    SLICE_X8Y314         FDRE                                         r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_3/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       2.751     3.272    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X8Y314         FDRE                                         r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_3/C

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_2/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.023ns  (logic 0.265ns (6.587%)  route 3.758ns (93.413%))
  Logic Levels:           2  (BUFGCE=1 LUT1=1)
  Clock Path Skew:        -0.454ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.192ns
    Source Clock Delay      (SCD):    3.646ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.973ns (routing 1.381ns, distribution 1.592ns)
  Clock Net Delay (Destination): 2.671ns (routing 1.256ns, distribution 1.415ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       2.973     3.646    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X82Y270        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y270        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     3.722 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.422     4.144    d_1_i/rst_dac0/U0/peripheral_aresetn[0]
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     4.172 r  d_1_i/rst_dac0/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=29204, routed)       1.624     5.796    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/aresetn
    SLICE_X18Y232        LUT1 (Prop_H5LUT_SLICEM_I0_O)
                                                      0.161     5.957 r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_xlnx_opt/O
                         net (fo=15, routed)          1.712     7.669    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_xlnx_opt_1
    SLICE_X19Y312        FDRE                                         r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_2/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       2.671     3.192    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X19Y312        FDRE                                         r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_2/C

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_3/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.007ns  (logic 0.226ns (5.640%)  route 3.781ns (94.360%))
  Logic Levels:           2  (BUFGCE=1 LUT1=1)
  Clock Path Skew:        -0.308ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.338ns
    Source Clock Delay      (SCD):    3.646ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.973ns (routing 1.381ns, distribution 1.592ns)
  Clock Net Delay (Destination): 2.817ns (routing 1.256ns, distribution 1.561ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       2.973     3.646    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X82Y270        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y270        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     3.722 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.422     4.144    d_1_i/rst_dac0/U0/peripheral_aresetn[0]
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     4.172 r  d_1_i/rst_dac0/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=29204, routed)       1.430     5.602    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/aresetn
    SLICE_X105Y169       LUT1 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.122     5.724 r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_xlnx_opt/O
                         net (fo=25, routed)          1.929     7.653    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_xlnx_opt_1
    SLICE_X112Y100       FDRE                                         r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_3/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       2.817     3.338    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X112Y100       FDRE                                         r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_3/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_r2_reg[19]/R
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.846ns  (logic 0.055ns (6.501%)  route 0.791ns (93.499%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.284ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.261ns
    Source Clock Delay      (SCD):    1.977ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.628ns (routing 0.748ns, distribution 0.880ns)
  Clock Net Delay (Destination): 1.813ns (routing 0.827ns, distribution 0.986ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       1.628     1.977    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X82Y270        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y270        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     2.015 f  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.224     2.239    d_1_i/rst_dac0/U0/peripheral_aresetn[0]
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.256 f  d_1_i/rst_dac0/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=29204, routed)       0.567     2.823    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aresetn
    SLICE_X81Y267        FDRE                                         r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_r2_reg[19]/R  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       1.813     2.261    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X81Y267        FDRE                                         r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_r2_reg[19]/C

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_r2_reg[21]/R
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.846ns  (logic 0.055ns (6.501%)  route 0.791ns (93.499%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.284ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.261ns
    Source Clock Delay      (SCD):    1.977ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.628ns (routing 0.748ns, distribution 0.880ns)
  Clock Net Delay (Destination): 1.813ns (routing 0.827ns, distribution 0.986ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       1.628     1.977    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X82Y270        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y270        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     2.015 f  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.224     2.239    d_1_i/rst_dac0/U0/peripheral_aresetn[0]
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.256 f  d_1_i/rst_dac0/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=29204, routed)       0.567     2.823    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aresetn
    SLICE_X81Y267        FDRE                                         r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_r2_reg[21]/R  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       1.813     2.261    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X81Y267        FDRE                                         r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_r2_reg[21]/C

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_r2_reg[0]/R
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.848ns  (logic 0.055ns (6.486%)  route 0.793ns (93.514%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.290ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.267ns
    Source Clock Delay      (SCD):    1.977ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.628ns (routing 0.748ns, distribution 0.880ns)
  Clock Net Delay (Destination): 1.819ns (routing 0.827ns, distribution 0.992ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       1.628     1.977    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X82Y270        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y270        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     2.015 f  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.224     2.239    d_1_i/rst_dac0/U0/peripheral_aresetn[0]
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.256 f  d_1_i/rst_dac0/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=29204, routed)       0.569     2.825    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aresetn
    SLICE_X81Y279        FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_r2_reg[0]/R  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       1.819     2.267    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X81Y279        FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_r2_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[1101]/R
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.848ns  (logic 0.055ns (6.486%)  route 0.793ns (93.514%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.290ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.267ns
    Source Clock Delay      (SCD):    1.977ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.628ns (routing 0.748ns, distribution 0.880ns)
  Clock Net Delay (Destination): 1.819ns (routing 0.827ns, distribution 0.992ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       1.628     1.977    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X82Y270        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y270        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     2.015 f  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.224     2.239    d_1_i/rst_dac0/U0/peripheral_aresetn[0]
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.256 f  d_1_i/rst_dac0/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=29204, routed)       0.569     2.825    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/clear
    SLICE_X81Y279        FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[1101]/R  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       1.819     2.267    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X81Y279        FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[1101]/C

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[1099]/R
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.849ns  (logic 0.055ns (6.478%)  route 0.794ns (93.522%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.291ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.268ns
    Source Clock Delay      (SCD):    1.977ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.628ns (routing 0.748ns, distribution 0.880ns)
  Clock Net Delay (Destination): 1.820ns (routing 0.827ns, distribution 0.993ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       1.628     1.977    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X82Y270        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y270        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     2.015 f  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.224     2.239    d_1_i/rst_dac0/U0/peripheral_aresetn[0]
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.256 f  d_1_i/rst_dac0/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=29204, routed)       0.570     2.826    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/clear
    SLICE_X81Y281        FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[1099]/R  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       1.820     2.268    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X81Y281        FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[1099]/C

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[1106]/R
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.849ns  (logic 0.055ns (6.478%)  route 0.794ns (93.522%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.291ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.268ns
    Source Clock Delay      (SCD):    1.977ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.628ns (routing 0.748ns, distribution 0.880ns)
  Clock Net Delay (Destination): 1.820ns (routing 0.827ns, distribution 0.993ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       1.628     1.977    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X82Y270        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y270        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     2.015 f  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.224     2.239    d_1_i/rst_dac0/U0/peripheral_aresetn[0]
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.256 f  d_1_i/rst_dac0/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=29204, routed)       0.570     2.826    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/clear
    SLICE_X81Y281        FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[1106]/R  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       1.820     2.268    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X81Y281        FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[1106]/C

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/ctrl_i/fifo_dout_r_reg[148]/R
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.849ns  (logic 0.055ns (6.478%)  route 0.794ns (93.522%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.291ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.268ns
    Source Clock Delay      (SCD):    1.977ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.628ns (routing 0.748ns, distribution 0.880ns)
  Clock Net Delay (Destination): 1.820ns (routing 0.827ns, distribution 0.993ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       1.628     1.977    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X82Y270        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y270        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     2.015 f  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.224     2.239    d_1_i/rst_dac0/U0/peripheral_aresetn[0]
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.256 f  d_1_i/rst_dac0/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=29204, routed)       0.570     2.826    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aresetn
    SLICE_X81Y281        FDRE                                         r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/ctrl_i/fifo_dout_r_reg[148]/R  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       1.820     2.268    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X81Y281        FDRE                                         r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/ctrl_i/fifo_dout_r_reg[148]/C

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[6].prodg_y_full_real_r_reg[6]/DSP_M_DATA_INST/RSTM
                            (rising edge-triggered cell DSP_M_DATA clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.854ns  (logic 0.055ns (6.440%)  route 0.799ns (93.560%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.327ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.304ns
    Source Clock Delay      (SCD):    1.977ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.628ns (routing 0.748ns, distribution 0.880ns)
  Clock Net Delay (Destination): 1.856ns (routing 0.827ns, distribution 1.029ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       1.628     1.977    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X82Y270        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y270        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     2.015 f  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.224     2.239    d_1_i/rst_dac0/U0/peripheral_aresetn[0]
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.256 f  d_1_i/rst_dac0/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=29204, routed)       0.575     2.831    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[6].prodg_y_full_real_r_reg[6]/RSTM
    DSP48E2_X16Y109      DSP_M_DATA                                   r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[6].prodg_y_full_real_r_reg[6]/DSP_M_DATA_INST/RSTM  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       1.856     2.304    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[6].prodg_y_full_real_r_reg[6]/CLK
    DSP48E2_X16Y109      DSP_M_DATA                                   r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[6].prodg_y_full_real_r_reg[6]/DSP_M_DATA_INST/CLK

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[481]/R
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.855ns  (logic 0.055ns (6.433%)  route 0.800ns (93.567%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.301ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.278ns
    Source Clock Delay      (SCD):    1.977ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.628ns (routing 0.748ns, distribution 0.880ns)
  Clock Net Delay (Destination): 1.830ns (routing 0.827ns, distribution 1.003ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       1.628     1.977    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X82Y270        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y270        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     2.015 f  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.224     2.239    d_1_i/rst_dac0/U0/peripheral_aresetn[0]
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.256 f  d_1_i/rst_dac0/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=29204, routed)       0.576     2.832    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/clear
    SLICE_X88Y269        FDRE                                         r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[481]/R  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       1.830     2.278    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X88Y269        FDRE                                         r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[481]/C

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[494]/R
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.855ns  (logic 0.055ns (6.433%)  route 0.800ns (93.567%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.301ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.278ns
    Source Clock Delay      (SCD):    1.977ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.628ns (routing 0.748ns, distribution 0.880ns)
  Clock Net Delay (Destination): 1.830ns (routing 0.827ns, distribution 1.003ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       1.628     1.977    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X82Y270        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y270        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     2.015 f  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.224     2.239    d_1_i/rst_dac0/U0/peripheral_aresetn[0]
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.256 f  d_1_i/rst_dac0/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=29204, routed)       0.576     2.832    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/clear
    SLICE_X88Y269        FDRE                                         r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[494]/R  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       1.830     2.278    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X88Y269        FDRE                                         r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[494]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_out1_d_1_clk_adc0_x2_0
  To Clock:  RFDAC0_CLK

Max Delay             4 Endpoints
Min Delay             4 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][1]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.381ns  (logic 0.238ns (17.239%)  route 1.143ns (82.761%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        -2.384ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.079ns
    Source Clock Delay      (SCD):    5.463ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.195ns (routing 0.858ns, distribution 1.337ns)
  Clock Net Delay (Destination): 2.558ns (routing 1.256ns, distribution 1.302ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.595     3.122    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.995 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.240    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.268 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       2.195     5.463    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/m_axis_aclk
    SLICE_X32Y212        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X32Y212        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     5.542 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[1]/Q
                         net (fo=204, routed)         0.755     6.297    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][3]_0[0]
    SLICE_X27Y231        LUT2 (Prop_C5LUT_SLICEM_I0_O)
                                                      0.159     6.456 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg[0][1]_i_1__0/O
                         net (fo=1, routed)           0.388     6.844    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/rptr_g[1]
    SLICE_X24Y231        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][1]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       2.558     3.079    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/s_axis_aclk
    SLICE_X24Y231        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][1]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[0]_rep/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][0]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.321ns  (logic 0.175ns (13.252%)  route 1.146ns (86.748%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        -2.392ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.076ns
    Source Clock Delay      (SCD):    5.468ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.200ns (routing 0.858ns, distribution 1.342ns)
  Clock Net Delay (Destination): 2.555ns (routing 1.256ns, distribution 1.299ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.595     3.122    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.995 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.240    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.268 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       2.200     5.468    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/m_axis_aclk
    SLICE_X31Y204        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[0]_rep/C
  -------------------------------------------------------------------    -------------------
    SLICE_X31Y204        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     5.545 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[0]_rep/Q
                         net (fo=131, routed)         0.174     5.719    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][0]_0[0]
    SLICE_X32Y208        LUT2 (Prop_A6LUT_SLICEL_I0_O)
                                                      0.098     5.817 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg[0][0]_i_1__0/O
                         net (fo=7, routed)           0.972     6.789    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/D[0]
    SLICE_X27Y235        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       2.555     3.076    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/s_axis_aclk
    SLICE_X27Y235        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][0]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[3]_rep__0/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][3]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.871ns  (logic 0.081ns (9.296%)  route 0.790ns (90.704%))
  Logic Levels:           0  
  Clock Path Skew:        -2.374ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.076ns
    Source Clock Delay      (SCD):    5.450ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.182ns (routing 0.858ns, distribution 1.324ns)
  Clock Net Delay (Destination): 2.555ns (routing 1.256ns, distribution 1.299ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.595     3.122    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.995 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.240    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.268 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       2.182     5.450    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/m_axis_aclk
    SLICE_X29Y214        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[3]_rep__0/C
  -------------------------------------------------------------------    -------------------
    SLICE_X29Y214        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.081     5.531 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[3]_rep__0/Q
                         net (fo=114, routed)         0.790     6.321    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/rptr_reg[3]_rep__0_n_0_alias
    SLICE_X23Y235        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][3]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       2.555     3.076    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/s_axis_aclk
    SLICE_X23Y235        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][3]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[2]_rep__0/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][2]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.858ns  (logic 0.150ns (17.480%)  route 0.708ns (82.520%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        -2.362ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.077ns
    Source Clock Delay      (SCD):    5.439ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.171ns (routing 0.858ns, distribution 1.313ns)
  Clock Net Delay (Destination): 2.556ns (routing 1.256ns, distribution 1.300ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.595     3.122    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.995 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.240    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.268 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       2.171     5.439    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/m_axis_aclk
    SLICE_X33Y213        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[2]_rep__0/C
  -------------------------------------------------------------------    -------------------
    SLICE_X33Y213        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.080     5.519 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[2]_rep__0/Q
                         net (fo=139, routed)         0.685     6.204    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/rptr_reg[2]_rep__0_n_0_alias
    SLICE_X27Y235        LUT2 (Prop_A5LUT_SLICEM_I0_O)
                                                      0.070     6.274 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg[0][2]_i_1__0/O
                         net (fo=1, routed)           0.023     6.297    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/rptr_g[2]
    SLICE_X27Y235        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][2]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       2.556     3.077    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/s_axis_aclk
    SLICE_X27Y235        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][2]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[3]_rep__0/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][2]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.367ns  (logic 0.099ns (26.954%)  route 0.268ns (73.046%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        -1.088ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.183ns
    Source Clock Delay      (SCD):    3.272ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.201ns (routing 0.470ns, distribution 0.731ns)
  Clock Net Delay (Destination): 1.735ns (routing 0.827ns, distribution 0.908ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.415     1.678    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.908 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.054    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.071 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.201     3.272    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/m_axis_aclk
    SLICE_X29Y214        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[3]_rep__0/C
  -------------------------------------------------------------------    -------------------
    SLICE_X29Y214        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.040     3.312 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[3]_rep__0/Q
                         net (fo=114, routed)         0.261     3.573    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/rptr_reg[3]_rep__0_n_0_alias
    SLICE_X27Y235        LUT2 (Prop_A5LUT_SLICEM_I1_O)
                                                      0.059     3.632 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg[0][2]_i_1__0/O
                         net (fo=1, routed)           0.007     3.639    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/rptr_g[2]
    SLICE_X27Y235        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][2]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       1.735     2.183    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/s_axis_aclk
    SLICE_X27Y235        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][2]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[3]_rep__0/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][3]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.392ns  (logic 0.040ns (10.204%)  route 0.352ns (89.796%))
  Logic Levels:           0  
  Clock Path Skew:        -1.091ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.181ns
    Source Clock Delay      (SCD):    3.272ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.201ns (routing 0.470ns, distribution 0.731ns)
  Clock Net Delay (Destination): 1.733ns (routing 0.827ns, distribution 0.906ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.415     1.678    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.908 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.054    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.071 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.201     3.272    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/m_axis_aclk
    SLICE_X29Y214        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[3]_rep__0/C
  -------------------------------------------------------------------    -------------------
    SLICE_X29Y214        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.040     3.312 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[3]_rep__0/Q
                         net (fo=114, routed)         0.352     3.664    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/rptr_reg[3]_rep__0_n_0_alias
    SLICE_X23Y235        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][3]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       1.733     2.181    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/s_axis_aclk
    SLICE_X23Y235        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][3]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][1]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.626ns  (logic 0.075ns (11.974%)  route 0.551ns (88.026%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        -1.091ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.184ns
    Source Clock Delay      (SCD):    3.276ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.205ns (routing 0.470ns, distribution 0.735ns)
  Clock Net Delay (Destination): 1.736ns (routing 0.827ns, distribution 0.909ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.415     1.678    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.908 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.054    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.071 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.205     3.276    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/m_axis_aclk
    SLICE_X30Y206        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X30Y206        FDRE (Prop_CFF2_SLICEM_C_Q)
                                                      0.039     3.315 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[2]/Q
                         net (fo=205, routed)         0.386     3.701    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][3]_0[1]
    SLICE_X27Y231        LUT2 (Prop_C5LUT_SLICEM_I1_O)
                                                      0.036     3.737 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg[0][1]_i_1__0/O
                         net (fo=1, routed)           0.165     3.902    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/rptr_g[1]
    SLICE_X24Y231        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][1]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       1.736     2.184    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/s_axis_aclk
    SLICE_X24Y231        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][1]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[0]_rep/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][0]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.647ns  (logic 0.079ns (12.217%)  route 0.568ns (87.783%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        -1.096ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.182ns
    Source Clock Delay      (SCD):    3.278ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.207ns (routing 0.470ns, distribution 0.737ns)
  Clock Net Delay (Destination): 1.734ns (routing 0.827ns, distribution 0.907ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.415     1.678    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.908 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.054    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.071 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.207     3.278    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/m_axis_aclk
    SLICE_X31Y204        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[0]_rep/C
  -------------------------------------------------------------------    -------------------
    SLICE_X31Y204        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     3.316 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[0]_rep/Q
                         net (fo=131, routed)         0.093     3.409    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][0]_0[0]
    SLICE_X32Y208        LUT2 (Prop_A6LUT_SLICEL_I0_O)
                                                      0.041     3.450 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg[0][0]_i_1__0/O
                         net (fo=7, routed)           0.475     3.925    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/D[0]
    SLICE_X27Y235        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       1.734     2.182    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/s_axis_aclk
    SLICE_X27Y235        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_out1_d_1_clk_core_0
  To Clock:  RFDAC0_CLK

Max Delay           822 Endpoints
Min Delay           822 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/rd_gptr_r_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/data_cdc_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.897ns  (logic 0.724ns (18.580%)  route 3.173ns (81.420%))
  Logic Levels:           7  (LUT3=2 LUT5=2 LUT6=3)
  Clock Path Skew:        -2.458ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.231ns
    Source Clock Delay      (SCD):    5.689ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.085ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      2.051ns (routing 0.920ns, distribution 1.131ns)
  Clock Net Delay (Destination): 2.710ns (routing 1.256ns, distribution 1.454ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.819     3.492    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.365 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.610    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.638 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        2.051     5.689    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/c_clk_i
    SLICE_X10Y332        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/rd_gptr_r_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X10Y332        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.081     5.770 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/rd_gptr_r_reg[7]/Q
                         net (fo=1, routed)           0.193     5.963    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/gcc_wr_ptr/out[7]
    SLICE_X10Y332        LUT6 (Prop_D6LUT_SLICEL_I3_O)
                                                      0.146     6.109 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/gcc_wr_ptr/count_gray_r[8]_i_4__24/O
                         net (fo=3, routed)           0.492     6.601    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/gcc_wr_ptr/count_gray_r[8]_i_4__24_n_0
    SLICE_X13Y331        LUT5 (Prop_E6LUT_SLICEM_I1_O)
                                                      0.124     6.725 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/gcc_wr_ptr/core_en_i_8/O
                         net (fo=2, routed)           0.401     7.126    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/c_fifo_wave_push_r_reg[0][1]
    SLICE_X15Y347        LUT5 (Prop_C6LUT_SLICEL_I2_O)
                                                      0.050     7.176 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/core_en_i_2/O
                         net (fo=5, routed)           0.664     7.839    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER_n_310
    SLICE_X26Y370        LUT6 (Prop_H6LUT_SLICEL_I1_O)
                                                      0.051     7.890 r  d_1_i/qick_processor_0/inst/QPROC/core_en/O
                         net (fo=600, routed)         0.274     8.164    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/E[0]
    SLICE_X26Y378        LUT6 (Prop_H6LUT_SLICEL_I2_O)
                                                      0.051     8.215 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/data_cdc[4]_i_3/O
                         net (fo=4, routed)           0.101     8.316    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/x1_ctrl_reg[usr_ctrl][8]_0
    SLICE_X26Y377        LUT3 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.122     8.438 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/data_cdc[3]_i_2/O
                         net (fo=33, routed)          0.274     8.711    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/data_cdc_reg[3]_0
    SLICE_X26Y363        LUT3 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.099     8.810 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/data_cdc[3]_i_1/O
                         net (fo=33, routed)          0.775     9.586    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/tproc_ctrl_2r_reg[1][0]
    SLICE_X12Y350        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/data_cdc_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       2.710     3.231    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/t_clk_i
    SLICE_X12Y350        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/data_cdc_reg[3]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/rd_gptr_r_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/data_cdc_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.668ns  (logic 0.540ns (14.724%)  route 3.128ns (85.276%))
  Logic Levels:           6  (LUT5=2 LUT6=4)
  Clock Path Skew:        -2.460ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.229ns
    Source Clock Delay      (SCD):    5.689ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.085ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      2.051ns (routing 0.920ns, distribution 1.131ns)
  Clock Net Delay (Destination): 2.708ns (routing 1.256ns, distribution 1.452ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.819     3.492    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.365 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.610    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.638 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        2.051     5.689    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/c_clk_i
    SLICE_X10Y332        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/rd_gptr_r_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X10Y332        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.081     5.770 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/rd_gptr_r_reg[7]/Q
                         net (fo=1, routed)           0.193     5.963    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/gcc_wr_ptr/out[7]
    SLICE_X10Y332        LUT6 (Prop_D6LUT_SLICEL_I3_O)
                                                      0.146     6.109 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/gcc_wr_ptr/count_gray_r[8]_i_4__24/O
                         net (fo=3, routed)           0.492     6.601    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/gcc_wr_ptr/count_gray_r[8]_i_4__24_n_0
    SLICE_X13Y331        LUT5 (Prop_E6LUT_SLICEM_I1_O)
                                                      0.124     6.725 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/gcc_wr_ptr/core_en_i_8/O
                         net (fo=2, routed)           0.401     7.126    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/c_fifo_wave_push_r_reg[0][1]
    SLICE_X15Y347        LUT5 (Prop_C6LUT_SLICEL_I2_O)
                                                      0.050     7.176 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/core_en_i_2/O
                         net (fo=5, routed)           0.664     7.839    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER_n_310
    SLICE_X26Y370        LUT6 (Prop_H6LUT_SLICEL_I1_O)
                                                      0.051     7.890 r  d_1_i/qick_processor_0/inst/QPROC/core_en/O
                         net (fo=600, routed)         0.274     8.164    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/E[0]
    SLICE_X26Y378        LUT6 (Prop_H6LUT_SLICEL_I2_O)
                                                      0.051     8.215 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/data_cdc[4]_i_3/O
                         net (fo=4, routed)           0.369     8.584    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/int_time_pen
    SLICE_X24Y366        LUT6 (Prop_C6LUT_SLICEM_I3_O)
                                                      0.037     8.621 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/data_cdc[4]_i_1/O
                         net (fo=1, routed)           0.736     9.357    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/p_8_out[4]
    SLICE_X12Y346        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/data_cdc_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       2.708     3.229    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/t_clk_i
    SLICE_X12Y346        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/data_cdc_reg[4]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/clr_fifo_ack_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[7]/CE
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.895ns  (logic 0.400ns (21.111%)  route 1.495ns (78.889%))
  Logic Levels:           4  (LUT3=1 LUT5=3)
  Clock Path Skew:        -2.451ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.171ns
    Source Clock Delay      (SCD):    5.622ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.085ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      1.984ns (routing 0.920ns, distribution 1.064ns)
  Clock Net Delay (Destination): 2.650ns (routing 1.256ns, distribution 1.394ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.819     3.492    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.365 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.610    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.638 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.984     5.622    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/c_clk_i
    SLICE_X25Y422        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/clr_fifo_ack_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X25Y422        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     5.701 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/clr_fifo_ack_reg/Q
                         net (fo=4, routed)           0.229     5.930    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/clr_fifo_ack
    SLICE_X25Y414        LUT3 (Prop_D5LUT_SLICEL_I2_O)
                                                      0.157     6.087 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/t_fifo_trig_empty_inferred_i_5/O
                         net (fo=1, routed)           0.215     6.302    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/D[0]
    SLICE_X23Y412        LUT5 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.039     6.341 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/trig_pop_r[9]_i_2/O
                         net (fo=1, routed)           0.274     6.615    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/trig_pop_r_reg[9]_0
    SLICE_X22Y403        LUT5 (Prop_A6LUT_SLICEL_I4_O)
                                                      0.090     6.705 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/trig_pop_r[9]_i_1/O
                         net (fo=2, routed)           0.421     7.126    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/trig_pop55_out
    SLICE_X25Y424        LUT5 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.035     7.161 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/count_gray_r[8]_i_1__17/O
                         net (fo=18, routed)          0.355     7.517    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/count_bin_2r
    SLICE_X26Y427        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[7]/CE
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       2.650     3.171    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X26Y427        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[7]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/clr_fifo_ack_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/count_gray_r_reg[5]/CE
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.895ns  (logic 0.400ns (21.111%)  route 1.495ns (78.889%))
  Logic Levels:           4  (LUT3=1 LUT5=3)
  Clock Path Skew:        -2.451ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.171ns
    Source Clock Delay      (SCD):    5.622ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.085ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      1.984ns (routing 0.920ns, distribution 1.064ns)
  Clock Net Delay (Destination): 2.650ns (routing 1.256ns, distribution 1.394ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.819     3.492    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.365 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.610    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.638 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.984     5.622    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/c_clk_i
    SLICE_X25Y422        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/clr_fifo_ack_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X25Y422        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     5.701 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/clr_fifo_ack_reg/Q
                         net (fo=4, routed)           0.229     5.930    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/clr_fifo_ack
    SLICE_X25Y414        LUT3 (Prop_D5LUT_SLICEL_I2_O)
                                                      0.157     6.087 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/t_fifo_trig_empty_inferred_i_5/O
                         net (fo=1, routed)           0.215     6.302    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/D[0]
    SLICE_X23Y412        LUT5 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.039     6.341 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/trig_pop_r[9]_i_2/O
                         net (fo=1, routed)           0.274     6.615    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/trig_pop_r_reg[9]_0
    SLICE_X22Y403        LUT5 (Prop_A6LUT_SLICEL_I4_O)
                                                      0.090     6.705 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/trig_pop_r[9]_i_1/O
                         net (fo=2, routed)           0.421     7.126    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/trig_pop55_out
    SLICE_X25Y424        LUT5 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.035     7.161 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/count_gray_r[8]_i_1__17/O
                         net (fo=18, routed)          0.355     7.517    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/count_bin_2r
    SLICE_X26Y427        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/count_gray_r_reg[5]/CE
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       2.650     3.171    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X26Y427        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/count_gray_r_reg[5]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/clr_fifo_ack_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[6]/CE
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.870ns  (logic 0.400ns (21.385%)  route 1.470ns (78.615%))
  Logic Levels:           4  (LUT3=1 LUT5=3)
  Clock Path Skew:        -2.453ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.169ns
    Source Clock Delay      (SCD):    5.622ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.085ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      1.984ns (routing 0.920ns, distribution 1.064ns)
  Clock Net Delay (Destination): 2.648ns (routing 1.256ns, distribution 1.392ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.819     3.492    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.365 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.610    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.638 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.984     5.622    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/c_clk_i
    SLICE_X25Y422        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/clr_fifo_ack_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X25Y422        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     5.701 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/clr_fifo_ack_reg/Q
                         net (fo=4, routed)           0.229     5.930    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/clr_fifo_ack
    SLICE_X25Y414        LUT3 (Prop_D5LUT_SLICEL_I2_O)
                                                      0.157     6.087 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/t_fifo_trig_empty_inferred_i_5/O
                         net (fo=1, routed)           0.215     6.302    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/D[0]
    SLICE_X23Y412        LUT5 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.039     6.341 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/trig_pop_r[9]_i_2/O
                         net (fo=1, routed)           0.274     6.615    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/trig_pop_r_reg[9]_0
    SLICE_X22Y403        LUT5 (Prop_A6LUT_SLICEL_I4_O)
                                                      0.090     6.705 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/trig_pop_r[9]_i_1/O
                         net (fo=2, routed)           0.421     7.126    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/trig_pop55_out
    SLICE_X25Y424        LUT5 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.035     7.161 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/count_gray_r[8]_i_1__17/O
                         net (fo=18, routed)          0.331     7.492    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/count_bin_2r
    SLICE_X26Y427        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[6]/CE
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       2.648     3.169    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X26Y427        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[6]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/clr_fifo_ack_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/count_gray_r_reg[6]/CE
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.870ns  (logic 0.400ns (21.385%)  route 1.470ns (78.615%))
  Logic Levels:           4  (LUT3=1 LUT5=3)
  Clock Path Skew:        -2.453ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.169ns
    Source Clock Delay      (SCD):    5.622ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.085ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      1.984ns (routing 0.920ns, distribution 1.064ns)
  Clock Net Delay (Destination): 2.648ns (routing 1.256ns, distribution 1.392ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.819     3.492    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.365 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.610    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.638 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.984     5.622    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/c_clk_i
    SLICE_X25Y422        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/clr_fifo_ack_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X25Y422        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     5.701 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/clr_fifo_ack_reg/Q
                         net (fo=4, routed)           0.229     5.930    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/clr_fifo_ack
    SLICE_X25Y414        LUT3 (Prop_D5LUT_SLICEL_I2_O)
                                                      0.157     6.087 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/t_fifo_trig_empty_inferred_i_5/O
                         net (fo=1, routed)           0.215     6.302    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/D[0]
    SLICE_X23Y412        LUT5 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.039     6.341 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/trig_pop_r[9]_i_2/O
                         net (fo=1, routed)           0.274     6.615    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/trig_pop_r_reg[9]_0
    SLICE_X22Y403        LUT5 (Prop_A6LUT_SLICEL_I4_O)
                                                      0.090     6.705 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/trig_pop_r[9]_i_1/O
                         net (fo=2, routed)           0.421     7.126    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/trig_pop55_out
    SLICE_X25Y424        LUT5 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.035     7.161 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/count_gray_r[8]_i_1__17/O
                         net (fo=18, routed)          0.331     7.492    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/count_bin_2r
    SLICE_X26Y427        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/count_gray_r_reg[6]/CE
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       2.648     3.169    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X26Y427        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/count_gray_r_reg[6]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/clr_fifo_ack_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/count_gray_r_reg[7]/CE
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.870ns  (logic 0.400ns (21.385%)  route 1.470ns (78.615%))
  Logic Levels:           4  (LUT3=1 LUT5=3)
  Clock Path Skew:        -2.453ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.169ns
    Source Clock Delay      (SCD):    5.622ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.085ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      1.984ns (routing 0.920ns, distribution 1.064ns)
  Clock Net Delay (Destination): 2.648ns (routing 1.256ns, distribution 1.392ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.819     3.492    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.365 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.610    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.638 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.984     5.622    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/c_clk_i
    SLICE_X25Y422        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/clr_fifo_ack_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X25Y422        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     5.701 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/clr_fifo_ack_reg/Q
                         net (fo=4, routed)           0.229     5.930    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/clr_fifo_ack
    SLICE_X25Y414        LUT3 (Prop_D5LUT_SLICEL_I2_O)
                                                      0.157     6.087 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/t_fifo_trig_empty_inferred_i_5/O
                         net (fo=1, routed)           0.215     6.302    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/D[0]
    SLICE_X23Y412        LUT5 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.039     6.341 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/trig_pop_r[9]_i_2/O
                         net (fo=1, routed)           0.274     6.615    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/trig_pop_r_reg[9]_0
    SLICE_X22Y403        LUT5 (Prop_A6LUT_SLICEL_I4_O)
                                                      0.090     6.705 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/trig_pop_r[9]_i_1/O
                         net (fo=2, routed)           0.421     7.126    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/trig_pop55_out
    SLICE_X25Y424        LUT5 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.035     7.161 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/count_gray_r[8]_i_1__17/O
                         net (fo=18, routed)          0.331     7.492    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/count_bin_2r
    SLICE_X26Y427        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/count_gray_r_reg[7]/CE
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       2.648     3.169    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X26Y427        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/count_gray_r_reg[7]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/clr_fifo_ack_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/count_gray_r_reg[8]/CE
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.870ns  (logic 0.400ns (21.385%)  route 1.470ns (78.615%))
  Logic Levels:           4  (LUT3=1 LUT5=3)
  Clock Path Skew:        -2.453ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.169ns
    Source Clock Delay      (SCD):    5.622ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.085ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      1.984ns (routing 0.920ns, distribution 1.064ns)
  Clock Net Delay (Destination): 2.648ns (routing 1.256ns, distribution 1.392ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.819     3.492    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.365 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.610    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.638 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.984     5.622    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/c_clk_i
    SLICE_X25Y422        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/clr_fifo_ack_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X25Y422        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     5.701 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/clr_fifo_ack_reg/Q
                         net (fo=4, routed)           0.229     5.930    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/clr_fifo_ack
    SLICE_X25Y414        LUT3 (Prop_D5LUT_SLICEL_I2_O)
                                                      0.157     6.087 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/t_fifo_trig_empty_inferred_i_5/O
                         net (fo=1, routed)           0.215     6.302    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/D[0]
    SLICE_X23Y412        LUT5 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.039     6.341 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/trig_pop_r[9]_i_2/O
                         net (fo=1, routed)           0.274     6.615    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/trig_pop_r_reg[9]_0
    SLICE_X22Y403        LUT5 (Prop_A6LUT_SLICEL_I4_O)
                                                      0.090     6.705 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/trig_pop_r[9]_i_1/O
                         net (fo=2, routed)           0.421     7.126    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/trig_pop55_out
    SLICE_X25Y424        LUT5 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.035     7.161 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/count_gray_r[8]_i_1__17/O
                         net (fo=18, routed)          0.331     7.492    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/count_bin_2r
    SLICE_X26Y427        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/count_gray_r_reg[8]/CE
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       2.648     3.169    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X26Y427        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/count_gray_r_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/clr_fifo_ack_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[0]/CE
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.858ns  (logic 0.400ns (21.531%)  route 1.458ns (78.469%))
  Logic Levels:           4  (LUT3=1 LUT5=3)
  Clock Path Skew:        -2.451ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.171ns
    Source Clock Delay      (SCD):    5.622ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.085ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      1.984ns (routing 0.920ns, distribution 1.064ns)
  Clock Net Delay (Destination): 2.650ns (routing 1.256ns, distribution 1.394ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.819     3.492    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.365 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.610    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.638 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.984     5.622    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/c_clk_i
    SLICE_X25Y422        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/clr_fifo_ack_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X25Y422        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     5.701 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/clr_fifo_ack_reg/Q
                         net (fo=4, routed)           0.229     5.930    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/clr_fifo_ack
    SLICE_X25Y414        LUT3 (Prop_D5LUT_SLICEL_I2_O)
                                                      0.157     6.087 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/t_fifo_trig_empty_inferred_i_5/O
                         net (fo=1, routed)           0.215     6.302    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/D[0]
    SLICE_X23Y412        LUT5 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.039     6.341 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/trig_pop_r[9]_i_2/O
                         net (fo=1, routed)           0.274     6.615    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/trig_pop_r_reg[9]_0
    SLICE_X22Y403        LUT5 (Prop_A6LUT_SLICEL_I4_O)
                                                      0.090     6.705 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/trig_pop_r[9]_i_1/O
                         net (fo=2, routed)           0.421     7.126    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/trig_pop55_out
    SLICE_X25Y424        LUT5 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.035     7.161 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/count_gray_r[8]_i_1__17/O
                         net (fo=18, routed)          0.318     7.480    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/count_bin_2r
    SLICE_X26Y426        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[0]/CE
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       2.650     3.171    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X26Y426        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/clr_fifo_req_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[0]/CE
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.784ns  (logic 0.354ns (19.847%)  route 1.430ns (80.153%))
  Logic Levels:           4  (LUT3=1 LUT5=3)
  Clock Path Skew:        -2.411ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.269ns
    Source Clock Delay      (SCD):    5.680ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.085ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      2.042ns (routing 0.920ns, distribution 1.122ns)
  Clock Net Delay (Destination): 2.748ns (routing 1.256ns, distribution 1.492ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.819     3.492    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.365 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.610    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.638 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        2.042     5.680    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/c_clk_i
    SLICE_X13Y358        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/clr_fifo_req_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X13Y358        FDCE (Prop_HFF2_SLICEM_C_Q)
                                                      0.078     5.758 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/clr_fifo_req_reg/Q
                         net (fo=5, routed)           0.549     6.307    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/clr_fifo_req
    SLICE_X9Y354         LUT3 (Prop_H6LUT_SLICEL_I1_O)
                                                      0.090     6.397 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/t_fifo_trig_empty_inferred_i_1/O
                         net (fo=1, routed)           0.135     6.532    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/gcc_rd_ptr/D[0]
    SLICE_X9Y351         LUT5 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.036     6.568 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/gcc_rd_ptr/trig_pop_r[13]_i_2/O
                         net (fo=1, routed)           0.199     6.767    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/trig_pop_r_reg[13]_0
    SLICE_X5Y351         LUT5 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.053     6.820 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/trig_pop_r[13]_i_1/O
                         net (fo=2, routed)           0.272     7.092    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/gcc_rd_ptr/trig_pop39_out
    SLICE_X3Y354         LUT5 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.097     7.189 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/gcc_rd_ptr/count_gray_r[8]_i_1__25/O
                         net (fo=18, routed)          0.274     7.464    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/gcc_rd_ptr/count_bin_2r
    SLICE_X3Y355         FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[0]/CE
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       2.748     3.269    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X3Y355         FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[0]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/wr_gptr_cdc_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.099ns  (logic 0.039ns (39.218%)  route 0.060ns (60.782%))
  Logic Levels:           0  
  Clock Path Skew:        -1.114ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.264ns
    Source Clock Delay      (SCD):    3.379ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.085ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      1.098ns (routing 0.503ns, distribution 0.595ns)
  Clock Net Delay (Destination): 1.816ns (routing 0.827ns, distribution 0.989ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       1.539     1.888    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     2.118 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.264    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.281 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.098     3.379    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X26Y424        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X26Y424        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     3.418 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[2]/Q
                         net (fo=2, routed)           0.060     3.478    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/wr_gptr[2]
    SLICE_X26Y425        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/wr_gptr_cdc_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       1.816     2.264    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/t_clk_i
    SLICE_X26Y425        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/wr_gptr_cdc_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[9].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[9].wave_fifo_inst/wr_gptr_cdc_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.080ns  (logic 0.038ns (47.689%)  route 0.042ns (52.311%))
  Logic Levels:           0  
  Clock Path Skew:        -1.108ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.292ns
    Source Clock Delay      (SCD):    3.401ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.085ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      1.120ns (routing 0.503ns, distribution 0.617ns)
  Clock Net Delay (Destination): 1.844ns (routing 0.827ns, distribution 1.017ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       1.539     1.888    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     2.118 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.264    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.281 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.120     3.401    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[9].wave_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X13Y329        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[9].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X13Y329        FDCE (Prop_CFF_SLICEM_C_Q)
                                                      0.038     3.439 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[9].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[2]/Q
                         net (fo=4, routed)           0.042     3.480    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[9].wave_fifo_inst/wr_gptr[2]
    SLICE_X13Y328        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[9].wave_fifo_inst/wr_gptr_cdc_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       1.844     2.292    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[9].wave_fifo_inst/t_clk_i
    SLICE_X13Y328        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[9].wave_fifo_inst/wr_gptr_cdc_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/clr_fifo_req_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/gcc_rd_ptr/clear_cdc_reg/D
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.107ns  (logic 0.041ns (38.181%)  route 0.066ns (61.819%))
  Logic Levels:           0  
  Clock Path Skew:        -1.112ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.264ns
    Source Clock Delay      (SCD):    3.376ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.085ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      1.095ns (routing 0.503ns, distribution 0.592ns)
  Clock Net Delay (Destination): 1.816ns (routing 0.827ns, distribution 0.989ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       1.539     1.888    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     2.118 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.264    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.281 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.095     3.376    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/c_clk_i
    SLICE_X20Y317        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/clr_fifo_req_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X20Y317        FDCE (Prop_DFF2_SLICEM_C_Q)
                                                      0.041     3.417 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/clr_fifo_req_reg/Q
                         net (fo=5, routed)           0.066     3.483    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/gcc_rd_ptr/clr_fifo_req
    SLICE_X19Y317        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/gcc_rd_ptr/clear_cdc_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       1.816     2.264    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X19Y317        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/gcc_rd_ptr/clear_cdc_reg/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/offset_dt_r_reg[15]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/time_updt_dt_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.119ns  (logic 0.054ns (45.378%)  route 0.065ns (54.622%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        -1.121ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.244ns
    Source Clock Delay      (SCD):    3.366ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.085ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      1.085ns (routing 0.503ns, distribution 0.582ns)
  Clock Net Delay (Destination): 1.796ns (routing 0.827ns, distribution 0.969ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       1.539     1.888    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     2.118 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.264    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.281 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.085     3.366    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/c_clk_i
    SLICE_X26Y362        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/offset_dt_r_reg[15]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X26Y362        FDRE (Prop_FFF2_SLICEL_C_Q)
                                                      0.040     3.406 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/offset_dt_r_reg[15]/Q
                         net (fo=1, routed)           0.049     3.455    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/time_updt_dt_reg[31][15]
    SLICE_X26Y361        LUT2 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.014     3.469 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/time_updt_dt[15]_i_1/O
                         net (fo=1, routed)           0.016     3.485    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t_n_23
    SLICE_X26Y361        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/time_updt_dt_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       1.796     2.244    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/t_clk_i
    SLICE_X26Y361        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/time_updt_dt_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/offset_dt_r_reg[23]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/time_updt_dt_reg[23]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.127ns  (logic 0.062ns (48.819%)  route 0.065ns (51.181%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        -1.121ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.244ns
    Source Clock Delay      (SCD):    3.366ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.085ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      1.085ns (routing 0.503ns, distribution 0.582ns)
  Clock Net Delay (Destination): 1.796ns (routing 0.827ns, distribution 0.969ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       1.539     1.888    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     2.118 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.264    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.281 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.085     3.366    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/c_clk_i
    SLICE_X26Y362        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/offset_dt_r_reg[23]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X26Y362        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.039     3.405 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/offset_dt_r_reg[23]/Q
                         net (fo=1, routed)           0.050     3.455    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/time_updt_dt_reg[31][23]
    SLICE_X26Y361        LUT2 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.023     3.478 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/time_updt_dt[23]_i_1/O
                         net (fo=1, routed)           0.015     3.493    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t_n_15
    SLICE_X26Y361        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/time_updt_dt_reg[23]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       1.796     2.244    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/t_clk_i
    SLICE_X26Y361        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/time_updt_dt_reg[23]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/clr_fifo_req_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_rd_ptr/clear_cdc_reg/D
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.101ns  (logic 0.038ns (37.590%)  route 0.063ns (62.410%))
  Logic Levels:           0  
  Clock Path Skew:        -1.109ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.286ns
    Source Clock Delay      (SCD):    3.395ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.085ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      1.114ns (routing 0.503ns, distribution 0.611ns)
  Clock Net Delay (Destination): 1.838ns (routing 0.827ns, distribution 1.011ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       1.539     1.888    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     2.118 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.264    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.281 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.114     3.395    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/c_clk_i
    SLICE_X13Y322        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/clr_fifo_req_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X13Y322        FDCE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     3.433 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/clr_fifo_req_reg/Q
                         net (fo=5, routed)           0.063     3.496    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_rd_ptr/clr_fifo_req
    SLICE_X14Y322        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_rd_ptr/clear_cdc_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       1.838     2.286    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X14Y322        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_rd_ptr/clear_cdc_reg/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/wr_gptr_cdc_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.097ns  (logic 0.039ns (40.338%)  route 0.058ns (59.662%))
  Logic Levels:           0  
  Clock Path Skew:        -1.111ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.288ns
    Source Clock Delay      (SCD):    3.400ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.085ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      1.119ns (routing 0.503ns, distribution 0.616ns)
  Clock Net Delay (Destination): 1.840ns (routing 0.827ns, distribution 1.013ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       1.539     1.888    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     2.118 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.264    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.281 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.119     3.400    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X13Y348        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X13Y348        FDCE (Prop_HFF2_SLICEM_C_Q)
                                                      0.039     3.439 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[0]/Q
                         net (fo=4, routed)           0.058     3.496    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/wr_gptr[0]
    SLICE_X14Y348        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/wr_gptr_cdc_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       1.840     2.288    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/t_clk_i
    SLICE_X14Y348        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/wr_gptr_cdc_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/wr_gptr_cdc_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.116ns  (logic 0.039ns (33.530%)  route 0.077ns (66.470%))
  Logic Levels:           0  
  Clock Path Skew:        -1.117ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.264ns
    Source Clock Delay      (SCD):    3.382ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.085ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      1.101ns (routing 0.503ns, distribution 0.598ns)
  Clock Net Delay (Destination): 1.816ns (routing 0.827ns, distribution 0.989ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       1.539     1.888    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     2.118 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.264    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.281 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.101     3.382    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X26Y424        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X26Y424        FDCE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     3.421 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[1]/Q
                         net (fo=2, routed)           0.077     3.498    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/wr_gptr[1]
    SLICE_X26Y425        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/wr_gptr_cdc_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       1.816     2.264    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/t_clk_i
    SLICE_X26Y425        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/wr_gptr_cdc_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[9].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[9].wave_fifo_inst/wr_gptr_cdc_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.103ns  (logic 0.039ns (38.016%)  route 0.064ns (61.984%))
  Logic Levels:           0  
  Clock Path Skew:        -1.102ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.296ns
    Source Clock Delay      (SCD):    3.398ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.085ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      1.117ns (routing 0.503ns, distribution 0.614ns)
  Clock Net Delay (Destination): 1.848ns (routing 0.827ns, distribution 1.021ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       1.539     1.888    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     2.118 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.264    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.281 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.117     3.398    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[9].wave_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X14Y329        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[9].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X14Y329        FDCE (Prop_CFF_SLICEL_C_Q)
                                                      0.039     3.437 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[9].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]/Q
                         net (fo=4, routed)           0.064     3.500    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[9].wave_fifo_inst/wr_gptr[8]
    SLICE_X14Y326        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[9].wave_fifo_inst/wr_gptr_cdc_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       1.848     2.296    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[9].wave_fifo_inst/t_clk_i
    SLICE_X14Y326        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[9].wave_fifo_inst/wr_gptr_cdc_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/wr_gptr_cdc_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.120ns  (logic 0.039ns (32.436%)  route 0.081ns (67.564%))
  Logic Levels:           0  
  Clock Path Skew:        -1.110ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.271ns
    Source Clock Delay      (SCD):    3.382ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.085ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      1.101ns (routing 0.503ns, distribution 0.598ns)
  Clock Net Delay (Destination): 1.823ns (routing 0.827ns, distribution 0.996ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       1.539     1.888    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     2.118 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.264    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.281 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.101     3.382    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X26Y424        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X26Y424        FDCE (Prop_GFF_SLICEL_C_Q)
                                                      0.039     3.421 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[3]/Q
                         net (fo=2, routed)           0.081     3.502    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/wr_gptr[3]
    SLICE_X25Y424        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/wr_gptr_cdc_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       1.823     2.271    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/t_clk_i
    SLICE_X25Y424        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/wr_gptr_cdc_reg[3]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_pl_0
  To Clock:  RFDAC0_CLK

Max Delay             4 Endpoints
Min Delay             4 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac1_done_i_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_done_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.982ns  (logic 0.079ns (8.045%)  route 0.903ns (91.955%))
  Logic Levels:           0  
  Clock Path Skew:        0.672ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.371ns
    Source Clock Delay      (SCD):    2.699ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.473ns (routing 0.662ns, distribution 1.811ns)
  Clock Net Delay (Destination): 2.850ns (routing 1.256ns, distribution 1.594ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.473     2.699    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    SLICE_X116Y248       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac1_done_i_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X116Y248       FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     2.778 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac1_done_i_reg/Q
                         net (fo=1, routed)           0.903     3.681    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_done_i/src_in
    SLICE_X117Y324       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_done_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       2.850     3.371    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_done_i/dest_clk
    SLICE_X117Y324       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_done_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac0_done_i_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac0_done_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.662ns  (logic 0.079ns (11.934%)  route 0.583ns (88.066%))
  Logic Levels:           0  
  Clock Path Skew:        0.695ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.360ns
    Source Clock Delay      (SCD):    2.664ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.438ns (routing 0.662ns, distribution 1.776ns)
  Clock Net Delay (Destination): 2.839ns (routing 1.256ns, distribution 1.583ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.438     2.664    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    SLICE_X111Y259       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac0_done_i_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X111Y259       FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     2.743 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac0_done_i_reg/Q
                         net (fo=1, routed)           0.583     3.326    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac0_done_i/src_in
    SLICE_X117Y278       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac0_done_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       2.839     3.360    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac0_done_i/dest_clk
    SLICE_X117Y278       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac0_done_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/QPROC_xREG/slv_reg1_reg[11]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/data_cdc_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.169ns  (logic 0.475ns (21.902%)  route 1.694ns (78.098%))
  Logic Levels:           4  (LUT3=2 LUT6=2)
  Clock Path Skew:        0.813ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.231ns
    Source Clock Delay      (SCD):    2.418ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.192ns (routing 0.662ns, distribution 1.530ns)
  Clock Net Delay (Destination): 2.710ns (routing 1.256ns, distribution 1.454ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.192     2.418    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/QPROC_xREG/ps_clk_i
    SLICE_X28Y356        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/QPROC_xREG/slv_reg1_reg[11]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X28Y356        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.079     2.497 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/QPROC_xREG/slv_reg1_reg[11]/Q
                         net (fo=2, routed)           0.270     2.767    d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_CFG[11]
    SLICE_X26Y370        LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.124     2.891 r  d_1_i/qick_processor_0/inst/QPROC/core_en/O
                         net (fo=600, routed)         0.274     3.165    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/E[0]
    SLICE_X26Y378        LUT6 (Prop_H6LUT_SLICEL_I2_O)
                                                      0.051     3.216 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/data_cdc[4]_i_3/O
                         net (fo=4, routed)           0.101     3.317    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/x1_ctrl_reg[usr_ctrl][8]_0
    SLICE_X26Y377        LUT3 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.122     3.439 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/data_cdc[3]_i_2/O
                         net (fo=33, routed)          0.274     3.712    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/data_cdc_reg[3]_0
    SLICE_X26Y363        LUT3 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.099     3.811 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/data_cdc[3]_i_1/O
                         net (fo=33, routed)          0.775     4.587    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/tproc_ctrl_2r_reg[1][0]
    SLICE_X12Y350        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/data_cdc_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       2.710     3.231    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/t_clk_i
    SLICE_X12Y350        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/data_cdc_reg[3]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/QPROC_xREG/slv_reg1_reg[11]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/data_cdc_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.940ns  (logic 0.291ns (15.004%)  route 1.649ns (84.996%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        0.811ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.229ns
    Source Clock Delay      (SCD):    2.418ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.192ns (routing 0.662ns, distribution 1.530ns)
  Clock Net Delay (Destination): 2.708ns (routing 1.256ns, distribution 1.452ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.192     2.418    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/QPROC_xREG/ps_clk_i
    SLICE_X28Y356        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/QPROC_xREG/slv_reg1_reg[11]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X28Y356        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.079     2.497 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/QPROC_xREG/slv_reg1_reg[11]/Q
                         net (fo=2, routed)           0.270     2.767    d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_CFG[11]
    SLICE_X26Y370        LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.124     2.891 r  d_1_i/qick_processor_0/inst/QPROC/core_en/O
                         net (fo=600, routed)         0.274     3.165    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/E[0]
    SLICE_X26Y378        LUT6 (Prop_H6LUT_SLICEL_I2_O)
                                                      0.051     3.216 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/data_cdc[4]_i_3/O
                         net (fo=4, routed)           0.369     3.585    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/int_time_pen
    SLICE_X24Y366        LUT6 (Prop_C6LUT_SLICEM_I3_O)
                                                      0.037     3.622 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/data_cdc[4]_i_1/O
                         net (fo=1, routed)           0.736     4.358    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/p_8_out[4]
    SLICE_X12Y346        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/data_cdc_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       2.708     3.229    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/t_clk_i
    SLICE_X12Y346        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/data_cdc_reg[4]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac0_done_i_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac0_done_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.319ns  (logic 0.039ns (12.226%)  route 0.280ns (87.774%))
  Logic Levels:           0  
  Clock Path Skew:        0.917ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.370ns
    Source Clock Delay      (SCD):    1.454ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.334ns (routing 0.358ns, distribution 0.976ns)
  Clock Net Delay (Destination): 1.922ns (routing 0.827ns, distribution 1.095ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.334     1.454    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    SLICE_X111Y259       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac0_done_i_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X111Y259       FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     1.493 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac0_done_i_reg/Q
                         net (fo=1, routed)           0.280     1.773    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac0_done_i/src_in
    SLICE_X117Y278       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac0_done_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       1.922     2.370    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac0_done_i/dest_clk
    SLICE_X117Y278       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac0_done_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac1_done_i_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_done_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.488ns  (logic 0.039ns (7.992%)  route 0.449ns (92.008%))
  Logic Levels:           0  
  Clock Path Skew:        0.915ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.382ns
    Source Clock Delay      (SCD):    1.468ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.348ns (routing 0.358ns, distribution 0.990ns)
  Clock Net Delay (Destination): 1.934ns (routing 0.827ns, distribution 1.107ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.348     1.468    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    SLICE_X116Y248       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac1_done_i_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X116Y248       FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     1.507 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac1_done_i_reg/Q
                         net (fo=1, routed)           0.449     1.956    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_done_i/src_in
    SLICE_X117Y324       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_done_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       1.934     2.382    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_done_i/dest_clk
    SLICE_X117Y324       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_done_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/QPROC_xREG/slv_reg1_reg[11]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/data_cdc_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.797ns  (logic 0.129ns (16.182%)  route 0.668ns (83.818%))
  Logic Levels:           2  (LUT6=2)
  Clock Path Skew:        0.970ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.286ns
    Source Clock Delay      (SCD):    1.316ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.196ns (routing 0.358ns, distribution 0.838ns)
  Clock Net Delay (Destination): 1.838ns (routing 0.827ns, distribution 1.011ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.196     1.316    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/QPROC_xREG/ps_clk_i
    SLICE_X28Y356        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/QPROC_xREG/slv_reg1_reg[11]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X28Y356        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.039     1.355 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/QPROC_xREG/slv_reg1_reg[11]/Q
                         net (fo=2, routed)           0.146     1.501    d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_CFG[11]
    SLICE_X26Y370        LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.050     1.551 r  d_1_i/qick_processor_0/inst/QPROC/core_en/O
                         net (fo=600, routed)         0.166     1.717    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/E[0]
    SLICE_X24Y366        LUT6 (Prop_C6LUT_SLICEM_I4_O)
                                                      0.040     1.757 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/data_cdc[4]_i_1/O
                         net (fo=1, routed)           0.356     2.113    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/p_8_out[4]
    SLICE_X12Y346        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/data_cdc_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       1.838     2.286    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/t_clk_i
    SLICE_X12Y346        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/data_cdc_reg[4]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/QPROC_xREG/slv_reg1_reg[11]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/data_cdc_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.964ns  (logic 0.171ns (17.733%)  route 0.793ns (82.267%))
  Logic Levels:           3  (LUT3=2 LUT6=1)
  Clock Path Skew:        0.971ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.287ns
    Source Clock Delay      (SCD):    1.316ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.196ns (routing 0.358ns, distribution 0.838ns)
  Clock Net Delay (Destination): 1.839ns (routing 0.827ns, distribution 1.012ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.196     1.316    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/QPROC_xREG/ps_clk_i
    SLICE_X28Y356        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/QPROC_xREG/slv_reg1_reg[11]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X28Y356        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.039     1.355 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/QPROC_xREG/slv_reg1_reg[11]/Q
                         net (fo=2, routed)           0.146     1.501    d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_CFG[11]
    SLICE_X26Y370        LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.050     1.551 r  d_1_i/qick_processor_0/inst/QPROC/core_en/O
                         net (fo=600, routed)         0.122     1.673    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/E[0]
    SLICE_X26Y377        LUT3 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.041     1.714 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/data_cdc[3]_i_2/O
                         net (fo=33, routed)          0.151     1.865    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/data_cdc_reg[3]_0
    SLICE_X26Y363        LUT3 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.041     1.906 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/data_cdc[3]_i_1/O
                         net (fo=33, routed)          0.374     2.280    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/tproc_ctrl_2r_reg[1][0]
    SLICE_X12Y350        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/data_cdc_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       1.839     2.287    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/t_clk_i
    SLICE_X12Y350        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/data_cdc_reg[3]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  
  To Clock:  clk_out1_d_1_clk_adc0_x2_0

Max Delay             1 Endpoint
Min Delay             1 Endpoint
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                            (internal pin)
  Destination:            d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.797ns  (logic 0.097ns (3.468%)  route 2.700ns (96.532%))
  Logic Levels:           1  (LUT1=1)
  Clock Uncertainty:      0.122ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Destination): 1.881ns (routing 0.782ns, distribution 1.099ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    PS8_X0Y0             PS8                          0.000     0.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                         net (fo=5, routed)           1.785     1.785    d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/ext_reset_in
    SLICE_X34Y301        LUT1 (Prop_D5LUT_SLICEM_I0_O)
                                                      0.097     1.882 r  d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1/O
                         net (fo=1, routed)           0.915     2.797    d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/exr_d1
    SLICE_X42Y263        FDRE                                         r  d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.341     2.727    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.357 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.572    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.596 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.881     5.477    d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/slowest_sync_clk
    SLICE_X42Y263        FDRE                                         r  d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                            (internal pin)
  Destination:            d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.359ns  (logic 0.037ns (2.722%)  route 1.322ns (97.278%))
  Logic Levels:           1  (LUT1=1)
  Clock Uncertainty:      0.122ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Destination): 1.306ns (routing 0.521ns, distribution 0.785ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    PS8_X0Y0             PS8                          0.000     0.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                         net (fo=5, routed)           0.914     0.914    d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/ext_reset_in
    SLICE_X34Y301        LUT1 (Prop_D5LUT_SLICEM_I0_O)
                                                      0.037     0.951 r  d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1/O
                         net (fo=1, routed)           0.408     1.359    d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/exr_d1
    SLICE_X42Y263        FDRE                                         r  d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.583     1.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.640 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.806    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.825 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.306     3.131    d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/slowest_sync_clk
    SLICE_X42Y263        FDRE                                         r  d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFDAC0_CLK
  To Clock:  clk_out1_d_1_clk_adc0_x2_0

Max Delay           349 Endpoints
Min Delay           349 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[10]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.960ns  (logic 0.079ns (2.669%)  route 2.881ns (97.331%))
  Logic Levels:           0  
  Clock Path Skew:        1.856ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.529ns
    Source Clock Delay      (SCD):    3.673ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      3.000ns (routing 1.381ns, distribution 1.619ns)
  Clock Net Delay (Destination): 1.933ns (routing 0.782ns, distribution 1.151ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       3.000     3.673    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X15Y395        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[10]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X15Y395        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     3.752 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[10]/Q
                         net (fo=2, routed)           2.881     6.633    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/trigger_resync_i/trigger
    SLICE_X65Y185        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.341     2.727    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.357 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.572    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.596 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.933     5.529    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/trigger_resync_i/s_axis_aclk
    SLICE_X65Y185        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[8]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.798ns  (logic 0.175ns (6.254%)  route 2.623ns (93.746%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        2.013ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.511ns
    Source Clock Delay      (SCD):    3.498ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.825ns (routing 1.381ns, distribution 1.444ns)
  Clock Net Delay (Destination): 1.915ns (routing 0.782ns, distribution 1.133ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       2.825     3.498    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X43Y390        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X43Y390        FDCE (Prop_CFF_SLICEL_C_Q)
                                                      0.079     3.577 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[8]/Q
                         net (fo=2, routed)           2.608     6.185    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/trigger
    SLICE_X68Y123        LUT2 (Prop_D5LUT_SLICEL_I1_O)
                                                      0.096     6.281 r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg[0]_i_1/O
                         net (fo=1, routed)           0.015     6.296    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_in
    SLICE_X68Y123        FDCE                                         r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.341     2.727    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.357 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.572    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.596 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.915     5.511    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/s00_axis_aclk
    SLICE_X68Y123        FDCE                                         r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[13]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.487ns  (logic 0.079ns (3.177%)  route 2.408ns (96.823%))
  Logic Levels:           0  
  Clock Path Skew:        1.754ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.410ns
    Source Clock Delay      (SCD):    3.655ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.982ns (routing 1.381ns, distribution 1.601ns)
  Clock Net Delay (Destination): 1.814ns (routing 0.782ns, distribution 1.032ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       2.982     3.655    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X19Y350        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[13]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X19Y350        FDCE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     3.734 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[13]/Q
                         net (fo=2, routed)           2.408     6.142    d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/trigger_resync_i/trigger
    SLICE_X56Y169        FDRE                                         r  d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.341     2.727    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.357 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.572    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.596 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.814     5.410    d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/trigger_resync_i/s_axis_aclk
    SLICE_X56Y169        FDRE                                         r  d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[11]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.371ns  (logic 0.079ns (3.332%)  route 2.292ns (96.668%))
  Logic Levels:           0  
  Clock Path Skew:        1.853ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.521ns
    Source Clock Delay      (SCD):    3.668ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.995ns (routing 1.381ns, distribution 1.614ns)
  Clock Net Delay (Destination): 1.925ns (routing 0.782ns, distribution 1.143ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       2.995     3.668    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X16Y329        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[11]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X16Y329        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     3.747 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[11]/Q
                         net (fo=2, routed)           2.292     6.039    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/trigger_resync_i/trigger
    SLICE_X65Y199        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.341     2.727    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.357 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.572    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.596 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.925     5.521    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/trigger_resync_i/s_axis_aclk
    SLICE_X65Y199        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[12]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.865ns  (logic 0.079ns (4.235%)  route 1.786ns (95.765%))
  Logic Levels:           0  
  Clock Path Skew:        1.898ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.549ns
    Source Clock Delay      (SCD):    3.650ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.977ns (routing 1.381ns, distribution 1.596ns)
  Clock Net Delay (Destination): 1.953ns (routing 0.782ns, distribution 1.171ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       2.977     3.650    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X19Y350        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[12]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X19Y350        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     3.729 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[12]/Q
                         net (fo=2, routed)           1.786     5.516    d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/trigger_resync_i/trigger
    SLICE_X33Y197        FDRE                                         r  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.341     2.727    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.357 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.572    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.596 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.953     5.549    d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/trigger_resync_i/s_axis_aclk
    SLICE_X33Y197        FDRE                                         r  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][3]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.937ns  (logic 0.080ns (4.130%)  route 1.857ns (95.870%))
  Logic Levels:           0  
  Clock Path Skew:        1.951ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.473ns
    Source Clock Delay      (SCD):    3.522ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.849ns (routing 1.381ns, distribution 1.468ns)
  Clock Net Delay (Destination): 1.877ns (routing 0.782ns, distribution 1.095ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       2.849     3.522    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/s_axis_aclk
    SLICE_X27Y231        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X27Y231        FDRE (Prop_AFF2_SLICEM_C_Q)
                                                      0.080     3.602 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_reg[3]/Q
                         net (fo=556, routed)         1.857     5.460    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][3]_0[3]
    SLICE_X40Y205        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.341     2.727    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.357 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.572    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.596 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.877     5.473    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/m_axis_aclk
    SLICE_X40Y205        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][3]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][2]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.851ns  (logic 0.213ns (11.505%)  route 1.638ns (88.495%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        1.942ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.465ns
    Source Clock Delay      (SCD):    3.522ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.849ns (routing 1.381ns, distribution 1.468ns)
  Clock Net Delay (Destination): 1.869ns (routing 0.782ns, distribution 1.087ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       2.849     3.522    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/s_axis_aclk
    SLICE_X27Y231        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X27Y231        FDRE (Prop_AFF2_SLICEM_C_Q)
                                                      0.080     3.602 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_reg[3]/Q
                         net (fo=556, routed)         1.623     5.226    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][3]_0[3]
    SLICE_X38Y206        LUT2 (Prop_D5LUT_SLICEL_I1_O)
                                                      0.133     5.359 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg[0][2]_i_1/O
                         net (fo=1, routed)           0.015     5.374    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/wptr_g[2]
    SLICE_X38Y206        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.341     2.727    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.357 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.572    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.596 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.869     5.465    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/m_axis_aclk
    SLICE_X38Y206        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][2]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.818ns  (logic 0.170ns (9.350%)  route 1.648ns (90.650%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        2.017ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.540ns
    Source Clock Delay      (SCD):    3.522ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.849ns (routing 1.381ns, distribution 1.468ns)
  Clock Net Delay (Destination): 1.944ns (routing 0.782ns, distribution 1.162ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       2.849     3.522    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/s_axis_aclk
    SLICE_X27Y231        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X27Y231        FDRE (Prop_DFF2_SLICEM_C_Q)
                                                      0.080     3.602 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_reg[0]/Q
                         net (fo=557, routed)         1.070     4.673    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][3]_0[0]
    SLICE_X34Y210        LUT2 (Prop_A6LUT_SLICEM_I0_O)
                                                      0.090     4.763 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg[0][0]_i_1/O
                         net (fo=2, routed)           0.578     5.341    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/wptr_reg[0][0]
    SLICE_X33Y205        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.341     2.727    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.357 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.572    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.596 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.944     5.540    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/m_axis_aclk
    SLICE_X33Y205        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][0]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][1]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.717ns  (logic 0.189ns (11.009%)  route 1.528ns (88.991%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        2.009ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.532ns
    Source Clock Delay      (SCD):    3.522ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.849ns (routing 1.381ns, distribution 1.468ns)
  Clock Net Delay (Destination): 1.936ns (routing 0.782ns, distribution 1.154ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       2.849     3.522    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/s_axis_aclk
    SLICE_X27Y231        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X27Y231        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     3.599 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_reg[2]/Q
                         net (fo=557, routed)         1.118     4.717    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][3]_0[2]
    SLICE_X34Y210        LUT2 (Prop_A5LUT_SLICEM_I1_O)
                                                      0.112     4.829 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg[0][1]_i_1/O
                         net (fo=1, routed)           0.410     5.239    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/wptr_g[1]
    SLICE_X37Y205        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.341     2.727    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.357 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.572    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.596 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.936     5.532    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/m_axis_aclk
    SLICE_X37Y205        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][1]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_336_349/RAMA_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[337]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.085ns  (logic 0.305ns (28.111%)  route 0.780ns (71.889%))
  Logic Levels:           0  
  Clock Path Skew:        1.998ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.539ns
    Source Clock Delay      (SCD):    3.541ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.868ns (routing 1.381ns, distribution 1.487ns)
  Clock Net Delay (Destination): 1.943ns (routing 0.782ns, distribution 1.161ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       2.868     3.541    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_336_349/WCLK
    SLICE_X27Y229        RAMD32                                       r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_336_349/RAMA_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X27Y229        RAMD32 (Prop_A6LUT_SLICEM_CLK_O)
                                                      0.305     3.846 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_336_349/RAMA_D1/O
                         net (fo=1, routed)           0.780     4.626    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob0[337]
    SLICE_X36Y185        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[337]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.341     2.727    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.357 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.572    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.596 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.943     5.539    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/m_axis_aclk
    SLICE_X36Y185        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[337]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[12]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.941ns  (logic 0.039ns (4.144%)  route 0.902ns (95.856%))
  Logic Levels:           0  
  Clock Path Skew:        1.199ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.174ns
    Source Clock Delay      (SCD):    1.976ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.627ns (routing 0.748ns, distribution 0.879ns)
  Clock Net Delay (Destination): 1.349ns (routing 0.521ns, distribution 0.828ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       1.627     1.976    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X19Y350        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[12]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X19Y350        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     2.015 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[12]/Q
                         net (fo=2, routed)           0.902     2.917    d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/trigger_resync_i/trigger
    SLICE_X33Y197        FDRE                                         r  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.583     1.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.640 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.806    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.825 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.349     3.174    d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/trigger_resync_i/s_axis_aclk
    SLICE_X33Y197        FDRE                                         r  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[11]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.153ns  (logic 0.039ns (3.382%)  route 1.114ns (96.618%))
  Logic Levels:           0  
  Clock Path Skew:        1.172ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.156ns
    Source Clock Delay      (SCD):    1.984ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.635ns (routing 0.748ns, distribution 0.887ns)
  Clock Net Delay (Destination): 1.331ns (routing 0.521ns, distribution 0.810ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       1.635     1.984    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X16Y329        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[11]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X16Y329        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     2.023 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[11]/Q
                         net (fo=2, routed)           1.114     3.137    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/trigger_resync_i/trigger
    SLICE_X65Y199        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.583     1.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.640 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.806    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.825 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.331     3.156    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/trigger_resync_i/s_axis_aclk
    SLICE_X65Y199        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[13]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.193ns  (logic 0.039ns (3.269%)  route 1.154ns (96.731%))
  Logic Levels:           0  
  Clock Path Skew:        1.104ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.082ns
    Source Clock Delay      (SCD):    1.979ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.630ns (routing 0.748ns, distribution 0.882ns)
  Clock Net Delay (Destination): 1.257ns (routing 0.521ns, distribution 0.736ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       1.630     1.979    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X19Y350        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[13]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X19Y350        FDCE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     2.018 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[13]/Q
                         net (fo=2, routed)           1.154     3.172    d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/trigger_resync_i/trigger
    SLICE_X56Y169        FDRE                                         r  d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.583     1.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.640 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.806    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.825 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.257     3.082    d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/trigger_resync_i/s_axis_aclk
    SLICE_X56Y169        FDRE                                         r  d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[8]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.421ns  (logic 0.072ns (5.068%)  route 1.349ns (94.932%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        1.257ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.148ns
    Source Clock Delay      (SCD):    1.891ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.542ns (routing 0.748ns, distribution 0.794ns)
  Clock Net Delay (Destination): 1.323ns (routing 0.521ns, distribution 0.802ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       1.542     1.891    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X43Y390        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X43Y390        FDCE (Prop_CFF_SLICEL_C_Q)
                                                      0.039     1.930 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[8]/Q
                         net (fo=2, routed)           1.343     3.273    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/trigger
    SLICE_X68Y123        LUT2 (Prop_D5LUT_SLICEL_I1_O)
                                                      0.033     3.306 r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg[0]_i_1/O
                         net (fo=1, routed)           0.006     3.312    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_in
    SLICE_X68Y123        FDCE                                         r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.583     1.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.640 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.806    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.825 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.323     3.148    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/s00_axis_aclk
    SLICE_X68Y123        FDCE                                         r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[10]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.445ns  (logic 0.039ns (2.700%)  route 1.406ns (97.300%))
  Logic Levels:           0  
  Clock Path Skew:        1.166ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.160ns
    Source Clock Delay      (SCD):    1.994ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.645ns (routing 0.748ns, distribution 0.897ns)
  Clock Net Delay (Destination): 1.335ns (routing 0.521ns, distribution 0.814ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       1.645     1.994    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X15Y395        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[10]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X15Y395        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     2.033 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[10]/Q
                         net (fo=2, routed)           1.406     3.439    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/trigger_resync_i/trigger
    SLICE_X65Y185        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.583     1.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.640 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.806    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.825 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.335     3.160    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/trigger_resync_i/s_axis_aclk
    SLICE_X65Y185        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_210_223/RAMD_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[217]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.173ns  (logic 0.111ns (64.162%)  route 0.062ns (35.838%))
  Logic Levels:           0  
  Clock Path Skew:        1.263ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.178ns
    Source Clock Delay      (SCD):    1.915ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.566ns (routing 0.748ns, distribution 0.818ns)
  Clock Net Delay (Destination): 1.353ns (routing 0.521ns, distribution 0.832ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       1.566     1.915    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_210_223/WCLK
    SLICE_X28Y221        RAMD32                                       r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_210_223/RAMD_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X28Y221        RAMD32 (Prop_D6LUT_SLICEM_CLK_O)
                                                      0.111     2.026 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_210_223/RAMD_D1/O
                         net (fo=1, routed)           0.062     2.088    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob0[217]
    SLICE_X29Y221        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[217]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.583     1.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.640 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.806    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.825 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.353     3.178    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/m_axis_aclk
    SLICE_X29Y221        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[217]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_210_223/RAME/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[218]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.180ns  (logic 0.108ns (60.000%)  route 0.072ns (40.000%))
  Logic Levels:           0  
  Clock Path Skew:        1.263ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.178ns
    Source Clock Delay      (SCD):    1.915ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.566ns (routing 0.748ns, distribution 0.818ns)
  Clock Net Delay (Destination): 1.353ns (routing 0.521ns, distribution 0.832ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       1.566     1.915    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_210_223/WCLK
    SLICE_X28Y221        RAMD32                                       r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_210_223/RAME/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X28Y221        RAMD32 (Prop_E5LUT_SLICEM_CLK_O)
                                                      0.108     2.023 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_210_223/RAME/O
                         net (fo=1, routed)           0.072     2.095    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob0[218]
    SLICE_X29Y221        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[218]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.583     1.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.640 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.806    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.825 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.353     3.178    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/m_axis_aclk
    SLICE_X29Y221        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[218]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_28_41/RAME/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[36]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.189ns  (logic 0.108ns (57.143%)  route 0.081ns (42.857%))
  Logic Levels:           0  
  Clock Path Skew:        1.260ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.171ns
    Source Clock Delay      (SCD):    1.911ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.562ns (routing 0.748ns, distribution 0.814ns)
  Clock Net Delay (Destination): 1.346ns (routing 0.521ns, distribution 0.825ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       1.562     1.911    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_28_41/WCLK
    SLICE_X28Y214        RAMD32                                       r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_28_41/RAME/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X28Y214        RAMD32 (Prop_E5LUT_SLICEM_CLK_O)
                                                      0.108     2.019 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_28_41/RAME/O
                         net (fo=1, routed)           0.081     2.100    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob0[36]
    SLICE_X28Y212        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[36]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.583     1.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.640 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.806    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.825 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.346     3.171    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/m_axis_aclk
    SLICE_X28Y212        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[36]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_0_13/RAME/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.184ns  (logic 0.108ns (58.696%)  route 0.076ns (41.304%))
  Logic Levels:           0  
  Clock Path Skew:        1.265ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.183ns
    Source Clock Delay      (SCD):    1.918ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.569ns (routing 0.748ns, distribution 0.821ns)
  Clock Net Delay (Destination): 1.358ns (routing 0.521ns, distribution 0.837ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       1.569     1.918    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_0_13/WCLK
    SLICE_X27Y224        RAMD32                                       r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_0_13/RAME/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X27Y224        RAMD32 (Prop_E5LUT_SLICEM_CLK_O)
                                                      0.108     2.026 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_0_13/RAME/O
                         net (fo=1, routed)           0.076     2.102    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob0[8]
    SLICE_X26Y224        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.583     1.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.640 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.806    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.825 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.358     3.183    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/m_axis_aclk
    SLICE_X26Y224        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_0_13/RAMB/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.196ns  (logic 0.110ns (56.122%)  route 0.086ns (43.878%))
  Logic Levels:           0  
  Clock Path Skew:        1.265ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.183ns
    Source Clock Delay      (SCD):    1.918ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.569ns (routing 0.748ns, distribution 0.821ns)
  Clock Net Delay (Destination): 1.358ns (routing 0.521ns, distribution 0.837ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       1.569     1.918    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_0_13/WCLK
    SLICE_X27Y224        RAMD32                                       r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_0_13/RAMB/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X27Y224        RAMD32 (Prop_B5LUT_SLICEM_CLK_O)
                                                      0.110     2.028 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_0_13/RAMB/O
                         net (fo=1, routed)           0.086     2.114    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob0[2]
    SLICE_X26Y224        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.583     1.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.640 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.806    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.825 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.358     3.183    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/m_axis_aclk
    SLICE_X26Y224        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[2]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_pl_0
  To Clock:  clk_out1_d_1_clk_adc0_x2_0

Max Delay           755 Endpoints
Min Delay           755 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/adc0_done_i_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc0_done_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.773ns  (logic 0.079ns (4.456%)  route 1.694ns (95.544%))
  Logic Levels:           0  
  Clock Path Skew:        3.147ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.771ns
    Source Clock Delay      (SCD):    2.623ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.397ns (routing 0.662ns, distribution 1.735ns)
  Clock Net Delay (Destination): 2.175ns (routing 0.782ns, distribution 1.393ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.397     2.623    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    SLICE_X114Y198       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/adc0_done_i_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X114Y198       FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     2.702 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/adc0_done_i_reg/Q
                         net (fo=1, routed)           1.694     4.396    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc0_done_i/src_in
    SLICE_X107Y59        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc0_done_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.341     2.727    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.357 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.572    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.596 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       2.175     5.771    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc0_done_i/dest_clk
    SLICE_X107Y59        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc0_done_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/adc2_done_i_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc2_done_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.927ns  (logic 0.079ns (8.522%)  route 0.848ns (91.478%))
  Logic Levels:           0  
  Clock Path Skew:        3.140ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.757ns
    Source Clock Delay      (SCD):    2.616ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.390ns (routing 0.662ns, distribution 1.728ns)
  Clock Net Delay (Destination): 2.161ns (routing 0.782ns, distribution 1.379ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.390     2.616    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    SLICE_X111Y202       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/adc2_done_i_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X111Y202       FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     2.695 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/adc2_done_i_reg/Q
                         net (fo=1, routed)           0.848     3.543    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc2_done_i/src_in
    SLICE_X108Y131       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc2_done_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.341     2.727    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.357 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.572    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.596 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       2.161     5.757    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc2_done_i/dest_clk
    SLICE_X108Y131       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc2_done_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.412ns  (logic 0.077ns (18.689%)  route 0.335ns (81.311%))
  Logic Levels:           0  
  Clock Path Skew:        3.228ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.569ns
    Source Clock Delay      (SCD):    2.340ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.114ns (routing 0.662ns, distribution 1.452ns)
  Clock Net Delay (Destination): 1.973ns (routing 0.782ns, distribution 1.191ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.114     2.340    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X30Y181        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X30Y181        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     2.417 r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/Q
                         net (fo=2, routed)           0.335     2.752    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/src_in
    SLICE_X30Y185        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.341     2.727    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.357 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.572    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.596 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.973     5.569    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/dest_clk
    SLICE_X30Y185        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.403ns  (logic 0.079ns (19.594%)  route 0.324ns (80.406%))
  Logic Levels:           0  
  Clock Path Skew:        3.138ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.405ns
    Source Clock Delay      (SCD):    2.267ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.041ns (routing 0.662ns, distribution 1.379ns)
  Clock Net Delay (Destination): 1.809ns (routing 0.782ns, distribution 1.027ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.041     2.267    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X55Y140        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X55Y140        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     2.346 r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/Q
                         net (fo=2, routed)           0.324     2.670    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/src_in
    SLICE_X58Y135        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.341     2.727    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.357 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.572    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.596 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.809     5.405    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/dest_clk
    SLICE_X58Y135        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_1/inst/axi_slv_i/slv_reg2_reg[25]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/len_r_reg[25]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.558ns  (logic 0.081ns (3.166%)  route 2.477ns (96.834%))
  Logic Levels:           0  
  Clock Path Skew:        3.279ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.551ns
    Source Clock Delay      (SCD):    2.272ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.046ns (routing 0.662ns, distribution 1.384ns)
  Clock Net Delay (Destination): 1.955ns (routing 0.782ns, distribution 1.173ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.046     2.272    d_1_i/axis_avg_buffer_1/inst/axi_slv_i/s_axi_aclk
    SLICE_X38Y266        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/axi_slv_i/slv_reg2_reg[25]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X38Y266        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.081     2.353 r  d_1_i/axis_avg_buffer_1/inst/axi_slv_i/slv_reg2_reg[25]/Q
                         net (fo=2, routed)           2.477     4.830    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/len_r_reg[31]_0[25]
    SLICE_X71Y190        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/len_r_reg[25]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.341     2.727    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.357 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.572    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.596 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.955     5.551    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/s_axis_aclk
    SLICE_X71Y190        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/len_r_reg[25]/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_1/inst/axi_slv_i/slv_reg2_reg[31]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/len_r_reg[31]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.323ns  (logic 0.080ns (3.444%)  route 2.243ns (96.556%))
  Logic Levels:           0  
  Clock Path Skew:        3.257ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.529ns
    Source Clock Delay      (SCD):    2.272ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.046ns (routing 0.662ns, distribution 1.384ns)
  Clock Net Delay (Destination): 1.933ns (routing 0.782ns, distribution 1.151ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.046     2.272    d_1_i/axis_avg_buffer_1/inst/axi_slv_i/s_axi_aclk
    SLICE_X38Y266        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/axi_slv_i/slv_reg2_reg[31]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X38Y266        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.080     2.352 r  d_1_i/axis_avg_buffer_1/inst/axi_slv_i/slv_reg2_reg[31]/Q
                         net (fo=2, routed)           2.243     4.595    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/len_r_reg[31]_0[31]
    SLICE_X65Y185        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/len_r_reg[31]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.341     2.727    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.357 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.572    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.596 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.933     5.529    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/s_axis_aclk
    SLICE_X65Y185        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/len_r_reg[31]/C

Slack:                    inf
  Source:                 d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/slv_reg0_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[0]/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.002ns  (logic 0.078ns (3.895%)  route 1.924ns (96.105%))
  Logic Levels:           0  
  Clock Path Skew:        2.938ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.518ns
    Source Clock Delay      (SCD):    2.580ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.354ns (routing 0.662ns, distribution 1.692ns)
  Clock Net Delay (Destination): 1.922ns (routing 0.782ns, distribution 1.140ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.354     2.580    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/s00_axi_aclk
    SLICE_X94Y31         FDRE                                         r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/slv_reg0_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y31         FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.078     2.658 r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/slv_reg0_reg[0]/Q
                         net (fo=2, routed)           1.924     4.582    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[0]_0[0]
    SLICE_X71Y127        FDCE                                         r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.341     2.727    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.357 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.572    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.596 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.922     5.518    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/s00_axis_aclk
    SLICE_X71Y127        FDCE                                         r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_1/inst/axi_slv_i/slv_reg2_reg[30]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/len_r_reg[30]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.310ns  (logic 0.079ns (3.420%)  route 2.231ns (96.580%))
  Logic Levels:           0  
  Clock Path Skew:        3.255ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.527ns
    Source Clock Delay      (SCD):    2.272ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.046ns (routing 0.662ns, distribution 1.384ns)
  Clock Net Delay (Destination): 1.931ns (routing 0.782ns, distribution 1.149ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.046     2.272    d_1_i/axis_avg_buffer_1/inst/axi_slv_i/s_axi_aclk
    SLICE_X38Y266        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/axi_slv_i/slv_reg2_reg[30]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X38Y266        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     2.351 r  d_1_i/axis_avg_buffer_1/inst/axi_slv_i/slv_reg2_reg[30]/Q
                         net (fo=2, routed)           2.231     4.582    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/len_r_reg[31]_0[30]
    SLICE_X64Y190        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/len_r_reg[30]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.341     2.727    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.357 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.572    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.596 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.931     5.527    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/s_axis_aclk
    SLICE_X64Y190        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/len_r_reg[30]/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_1/inst/axi_slv_i/slv_reg2_reg[27]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/len_r_reg[27]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.279ns  (logic 0.081ns (3.554%)  route 2.198ns (96.446%))
  Logic Levels:           0  
  Clock Path Skew:        3.257ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.529ns
    Source Clock Delay      (SCD):    2.272ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.046ns (routing 0.662ns, distribution 1.384ns)
  Clock Net Delay (Destination): 1.933ns (routing 0.782ns, distribution 1.151ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.046     2.272    d_1_i/axis_avg_buffer_1/inst/axi_slv_i/s_axi_aclk
    SLICE_X38Y266        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/axi_slv_i/slv_reg2_reg[27]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X38Y266        FDRE (Prop_FFF2_SLICEL_C_Q)
                                                      0.081     2.353 r  d_1_i/axis_avg_buffer_1/inst/axi_slv_i/slv_reg2_reg[27]/Q
                         net (fo=2, routed)           2.198     4.551    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/len_r_reg[31]_0[27]
    SLICE_X65Y185        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/len_r_reg[27]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.341     2.727    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.357 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.572    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.596 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.933     5.529    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/s_axis_aclk
    SLICE_X65Y185        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/len_r_reg[27]/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_1/inst/axi_slv_i/slv_reg2_reg[29]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/len_r_reg[29]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.231ns  (logic 0.081ns (3.631%)  route 2.150ns (96.369%))
  Logic Levels:           0  
  Clock Path Skew:        3.255ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.527ns
    Source Clock Delay      (SCD):    2.272ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.046ns (routing 0.662ns, distribution 1.384ns)
  Clock Net Delay (Destination): 1.931ns (routing 0.782ns, distribution 1.149ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.046     2.272    d_1_i/axis_avg_buffer_1/inst/axi_slv_i/s_axi_aclk
    SLICE_X38Y266        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/axi_slv_i/slv_reg2_reg[29]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X38Y266        FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.081     2.353 r  d_1_i/axis_avg_buffer_1/inst/axi_slv_i/slv_reg2_reg[29]/Q
                         net (fo=2, routed)           2.150     4.503    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/len_r_reg[31]_0[29]
    SLICE_X64Y190        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/len_r_reg[29]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.341     2.727    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.357 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.572    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.596 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.931     5.527    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/s_axis_aclk
    SLICE_X64Y190        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/len_r_reg[29]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.100ns  (logic 0.038ns (38.000%)  route 0.062ns (62.000%))
  Logic Levels:           0  
  Clock Path Skew:        1.825ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.077ns
    Source Clock Delay      (SCD):    1.252ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.132ns (routing 0.358ns, distribution 0.774ns)
  Clock Net Delay (Destination): 1.252ns (routing 0.521ns, distribution 0.731ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.132     1.252    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X56Y135        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X56Y135        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     1.290 r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[3]/Q
                         net (fo=1, routed)           0.062     1.352    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff[3]
    SLICE_X57Y135        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.583     1.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.640 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.806    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.825 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.252     3.077    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X57Y135        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[3]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.131ns  (logic 0.040ns (30.534%)  route 0.091ns (69.466%))
  Logic Levels:           0  
  Clock Path Skew:        1.830ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.077ns
    Source Clock Delay      (SCD):    1.247ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.127ns (routing 0.358ns, distribution 0.769ns)
  Clock Net Delay (Destination): 1.252ns (routing 0.521ns, distribution 0.731ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.127     1.247    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X57Y135        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X57Y135        FDRE (Prop_BFF2_SLICEL_C_Q)
                                                      0.040     1.287 r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[2]/Q
                         net (fo=1, routed)           0.091     1.378    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff[2]
    SLICE_X57Y135        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.583     1.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.640 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.806    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.825 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.252     3.077    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X57Y135        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.150ns  (logic 0.041ns (27.333%)  route 0.109ns (72.667%))
  Logic Levels:           0  
  Clock Path Skew:        1.830ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.077ns
    Source Clock Delay      (SCD):    1.247ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.127ns (routing 0.358ns, distribution 0.769ns)
  Clock Net Delay (Destination): 1.252ns (routing 0.521ns, distribution 0.731ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.127     1.247    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X57Y135        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X57Y135        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.041     1.288 r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[0]/Q
                         net (fo=1, routed)           0.109     1.397    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff[0]
    SLICE_X57Y135        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.583     1.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.640 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.806    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.825 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.252     3.077    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X57Y135        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.134ns  (logic 0.038ns (28.358%)  route 0.096ns (71.642%))
  Logic Levels:           0  
  Clock Path Skew:        1.912ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.183ns
    Source Clock Delay      (SCD):    1.271ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.151ns (routing 0.358ns, distribution 0.793ns)
  Clock Net Delay (Destination): 1.358ns (routing 0.521ns, distribution 0.837ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.151     1.271    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X30Y189        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X30Y189        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     1.309 r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[0]/Q
                         net (fo=1, routed)           0.096     1.405    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff[0]
    SLICE_X30Y186        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.583     1.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.640 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.806    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.825 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.358     3.183    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X30Y186        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.182ns  (logic 0.039ns (21.432%)  route 0.143ns (78.568%))
  Logic Levels:           0  
  Clock Path Skew:        1.835ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.076ns
    Source Clock Delay      (SCD):    1.241ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.121ns (routing 0.358ns, distribution 0.763ns)
  Clock Net Delay (Destination): 1.251ns (routing 0.521ns, distribution 0.730ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.121     1.241    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X55Y140        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X55Y140        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.039     1.280 r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/Q
                         net (fo=2, routed)           0.143     1.423    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/src_in
    SLICE_X58Y135        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.583     1.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.640 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.806    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.825 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.251     3.076    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/dest_clk
    SLICE_X58Y135        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.179ns  (logic 0.040ns (22.346%)  route 0.139ns (77.654%))
  Logic Levels:           0  
  Clock Path Skew:        1.830ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.077ns
    Source Clock Delay      (SCD):    1.247ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.127ns (routing 0.358ns, distribution 0.769ns)
  Clock Net Delay (Destination): 1.252ns (routing 0.521ns, distribution 0.731ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.127     1.247    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X57Y135        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X57Y135        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.040     1.287 r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[4]/Q
                         net (fo=1, routed)           0.139     1.426    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff[4]
    SLICE_X57Y135        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.583     1.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.640 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.806    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.825 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.252     3.077    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X57Y135        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[4]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.151ns  (logic 0.039ns (25.828%)  route 0.112ns (74.172%))
  Logic Levels:           0  
  Clock Path Skew:        1.903ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.178ns
    Source Clock Delay      (SCD):    1.275ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.155ns (routing 0.358ns, distribution 0.797ns)
  Clock Net Delay (Destination): 1.353ns (routing 0.521ns, distribution 0.832ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.155     1.275    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X31Y190        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X31Y190        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.039     1.314 r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[2]/Q
                         net (fo=1, routed)           0.112     1.426    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff[2]
    SLICE_X31Y190        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.583     1.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.640 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.806    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.825 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.353     3.178    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X31Y190        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.181ns  (logic 0.040ns (22.099%)  route 0.141ns (77.901%))
  Logic Levels:           0  
  Clock Path Skew:        1.830ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.077ns
    Source Clock Delay      (SCD):    1.247ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.127ns (routing 0.358ns, distribution 0.769ns)
  Clock Net Delay (Destination): 1.252ns (routing 0.521ns, distribution 0.731ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.127     1.247    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X57Y135        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X57Y135        FDRE (Prop_CFF2_SLICEL_C_Q)
                                                      0.040     1.287 r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[1]/Q
                         net (fo=1, routed)           0.141     1.428    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff[1]
    SLICE_X57Y135        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.583     1.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.640 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.806    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.825 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.252     3.077    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X57Y135        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.161ns  (logic 0.039ns (24.224%)  route 0.122ns (75.776%))
  Logic Levels:           0  
  Clock Path Skew:        1.903ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.178ns
    Source Clock Delay      (SCD):    1.275ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.155ns (routing 0.358ns, distribution 0.797ns)
  Clock Net Delay (Destination): 1.353ns (routing 0.521ns, distribution 0.832ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.155     1.275    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X31Y190        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X31Y190        FDRE (Prop_GFF_SLICEM_C_Q)
                                                      0.039     1.314 r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[3]/Q
                         net (fo=1, routed)           0.122     1.436    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff[3]
    SLICE_X31Y190        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.583     1.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.640 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.806    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.825 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.353     3.178    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X31Y190        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[3]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.165ns  (logic 0.038ns (23.030%)  route 0.127ns (76.970%))
  Logic Levels:           0  
  Clock Path Skew:        1.909ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.185ns
    Source Clock Delay      (SCD):    1.277ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.157ns (routing 0.358ns, distribution 0.799ns)
  Clock Net Delay (Destination): 1.360ns (routing 0.521ns, distribution 0.839ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.157     1.277    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X30Y181        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X30Y181        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     1.315 r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/Q
                         net (fo=2, routed)           0.127     1.442    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/src_in
    SLICE_X30Y185        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.583     1.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.640 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.806    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.825 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.360     3.185    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/dest_clk
    SLICE_X30Y185        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  mmcm_clkout0
  To Clock:  clk_out1_d_1_clk_adc0_x2_0

Max Delay             7 Endpoints
Min Delay             7 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/rst_ddr4/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.514ns  (logic 0.169ns (11.162%)  route 1.345ns (88.838%))
  Logic Levels:           1  (LUT1=1)
  Clock Path Skew:        0.690ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.545ns
    Source Clock Delay      (SCD):    4.855ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      2.093ns (routing 0.788ns, distribution 1.305ns)
  Clock Net Delay (Destination): 1.949ns (routing 0.782ns, distribution 1.167ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.093     4.855    d_1_i/ddr4/rst_ddr4/U0/slowest_sync_clk
    SLICE_X80Y209        FDRE                                         r  d_1_i/ddr4/rst_ddr4/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y209        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     4.934 f  d_1_i/ddr4/rst_ddr4/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.107     6.041    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/m_axis_aresetn
    SLICE_X33Y225        LUT1 (Prop_E6LUT_SLICEL_I0_O)
                                                      0.090     6.131 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst_i_1/O
                         net (fo=1, routed)           0.238     6.369    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/src_rst
    SLICE_X33Y225        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.341     2.727    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.357 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.572    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.596 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.949     5.545    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/dest_clk
    SLICE_X33Y225        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.149ns  (logic 0.079ns (6.876%)  route 1.070ns (93.124%))
  Logic Levels:           0  
  Clock Path Skew:        0.452ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.542ns
    Source Clock Delay      (SCD):    5.090ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      2.328ns (routing 0.788ns, distribution 1.540ns)
  Clock Net Delay (Destination): 1.946ns (routing 0.782ns, distribution 1.164ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.328     5.090    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/rd_clk
    SLICE_X35Y233        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X35Y233        FDRE (Prop_FFF2_SLICEM_C_Q)
                                                      0.079     5.169 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/Q
                         net (fo=1, routed)           1.070     6.239    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/src_rst
    SLICE_X36Y221        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.341     2.727    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.357 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.572    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.596 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.946     5.542    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/dest_clk
    SLICE_X36Y221        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.399ns  (logic 0.077ns (19.298%)  route 0.322ns (80.702%))
  Logic Levels:           0  
  Clock Path Skew:        0.460ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.566ns
    Source Clock Delay      (SCD):    5.106ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      2.344ns (routing 0.788ns, distribution 1.556ns)
  Clock Net Delay (Destination): 1.970ns (routing 0.782ns, distribution 1.188ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.344     5.106    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X28Y235        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X28Y235        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     5.183 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[4]/Q
                         net (fo=1, routed)           0.322     5.505    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[4]
    SLICE_X29Y235        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.341     2.727    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.357 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.572    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.596 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.970     5.566    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X29Y235        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.330ns  (logic 0.078ns (23.636%)  route 0.252ns (76.364%))
  Logic Levels:           0  
  Clock Path Skew:        0.470ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.536ns
    Source Clock Delay      (SCD):    5.066ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      2.304ns (routing 0.788ns, distribution 1.516ns)
  Clock Net Delay (Destination): 1.940ns (routing 0.782ns, distribution 1.158ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.304     5.066    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X35Y217        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X35Y217        FDRE (Prop_GFF_SLICEM_C_Q)
                                                      0.078     5.144 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/Q
                         net (fo=1, routed)           0.252     5.396    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[2]
    SLICE_X35Y217        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.341     2.727    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.357 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.572    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.596 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.940     5.536    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X35Y217        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.328ns  (logic 0.079ns (24.085%)  route 0.249ns (75.915%))
  Logic Levels:           0  
  Clock Path Skew:        0.470ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.536ns
    Source Clock Delay      (SCD):    5.066ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      2.304ns (routing 0.788ns, distribution 1.516ns)
  Clock Net Delay (Destination): 1.940ns (routing 0.782ns, distribution 1.158ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.304     5.066    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X35Y217        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X35Y217        FDRE (Prop_GFF2_SLICEM_C_Q)
                                                      0.079     5.145 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/Q
                         net (fo=1, routed)           0.249     5.394    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[3]
    SLICE_X35Y217        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.341     2.727    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.357 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.572    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.596 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.940     5.536    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X35Y217        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.341ns  (logic 0.079ns (23.167%)  route 0.262ns (76.833%))
  Logic Levels:           0  
  Clock Path Skew:        0.461ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.460ns
    Source Clock Delay      (SCD):    4.999ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      2.237ns (routing 0.788ns, distribution 1.449ns)
  Clock Net Delay (Destination): 1.864ns (routing 0.782ns, distribution 1.082ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.237     4.999    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X40Y214        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X40Y214        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     5.078 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/Q
                         net (fo=1, routed)           0.262     5.340    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[0]
    SLICE_X40Y214        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.341     2.727    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.357 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.572    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.596 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.864     5.460    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X40Y214        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.298ns  (logic 0.080ns (26.846%)  route 0.218ns (73.154%))
  Logic Levels:           0  
  Clock Path Skew:        0.461ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.460ns
    Source Clock Delay      (SCD):    4.999ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      2.237ns (routing 0.788ns, distribution 1.449ns)
  Clock Net Delay (Destination): 1.864ns (routing 0.782ns, distribution 1.082ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.237     4.999    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X40Y214        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X40Y214        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.080     5.079 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/Q
                         net (fo=1, routed)           0.218     5.297    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[1]
    SLICE_X40Y214        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.341     2.727    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.357 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.572    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.596 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.864     5.460    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X40Y214        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.129ns  (logic 0.039ns (30.233%)  route 0.090ns (69.767%))
  Logic Levels:           0  
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.110ns
    Source Clock Delay      (SCD):    3.088ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      1.235ns (routing 0.435ns, distribution 0.800ns)
  Clock Net Delay (Destination): 1.285ns (routing 0.521ns, distribution 0.764ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.836    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.853 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.235     3.088    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X40Y214        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X40Y214        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.039     3.127 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/Q
                         net (fo=1, routed)           0.090     3.217    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[1]
    SLICE_X40Y214        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.583     1.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.640 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.806    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.825 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.285     3.110    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X40Y214        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.148ns  (logic 0.039ns (26.351%)  route 0.109ns (73.649%))
  Logic Levels:           0  
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.110ns
    Source Clock Delay      (SCD):    3.088ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      1.235ns (routing 0.435ns, distribution 0.800ns)
  Clock Net Delay (Destination): 1.285ns (routing 0.521ns, distribution 0.764ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.836    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.853 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.235     3.088    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X40Y214        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X40Y214        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     3.127 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/Q
                         net (fo=1, routed)           0.109     3.236    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[0]
    SLICE_X40Y214        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.583     1.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.640 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.806    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.825 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.285     3.110    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X40Y214        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.141ns  (logic 0.039ns (27.660%)  route 0.102ns (72.340%))
  Logic Levels:           0  
  Clock Path Skew:        0.042ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.168ns
    Source Clock Delay      (SCD):    3.126ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      1.273ns (routing 0.435ns, distribution 0.838ns)
  Clock Net Delay (Destination): 1.343ns (routing 0.521ns, distribution 0.822ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.836    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.853 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.273     3.126    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X35Y217        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X35Y217        FDRE (Prop_GFF2_SLICEM_C_Q)
                                                      0.039     3.165 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/Q
                         net (fo=1, routed)           0.102     3.267    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[3]
    SLICE_X35Y217        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.583     1.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.640 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.806    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.825 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.343     3.168    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X35Y217        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.144ns  (logic 0.039ns (27.083%)  route 0.105ns (72.917%))
  Logic Levels:           0  
  Clock Path Skew:        0.042ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.168ns
    Source Clock Delay      (SCD):    3.126ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      1.273ns (routing 0.435ns, distribution 0.838ns)
  Clock Net Delay (Destination): 1.343ns (routing 0.521ns, distribution 0.822ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.836    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.853 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.273     3.126    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X35Y217        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X35Y217        FDRE (Prop_GFF_SLICEM_C_Q)
                                                      0.039     3.165 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/Q
                         net (fo=1, routed)           0.105     3.270    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[2]
    SLICE_X35Y217        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.583     1.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.640 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.806    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.825 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.343     3.168    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X35Y217        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.178ns  (logic 0.038ns (21.348%)  route 0.140ns (78.652%))
  Logic Levels:           0  
  Clock Path Skew:        0.036ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.183ns
    Source Clock Delay      (SCD):    3.147ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      1.294ns (routing 0.435ns, distribution 0.859ns)
  Clock Net Delay (Destination): 1.358ns (routing 0.521ns, distribution 0.837ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.836    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.853 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.294     3.147    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X28Y235        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X28Y235        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     3.185 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[4]/Q
                         net (fo=1, routed)           0.140     3.325    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[4]
    SLICE_X29Y235        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.583     1.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.640 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.806    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.825 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.358     3.183    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X29Y235        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.504ns  (logic 0.040ns (7.937%)  route 0.464ns (92.064%))
  Logic Levels:           0  
  Clock Path Skew:        0.034ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.170ns
    Source Clock Delay      (SCD):    3.136ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      1.283ns (routing 0.435ns, distribution 0.848ns)
  Clock Net Delay (Destination): 1.345ns (routing 0.521ns, distribution 0.824ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.836    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.853 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.283     3.136    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/rd_clk
    SLICE_X35Y233        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X35Y233        FDRE (Prop_FFF2_SLICEM_C_Q)
                                                      0.040     3.176 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/Q
                         net (fo=1, routed)           0.464     3.640    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/src_rst
    SLICE_X36Y221        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.583     1.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.640 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.806    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.825 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.345     3.170    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/dest_clk
    SLICE_X36Y221        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/rst_ddr4/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.675ns  (logic 0.074ns (10.963%)  route 0.601ns (89.037%))
  Logic Levels:           1  (LUT1=1)
  Clock Path Skew:        0.161ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.168ns
    Source Clock Delay      (SCD):    3.008ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      1.155ns (routing 0.435ns, distribution 0.720ns)
  Clock Net Delay (Destination): 1.343ns (routing 0.521ns, distribution 0.822ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.836    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.853 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.155     3.008    d_1_i/ddr4/rst_ddr4/U0/slowest_sync_clk
    SLICE_X80Y209        FDRE                                         r  d_1_i/ddr4/rst_ddr4/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y209        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     3.047 f  d_1_i/ddr4/rst_ddr4/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.521     3.568    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/m_axis_aresetn
    SLICE_X33Y225        LUT1 (Prop_E6LUT_SLICEL_I0_O)
                                                      0.035     3.603 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst_i_1/O
                         net (fo=1, routed)           0.080     3.683    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/src_rst
    SLICE_X33Y225        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.583     1.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.640 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.806    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.825 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.343     3.168    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/dest_clk
    SLICE_X33Y225        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  
  To Clock:  clk_out1_d_1_clk_core_0

Max Delay             1 Endpoint
Min Delay             1 Endpoint
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                            (internal pin)
  Destination:            d_1_i/rst_core/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.930ns  (logic 0.051ns (2.643%)  route 1.879ns (97.357%))
  Logic Levels:           1  (LUT1=1)
  Clock Uncertainty:      0.123ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.085ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Destination): 1.693ns (routing 0.838ns, distribution 0.855ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    PS8_X0Y0             PS8                          0.000     0.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                         net (fo=5, routed)           1.721     1.721    d_1_i/rst_core/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/ext_reset_in
    SLICE_X37Y302        LUT1 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.051     1.772 r  d_1_i/rst_core/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1/O
                         net (fo=1, routed)           0.158     1.930    d_1_i/rst_core/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/exr_d1
    SLICE_X37Y302        FDRE                                         r  d_1_i/rst_core/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.549     3.070    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.700 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.915    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.939 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.693     5.632    d_1_i/rst_core/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/slowest_sync_clk
    SLICE_X37Y302        FDRE                                         r  d_1_i/rst_core/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                            (internal pin)
  Destination:            d_1_i/rst_core/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.960ns  (logic 0.022ns (2.291%)  route 0.938ns (97.709%))
  Logic Levels:           1  (LUT1=1)
  Clock Uncertainty:      0.123ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.085ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Destination): 1.172ns (routing 0.553ns, distribution 0.619ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    PS8_X0Y0             PS8                          0.000     0.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                         net (fo=5, routed)           0.883     0.883    d_1_i/rst_core/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/ext_reset_in
    SLICE_X37Y302        LUT1 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.022     0.905 r  d_1_i/rst_core/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1/O
                         net (fo=1, routed)           0.055     0.960    d_1_i/rst_core/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/exr_d1
    SLICE_X37Y302        FDRE                                         r  d_1_i/rst_core/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       1.708     2.156    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.861 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     2.027    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     2.046 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.172     3.218    d_1_i/rst_core/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/slowest_sync_clk
    SLICE_X37Y302        FDRE                                         r  d_1_i/rst_core/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFDAC0_CLK
  To Clock:  clk_out1_d_1_clk_core_0

Max Delay           303 Endpoints
Min Delay           303 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/rd_gptr_cdc_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.275ns  (logic 0.079ns (6.197%)  route 1.196ns (93.803%))
  Logic Levels:           0  
  Clock Path Skew:        2.023ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.759ns
    Source Clock Delay      (SCD):    3.735ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.085ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      3.062ns (routing 1.381ns, distribution 1.681ns)
  Clock Net Delay (Destination): 1.820ns (routing 0.838ns, distribution 0.982ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       3.062     3.735    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X3Y355         FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X3Y355         FDCE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     3.814 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[3]/Q
                         net (fo=3, routed)           1.196     5.010    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/rd_gptr[3]
    SLICE_X12Y356        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/rd_gptr_cdc_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.549     3.070    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.700 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.915    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.939 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.820     5.759    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/c_clk_i
    SLICE_X12Y356        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/rd_gptr_cdc_reg[3]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.t_time_abs_cdc_reg[17]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.c_time_abs_r_reg[17]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.286ns  (logic 0.078ns (6.065%)  route 1.208ns (93.935%))
  Logic Levels:           0  
  Clock Path Skew:        2.089ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.669ns
    Source Clock Delay      (SCD):    3.580ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.085ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      2.907ns (routing 1.381ns, distribution 1.526ns)
  Clock Net Delay (Destination): 1.730ns (routing 0.838ns, distribution 0.892ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       2.907     3.580    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/t_clk_i
    SLICE_X34Y374        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.t_time_abs_cdc_reg[17]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X34Y374        FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.078     3.658 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.t_time_abs_cdc_reg[17]/Q
                         net (fo=1, routed)           1.208     4.866    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/t_time_abs_cdc[17]
    SLICE_X34Y374        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.c_time_abs_r_reg[17]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.549     3.070    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.700 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.915    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.939 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.730     5.669    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/c_clk_i
    SLICE_X34Y374        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.c_time_abs_r_reg[17]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/gcc_rd_ptr/clear_r_reg/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/clr_fifo_ack_reg/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.161ns  (logic 0.230ns (19.805%)  route 0.931ns (80.195%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        2.067ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.766ns
    Source Clock Delay      (SCD):    3.699ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.085ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      3.026ns (routing 1.381ns, distribution 1.645ns)
  Clock Net Delay (Destination): 1.827ns (routing 0.838ns, distribution 0.989ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       3.026     3.699    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X13Y387        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/gcc_rd_ptr/clear_r_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X13Y387        FDCE (Prop_AFF2_SLICEM_C_Q)
                                                      0.080     3.779 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/gcc_rd_ptr/clear_r_reg/Q
                         net (fo=20, routed)          0.880     4.659    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/gcc_wr_ptr/out
    SLICE_X15Y387        LUT3 (Prop_H6LUT_SLICEL_I1_O)
                                                      0.150     4.809 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/gcc_wr_ptr/clr_fifo_ack_i_1__5/O
                         net (fo=1, routed)           0.051     4.860    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/gcc_wr_ptr_n_1
    SLICE_X15Y387        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/clr_fifo_ack_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.549     3.070    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.700 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.915    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.939 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.827     5.766    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/c_clk_i
    SLICE_X15Y387        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/clr_fifo_ack_reg/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/rd_gptr_cdc_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.158ns  (logic 0.079ns (6.820%)  route 1.079ns (93.180%))
  Logic Levels:           0  
  Clock Path Skew:        1.957ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.654ns
    Source Clock Delay      (SCD):    3.697ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.085ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      3.024ns (routing 1.381ns, distribution 1.643ns)
  Clock Net Delay (Destination): 1.715ns (routing 0.838ns, distribution 0.877ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       3.024     3.697    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X16Y314        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X16Y314        FDCE (Prop_CFF_SLICEL_C_Q)
                                                      0.079     3.776 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[3]/Q
                         net (fo=5, routed)           1.079     4.855    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/rd_gptr[3]
    SLICE_X21Y317        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/rd_gptr_cdc_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.549     3.070    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.700 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.915    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.939 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.715     5.654    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/c_clk_i
    SLICE_X21Y317        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[7].wave_fifo_inst/rd_gptr_cdc_reg[3]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/rd_gptr_cdc_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.037ns  (logic 0.079ns (7.620%)  route 0.958ns (92.380%))
  Logic Levels:           0  
  Clock Path Skew:        1.947ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.641ns
    Source Clock Delay      (SCD):    3.693ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.085ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      3.020ns (routing 1.381ns, distribution 1.639ns)
  Clock Net Delay (Destination): 1.702ns (routing 0.838ns, distribution 0.864ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       3.020     3.693    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X12Y322        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X12Y322        FDCE (Prop_FFF_SLICEL_C_Q)
                                                      0.079     3.772 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[3]/Q
                         net (fo=5, routed)           0.958     4.730    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/rd_gptr[3]
    SLICE_X27Y320        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/rd_gptr_cdc_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.549     3.070    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.700 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.915    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.939 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.702     5.641    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/c_clk_i
    SLICE_X27Y320        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/rd_gptr_cdc_reg[3]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[7]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].trig_fifo_inst/rd_gptr_cdc_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.985ns  (logic 0.079ns (8.022%)  route 0.906ns (91.978%))
  Logic Levels:           0  
  Clock Path Skew:        2.058ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.769ns
    Source Clock Delay      (SCD):    3.711ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.085ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      3.038ns (routing 1.381ns, distribution 1.657ns)
  Clock Net Delay (Destination): 1.830ns (routing 0.838ns, distribution 0.992ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       3.038     3.711    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X15Y403        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X15Y403        FDCE (Prop_GFF_SLICEL_C_Q)
                                                      0.079     3.790 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[7]/Q
                         net (fo=3, routed)           0.906     4.695    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].trig_fifo_inst/rd_gptr[7]
    SLICE_X16Y397        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].trig_fifo_inst/rd_gptr_cdc_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.549     3.070    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.700 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.915    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.939 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.830     5.769    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].trig_fifo_inst/c_clk_i
    SLICE_X16Y397        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].trig_fifo_inst/rd_gptr_cdc_reg[7]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[11].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[8]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[11].trig_fifo_inst/rd_gptr_cdc_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.944ns  (logic 0.079ns (8.366%)  route 0.865ns (91.634%))
  Logic Levels:           0  
  Clock Path Skew:        1.993ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.743ns
    Source Clock Delay      (SCD):    3.750ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.085ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      3.077ns (routing 1.381ns, distribution 1.696ns)
  Clock Net Delay (Destination): 1.804ns (routing 0.838ns, distribution 0.966ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       3.077     3.750    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[11].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X2Y347         FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[11].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X2Y347         FDCE (Prop_BFF_SLICEL_C_Q)
                                                      0.079     3.829 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[11].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[8]/Q
                         net (fo=3, routed)           0.865     4.694    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[11].trig_fifo_inst/rd_gptr[8]
    SLICE_X15Y354        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[11].trig_fifo_inst/rd_gptr_cdc_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.549     3.070    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.700 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.915    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.939 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.804     5.743    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[11].trig_fifo_inst/c_clk_i
    SLICE_X15Y354        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[11].trig_fifo_inst/rd_gptr_cdc_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/rd_gptr_cdc_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.962ns  (logic 0.079ns (8.216%)  route 0.883ns (91.784%))
  Logic Levels:           0  
  Clock Path Skew:        2.039ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.739ns
    Source Clock Delay      (SCD):    3.700ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.085ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      3.027ns (routing 1.381ns, distribution 1.646ns)
  Clock Net Delay (Destination): 1.800ns (routing 0.838ns, distribution 0.962ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       3.027     3.700    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X14Y346        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X14Y346        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     3.779 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[2]/Q
                         net (fo=5, routed)           0.883     4.661    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/rd_gptr[2]
    SLICE_X15Y347        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/rd_gptr_cdc_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.549     3.070    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.700 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.915    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.939 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.800     5.739    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/c_clk_i
    SLICE_X15Y347        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/rd_gptr_cdc_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[7]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/rd_gptr_cdc_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.973ns  (logic 0.079ns (8.118%)  route 0.894ns (91.882%))
  Logic Levels:           0  
  Clock Path Skew:        1.959ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.646ns
    Source Clock Delay      (SCD):    3.687ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.085ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      3.014ns (routing 1.381ns, distribution 1.633ns)
  Clock Net Delay (Destination): 1.707ns (routing 0.838ns, distribution 0.869ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       3.014     3.687    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X12Y323        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X12Y323        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     3.766 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[7]/Q
                         net (fo=5, routed)           0.894     4.661    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/rd_gptr[7]
    SLICE_X29Y319        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/rd_gptr_cdc_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.549     3.070    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.700 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.915    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.939 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.707     5.646    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/c_clk_i
    SLICE_X29Y319        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/rd_gptr_cdc_reg[7]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/gcc_rd_ptr/clear_r_reg/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/clr_fifo_ack_reg/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.930ns  (logic 0.203ns (21.834%)  route 0.727ns (78.166%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        2.041ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.757ns
    Source Clock Delay      (SCD):    3.716ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.085ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      3.043ns (routing 1.381ns, distribution 1.662ns)
  Clock Net Delay (Destination): 1.818ns (routing 0.838ns, distribution 0.980ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       3.043     3.716    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X9Y356         FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/gcc_rd_ptr/clear_r_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X9Y356         FDCE (Prop_AFF2_SLICEL_C_Q)
                                                      0.081     3.797 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/gcc_rd_ptr/clear_r_reg/Q
                         net (fo=20, routed)          0.655     4.452    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/gcc_wr_ptr/out
    SLICE_X13Y358        LUT3 (Prop_D6LUT_SLICEM_I1_O)
                                                      0.122     4.574 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/gcc_wr_ptr/clr_fifo_ack_i_1__12/O
                         net (fo=1, routed)           0.072     4.646    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/gcc_wr_ptr_n_1
    SLICE_X13Y358        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/clr_fifo_ack_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.549     3.070    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.700 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.915    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.939 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.818     5.757    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/c_clk_i
    SLICE_X13Y358        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/clr_fifo_ack_reg/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[6]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/rd_gptr_cdc_reg[6]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.102ns  (logic 0.039ns (38.099%)  route 0.063ns (61.901%))
  Logic Levels:           0  
  Clock Path Skew:        1.436ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.308ns
    Source Clock Delay      (SCD):    1.872ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.085ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      1.523ns (routing 0.748ns, distribution 0.775ns)
  Clock Net Delay (Destination): 1.262ns (routing 0.553ns, distribution 0.709ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       1.523     1.872    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X49Y327        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y327        FDCE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     1.911 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[6]/Q
                         net (fo=5, routed)           0.063     1.974    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/rd_gptr[6]
    SLICE_X49Y326        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/rd_gptr_cdc_reg[6]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       1.708     2.156    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.861 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     2.027    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     2.046 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.262     3.308    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/c_clk_i
    SLICE_X49Y326        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/rd_gptr_cdc_reg[6]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/rd_gptr_cdc_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.099ns  (logic 0.039ns (39.521%)  route 0.060ns (60.480%))
  Logic Levels:           0  
  Clock Path Skew:        1.414ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.294ns
    Source Clock Delay      (SCD):    1.881ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.085ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      1.532ns (routing 0.748ns, distribution 0.784ns)
  Clock Net Delay (Destination): 1.248ns (routing 0.553ns, distribution 0.695ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       1.532     1.881    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X44Y340        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X44Y340        FDCE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     1.920 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[3]/Q
                         net (fo=5, routed)           0.060     1.979    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/rd_gptr[3]
    SLICE_X44Y339        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/rd_gptr_cdc_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       1.708     2.156    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.861 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     2.027    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     2.046 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.248     3.294    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/c_clk_i
    SLICE_X44Y339        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/rd_gptr_cdc_reg[3]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[5]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/rd_gptr_cdc_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.112ns  (logic 0.039ns (34.806%)  route 0.073ns (65.194%))
  Logic Levels:           0  
  Clock Path Skew:        1.428ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.299ns
    Source Clock Delay      (SCD):    1.872ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.085ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      1.523ns (routing 0.748ns, distribution 0.775ns)
  Clock Net Delay (Destination): 1.253ns (routing 0.553ns, distribution 0.700ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       1.523     1.872    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X49Y327        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y327        FDCE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     1.911 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[5]/Q
                         net (fo=5, routed)           0.073     1.984    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/rd_gptr[5]
    SLICE_X51Y327        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/rd_gptr_cdc_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       1.708     2.156    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.861 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     2.027    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     2.046 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.253     3.299    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/c_clk_i
    SLICE_X51Y327        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/rd_gptr_cdc_reg[5]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/rd_gptr_cdc_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.102ns  (logic 0.039ns (38.188%)  route 0.063ns (61.812%))
  Logic Levels:           0  
  Clock Path Skew:        1.421ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.307ns
    Source Clock Delay      (SCD):    1.886ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.085ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      1.537ns (routing 0.748ns, distribution 0.789ns)
  Clock Net Delay (Destination): 1.261ns (routing 0.553ns, distribution 0.708ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       1.537     1.886    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X43Y393        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X43Y393        FDCE (Prop_BFF_SLICEL_C_Q)
                                                      0.039     1.925 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[2]/Q
                         net (fo=3, routed)           0.063     1.988    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/rd_gptr[2]
    SLICE_X43Y392        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/rd_gptr_cdc_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       1.708     2.156    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.861 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     2.027    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     2.046 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.261     3.307    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/c_clk_i
    SLICE_X43Y392        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/rd_gptr_cdc_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[7]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/rd_gptr_cdc_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.126ns  (logic 0.039ns (30.999%)  route 0.087ns (69.001%))
  Logic Levels:           0  
  Clock Path Skew:        1.435ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.304ns
    Source Clock Delay      (SCD):    1.869ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.085ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      1.520ns (routing 0.748ns, distribution 0.772ns)
  Clock Net Delay (Destination): 1.258ns (routing 0.553ns, distribution 0.705ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       1.520     1.869    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X49Y327        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y327        FDCE (Prop_CFF_SLICEL_C_Q)
                                                      0.039     1.908 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[7]/Q
                         net (fo=5, routed)           0.087     1.994    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/rd_gptr[7]
    SLICE_X49Y326        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/rd_gptr_cdc_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       1.708     2.156    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.861 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     2.027    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     2.046 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.258     3.304    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/c_clk_i
    SLICE_X49Y326        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/rd_gptr_cdc_reg[7]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/rd_gptr_cdc_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.101ns  (logic 0.039ns (38.664%)  route 0.062ns (61.336%))
  Logic Levels:           0  
  Clock Path Skew:        1.417ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.311ns
    Source Clock Delay      (SCD):    1.895ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.085ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      1.546ns (routing 0.748ns, distribution 0.798ns)
  Clock Net Delay (Destination): 1.265ns (routing 0.553ns, distribution 0.712ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       1.546     1.895    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X42Y392        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X42Y392        FDCE (Prop_HFF_SLICEM_C_Q)
                                                      0.039     1.934 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[1]/Q
                         net (fo=3, routed)           0.062     1.995    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/rd_gptr[1]
    SLICE_X43Y392        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/rd_gptr_cdc_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       1.708     2.156    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.861 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     2.027    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     2.046 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.265     3.311    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/c_clk_i
    SLICE_X43Y392        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/rd_gptr_cdc_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/rd_gptr_cdc_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.124ns  (logic 0.039ns (31.412%)  route 0.085ns (68.588%))
  Logic Levels:           0  
  Clock Path Skew:        1.424ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.295ns
    Source Clock Delay      (SCD):    1.872ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.085ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      1.523ns (routing 0.748ns, distribution 0.775ns)
  Clock Net Delay (Destination): 1.249ns (routing 0.553ns, distribution 0.696ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       1.523     1.872    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X49Y327        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y327        FDCE (Prop_FFF_SLICEL_C_Q)
                                                      0.039     1.911 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[3]/Q
                         net (fo=5, routed)           0.085     1.996    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/rd_gptr[3]
    SLICE_X51Y327        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/rd_gptr_cdc_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       1.708     2.156    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.861 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     2.027    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     2.046 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.249     3.295    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/c_clk_i
    SLICE_X51Y327        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/rd_gptr_cdc_reg[3]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.t_time_abs_cdc_reg[29]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.c_time_abs_r_reg[29]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.099ns  (logic 0.039ns (39.394%)  route 0.060ns (60.606%))
  Logic Levels:           0  
  Clock Path Skew:        1.413ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.314ns
    Source Clock Delay      (SCD):    1.902ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.085ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      1.553ns (routing 0.748ns, distribution 0.805ns)
  Clock Net Delay (Destination): 1.268ns (routing 0.553ns, distribution 0.715ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       1.553     1.902    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/t_clk_i
    SLICE_X40Y376        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.t_time_abs_cdc_reg[29]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X40Y376        FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.039     1.941 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.t_time_abs_cdc_reg[29]/Q
                         net (fo=1, routed)           0.060     2.001    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/t_time_abs_cdc[29]
    SLICE_X40Y376        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.c_time_abs_r_reg[29]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       1.708     2.156    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.861 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     2.027    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     2.046 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.268     3.314    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/c_clk_i
    SLICE_X40Y376        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.c_time_abs_r_reg[29]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.t_time_abs_cdc_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.c_time_abs_r_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.104ns  (logic 0.039ns (37.500%)  route 0.065ns (62.500%))
  Logic Levels:           0  
  Clock Path Skew:        1.405ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.311ns
    Source Clock Delay      (SCD):    1.906ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.085ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      1.557ns (routing 0.748ns, distribution 0.809ns)
  Clock Net Delay (Destination): 1.265ns (routing 0.553ns, distribution 0.712ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       1.557     1.906    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/t_clk_i
    SLICE_X40Y374        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.t_time_abs_cdc_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X40Y374        FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.039     1.945 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.t_time_abs_cdc_reg[3]/Q
                         net (fo=1, routed)           0.065     2.010    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/t_time_abs_cdc[3]
    SLICE_X40Y374        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.c_time_abs_r_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       1.708     2.156    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.861 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     2.027    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     2.046 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.265     3.311    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/c_clk_i
    SLICE_X40Y374        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.c_time_abs_r_reg[3]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[6]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/rd_gptr_cdc_reg[6]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.113ns  (logic 0.038ns (33.695%)  route 0.075ns (66.305%))
  Logic Levels:           0  
  Clock Path Skew:        1.403ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.304ns
    Source Clock Delay      (SCD):    1.902ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.085ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      1.553ns (routing 0.748ns, distribution 0.805ns)
  Clock Net Delay (Destination): 1.258ns (routing 0.553ns, distribution 0.705ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       1.553     1.902    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X42Y391        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X42Y391        FDCE (Prop_CFF_SLICEM_C_Q)
                                                      0.038     1.940 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[6]/Q
                         net (fo=3, routed)           0.075     2.014    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/rd_gptr[6]
    SLICE_X41Y390        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/rd_gptr_cdc_reg[6]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       1.708     2.156    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.861 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     2.027    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     2.046 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.258     3.304    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/c_clk_i
    SLICE_X41Y390        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/rd_gptr_cdc_reg[6]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_pl_0
  To Clock:  clk_out1_d_1_clk_core_0

Max Delay          3741 Endpoints
Min Delay          3741 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMD/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[6]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.604ns  (logic 0.287ns (17.893%)  route 1.317ns (82.107%))
  Logic Levels:           0  
  Clock Path Skew:        3.301ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.774ns
    Source Clock Delay      (SCD):    2.473ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.244ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.335ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      2.247ns (routing 0.662ns, distribution 1.585ns)
  Clock Net Delay (Destination): 1.835ns (routing 0.838ns, distribution 0.997ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.247     2.473    d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/WCLK
    SLICE_X20Y283        RAMD32                                       r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMD/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X20Y283        RAMD32 (Prop_D5LUT_SLICEM_CLK_O)
                                                      0.287     2.760 r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMD/O
                         net (fo=1, routed)           1.317     4.077    d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[6]
    SLICE_X11Y317        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[6]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.549     3.070    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.700 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.915    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.939 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.835     5.774    d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X11Y317        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[6]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMA_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[29]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.480ns  (logic 0.305ns (20.608%)  route 1.175ns (79.392%))
  Logic Levels:           0  
  Clock Path Skew:        3.286ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.765ns
    Source Clock Delay      (SCD):    2.479ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.244ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.335ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      2.253ns (routing 0.662ns, distribution 1.591ns)
  Clock Net Delay (Destination): 1.826ns (routing 0.838ns, distribution 0.988ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.253     2.479    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/WCLK
    SLICE_X20Y295        RAMD32                                       r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMA_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X20Y295        RAMD32 (Prop_A6LUT_SLICEM_CLK_O)
                                                      0.305     2.784 r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMA_D1/O
                         net (fo=1, routed)           1.175     3.959    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[29]
    SLICE_X10Y333        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[29]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.549     3.070    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.700 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.915    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.939 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.826     5.765    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X10Y333        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[29]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMC_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[33]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.411ns  (logic 0.307ns (21.758%)  route 1.104ns (78.242%))
  Logic Levels:           0  
  Clock Path Skew:        3.286ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.765ns
    Source Clock Delay      (SCD):    2.479ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.244ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.335ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      2.253ns (routing 0.662ns, distribution 1.591ns)
  Clock Net Delay (Destination): 1.826ns (routing 0.838ns, distribution 0.988ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.253     2.479    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/WCLK
    SLICE_X20Y295        RAMD32                                       r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMC_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X20Y295        RAMD32 (Prop_C6LUT_SLICEM_CLK_O)
                                                      0.307     2.786 r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMC_D1/O
                         net (fo=1, routed)           1.104     3.890    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[33]
    SLICE_X10Y333        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[33]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.549     3.070    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.700 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.915    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.939 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.826     5.765    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X10Y333        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[33]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMF/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[38]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.380ns  (logic 0.295ns (21.377%)  route 1.085ns (78.623%))
  Logic Levels:           0  
  Clock Path Skew:        3.284ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.763ns
    Source Clock Delay      (SCD):    2.479ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.244ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.335ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      2.253ns (routing 0.662ns, distribution 1.591ns)
  Clock Net Delay (Destination): 1.824ns (routing 0.838ns, distribution 0.986ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.253     2.479    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/WCLK
    SLICE_X20Y295        RAMD32                                       r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMF/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X20Y295        RAMD32 (Prop_F5LUT_SLICEM_CLK_O)
                                                      0.295     2.774 r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMF/O
                         net (fo=1, routed)           1.085     3.859    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[38]
    SLICE_X10Y333        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[38]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.549     3.070    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.700 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.915    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.939 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.824     5.763    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X10Y333        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[38]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMG/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[40]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.365ns  (logic 0.281ns (20.586%)  route 1.084ns (79.414%))
  Logic Levels:           0  
  Clock Path Skew:        3.286ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.765ns
    Source Clock Delay      (SCD):    2.479ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.244ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.335ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      2.253ns (routing 0.662ns, distribution 1.591ns)
  Clock Net Delay (Destination): 1.826ns (routing 0.838ns, distribution 0.988ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.253     2.479    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/WCLK
    SLICE_X20Y295        RAMD32                                       r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMG/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X20Y295        RAMD32 (Prop_G5LUT_SLICEM_CLK_O)
                                                      0.281     2.760 r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMG/O
                         net (fo=1, routed)           1.084     3.844    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[40]
    SLICE_X10Y333        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[40]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.549     3.070    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.700 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.915    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.939 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.826     5.765    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X10Y333        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[40]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27/RAMG_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[27]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.374ns  (logic 0.295ns (21.470%)  route 1.079ns (78.530%))
  Logic Levels:           0  
  Clock Path Skew:        3.326ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.757ns
    Source Clock Delay      (SCD):    2.431ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.244ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.335ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      2.205ns (routing 0.662ns, distribution 1.543ns)
  Clock Net Delay (Destination): 1.818ns (routing 0.838ns, distribution 0.980ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.205     2.431    d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27/WCLK
    SLICE_X21Y283        RAMD32                                       r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27/RAMG_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X21Y283        RAMD32 (Prop_G6LUT_SLICEM_CLK_O)
                                                      0.295     2.726 r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27/RAMG_D1/O
                         net (fo=1, routed)           1.079     3.805    d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[27]
    SLICE_X14Y302        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[27]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.549     3.070    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.700 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.915    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.939 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.818     5.757    d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X14Y302        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[27]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAME/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[36]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.321ns  (logic 0.288ns (21.802%)  route 1.033ns (78.198%))
  Logic Levels:           0  
  Clock Path Skew:        3.283ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.762ns
    Source Clock Delay      (SCD):    2.479ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.244ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.335ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      2.253ns (routing 0.662ns, distribution 1.591ns)
  Clock Net Delay (Destination): 1.823ns (routing 0.838ns, distribution 0.985ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.253     2.479    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/WCLK
    SLICE_X20Y295        RAMD32                                       r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAME/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X20Y295        RAMD32 (Prop_E5LUT_SLICEM_CLK_O)
                                                      0.288     2.767 r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAME/O
                         net (fo=1, routed)           1.033     3.800    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[36]
    SLICE_X10Y332        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[36]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.549     3.070    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.700 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.915    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.939 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.823     5.762    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X10Y332        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[36]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMD/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[6]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.319ns  (logic 0.287ns (21.759%)  route 1.032ns (78.241%))
  Logic Levels:           0  
  Clock Path Skew:        3.282ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.761ns
    Source Clock Delay      (SCD):    2.479ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.244ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.335ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      2.253ns (routing 0.662ns, distribution 1.591ns)
  Clock Net Delay (Destination): 1.822ns (routing 0.838ns, distribution 0.984ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.253     2.479    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/WCLK
    SLICE_X20Y294        RAMD32                                       r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMD/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X20Y294        RAMD32 (Prop_D5LUT_SLICEM_CLK_O)
                                                      0.287     2.766 r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMD/O
                         net (fo=1, routed)           1.032     3.798    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[6]
    SLICE_X11Y330        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[6]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.549     3.070    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.700 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.915    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.939 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.822     5.761    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X11Y330        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[6]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMD/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[34]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.311ns  (logic 0.287ns (21.892%)  route 1.024ns (78.108%))
  Logic Levels:           0  
  Clock Path Skew:        3.286ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.765ns
    Source Clock Delay      (SCD):    2.479ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.244ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.335ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      2.253ns (routing 0.662ns, distribution 1.591ns)
  Clock Net Delay (Destination): 1.826ns (routing 0.838ns, distribution 0.988ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.253     2.479    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/WCLK
    SLICE_X20Y295        RAMD32                                       r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMD/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X20Y295        RAMD32 (Prop_D5LUT_SLICEM_CLK_O)
                                                      0.287     2.766 r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMD/O
                         net (fo=1, routed)           1.024     3.790    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[34]
    SLICE_X10Y328        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[34]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.549     3.070    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.700 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.915    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.939 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.826     5.765    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X10Y328        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[34]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMD/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[34]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.338ns  (logic 0.287ns (21.450%)  route 1.051ns (78.550%))
  Logic Levels:           0  
  Clock Path Skew:        3.344ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.776ns
    Source Clock Delay      (SCD):    2.432ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.244ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.335ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      2.206ns (routing 0.662ns, distribution 1.544ns)
  Clock Net Delay (Destination): 1.837ns (routing 0.838ns, distribution 0.999ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.206     2.432    d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/WCLK
    SLICE_X21Y284        RAMD32                                       r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMD/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X21Y284        RAMD32 (Prop_D5LUT_SLICEM_CLK_O)
                                                      0.287     2.719 r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMD/O
                         net (fo=1, routed)           1.051     3.770    d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[34]
    SLICE_X11Y315        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[34]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.549     3.070    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.700 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.915    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.939 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.837     5.776    d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X11Y315        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[34]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.096ns  (logic 0.039ns (40.586%)  route 0.057ns (59.414%))
  Logic Levels:           0  
  Clock Path Skew:        2.029ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.301ns
    Source Clock Delay      (SCD):    1.272ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.244ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.335ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      1.152ns (routing 0.358ns, distribution 0.794ns)
  Clock Net Delay (Destination): 1.255ns (routing 0.553ns, distribution 0.702ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.152     1.272    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_clk
    SLICE_X58Y321        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X58Y321        FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.039     1.311 r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/Q
                         net (fo=2, routed)           0.057     1.368    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/src_rst
    SLICE_X59Y321        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       1.708     2.156    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.861 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     2.027    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     2.046 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.255     3.301    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/dest_clk
    SLICE_X59Y321        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.101ns  (logic 0.038ns (37.624%)  route 0.063ns (62.376%))
  Logic Levels:           0  
  Clock Path Skew:        2.031ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.337ns
    Source Clock Delay      (SCD):    1.306ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.244ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.335ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      1.186ns (routing 0.358ns, distribution 0.828ns)
  Clock Net Delay (Destination): 1.291ns (routing 0.553ns, distribution 0.738ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.186     1.306    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk
    SLICE_X63Y325        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X63Y325        FDRE (Prop_CFF_SLICEM_C_Q)
                                                      0.038     1.344 r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[0]/Q
                         net (fo=1, routed)           0.063     1.407    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[0]
    SLICE_X63Y325        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       1.708     2.156    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.861 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     2.027    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     2.046 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.291     3.337    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk
    SLICE_X63Y325        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.118ns  (logic 0.039ns (33.051%)  route 0.079ns (66.949%))
  Logic Levels:           0  
  Clock Path Skew:        2.038ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.337ns
    Source Clock Delay      (SCD):    1.299ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.244ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.335ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      1.179ns (routing 0.358ns, distribution 0.821ns)
  Clock Net Delay (Destination): 1.291ns (routing 0.553ns, distribution 0.738ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.179     1.299    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk
    SLICE_X64Y336        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X64Y336        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.039     1.338 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[4]/Q
                         net (fo=1, routed)           0.079     1.417    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[4]
    SLICE_X64Y336        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       1.708     2.156    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.861 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     2.027    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     2.046 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.291     3.337    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk
    SLICE_X64Y336        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.119ns  (logic 0.038ns (31.933%)  route 0.081ns (68.067%))
  Logic Levels:           0  
  Clock Path Skew:        2.025ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.331ns
    Source Clock Delay      (SCD):    1.306ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.244ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.335ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      1.186ns (routing 0.358ns, distribution 0.828ns)
  Clock Net Delay (Destination): 1.285ns (routing 0.553ns, distribution 0.732ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.186     1.306    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk
    SLICE_X63Y325        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X63Y325        FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.038     1.344 r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]/Q
                         net (fo=1, routed)           0.081     1.425    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[2]
    SLICE_X62Y326        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       1.708     2.156    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.861 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     2.027    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     2.046 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.285     3.331    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk
    SLICE_X62Y326        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.158ns  (logic 0.038ns (24.051%)  route 0.120ns (75.949%))
  Logic Levels:           0  
  Clock Path Skew:        2.037ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.336ns
    Source Clock Delay      (SCD):    1.299ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.244ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.335ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      1.179ns (routing 0.358ns, distribution 0.821ns)
  Clock Net Delay (Destination): 1.290ns (routing 0.553ns, distribution 0.737ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.179     1.299    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk
    SLICE_X63Y333        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X63Y333        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     1.337 r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[4]/Q
                         net (fo=1, routed)           0.120     1.457    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[4]
    SLICE_X63Y333        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       1.708     2.156    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.861 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     2.027    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     2.046 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.290     3.336    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk
    SLICE_X63Y333        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.158ns  (logic 0.039ns (24.684%)  route 0.119ns (75.316%))
  Logic Levels:           0  
  Clock Path Skew:        2.031ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.337ns
    Source Clock Delay      (SCD):    1.306ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.244ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.335ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      1.186ns (routing 0.358ns, distribution 0.828ns)
  Clock Net Delay (Destination): 1.291ns (routing 0.553ns, distribution 0.738ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.186     1.306    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk
    SLICE_X63Y325        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X63Y325        FDRE (Prop_CFF2_SLICEM_C_Q)
                                                      0.039     1.345 r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[1]/Q
                         net (fo=1, routed)           0.119     1.464    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[1]
    SLICE_X63Y325        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       1.708     2.156    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.861 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     2.027    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     2.046 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.291     3.337    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk
    SLICE_X63Y325        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.167ns  (logic 0.039ns (23.353%)  route 0.128ns (76.647%))
  Logic Levels:           0  
  Clock Path Skew:        2.028ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.330ns
    Source Clock Delay      (SCD):    1.302ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.244ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.335ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      1.182ns (routing 0.358ns, distribution 0.824ns)
  Clock Net Delay (Destination): 1.284ns (routing 0.553ns, distribution 0.731ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.182     1.302    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk
    SLICE_X63Y330        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X63Y330        FDRE (Prop_CFF2_SLICEM_C_Q)
                                                      0.039     1.341 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/Q
                         net (fo=1, routed)           0.128     1.469    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[3]
    SLICE_X64Y332        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       1.708     2.156    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.861 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     2.027    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     2.046 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.284     3.330    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk
    SLICE_X64Y332        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.170ns  (logic 0.040ns (23.529%)  route 0.130ns (76.471%))
  Logic Levels:           0  
  Clock Path Skew:        2.029ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.335ns
    Source Clock Delay      (SCD):    1.306ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.244ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.335ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      1.186ns (routing 0.358ns, distribution 0.828ns)
  Clock Net Delay (Destination): 1.289ns (routing 0.553ns, distribution 0.736ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.186     1.306    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk
    SLICE_X63Y325        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X63Y325        FDRE (Prop_BFF2_SLICEM_C_Q)
                                                      0.040     1.346 r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/Q
                         net (fo=1, routed)           0.130     1.476    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[3]
    SLICE_X62Y325        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       1.708     2.156    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.861 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     2.027    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     2.046 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.289     3.335    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk
    SLICE_X62Y325        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.099ns  (logic 0.039ns (39.394%)  route 0.060ns (60.606%))
  Logic Levels:           0  
  Clock Path Skew:        1.930ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.319ns
    Source Clock Delay      (SCD):    1.389ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.244ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.335ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      1.269ns (routing 0.358ns, distribution 0.911ns)
  Clock Net Delay (Destination): 1.273ns (routing 0.553ns, distribution 0.720ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.269     1.389    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk
    SLICE_X11Y308        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X11Y308        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.039     1.428 r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[0]/Q
                         net (fo=1, routed)           0.060     1.488    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[0]
    SLICE_X10Y308        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       1.708     2.156    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.861 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     2.027    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     2.046 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.273     3.319    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk
    SLICE_X10Y308        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.189ns  (logic 0.038ns (20.106%)  route 0.151ns (79.894%))
  Logic Levels:           0  
  Clock Path Skew:        2.045ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.347ns
    Source Clock Delay      (SCD):    1.302ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.244ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.335ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      1.182ns (routing 0.358ns, distribution 0.824ns)
  Clock Net Delay (Destination): 1.301ns (routing 0.553ns, distribution 0.748ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.182     1.302    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk
    SLICE_X63Y330        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X63Y330        FDRE (Prop_CFF_SLICEM_C_Q)
                                                      0.038     1.340 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]/Q
                         net (fo=1, routed)           0.151     1.491    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[2]
    SLICE_X66Y334        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       1.708     2.156    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.861 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     2.027    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     2.046 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.301     3.347    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk
    SLICE_X66Y334        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  
  To Clock:  clk_pl_0

Max Delay           107 Endpoints
Min Delay           107 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_ADC0[15]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc00_fifo_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.154ns  (logic 0.000ns (0.000%)  route 2.154ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.146ns (routing 0.598ns, distribution 1.548ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_ADC0[15]
                         net (fo=1, routed)           2.154     2.154    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc00_fifo_irq/src_in
    SLICE_X116Y204       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc00_fifo_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.146     2.328    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc00_fifo_irq/dest_clk
    SLICE_X116Y204       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc00_fifo_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_ADC0[3]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc00_over_range/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.104ns  (logic 0.000ns (0.000%)  route 2.104ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.142ns (routing 0.598ns, distribution 1.544ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_ADC0[3]
                         net (fo=1, routed)           2.104     2.104    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc00_over_range/src_in
    SLICE_X114Y203       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc00_over_range/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.142     2.324    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc00_over_range/dest_clk
    SLICE_X114Y203       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc00_over_range/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_ADC0[2]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc00_over_vol/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.052ns  (logic 0.000ns (0.000%)  route 2.052ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.137ns (routing 0.598ns, distribution 1.539ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_ADC0[2]
                         net (fo=1, routed)           2.052     2.052    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc00_over_vol/src_in
    SLICE_X110Y211       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc00_over_vol/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.137     2.319    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc00_over_vol/dest_clk
    SLICE_X110Y211       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc00_over_vol/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_ADC1[2]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc01_over_vol/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.046ns  (logic 0.000ns (0.000%)  route 2.046ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.133ns (routing 0.598ns, distribution 1.535ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_ADC1[2]
                         net (fo=1, routed)           2.046     2.046    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc01_over_vol/src_in
    SLICE_X111Y207       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc01_over_vol/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.133     2.315    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc01_over_vol/dest_clk
    SLICE_X111Y207       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc01_over_vol/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_ADC1[14]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc01_data_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.984ns  (logic 0.000ns (0.000%)  route 1.984ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.161ns (routing 0.598ns, distribution 1.563ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_ADC1[14]
                         net (fo=1, routed)           1.984     1.984    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc01_data_irq/src_in
    SLICE_X114Y192       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc01_data_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.161     2.343    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc01_data_irq/dest_clk
    SLICE_X114Y192       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc01_data_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                            (internal pin)
  Destination:            d_1_i/rst_100/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.982ns  (logic 0.090ns (4.540%)  route 1.892ns (95.460%))
  Logic Levels:           1  (LUT1=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.934ns (routing 0.598ns, distribution 1.336ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    PS8_X0Y0             PS8                          0.000     0.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                         net (fo=5, routed)           1.713     1.713    d_1_i/rst_100/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/ext_reset_in
    SLICE_X69Y105        LUT1 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.090     1.803 r  d_1_i/rst_100/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1/O
                         net (fo=1, routed)           0.179     1.982    d_1_i/rst_100/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/exr_d1
    SLICE_X69Y105        FDRE                                         r  d_1_i/rst_100/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.934     2.116    d_1_i/rst_100/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/slowest_sync_clk
    SLICE_X69Y105        FDRE                                         r  d_1_i/rst_100/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[1]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc0_supplies_up_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.941ns  (logic 0.000ns (0.000%)  route 1.941ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.164ns (routing 0.598ns, distribution 1.566ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[1]
                         net (fo=2, routed)           1.941     1.941    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc0_supplies_up_i/src_in
    SLICE_X115Y179       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc0_supplies_up_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.164     2.346    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc0_supplies_up_i/dest_clk
    SLICE_X115Y179       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc0_supplies_up_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_ADC0[14]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc00_data_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.934ns  (logic 0.000ns (0.000%)  route 1.934ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.153ns (routing 0.598ns, distribution 1.555ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_ADC0[14]
                         net (fo=1, routed)           1.934     1.934    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc00_data_irq/src_in
    SLICE_X116Y198       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc00_data_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.153     2.335    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc00_data_irq/dest_clk
    SLICE_X116Y198       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc00_data_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_ADC1[15]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc01_fifo_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.924ns  (logic 0.000ns (0.000%)  route 1.924ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.146ns (routing 0.598ns, distribution 1.548ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_ADC1[15]
                         net (fo=1, routed)           1.924     1.924    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc01_fifo_irq/src_in
    SLICE_X114Y199       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc01_fifo_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.146     2.328    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc01_fifo_irq/dest_clk
    SLICE_X114Y199       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc01_fifo_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_ADC1[3]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc01_over_range/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.867ns  (logic 0.000ns (0.000%)  route 1.867ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.157ns (routing 0.598ns, distribution 1.559ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_ADC1[3]
                         net (fo=1, routed)           1.867     1.867    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc01_over_range/src_in
    SLICE_X115Y202       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc01_over_range/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.157     2.339    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc01_over_range/dest_clk
    SLICE_X115Y202       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc01_over_range/syncstages_ff_reg[0]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_ADC3[3]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc33_over_range/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.160ns  (logic 0.000ns (0.000%)  route 0.160ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.477ns (routing 0.404ns, distribution 1.073ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_ADC3[3]
                         net (fo=1, routed)           0.160     0.160    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc33_over_range/src_in
    SLICE_X116Y232       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc33_over_range/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.477     1.624    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc33_over_range/dest_clk
    SLICE_X116Y232       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc33_over_range/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_ADC3[15]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc33_fifo_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.174ns  (logic 0.000ns (0.000%)  route 0.174ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.478ns (routing 0.404ns, distribution 1.074ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_ADC3[15]
                         net (fo=1, routed)           0.174     0.174    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc33_fifo_irq/src_in
    SLICE_X116Y237       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc33_fifo_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.478     1.625    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc33_fifo_irq/dest_clk
    SLICE_X116Y237       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc33_fifo_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_DAC0[14]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac00_data_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.182ns  (logic 0.000ns (0.000%)  route 0.182ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.515ns (routing 0.404ns, distribution 1.111ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_DAC0[14]
                         net (fo=1, routed)           0.182     0.182    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac00_data_irq/src_in
    SLICE_X116Y248       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac00_data_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.515     1.662    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac00_data_irq/dest_clk
    SLICE_X116Y248       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac00_data_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_ADC2[15]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc32_fifo_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.186ns  (logic 0.000ns (0.000%)  route 0.186ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.485ns (routing 0.404ns, distribution 1.081ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_ADC2[15]
                         net (fo=1, routed)           0.186     0.186    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc32_fifo_irq/src_in
    SLICE_X116Y228       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc32_fifo_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.485     1.632    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc32_fifo_irq/dest_clk
    SLICE_X116Y228       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc32_fifo_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_ADC2[14]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc32_data_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.193ns  (logic 0.000ns (0.000%)  route 0.193ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.488ns (routing 0.404ns, distribution 1.084ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_ADC2[14]
                         net (fo=1, routed)           0.193     0.193    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc32_data_irq/src_in
    SLICE_X115Y227       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc32_data_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.488     1.635    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc32_data_irq/dest_clk
    SLICE_X115Y227       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc32_data_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_ADC1[15]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc31_fifo_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.202ns  (logic 0.000ns (0.000%)  route 0.202ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.476ns (routing 0.404ns, distribution 1.072ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_ADC1[15]
                         net (fo=1, routed)           0.202     0.202    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc31_fifo_irq/src_in
    SLICE_X117Y216       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc31_fifo_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.476     1.623    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc31_fifo_irq/dest_clk
    SLICE_X117Y216       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc31_fifo_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_ADC3[14]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc33_data_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.219ns  (logic 0.000ns (0.000%)  route 0.219ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.485ns (routing 0.404ns, distribution 1.081ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_ADC3[14]
                         net (fo=1, routed)           0.219     0.219    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc33_data_irq/src_in
    SLICE_X115Y236       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc33_data_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.485     1.632    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc33_data_irq/dest_clk
    SLICE_X115Y236       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc33_data_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_ADC3[14]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc23_data_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.223ns  (logic 0.000ns (0.000%)  route 0.223ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.481ns (routing 0.404ns, distribution 1.077ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_ADC3[14]
                         net (fo=1, routed)           0.223     0.223    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc23_data_irq/src_in
    SLICE_X116Y180       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc23_data_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.481     1.628    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc23_data_irq/dest_clk
    SLICE_X116Y180       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc23_data_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_ADC1[14]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc31_data_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.223ns  (logic 0.000ns (0.000%)  route 0.223ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.475ns (routing 0.404ns, distribution 1.071ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_ADC1[14]
                         net (fo=1, routed)           0.223     0.223    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc31_data_irq/src_in
    SLICE_X118Y218       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc31_data_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.475     1.622    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc31_data_irq/dest_clk
    SLICE_X118Y218       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc31_data_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_DAC1[15]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac01_fifo_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.225ns  (logic 0.000ns (0.000%)  route 0.225ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.511ns (routing 0.404ns, distribution 1.107ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_DAC1[15]
                         net (fo=1, routed)           0.225     0.225    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac01_fifo_irq/src_in
    SLICE_X113Y262       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac01_fifo_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.511     1.658    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac01_fifo_irq/dest_clk
    SLICE_X113Y262       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac01_fifo_irq/syncstages_ff_reg[0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFADC0_CLK
  To Clock:  clk_pl_0

Max Delay             8 Endpoints
Min Delay             8 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.161ns  (logic 1.066ns (25.619%)  route 3.095ns (74.381%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        2.338ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.338ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.156ns (routing 0.598ns, distribution 1.558ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[15])
                                                      0.525     0.525 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[15]
                         net (fo=1, routed)           2.209     2.734    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[15]
    SLICE_X113Y214       LUT6 (Prop_C6LUT_SLICEM_I2_O)
                                                      0.098     2.832 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_36/O
                         net (fo=1, routed)           0.168     3.000    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_36_n_0
    SLICE_X112Y215       LUT6 (Prop_G6LUT_SLICEM_I5_O)
                                                      0.150     3.150 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_15/O
                         net (fo=1, routed)           0.366     3.516    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_15_n_0
    SLICE_X115Y215       LUT6 (Prop_F6LUT_SLICEM_I1_O)
                                                      0.148     3.664 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_4/O
                         net (fo=1, routed)           0.280     3.944    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_4_n_0
    SLICE_X115Y224       LUT6 (Prop_D6LUT_SLICEM_I2_O)
                                                      0.145     4.089 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.072     4.161    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X115Y224       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.156     2.338    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X115Y224       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.752ns  (logic 0.984ns (26.226%)  route 2.768ns (73.774%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        2.338ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.338ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.156ns (routing 0.598ns, distribution 1.558ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[14])
                                                      0.698     0.698 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[14]
                         net (fo=1, routed)           2.052     2.750    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[14]
    SLICE_X114Y215       LUT6 (Prop_C6LUT_SLICEL_I2_O)
                                                      0.123     2.873 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_35/O
                         net (fo=1, routed)           0.041     2.914    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_35_n_0
    SLICE_X114Y215       LUT6 (Prop_D6LUT_SLICEL_I5_O)
                                                      0.036     2.950 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_17/O
                         net (fo=1, routed)           0.088     3.038    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_17_n_0
    SLICE_X115Y215       LUT6 (Prop_G6LUT_SLICEM_I3_O)
                                                      0.090     3.128 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_5/O
                         net (fo=1, routed)           0.521     3.649    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_5_n_0
    SLICE_X113Y237       LUT6 (Prop_C6LUT_SLICEM_I3_O)
                                                      0.037     3.686 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.066     3.752    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X113Y237       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.156     2.338    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y237       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.752ns  (logic 0.829ns (22.095%)  route 2.923ns (77.905%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        2.331ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.331ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.149ns (routing 0.598ns, distribution 1.551ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[9])
                                                      0.532     0.532 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[9]
                         net (fo=1, routed)           2.531     3.063    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[9]
    SLICE_X114Y218       LUT6 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.050     3.113 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_12/O
                         net (fo=1, routed)           0.044     3.157    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_12_n_0
    SLICE_X114Y218       LUT6 (Prop_F6LUT_SLICEL_I2_O)
                                                      0.097     3.254 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_3/O
                         net (fo=1, routed)           0.289     3.543    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_3_n_0
    SLICE_X113Y223       LUT6 (Prop_G6LUT_SLICEM_I1_O)
                                                      0.150     3.693 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.059     3.752    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    SLICE_X113Y223       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.149     2.331    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y223       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.476ns  (logic 1.055ns (30.351%)  route 2.421ns (69.649%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        2.338ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.338ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.156ns (routing 0.598ns, distribution 1.558ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[13])
                                                      0.771     0.771 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[13]
                         net (fo=1, routed)           1.981     2.752    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[13]
    SLICE_X115Y217       LUT6 (Prop_F6LUT_SLICEM_I0_O)
                                                      0.123     2.875 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_17/O
                         net (fo=1, routed)           0.095     2.970    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_17_n_0
    SLICE_X114Y217       LUT6 (Prop_H6LUT_SLICEL_I1_O)
                                                      0.124     3.094 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_4/O
                         net (fo=1, routed)           0.273     3.367    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_4_n_0
    SLICE_X113Y225       LUT6 (Prop_D6LUT_SLICEM_I2_O)
                                                      0.037     3.404 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.072     3.476    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X113Y225       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.156     2.338    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y225       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.440ns  (logic 0.812ns (23.605%)  route 2.628ns (76.395%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        2.333ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.333ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.151ns (routing 0.598ns, distribution 1.553ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[10])
                                                      0.536     0.536 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[10]
                         net (fo=1, routed)           2.246     2.782    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[10]
    SLICE_X115Y215       LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.088     2.870 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_7/O
                         net (fo=1, routed)           0.123     2.993    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_7_n_0
    SLICE_X115Y215       LUT6 (Prop_H6LUT_SLICEM_I3_O)
                                                      0.152     3.145 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_2/O
                         net (fo=1, routed)           0.210     3.355    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_2_n_0
    SLICE_X114Y222       LUT5 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.036     3.391 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.049     3.440    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X114Y222       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.151     2.333    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X114Y222       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.304ns  (logic 0.891ns (26.967%)  route 2.413ns (73.033%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        2.343ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.343ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.161ns (routing 0.598ns, distribution 1.563ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[12])
                                                      0.611     0.611 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[12]
                         net (fo=1, routed)           1.971     2.582    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[12]
    SLICE_X114Y218       LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.036     2.618 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_13/O
                         net (fo=1, routed)           0.043     2.661    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_13_n_0
    SLICE_X114Y218       LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.099     2.760 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_4/O
                         net (fo=1, routed)           0.333     3.093    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_4_n_0
    SLICE_X113Y227       LUT6 (Prop_C6LUT_SLICEM_I2_O)
                                                      0.145     3.238 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.066     3.304    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X113Y227       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.161     2.343    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y227       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.263ns  (logic 0.966ns (29.605%)  route 2.297ns (70.395%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        2.329ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.329ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.147ns (routing 0.598ns, distribution 1.549ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[8])
                                                      0.788     0.788 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[8]
                         net (fo=1, routed)           1.854     2.642    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[8]
    SLICE_X115Y216       LUT6 (Prop_H6LUT_SLICEM_I3_O)
                                                      0.090     2.732 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_13/O
                         net (fo=1, routed)           0.042     2.774    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_13_n_0
    SLICE_X115Y216       LUT6 (Prop_G6LUT_SLICEM_I2_O)
                                                      0.037     2.811 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_3/O
                         net (fo=1, routed)           0.329     3.140    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_3_n_0
    SLICE_X113Y226       LUT6 (Prop_D6LUT_SLICEM_I1_O)
                                                      0.051     3.191 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.072     3.263    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    SLICE_X113Y226       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.147     2.329    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y226       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.019ns  (logic 0.899ns (29.778%)  route 2.120ns (70.222%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        2.331ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.331ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.149ns (routing 0.598ns, distribution 1.551ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[11])
                                                      0.588     0.588 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[11]
                         net (fo=1, routed)           1.737     2.325    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[11]
    SLICE_X114Y217       LUT6 (Prop_C6LUT_SLICEL_I1_O)
                                                      0.123     2.448 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_9/O
                         net (fo=1, routed)           0.041     2.489    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_9_n_0
    SLICE_X114Y217       LUT6 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.036     2.525 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_2/O
                         net (fo=1, routed)           0.284     2.809    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_2_n_0
    SLICE_X113Y223       LUT6 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.152     2.961 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.058     3.019    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X113Y223       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.149     2.331    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y223       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.452ns  (logic 0.308ns (21.212%)  route 1.144ns (78.788%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        1.622ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.622ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.475ns (routing 0.404ns, distribution 1.071ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[8])
                                                      0.237     0.237 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[8]
                         net (fo=1, routed)           0.927     1.164    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[8]
    SLICE_X115Y216       LUT6 (Prop_H6LUT_SLICEM_I3_O)
                                                      0.035     1.199 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_13/O
                         net (fo=1, routed)           0.024     1.223    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_13_n_0
    SLICE_X115Y216       LUT6 (Prop_G6LUT_SLICEM_I2_O)
                                                      0.014     1.237 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_3/O
                         net (fo=1, routed)           0.167     1.404    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_3_n_0
    SLICE_X113Y226       LUT6 (Prop_D6LUT_SLICEM_I1_O)
                                                      0.022     1.426 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.026     1.452    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    SLICE_X113Y226       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.475     1.622    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y226       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.453ns  (logic 0.390ns (26.841%)  route 1.063ns (73.159%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        1.623ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.623ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.476ns (routing 0.404ns, distribution 1.072ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[11])
                                                      0.265     0.265 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[11]
                         net (fo=1, routed)           0.878     1.143    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[11]
    SLICE_X114Y217       LUT6 (Prop_C6LUT_SLICEL_I1_O)
                                                      0.050     1.193 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_9/O
                         net (fo=1, routed)           0.022     1.215    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_9_n_0
    SLICE_X114Y217       LUT6 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.014     1.229 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_2/O
                         net (fo=1, routed)           0.142     1.371    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_2_n_0
    SLICE_X113Y223       LUT6 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.061     1.432 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.021     1.453    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X113Y223       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.476     1.623    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y223       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.545ns  (logic 0.355ns (22.977%)  route 1.190ns (77.023%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        1.629ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.629ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.482ns (routing 0.404ns, distribution 1.078ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[13])
                                                      0.241     0.241 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[13]
                         net (fo=1, routed)           0.977     1.218    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[13]
    SLICE_X115Y217       LUT6 (Prop_F6LUT_SLICEM_I0_O)
                                                      0.050     1.268 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_17/O
                         net (fo=1, routed)           0.050     1.318    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_17_n_0
    SLICE_X114Y217       LUT6 (Prop_H6LUT_SLICEL_I1_O)
                                                      0.050     1.368 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_4/O
                         net (fo=1, routed)           0.137     1.505    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_4_n_0
    SLICE_X113Y225       LUT6 (Prop_D6LUT_SLICEM_I2_O)
                                                      0.014     1.519 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.026     1.545    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X113Y225       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.482     1.629    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y225       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.604ns  (logic 0.388ns (24.190%)  route 1.216ns (75.810%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        1.635ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.635ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.488ns (routing 0.404ns, distribution 1.084ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[12])
                                                      0.274     0.274 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[12]
                         net (fo=1, routed)           1.002     1.276    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[12]
    SLICE_X114Y218       LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.014     1.290 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_13/O
                         net (fo=1, routed)           0.023     1.313    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_13_n_0
    SLICE_X114Y218       LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.041     1.354 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_4/O
                         net (fo=1, routed)           0.167     1.521    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_4_n_0
    SLICE_X113Y227       LUT6 (Prop_C6LUT_SLICEM_I2_O)
                                                      0.059     1.580 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.024     1.604    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X113Y227       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.488     1.635    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y227       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.671ns  (logic 0.337ns (20.168%)  route 1.334ns (79.832%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        1.625ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.625ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.478ns (routing 0.404ns, distribution 1.074ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[10])
                                                      0.227     0.227 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[10]
                         net (fo=1, routed)           1.147     1.374    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[10]
    SLICE_X115Y215       LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.035     1.409 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_7/O
                         net (fo=1, routed)           0.062     1.471    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_7_n_0
    SLICE_X115Y215       LUT6 (Prop_H6LUT_SLICEM_I3_O)
                                                      0.061     1.532 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_2/O
                         net (fo=1, routed)           0.109     1.641    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_2_n_0
    SLICE_X114Y222       LUT5 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.014     1.655 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.016     1.671    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X114Y222       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.478     1.625    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X114Y222       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.811ns  (logic 0.398ns (21.977%)  route 1.413ns (78.023%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        1.628ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.628ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.481ns (routing 0.404ns, distribution 1.077ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[14])
                                                      0.285     0.285 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[14]
                         net (fo=1, routed)           1.049     1.334    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[14]
    SLICE_X114Y215       LUT6 (Prop_C6LUT_SLICEL_I2_O)
                                                      0.050     1.384 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_35/O
                         net (fo=1, routed)           0.022     1.406    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_35_n_0
    SLICE_X114Y215       LUT6 (Prop_D6LUT_SLICEL_I5_O)
                                                      0.014     1.420 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_17/O
                         net (fo=1, routed)           0.049     1.469    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_17_n_0
    SLICE_X115Y215       LUT6 (Prop_G6LUT_SLICEM_I3_O)
                                                      0.035     1.504 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_5/O
                         net (fo=1, routed)           0.269     1.773    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_5_n_0
    SLICE_X113Y237       LUT6 (Prop_C6LUT_SLICEM_I3_O)
                                                      0.014     1.787 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.024     1.811    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X113Y237       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.481     1.628    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y237       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.837ns  (logic 0.350ns (19.053%)  route 1.487ns (80.947%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        1.623ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.623ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.476ns (routing 0.404ns, distribution 1.072ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[9])
                                                      0.228     0.228 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[9]
                         net (fo=1, routed)           1.296     1.524    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[9]
    SLICE_X114Y218       LUT6 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.022     1.546 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_12/O
                         net (fo=1, routed)           0.025     1.571    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_12_n_0
    SLICE_X114Y218       LUT6 (Prop_F6LUT_SLICEL_I2_O)
                                                      0.040     1.611 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_3/O
                         net (fo=1, routed)           0.145     1.756    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_3_n_0
    SLICE_X113Y223       LUT6 (Prop_G6LUT_SLICEM_I1_O)
                                                      0.060     1.816 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.021     1.837    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    SLICE_X113Y223       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.476     1.623    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y223       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        2.016ns  (logic 0.468ns (23.214%)  route 1.548ns (76.786%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        1.630ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.630ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.483ns (routing 0.404ns, distribution 1.079ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[15])
                                                      0.250     0.250 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[15]
                         net (fo=1, routed)           1.137     1.387    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[15]
    SLICE_X113Y214       LUT6 (Prop_C6LUT_SLICEM_I2_O)
                                                      0.040     1.427 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_36/O
                         net (fo=1, routed)           0.087     1.514    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_36_n_0
    SLICE_X112Y215       LUT6 (Prop_G6LUT_SLICEM_I5_O)
                                                      0.060     1.574 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_15/O
                         net (fo=1, routed)           0.158     1.732    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_15_n_0
    SLICE_X115Y215       LUT6 (Prop_F6LUT_SLICEM_I1_O)
                                                      0.059     1.791 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_4/O
                         net (fo=1, routed)           0.140     1.931    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_4_n_0
    SLICE_X115Y224       LUT6 (Prop_D6LUT_SLICEM_I2_O)
                                                      0.059     1.990 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.026     2.016    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X115Y224       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.483     1.630    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X115Y224       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFADC1_CLK
  To Clock:  clk_pl_0

Max Delay             8 Endpoints
Min Delay             8 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.313ns  (logic 1.124ns (33.927%)  route 2.189ns (66.073%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        2.329ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.329ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.147ns (routing 0.598ns, distribution 1.549ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[8])
                                                      0.788     0.788 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[8]
                         net (fo=1, routed)           1.731     2.519    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_23_0[8]
    SLICE_X114Y220       LUT5 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.123     2.642 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_26/O
                         net (fo=1, routed)           0.086     2.728    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_26_n_0
    SLICE_X114Y220       LUT6 (Prop_C6LUT_SLICEL_I5_O)
                                                      0.035     2.763 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_16/O
                         net (fo=1, routed)           0.041     2.804    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_16_n_0
    SLICE_X114Y220       LUT6 (Prop_B6LUT_SLICEL_I2_O)
                                                      0.090     2.894 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_4/O
                         net (fo=1, routed)           0.259     3.153    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_4_n_0
    SLICE_X113Y226       LUT6 (Prop_D6LUT_SLICEM_I2_O)
                                                      0.088     3.241 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.072     3.313    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    SLICE_X113Y226       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.147     2.329    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y226       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.229ns  (logic 0.957ns (29.638%)  route 2.272ns (70.362%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        2.331ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.331ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.149ns (routing 0.598ns, distribution 1.551ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[11])
                                                      0.588     0.588 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[11]
                         net (fo=1, routed)           1.787     2.375    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_23_0[11]
    SLICE_X115Y220       LUT5 (Prop_G6LUT_SLICEM_I4_O)
                                                      0.090     2.465 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_25/O
                         net (fo=1, routed)           0.175     2.640    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_25_n_0
    SLICE_X113Y220       LUT6 (Prop_B6LUT_SLICEM_I5_O)
                                                      0.125     2.765 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_13/O
                         net (fo=1, routed)           0.046     2.811    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_13_n_0
    SLICE_X113Y220       LUT6 (Prop_A6LUT_SLICEM_I2_O)
                                                      0.053     2.864 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_3/O
                         net (fo=1, routed)           0.206     3.070    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_3_n_0
    SLICE_X113Y223       LUT6 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.101     3.171 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.058     3.229    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X113Y223       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.149     2.331    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y223       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.111ns  (logic 0.982ns (31.565%)  route 2.129ns (68.435%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        2.338ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.338ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.156ns (routing 0.598ns, distribution 1.558ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[13])
                                                      0.771     0.771 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[13]
                         net (fo=1, routed)           1.847     2.618    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_23_0[13]
    SLICE_X113Y224       LUT5 (Prop_E6LUT_SLICEM_I4_O)
                                                      0.052     2.670 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_21/O
                         net (fo=1, routed)           0.040     2.710    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_21_n_0
    SLICE_X113Y224       LUT6 (Prop_C6LUT_SLICEM_I5_O)
                                                      0.037     2.747 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_5/O
                         net (fo=1, routed)           0.170     2.917    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_5_n_0
    SLICE_X113Y225       LUT6 (Prop_D6LUT_SLICEM_I3_O)
                                                      0.122     3.039 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.072     3.111    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X113Y225       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.156     2.338    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y225       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.096ns  (logic 0.941ns (30.394%)  route 2.155ns (69.606%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        2.338ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.338ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.156ns (routing 0.598ns, distribution 1.558ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[14])
                                                      0.698     0.698 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[14]
                         net (fo=1, routed)           1.571     2.269    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_23_0[14]
    SLICE_X110Y220       LUT6 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.100     2.369 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_41/O
                         net (fo=1, routed)           0.048     2.417    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_41_n_0
    SLICE_X110Y220       LUT6 (Prop_H6LUT_SLICEM_I3_O)
                                                      0.053     2.470 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_20/O
                         net (fo=1, routed)           0.102     2.572    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_20_n_0
    SLICE_X112Y220       LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                      0.039     2.611 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6/O
                         net (fo=1, routed)           0.368     2.979    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6_n_0
    SLICE_X113Y237       LUT6 (Prop_C6LUT_SLICEM_I5_O)
                                                      0.051     3.030 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.066     3.096    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X113Y237       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.156     2.338    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y237       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.015ns  (logic 0.828ns (27.463%)  route 2.187ns (72.537%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        2.338ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.338ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.156ns (routing 0.598ns, distribution 1.558ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[15])
                                                      0.525     0.525 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[15]
                         net (fo=1, routed)           1.588     2.113    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_23_0[15]
    SLICE_X112Y222       LUT6 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.125     2.238 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_52/O
                         net (fo=1, routed)           0.042     2.280    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_52_n_0
    SLICE_X112Y222       LUT5 (Prop_G6LUT_SLICEM_I2_O)
                                                      0.037     2.317 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_23/O
                         net (fo=1, routed)           0.206     2.523    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_23_n_0
    SLICE_X113Y218       LUT6 (Prop_G6LUT_SLICEM_I3_O)
                                                      0.090     2.613 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_5/O
                         net (fo=1, routed)           0.279     2.892    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_5_n_0
    SLICE_X115Y224       LUT6 (Prop_D6LUT_SLICEM_I4_O)
                                                      0.051     2.943 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.072     3.015    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X115Y224       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.156     2.338    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X115Y224       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.879ns  (logic 0.921ns (31.990%)  route 1.958ns (68.010%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        2.331ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.331ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.149ns (routing 0.598ns, distribution 1.551ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[9])
                                                      0.532     0.532 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[9]
                         net (fo=1, routed)           1.511     2.043    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_23_0[9]
    SLICE_X115Y219       LUT5 (Prop_B6LUT_SLICEM_I4_O)
                                                      0.100     2.143 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_23/O
                         net (fo=1, routed)           0.045     2.188    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_23_n_0
    SLICE_X115Y219       LUT6 (Prop_G6LUT_SLICEM_I5_O)
                                                      0.100     2.288 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_15/O
                         net (fo=1, routed)           0.144     2.432    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_15_n_0
    SLICE_X115Y220       LUT6 (Prop_D6LUT_SLICEM_I2_O)
                                                      0.099     2.531 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_4/O
                         net (fo=1, routed)           0.199     2.730    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_4_n_0
    SLICE_X113Y223       LUT6 (Prop_G6LUT_SLICEM_I2_O)
                                                      0.090     2.820 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.059     2.879    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    SLICE_X113Y223       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.149     2.331    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y223       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.686ns  (logic 0.884ns (32.911%)  route 1.802ns (67.089%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        2.343ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.343ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.161ns (routing 0.598ns, distribution 1.563ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[12])
                                                      0.611     0.611 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[12]
                         net (fo=1, routed)           1.356     1.967    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_23_0[12]
    SLICE_X114Y220       LUT5 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.099     2.066 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_14/O
                         net (fo=1, routed)           0.288     2.354    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_14_n_0
    SLICE_X113Y227       LUT6 (Prop_G6LUT_SLICEM_I5_O)
                                                      0.123     2.477 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_5/O
                         net (fo=1, routed)           0.092     2.569    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_5_n_0
    SLICE_X113Y227       LUT6 (Prop_C6LUT_SLICEM_I3_O)
                                                      0.051     2.620 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.066     2.686    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X113Y227       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.161     2.343    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y227       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.591ns  (logic 0.758ns (29.255%)  route 1.833ns (70.745%))
  Logic Levels:           3  (LUT5=2 LUT6=1)
  Clock Path Skew:        2.333ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.333ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.151ns (routing 0.598ns, distribution 1.553ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[10])
                                                      0.536     0.536 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[10]
                         net (fo=1, routed)           1.662     2.198    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_23_0[10]
    SLICE_X114Y221       LUT5 (Prop_A6LUT_SLICEL_I4_O)
                                                      0.098     2.296 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_10/O
                         net (fo=1, routed)           0.040     2.336    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_10_n_0
    SLICE_X114Y221       LUT6 (Prop_C6LUT_SLICEL_I2_O)
                                                      0.035     2.371 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_3/O
                         net (fo=1, routed)           0.082     2.453    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_3_n_0
    SLICE_X114Y222       LUT5 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.089     2.542 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.049     2.591    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X114Y222       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.151     2.333    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X114Y222       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.246ns  (logic 0.317ns (25.441%)  route 0.929ns (74.559%))
  Logic Levels:           3  (LUT5=2 LUT6=1)
  Clock Path Skew:        1.625ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.625ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.478ns (routing 0.404ns, distribution 1.074ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[10])
                                                      0.227     0.227 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[10]
                         net (fo=1, routed)           0.843     1.070    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_23_0[10]
    SLICE_X114Y221       LUT5 (Prop_A6LUT_SLICEL_I4_O)
                                                      0.041     1.111 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_10/O
                         net (fo=1, routed)           0.024     1.135    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_10_n_0
    SLICE_X114Y221       LUT6 (Prop_C6LUT_SLICEL_I2_O)
                                                      0.014     1.149 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_3/O
                         net (fo=1, routed)           0.046     1.195    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_3_n_0
    SLICE_X114Y222       LUT5 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.035     1.230 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.016     1.246    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X114Y222       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.478     1.625    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X114Y222       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.278ns  (logic 0.387ns (30.282%)  route 0.891ns (69.718%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        1.635ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.635ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.488ns (routing 0.404ns, distribution 1.084ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[12])
                                                      0.274     0.274 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[12]
                         net (fo=1, routed)           0.676     0.950    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_23_0[12]
    SLICE_X114Y220       LUT5 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.041     0.991 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_14/O
                         net (fo=1, routed)           0.146     1.137    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_14_n_0
    SLICE_X113Y227       LUT6 (Prop_G6LUT_SLICEM_I5_O)
                                                      0.050     1.187 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_5/O
                         net (fo=1, routed)           0.045     1.232    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_5_n_0
    SLICE_X113Y227       LUT6 (Prop_C6LUT_SLICEM_I3_O)
                                                      0.022     1.254 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.024     1.278    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X113Y227       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.488     1.635    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y227       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.362ns  (logic 0.385ns (28.267%)  route 0.977ns (71.733%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.623ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.623ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.476ns (routing 0.404ns, distribution 1.072ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[9])
                                                      0.228     0.228 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[9]
                         net (fo=1, routed)           0.761     0.989    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_23_0[9]
    SLICE_X115Y219       LUT5 (Prop_B6LUT_SLICEM_I4_O)
                                                      0.041     1.030 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_23/O
                         net (fo=1, routed)           0.025     1.055    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_23_n_0
    SLICE_X115Y219       LUT6 (Prop_G6LUT_SLICEM_I5_O)
                                                      0.040     1.095 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_15/O
                         net (fo=1, routed)           0.069     1.164    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_15_n_0
    SLICE_X115Y220       LUT6 (Prop_D6LUT_SLICEM_I2_O)
                                                      0.041     1.205 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_4/O
                         net (fo=1, routed)           0.101     1.306    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_4_n_0
    SLICE_X113Y223       LUT6 (Prop_G6LUT_SLICEM_I2_O)
                                                      0.035     1.341 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.021     1.362    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    SLICE_X113Y223       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.476     1.623    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y223       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.398ns  (logic 0.327ns (23.391%)  route 1.071ns (76.609%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        1.629ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.629ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.482ns (routing 0.404ns, distribution 1.078ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[13])
                                                      0.241     0.241 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[13]
                         net (fo=1, routed)           0.936     1.177    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_23_0[13]
    SLICE_X113Y224       LUT5 (Prop_E6LUT_SLICEM_I4_O)
                                                      0.022     1.199 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_21/O
                         net (fo=1, routed)           0.024     1.223    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_21_n_0
    SLICE_X113Y224       LUT6 (Prop_C6LUT_SLICEM_I5_O)
                                                      0.014     1.237 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_5/O
                         net (fo=1, routed)           0.085     1.322    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_5_n_0
    SLICE_X113Y225       LUT6 (Prop_D6LUT_SLICEM_I3_O)
                                                      0.050     1.372 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.026     1.398    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X113Y225       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.482     1.629    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y225       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.467ns  (logic 0.372ns (25.358%)  route 1.095ns (74.642%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.630ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.630ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.483ns (routing 0.404ns, distribution 1.079ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[15])
                                                      0.250     0.250 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[15]
                         net (fo=1, routed)           0.796     1.046    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_23_0[15]
    SLICE_X112Y222       LUT6 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.051     1.097 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_52/O
                         net (fo=1, routed)           0.024     1.121    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_52_n_0
    SLICE_X112Y222       LUT5 (Prop_G6LUT_SLICEM_I2_O)
                                                      0.014     1.135 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_23/O
                         net (fo=1, routed)           0.108     1.243    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_23_n_0
    SLICE_X113Y218       LUT6 (Prop_G6LUT_SLICEM_I3_O)
                                                      0.035     1.278 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_5/O
                         net (fo=1, routed)           0.141     1.419    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_5_n_0
    SLICE_X115Y224       LUT6 (Prop_D6LUT_SLICEM_I4_O)
                                                      0.022     1.441 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.026     1.467    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X115Y224       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.483     1.630    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X115Y224       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.476ns  (logic 0.385ns (26.084%)  route 1.091ns (73.916%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        1.628ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.628ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.481ns (routing 0.404ns, distribution 1.077ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[14])
                                                      0.285     0.285 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[14]
                         net (fo=1, routed)           0.796     1.081    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_23_0[14]
    SLICE_X110Y220       LUT6 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.040     1.121 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_41/O
                         net (fo=1, routed)           0.027     1.148    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_41_n_0
    SLICE_X110Y220       LUT6 (Prop_H6LUT_SLICEM_I3_O)
                                                      0.023     1.171 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_20/O
                         net (fo=1, routed)           0.054     1.225    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_20_n_0
    SLICE_X112Y220       LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                      0.015     1.240 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6/O
                         net (fo=1, routed)           0.190     1.430    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6_n_0
    SLICE_X113Y237       LUT6 (Prop_C6LUT_SLICEM_I5_O)
                                                      0.022     1.452 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.024     1.476    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X113Y237       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.481     1.628    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y237       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.480ns  (logic 0.372ns (25.135%)  route 1.108ns (74.865%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.622ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.622ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.475ns (routing 0.404ns, distribution 1.071ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[8])
                                                      0.237     0.237 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[8]
                         net (fo=1, routed)           0.888     1.125    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_23_0[8]
    SLICE_X114Y220       LUT5 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.050     1.175 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_26/O
                         net (fo=1, routed)           0.043     1.218    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_26_n_0
    SLICE_X114Y220       LUT6 (Prop_C6LUT_SLICEL_I5_O)
                                                      0.014     1.232 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_16/O
                         net (fo=1, routed)           0.022     1.254    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_16_n_0
    SLICE_X114Y220       LUT6 (Prop_B6LUT_SLICEL_I2_O)
                                                      0.036     1.290 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_4/O
                         net (fo=1, routed)           0.129     1.419    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_4_n_0
    SLICE_X113Y226       LUT6 (Prop_D6LUT_SLICEM_I2_O)
                                                      0.035     1.454 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.026     1.480    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    SLICE_X113Y226       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.475     1.622    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y226       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.556ns  (logic 0.414ns (26.607%)  route 1.142ns (73.393%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.623ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.623ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.476ns (routing 0.404ns, distribution 1.072ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[11])
                                                      0.265     0.265 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[11]
                         net (fo=1, routed)           0.903     1.168    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_23_0[11]
    SLICE_X115Y220       LUT5 (Prop_G6LUT_SLICEM_I4_O)
                                                      0.035     1.203 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_25/O
                         net (fo=1, routed)           0.087     1.290    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_25_n_0
    SLICE_X113Y220       LUT6 (Prop_B6LUT_SLICEM_I5_O)
                                                      0.050     1.340 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_13/O
                         net (fo=1, routed)           0.025     1.365    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_13_n_0
    SLICE_X113Y220       LUT6 (Prop_A6LUT_SLICEM_I2_O)
                                                      0.023     1.388 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_3/O
                         net (fo=1, routed)           0.106     1.494    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_3_n_0
    SLICE_X113Y223       LUT6 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.041     1.535 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.021     1.556    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X113Y223       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.476     1.623    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y223       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFADC2_CLK
  To Clock:  clk_pl_0

Max Delay             8 Endpoints
Min Delay             8 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.220ns  (logic 1.011ns (31.398%)  route 2.209ns (68.602%))
  Logic Levels:           5  (LUT5=2 LUT6=3)
  Clock Path Skew:        2.333ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.333ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.151ns (routing 0.598ns, distribution 1.553ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[10])
                                                      0.536     0.536 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[10]
                         net (fo=1, routed)           1.119     1.655    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_22_1[10]
    SLICE_X107Y218       LUT5 (Prop_B6LUT_SLICEM_I3_O)
                                                      0.089     1.744 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_29/O
                         net (fo=1, routed)           0.096     1.840    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_29_n_0
    SLICE_X107Y218       LUT6 (Prop_D6LUT_SLICEM_I5_O)
                                                      0.088     1.928 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_24/O
                         net (fo=1, routed)           0.539     2.467    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_24_n_0
    SLICE_X112Y215       LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.125     2.592 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_16/O
                         net (fo=1, routed)           0.317     2.909    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_16_n_0
    SLICE_X114Y222       LUT6 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.123     3.032 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_4/O
                         net (fo=1, routed)           0.089     3.121    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_4_n_0
    SLICE_X114Y222       LUT5 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.050     3.171 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.049     3.220    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X114Y222       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.151     2.333    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X114Y222       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.202ns  (logic 0.942ns (29.419%)  route 2.260ns (70.581%))
  Logic Levels:           5  (LUT5=2 LUT6=3)
  Clock Path Skew:        2.331ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.331ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.149ns (routing 0.598ns, distribution 1.551ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[9])
                                                      0.532     0.532 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[9]
                         net (fo=1, routed)           1.287     1.819    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_22_1[9]
    SLICE_X107Y216       LUT5 (Prop_E6LUT_SLICEM_I3_O)
                                                      0.148     1.967 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_29/O
                         net (fo=1, routed)           0.040     2.007    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_29_n_0
    SLICE_X107Y216       LUT6 (Prop_C6LUT_SLICEM_I5_O)
                                                      0.037     2.044 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_26/O
                         net (fo=1, routed)           0.518     2.562    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_26_n_0
    SLICE_X112Y215       LUT5 (Prop_F6LUT_SLICEM_I1_O)
                                                      0.088     2.650 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_18/O
                         net (fo=1, routed)           0.314     2.964    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_18_n_0
    SLICE_X113Y223       LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.037     3.001 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_6/O
                         net (fo=1, routed)           0.042     3.043    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_6_n_0
    SLICE_X113Y223       LUT6 (Prop_G6LUT_SLICEM_I4_O)
                                                      0.100     3.143 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.059     3.202    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    SLICE_X113Y223       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.149     2.331    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y223       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.189ns  (logic 1.128ns (35.372%)  route 2.061ns (64.628%))
  Logic Levels:           5  (LUT5=1 LUT6=4)
  Clock Path Skew:        2.338ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.338ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.156ns (routing 0.598ns, distribution 1.558ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[14])
                                                      0.698     0.698 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[14]
                         net (fo=1, routed)           1.182     1.880    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_22_1[14]
    SLICE_X109Y214       LUT6 (Prop_G6LUT_SLICEM_I2_O)
                                                      0.150     2.030 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_63/O
                         net (fo=1, routed)           0.048     2.078    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_63_n_0
    SLICE_X109Y214       LUT5 (Prop_H6LUT_SLICEM_I2_O)
                                                      0.053     2.131 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_46/O
                         net (fo=1, routed)           0.162     2.293    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_46_n_0
    SLICE_X110Y212       LUT6 (Prop_G6LUT_SLICEM_I5_O)
                                                      0.123     2.416 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_21/O
                         net (fo=1, routed)           0.235     2.651    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_21_n_0
    SLICE_X112Y220       LUT6 (Prop_H6LUT_SLICEM_I3_O)
                                                      0.053     2.704 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6/O
                         net (fo=1, routed)           0.368     3.072    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6_n_0
    SLICE_X113Y237       LUT6 (Prop_C6LUT_SLICEM_I5_O)
                                                      0.051     3.123 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.066     3.189    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X113Y237       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.156     2.338    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y237       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.082ns  (logic 1.061ns (34.426%)  route 2.021ns (65.574%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        2.338ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.338ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.156ns (routing 0.598ns, distribution 1.558ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[13])
                                                      0.771     0.771 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[13]
                         net (fo=1, routed)           1.056     1.827    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_22_1[13]
    SLICE_X107Y216       LUT5 (Prop_F6LUT_SLICEM_I3_O)
                                                      0.088     1.915 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_60/O
                         net (fo=1, routed)           0.086     2.001    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_60_n_0
    SLICE_X107Y216       LUT6 (Prop_D6LUT_SLICEM_I5_O)
                                                      0.051     2.052 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_27/O
                         net (fo=1, routed)           0.511     2.563    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_27_n_0
    SLICE_X112Y217       LUT6 (Prop_B6LUT_SLICEM_I0_O)
                                                      0.100     2.663 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_7/O
                         net (fo=1, routed)           0.296     2.959    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_7_n_0
    SLICE_X113Y225       LUT6 (Prop_D6LUT_SLICEM_I5_O)
                                                      0.051     3.010 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.072     3.082    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X113Y225       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.156     2.338    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y225       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.046ns  (logic 0.862ns (28.299%)  route 2.184ns (71.701%))
  Logic Levels:           5  (LUT5=2 LUT6=3)
  Clock Path Skew:        2.331ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.331ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.149ns (routing 0.598ns, distribution 1.551ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[11])
                                                      0.588     0.588 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[11]
                         net (fo=1, routed)           1.114     1.702    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_22_1[11]
    SLICE_X106Y216       LUT5 (Prop_B6LUT_SLICEL_I3_O)
                                                      0.036     1.738 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_41/O
                         net (fo=1, routed)           0.090     1.828    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_41_n_0
    SLICE_X106Y216       LUT6 (Prop_D6LUT_SLICEL_I5_O)
                                                      0.050     1.878 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_31/O
                         net (fo=1, routed)           0.576     2.454    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_31_n_0
    SLICE_X112Y215       LUT5 (Prop_B6LUT_SLICEM_I1_O)
                                                      0.037     2.491 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_19/O
                         net (fo=1, routed)           0.302     2.793    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_19_n_0
    SLICE_X113Y223       LUT6 (Prop_F6LUT_SLICEM_I0_O)
                                                      0.098     2.891 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_5/O
                         net (fo=1, routed)           0.044     2.935    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_5_n_0
    SLICE_X113Y223       LUT6 (Prop_H6LUT_SLICEM_I3_O)
                                                      0.053     2.988 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.058     3.046    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X113Y223       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.149     2.331    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y223       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.837ns  (logic 1.206ns (42.510%)  route 1.631ns (57.490%))
  Logic Levels:           5  (LUT5=2 LUT6=3)
  Clock Path Skew:        2.329ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.329ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.147ns (routing 0.598ns, distribution 1.549ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[8])
                                                      0.788     0.788 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[8]
                         net (fo=1, routed)           1.002     1.790    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_22_1[8]
    SLICE_X108Y215       LUT5 (Prop_A6LUT_SLICEL_I3_O)
                                                      0.050     1.840 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_31/O
                         net (fo=1, routed)           0.098     1.938    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_31_n_0
    SLICE_X108Y215       LUT6 (Prop_C6LUT_SLICEL_I5_O)
                                                      0.088     2.026 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_29/O
                         net (fo=1, routed)           0.152     2.178    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_29_n_0
    SLICE_X110Y215       LUT5 (Prop_C6LUT_SLICEM_I1_O)
                                                      0.098     2.276 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_19/O
                         net (fo=1, routed)           0.040     2.316    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_19_n_0
    SLICE_X110Y215       LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.037     2.353 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_6/O
                         net (fo=1, routed)           0.267     2.620    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_6_n_0
    SLICE_X113Y226       LUT6 (Prop_D6LUT_SLICEM_I4_O)
                                                      0.145     2.765 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.072     2.837    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    SLICE_X113Y226       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.147     2.329    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y226       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.666ns  (logic 0.881ns (33.046%)  route 1.785ns (66.954%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        2.343ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.343ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.161ns (routing 0.598ns, distribution 1.563ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[12])
                                                      0.611     0.611 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[12]
                         net (fo=1, routed)           0.964     1.575    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_22_1[12]
    SLICE_X108Y215       LUT5 (Prop_B6LUT_SLICEL_I3_O)
                                                      0.036     1.611 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_20/O
                         net (fo=1, routed)           0.105     1.716    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_20_n_0
    SLICE_X108Y215       LUT6 (Prop_D6LUT_SLICEL_I5_O)
                                                      0.146     1.862 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_15/O
                         net (fo=1, routed)           0.255     2.117    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_15_n_0
    SLICE_X112Y217       LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.051     2.168 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_6/O
                         net (fo=1, routed)           0.395     2.563    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_6_n_0
    SLICE_X113Y227       LUT6 (Prop_C6LUT_SLICEM_I5_O)
                                                      0.037     2.600 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.066     2.666    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X113Y227       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.161     2.343    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y227       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.447ns  (logic 0.876ns (35.799%)  route 1.571ns (64.201%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        2.338ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.338ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.156ns (routing 0.598ns, distribution 1.558ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[15])
                                                      0.525     0.525 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[15]
                         net (fo=1, routed)           0.892     1.417    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_22_1[15]
    SLICE_X109Y215       LUT6 (Prop_H6LUT_SLICEM_I5_O)
                                                      0.125     1.542 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_47/O
                         net (fo=1, routed)           0.040     1.582    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_47_n_0
    SLICE_X109Y215       LUT5 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.052     1.634 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_22/O
                         net (fo=1, routed)           0.288     1.922    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_22_n_0
    SLICE_X113Y218       LUT6 (Prop_G6LUT_SLICEM_I2_O)
                                                      0.123     2.045 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_5/O
                         net (fo=1, routed)           0.279     2.324    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_5_n_0
    SLICE_X115Y224       LUT6 (Prop_D6LUT_SLICEM_I4_O)
                                                      0.051     2.375 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.072     2.447    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X115Y224       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.156     2.338    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X115Y224       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.175ns  (logic 0.395ns (33.617%)  route 0.780ns (66.383%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.630ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.630ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.483ns (routing 0.404ns, distribution 1.079ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[15])
                                                      0.250     0.250 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[15]
                         net (fo=1, routed)           0.438     0.688    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_22_1[15]
    SLICE_X109Y215       LUT6 (Prop_H6LUT_SLICEM_I5_O)
                                                      0.051     0.739 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_47/O
                         net (fo=1, routed)           0.024     0.763    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_47_n_0
    SLICE_X109Y215       LUT5 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.022     0.785 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_22/O
                         net (fo=1, routed)           0.151     0.936    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_22_n_0
    SLICE_X113Y218       LUT6 (Prop_G6LUT_SLICEM_I2_O)
                                                      0.050     0.986 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_5/O
                         net (fo=1, routed)           0.141     1.127    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_5_n_0
    SLICE_X115Y224       LUT6 (Prop_D6LUT_SLICEM_I4_O)
                                                      0.022     1.149 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.026     1.175    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X115Y224       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.483     1.630    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X115Y224       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.218ns  (logic 0.407ns (33.415%)  route 0.811ns (66.585%))
  Logic Levels:           5  (LUT5=2 LUT6=3)
  Clock Path Skew:        1.622ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.622ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.475ns (routing 0.404ns, distribution 1.071ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[8])
                                                      0.237     0.237 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[8]
                         net (fo=1, routed)           0.493     0.730    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_22_1[8]
    SLICE_X108Y215       LUT5 (Prop_A6LUT_SLICEL_I3_O)
                                                      0.022     0.752 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_31/O
                         net (fo=1, routed)           0.048     0.800    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_31_n_0
    SLICE_X108Y215       LUT6 (Prop_C6LUT_SLICEL_I5_O)
                                                      0.035     0.835 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_29/O
                         net (fo=1, routed)           0.078     0.913    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_29_n_0
    SLICE_X110Y215       LUT5 (Prop_C6LUT_SLICEM_I1_O)
                                                      0.040     0.953 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_19/O
                         net (fo=1, routed)           0.022     0.975    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_19_n_0
    SLICE_X110Y215       LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.014     0.989 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_6/O
                         net (fo=1, routed)           0.144     1.133    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_6_n_0
    SLICE_X113Y226       LUT6 (Prop_D6LUT_SLICEM_I4_O)
                                                      0.059     1.192 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.026     1.218    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    SLICE_X113Y226       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.475     1.622    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y226       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.277ns  (logic 0.384ns (30.070%)  route 0.893ns (69.930%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.635ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.635ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.488ns (routing 0.404ns, distribution 1.084ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[12])
                                                      0.274     0.274 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[12]
                         net (fo=1, routed)           0.485     0.759    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_22_1[12]
    SLICE_X108Y215       LUT5 (Prop_B6LUT_SLICEL_I3_O)
                                                      0.015     0.774 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_20/O
                         net (fo=1, routed)           0.051     0.825    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_20_n_0
    SLICE_X108Y215       LUT6 (Prop_D6LUT_SLICEL_I5_O)
                                                      0.059     0.884 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_15/O
                         net (fo=1, routed)           0.132     1.016    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_15_n_0
    SLICE_X112Y217       LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.022     1.038 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_6/O
                         net (fo=1, routed)           0.201     1.239    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_6_n_0
    SLICE_X113Y227       LUT6 (Prop_C6LUT_SLICEM_I5_O)
                                                      0.014     1.253 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.024     1.277    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X113Y227       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.488     1.635    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y227       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.350ns  (logic 0.361ns (26.741%)  route 0.989ns (73.259%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.629ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.629ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.482ns (routing 0.404ns, distribution 1.078ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[13])
                                                      0.241     0.241 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[13]
                         net (fo=1, routed)           0.527     0.768    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_22_1[13]
    SLICE_X107Y216       LUT5 (Prop_F6LUT_SLICEM_I3_O)
                                                      0.035     0.803 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_60/O
                         net (fo=1, routed)           0.041     0.844    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_60_n_0
    SLICE_X107Y216       LUT6 (Prop_D6LUT_SLICEM_I5_O)
                                                      0.022     0.866 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_27/O
                         net (fo=1, routed)           0.245     1.111    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_27_n_0
    SLICE_X112Y217       LUT6 (Prop_B6LUT_SLICEM_I0_O)
                                                      0.041     1.152 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_7/O
                         net (fo=1, routed)           0.150     1.302    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_7_n_0
    SLICE_X113Y225       LUT6 (Prop_D6LUT_SLICEM_I5_O)
                                                      0.022     1.324 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.026     1.350    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X113Y225       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.482     1.629    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y225       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.452ns  (logic 0.379ns (26.102%)  route 1.073ns (73.898%))
  Logic Levels:           5  (LUT5=2 LUT6=3)
  Clock Path Skew:        1.623ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.623ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.476ns (routing 0.404ns, distribution 1.072ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[11])
                                                      0.265     0.265 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[11]
                         net (fo=1, routed)           0.554     0.819    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_22_1[11]
    SLICE_X106Y216       LUT5 (Prop_B6LUT_SLICEL_I3_O)
                                                      0.015     0.834 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_41/O
                         net (fo=1, routed)           0.044     0.878    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_41_n_0
    SLICE_X106Y216       LUT6 (Prop_D6LUT_SLICEL_I5_O)
                                                      0.022     0.900 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_31/O
                         net (fo=1, routed)           0.278     1.178    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_31_n_0
    SLICE_X112Y215       LUT5 (Prop_B6LUT_SLICEM_I1_O)
                                                      0.014     1.192 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_19/O
                         net (fo=1, routed)           0.152     1.344    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_19_n_0
    SLICE_X113Y223       LUT6 (Prop_F6LUT_SLICEM_I0_O)
                                                      0.040     1.384 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_5/O
                         net (fo=1, routed)           0.024     1.408    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_5_n_0
    SLICE_X113Y223       LUT6 (Prop_H6LUT_SLICEM_I3_O)
                                                      0.023     1.431 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.021     1.452    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X113Y223       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.476     1.623    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y223       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.505ns  (logic 0.463ns (30.764%)  route 1.042ns (69.236%))
  Logic Levels:           5  (LUT5=1 LUT6=4)
  Clock Path Skew:        1.628ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.628ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.481ns (routing 0.404ns, distribution 1.077ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[14])
                                                      0.285     0.285 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[14]
                         net (fo=1, routed)           0.594     0.879    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_22_1[14]
    SLICE_X109Y214       LUT6 (Prop_G6LUT_SLICEM_I2_O)
                                                      0.060     0.939 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_63/O
                         net (fo=1, routed)           0.027     0.966    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_63_n_0
    SLICE_X109Y214       LUT5 (Prop_H6LUT_SLICEM_I2_O)
                                                      0.023     0.989 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_46/O
                         net (fo=1, routed)           0.084     1.073    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_46_n_0
    SLICE_X110Y212       LUT6 (Prop_G6LUT_SLICEM_I5_O)
                                                      0.050     1.123 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_21/O
                         net (fo=1, routed)           0.123     1.246    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_21_n_0
    SLICE_X112Y220       LUT6 (Prop_H6LUT_SLICEM_I3_O)
                                                      0.023     1.269 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6/O
                         net (fo=1, routed)           0.190     1.459    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6_n_0
    SLICE_X113Y237       LUT6 (Prop_C6LUT_SLICEM_I5_O)
                                                      0.022     1.481 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.024     1.505    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X113Y237       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.481     1.628    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y237       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.508ns  (logic 0.420ns (27.851%)  route 1.088ns (72.149%))
  Logic Levels:           5  (LUT5=2 LUT6=3)
  Clock Path Skew:        1.625ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.625ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.478ns (routing 0.404ns, distribution 1.074ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[10])
                                                      0.227     0.227 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[10]
                         net (fo=1, routed)           0.558     0.785    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_22_1[10]
    SLICE_X107Y218       LUT5 (Prop_B6LUT_SLICEM_I3_O)
                                                      0.035     0.820 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_29/O
                         net (fo=1, routed)           0.045     0.865    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_29_n_0
    SLICE_X107Y218       LUT6 (Prop_D6LUT_SLICEM_I5_O)
                                                      0.035     0.900 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_24/O
                         net (fo=1, routed)           0.261     1.161    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_24_n_0
    SLICE_X112Y215       LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.051     1.212 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_16/O
                         net (fo=1, routed)           0.164     1.376    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_16_n_0
    SLICE_X114Y222       LUT6 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.050     1.426 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_4/O
                         net (fo=1, routed)           0.044     1.470    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_4_n_0
    SLICE_X114Y222       LUT5 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.022     1.492 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.016     1.508    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X114Y222       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.478     1.625    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X114Y222       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.533ns  (logic 0.390ns (25.440%)  route 1.143ns (74.560%))
  Logic Levels:           5  (LUT5=2 LUT6=3)
  Clock Path Skew:        1.623ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.623ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.476ns (routing 0.404ns, distribution 1.072ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[9])
                                                      0.228     0.228 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[9]
                         net (fo=1, routed)           0.645     0.873    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_22_1[9]
    SLICE_X107Y216       LUT5 (Prop_E6LUT_SLICEM_I3_O)
                                                      0.059     0.932 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_29/O
                         net (fo=1, routed)           0.024     0.956    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_29_n_0
    SLICE_X107Y216       LUT6 (Prop_C6LUT_SLICEM_I5_O)
                                                      0.014     0.970 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_26/O
                         net (fo=1, routed)           0.271     1.241    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_26_n_0
    SLICE_X112Y215       LUT5 (Prop_F6LUT_SLICEM_I1_O)
                                                      0.035     1.276 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_18/O
                         net (fo=1, routed)           0.159     1.435    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_18_n_0
    SLICE_X113Y223       LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.014     1.449 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_6/O
                         net (fo=1, routed)           0.023     1.472    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_6_n_0
    SLICE_X113Y223       LUT6 (Prop_G6LUT_SLICEM_I4_O)
                                                      0.040     1.512 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.021     1.533    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    SLICE_X113Y223       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.476     1.623    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y223       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFADC3_CLK
  To Clock:  clk_pl_0

Max Delay             8 Endpoints
Min Delay             8 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.369ns  (logic 0.900ns (37.991%)  route 1.469ns (62.009%))
  Logic Levels:           5  (LUT4=1 LUT5=1 LUT6=3)
  Clock Path Skew:        2.338ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.338ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.156ns (routing 0.598ns, distribution 1.558ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[15])
                                                      0.525     0.525 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[15]
                         net (fo=1, routed)           0.495     1.020    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_55_0[15]
    SLICE_X115Y229       LUT4 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.039     1.059 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_84/O
                         net (fo=1, routed)           0.173     1.232    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_84_n_0
    SLICE_X115Y230       LUT5 (Prop_F6LUT_SLICEM_I2_O)
                                                      0.148     1.380 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_55/O
                         net (fo=1, routed)           0.178     1.558    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_55_n_0
    SLICE_X113Y229       LUT6 (Prop_G6LUT_SLICEM_I3_O)
                                                      0.037     1.595 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_25/O
                         net (fo=1, routed)           0.272     1.867    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_25_n_0
    SLICE_X113Y218       LUT6 (Prop_G6LUT_SLICEM_I5_O)
                                                      0.100     1.967 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_5/O
                         net (fo=1, routed)           0.279     2.246    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_5_n_0
    SLICE_X115Y224       LUT6 (Prop_D6LUT_SLICEM_I4_O)
                                                      0.051     2.297 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.072     2.369    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X115Y224       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.156     2.338    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X115Y224       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.335ns  (logic 0.944ns (40.428%)  route 1.391ns (59.572%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        2.338ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.338ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.156ns (routing 0.598ns, distribution 1.558ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[14])
                                                      0.698     0.698 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[14]
                         net (fo=1, routed)           0.551     1.249    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_55_0[14]
    SLICE_X115Y228       LUT5 (Prop_G6LUT_SLICEM_I4_O)
                                                      0.052     1.301 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_38/O
                         net (fo=1, routed)           0.048     1.349    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_38_n_0
    SLICE_X115Y228       LUT6 (Prop_H6LUT_SLICEM_I3_O)
                                                      0.053     1.402 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_19/O
                         net (fo=1, routed)           0.358     1.760    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_19_n_0
    SLICE_X112Y220       LUT6 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.090     1.850 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6/O
                         net (fo=1, routed)           0.368     2.218    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6_n_0
    SLICE_X113Y237       LUT6 (Prop_C6LUT_SLICEM_I5_O)
                                                      0.051     2.269 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.066     2.335    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X113Y237       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.156     2.338    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y237       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.096ns  (logic 1.178ns (56.202%)  route 0.918ns (43.798%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        2.329ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.329ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.147ns (routing 0.598ns, distribution 1.549ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[8])
                                                      0.788     0.788 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[8]
                         net (fo=1, routed)           0.576     1.364    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_55_0[8]
    SLICE_X115Y226       LUT5 (Prop_G6LUT_SLICEM_I4_O)
                                                      0.150     1.514 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_28/O
                         net (fo=1, routed)           0.048     1.562    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_28_n_0
    SLICE_X115Y226       LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.053     1.615 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_18/O
                         net (fo=1, routed)           0.041     1.656    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_18_n_0
    SLICE_X115Y226       LUT5 (Prop_F6LUT_SLICEM_I4_O)
                                                      0.088     1.744 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_5/O
                         net (fo=1, routed)           0.181     1.925    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_5_n_0
    SLICE_X113Y226       LUT6 (Prop_D6LUT_SLICEM_I3_O)
                                                      0.099     2.024 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.072     2.096    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    SLICE_X113Y226       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.147     2.329    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y226       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.032ns  (logic 1.004ns (49.409%)  route 1.028ns (50.591%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        2.331ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.331ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.149ns (routing 0.598ns, distribution 1.551ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[11])
                                                      0.588     0.588 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[11]
                         net (fo=1, routed)           0.515     1.103    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_55_0[11]
    SLICE_X116Y223       LUT5 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.090     1.193 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_29/O
                         net (fo=1, routed)           0.169     1.362    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_29_n_0
    SLICE_X114Y226       LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.150     1.512 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_18/O
                         net (fo=1, routed)           0.190     1.702    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_18_n_0
    SLICE_X114Y223       LUT5 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.051     1.753 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_4/O
                         net (fo=1, routed)           0.096     1.849    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_4_n_0
    SLICE_X113Y223       LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                      0.125     1.974 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.058     2.032    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X113Y223       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.149     2.331    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y223       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.973ns  (logic 0.951ns (48.201%)  route 1.022ns (51.799%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        2.343ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.343ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.161ns (routing 0.598ns, distribution 1.563ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[12])
                                                      0.611     0.611 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[12]
                         net (fo=1, routed)           0.635     1.246    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_55_0[12]
    SLICE_X113Y229       LUT5 (Prop_C6LUT_SLICEM_I4_O)
                                                      0.037     1.283 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_18/O
                         net (fo=1, routed)           0.177     1.460    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_18_n_0
    SLICE_X113Y229       LUT6 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.090     1.550 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_10/O
                         net (fo=1, routed)           0.096     1.646    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_10_n_0
    SLICE_X113Y227       LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                      0.090     1.736 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_3/O
                         net (fo=1, routed)           0.048     1.784    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_3_n_0
    SLICE_X113Y227       LUT6 (Prop_C6LUT_SLICEM_I1_O)
                                                      0.123     1.907 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.066     1.973    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X113Y227       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.161     2.343    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y227       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.883ns  (logic 0.929ns (49.336%)  route 0.954ns (50.664%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        2.331ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.331ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.149ns (routing 0.598ns, distribution 1.551ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[9])
                                                      0.532     0.532 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[9]
                         net (fo=1, routed)           0.612     1.144    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_55_0[9]
    SLICE_X114Y227       LUT5 (Prop_E6LUT_SLICEL_I4_O)
                                                      0.147     1.291 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_25/O
                         net (fo=1, routed)           0.057     1.348    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_25_n_0
    SLICE_X114Y227       LUT6 (Prop_F6LUT_SLICEL_I4_O)
                                                      0.148     1.496 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_17/O
                         net (fo=1, routed)           0.135     1.631    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_17_n_0
    SLICE_X114Y223       LUT5 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.050     1.681 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_5/O
                         net (fo=1, routed)           0.091     1.772    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_5_n_0
    SLICE_X113Y223       LUT6 (Prop_G6LUT_SLICEM_I3_O)
                                                      0.052     1.824 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.059     1.883    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    SLICE_X113Y223       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.149     2.331    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y223       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.869ns  (logic 0.980ns (52.434%)  route 0.889ns (47.566%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        2.338ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.338ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.156ns (routing 0.598ns, distribution 1.558ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[13])
                                                      0.771     0.771 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[13]
                         net (fo=1, routed)           0.515     1.286    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_55_0[13]
    SLICE_X116Y224       LUT5 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.050     1.336 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_37/O
                         net (fo=1, routed)           0.175     1.511    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_37_n_0
    SLICE_X114Y225       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.036     1.547 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_12/O
                         net (fo=1, routed)           0.039     1.586    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_12_n_0
    SLICE_X114Y225       LUT6 (Prop_G6LUT_SLICEL_I2_O)
                                                      0.035     1.621 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_3/O
                         net (fo=1, routed)           0.088     1.709    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_3_n_0
    SLICE_X113Y225       LUT6 (Prop_D6LUT_SLICEM_I1_O)
                                                      0.088     1.797 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.072     1.869    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X113Y225       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.156     2.338    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y225       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.833ns  (logic 0.833ns (45.445%)  route 1.000ns (54.555%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        2.333ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.333ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.151ns (routing 0.598ns, distribution 1.553ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[10])
                                                      0.536     0.536 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[10]
                         net (fo=1, routed)           0.549     1.085    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_55_0[10]
    SLICE_X116Y227       LUT5 (Prop_C6LUT_SLICEL_I4_O)
                                                      0.035     1.120 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_23/O
                         net (fo=1, routed)           0.163     1.283    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_23_n_0
    SLICE_X114Y227       LUT6 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.123     1.406 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_13/O
                         net (fo=1, routed)           0.150     1.556    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_13_n_0
    SLICE_X114Y222       LUT6 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.089     1.645 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_4/O
                         net (fo=1, routed)           0.089     1.734    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_4_n_0
    SLICE_X114Y222       LUT5 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.050     1.784 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.049     1.833    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X114Y222       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.151     2.333    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X114Y222       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.746ns  (logic 0.327ns (43.834%)  route 0.419ns (56.166%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.629ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.629ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.482ns (routing 0.404ns, distribution 1.078ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[13])
                                                      0.241     0.241 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[13]
                         net (fo=1, routed)           0.237     0.478    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_55_0[13]
    SLICE_X116Y224       LUT5 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.022     0.500 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_37/O
                         net (fo=1, routed)           0.090     0.590    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_37_n_0
    SLICE_X114Y225       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.015     0.605 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_12/O
                         net (fo=1, routed)           0.021     0.626    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_12_n_0
    SLICE_X114Y225       LUT6 (Prop_G6LUT_SLICEL_I2_O)
                                                      0.014     0.640 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_3/O
                         net (fo=1, routed)           0.045     0.685    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_3_n_0
    SLICE_X113Y225       LUT6 (Prop_D6LUT_SLICEM_I1_O)
                                                      0.035     0.720 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.026     0.746    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X113Y225       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.482     1.629    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y225       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.830ns  (logic 0.348ns (41.928%)  route 0.482ns (58.072%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        1.625ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.625ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.478ns (routing 0.404ns, distribution 1.074ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[10])
                                                      0.227     0.227 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[10]
                         net (fo=1, routed)           0.261     0.488    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_55_0[10]
    SLICE_X116Y227       LUT5 (Prop_C6LUT_SLICEL_I4_O)
                                                      0.014     0.502 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_23/O
                         net (fo=1, routed)           0.080     0.582    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_23_n_0
    SLICE_X114Y227       LUT6 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.050     0.632 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_13/O
                         net (fo=1, routed)           0.081     0.713    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_13_n_0
    SLICE_X114Y222       LUT6 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.035     0.748 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_4/O
                         net (fo=1, routed)           0.044     0.792    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_4_n_0
    SLICE_X114Y222       LUT5 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.022     0.814 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.016     0.830    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X114Y222       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.478     1.625    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X114Y222       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.834ns  (logic 0.396ns (47.482%)  route 0.438ns (52.518%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        1.622ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.622ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.475ns (routing 0.404ns, distribution 1.071ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[8])
                                                      0.237     0.237 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[8]
                         net (fo=1, routed)           0.270     0.507    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_55_0[8]
    SLICE_X115Y226       LUT5 (Prop_G6LUT_SLICEM_I4_O)
                                                      0.060     0.567 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_28/O
                         net (fo=1, routed)           0.027     0.594    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_28_n_0
    SLICE_X115Y226       LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.023     0.617 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_18/O
                         net (fo=1, routed)           0.024     0.641    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_18_n_0
    SLICE_X115Y226       LUT5 (Prop_F6LUT_SLICEM_I4_O)
                                                      0.035     0.676 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_5/O
                         net (fo=1, routed)           0.091     0.767    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_5_n_0
    SLICE_X113Y226       LUT6 (Prop_D6LUT_SLICEM_I3_O)
                                                      0.041     0.808 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.026     0.834    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    SLICE_X113Y226       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.475     1.622    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y226       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.852ns  (logic 0.390ns (45.775%)  route 0.462ns (54.225%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        1.623ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.623ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.476ns (routing 0.404ns, distribution 1.072ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[9])
                                                      0.228     0.228 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[9]
                         net (fo=1, routed)           0.289     0.517    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_55_0[9]
    SLICE_X114Y227       LUT5 (Prop_E6LUT_SLICEL_I4_O)
                                                      0.059     0.576 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_25/O
                         net (fo=1, routed)           0.031     0.607    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_25_n_0
    SLICE_X114Y227       LUT6 (Prop_F6LUT_SLICEL_I4_O)
                                                      0.059     0.666 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_17/O
                         net (fo=1, routed)           0.074     0.740    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_17_n_0
    SLICE_X114Y223       LUT5 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.022     0.762 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_5/O
                         net (fo=1, routed)           0.047     0.809    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_5_n_0
    SLICE_X113Y223       LUT6 (Prop_G6LUT_SLICEM_I3_O)
                                                      0.022     0.831 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.021     0.852    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    SLICE_X113Y223       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.476     1.623    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y223       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.888ns  (logic 0.408ns (45.946%)  route 0.480ns (54.054%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.635ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.635ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.488ns (routing 0.404ns, distribution 1.084ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[12])
                                                      0.274     0.274 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[12]
                         net (fo=1, routed)           0.304     0.578    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_55_0[12]
    SLICE_X113Y229       LUT5 (Prop_C6LUT_SLICEM_I4_O)
                                                      0.014     0.592 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_18/O
                         net (fo=1, routed)           0.073     0.665    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_18_n_0
    SLICE_X113Y229       LUT6 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.035     0.700 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_10/O
                         net (fo=1, routed)           0.051     0.751    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_10_n_0
    SLICE_X113Y227       LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                      0.035     0.786 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_3/O
                         net (fo=1, routed)           0.028     0.814    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_3_n_0
    SLICE_X113Y227       LUT6 (Prop_C6LUT_SLICEM_I1_O)
                                                      0.050     0.864 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.024     0.888    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X113Y227       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.488     1.635    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y227       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.930ns  (logic 0.434ns (46.667%)  route 0.496ns (53.333%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        1.623ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.623ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.476ns (routing 0.404ns, distribution 1.072ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[11])
                                                      0.265     0.265 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[11]
                         net (fo=1, routed)           0.246     0.511    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_55_0[11]
    SLICE_X116Y223       LUT5 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.035     0.546 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_29/O
                         net (fo=1, routed)           0.086     0.632    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_29_n_0
    SLICE_X114Y226       LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.060     0.692 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_18/O
                         net (fo=1, routed)           0.094     0.786    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_18_n_0
    SLICE_X114Y223       LUT5 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.023     0.809 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_4/O
                         net (fo=1, routed)           0.049     0.858    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_4_n_0
    SLICE_X113Y223       LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                      0.051     0.909 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.021     0.930    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X113Y223       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.476     1.623    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y223       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.074ns  (logic 0.387ns (36.034%)  route 0.687ns (63.966%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.628ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.628ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.481ns (routing 0.404ns, distribution 1.077ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[14])
                                                      0.285     0.285 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[14]
                         net (fo=1, routed)           0.262     0.547    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_55_0[14]
    SLICE_X115Y228       LUT5 (Prop_G6LUT_SLICEM_I4_O)
                                                      0.022     0.569 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_38/O
                         net (fo=1, routed)           0.027     0.596    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_38_n_0
    SLICE_X115Y228       LUT6 (Prop_H6LUT_SLICEM_I3_O)
                                                      0.023     0.619 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_19/O
                         net (fo=1, routed)           0.184     0.803    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_19_n_0
    SLICE_X112Y220       LUT6 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.035     0.838 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6/O
                         net (fo=1, routed)           0.190     1.028    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6_n_0
    SLICE_X113Y237       LUT6 (Prop_C6LUT_SLICEM_I5_O)
                                                      0.022     1.050 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.024     1.074    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X113Y237       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.481     1.628    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y237       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.114ns  (logic 0.400ns (35.907%)  route 0.714ns (64.093%))
  Logic Levels:           5  (LUT4=1 LUT5=1 LUT6=3)
  Clock Path Skew:        1.630ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.630ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.483ns (routing 0.404ns, distribution 1.079ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[15])
                                                      0.250     0.250 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[15]
                         net (fo=1, routed)           0.229     0.479    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_55_0[15]
    SLICE_X115Y229       LUT4 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.015     0.494 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_84/O
                         net (fo=1, routed)           0.086     0.580    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_84_n_0
    SLICE_X115Y230       LUT5 (Prop_F6LUT_SLICEM_I2_O)
                                                      0.059     0.639 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_55/O
                         net (fo=1, routed)           0.090     0.729    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_55_n_0
    SLICE_X113Y229       LUT6 (Prop_G6LUT_SLICEM_I3_O)
                                                      0.014     0.743 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_25/O
                         net (fo=1, routed)           0.142     0.885    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_25_n_0
    SLICE_X113Y218       LUT6 (Prop_G6LUT_SLICEM_I5_O)
                                                      0.040     0.925 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_5/O
                         net (fo=1, routed)           0.141     1.066    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_5_n_0
    SLICE_X115Y224       LUT6 (Prop_D6LUT_SLICEM_I4_O)
                                                      0.022     1.088 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.026     1.114    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X115Y224       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.483     1.630    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X115Y224       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFDAC0_CLK
  To Clock:  clk_pl_0

Max Delay            10 Endpoints
Min Delay            10 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.844ns  (logic 0.174ns (9.436%)  route 1.670ns (90.564%))
  Logic Levels:           2  (BUFGCE=1 LUT1=1)
  Clock Path Skew:        -1.279ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.367ns
    Source Clock Delay      (SCD):    3.646ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.973ns (routing 1.381ns, distribution 1.592ns)
  Clock Net Delay (Destination): 2.185ns (routing 0.598ns, distribution 1.587ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       2.973     3.646    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X82Y270        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y270        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     3.722 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.422     4.144    d_1_i/rst_dac0/U0/peripheral_aresetn[0]
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     4.172 r  d_1_i/rst_dac0/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=29204, routed)       1.225     5.397    d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/src_in
    SLICE_X110Y263       LUT1 (Prop_A5LUT_SLICEM_I0_O)
                                                      0.070     5.467 r  d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/syncstages_ff_reg[0]_xlnx_opt/O
                         net (fo=1, routed)           0.023     5.490    d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/syncstages_ff_reg[0]_xlnx_opt_1
    SLICE_X110Y263       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.185     2.367    d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/dest_clk
    SLICE_X110Y263       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/cdc_dac1_clk_valid_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.837ns  (logic 0.216ns (11.758%)  route 1.621ns (88.242%))
  Logic Levels:           2  (BUFGCE=1 LUT1=1)
  Clock Path Skew:        -1.265ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.381ns
    Source Clock Delay      (SCD):    3.646ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.973ns (routing 1.381ns, distribution 1.592ns)
  Clock Net Delay (Destination): 2.199ns (routing 0.598ns, distribution 1.601ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       2.973     3.646    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X82Y270        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y270        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     3.722 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.422     4.144    d_1_i/rst_dac0/U0/peripheral_aresetn[0]
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     4.172 r  d_1_i/rst_dac0/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=29204, routed)       1.182     5.354    d_1_i/usp_rf_data_converter_0/inst/cdc_dac1_clk_valid_i/src_in
    SLICE_X116Y255       LUT1 (Prop_A5LUT_SLICEL_I0_O)
                                                      0.112     5.466 r  d_1_i/usp_rf_data_converter_0/inst/cdc_dac1_clk_valid_i/syncstages_ff_reg[0]_xlnx_opt/O
                         net (fo=1, routed)           0.017     5.483    d_1_i/usp_rf_data_converter_0/inst/cdc_dac1_clk_valid_i/syncstages_ff_reg[0]_xlnx_opt_1
    SLICE_X116Y255       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_dac1_clk_valid_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.199     2.381    d_1_i/usp_rf_data_converter_0/inst/cdc_dac1_clk_valid_i/dest_clk
    SLICE_X116Y255       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_dac1_clk_valid_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.873ns  (logic 1.221ns (42.499%)  route 1.652ns (57.501%))
  Logic Levels:           5  (LUT5=1 LUT6=4)
  Clock Path Skew:        2.331ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.331ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.149ns (routing 0.598ns, distribution 1.551ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[9])
                                                      0.674     0.674 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[9]
                         net (fo=1, routed)           0.687     1.361    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_31_0[9]
    SLICE_X113Y249       LUT6 (Prop_C6LUT_SLICEM_I5_O)
                                                      0.145     1.506 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_27/O
                         net (fo=1, routed)           0.095     1.601    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_27_n_0
    SLICE_X113Y249       LUT6 (Prop_H6LUT_SLICEM_I5_O)
                                                      0.101     1.702 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_19/O
                         net (fo=1, routed)           0.268     1.970    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_19_n_0
    SLICE_X112Y246       LUT5 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.088     2.058 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_9/O
                         net (fo=1, routed)           0.282     2.340    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_9_n_0
    SLICE_X112Y239       LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.090     2.430 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_2/O
                         net (fo=1, routed)           0.261     2.691    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_2_n_0
    SLICE_X113Y223       LUT6 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.123     2.814 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.059     2.873    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    SLICE_X113Y223       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.149     2.331    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y223       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.723ns  (logic 1.327ns (48.733%)  route 1.396ns (51.267%))
  Logic Levels:           5  (LUT4=1 LUT5=1 LUT6=3)
  Clock Path Skew:        2.338ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.338ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.156ns (routing 0.598ns, distribution 1.558ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[15])
                                                      0.840     0.840 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[15]
                         net (fo=1, routed)           0.644     1.484    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_31_0[15]
    SLICE_X113Y246       LUT4 (Prop_B6LUT_SLICEM_I0_O)
                                                      0.149     1.633 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_65/O
                         net (fo=1, routed)           0.150     1.783    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_65_n_0
    SLICE_X113Y246       LUT5 (Prop_C6LUT_SLICEM_I3_O)
                                                      0.051     1.834 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_31/O
                         net (fo=1, routed)           0.087     1.921    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_31_n_0
    SLICE_X113Y245       LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.098     2.019 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_11/O
                         net (fo=1, routed)           0.127     2.146    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_11_n_0
    SLICE_X115Y245       LUT6 (Prop_H6LUT_SLICEM_I5_O)
                                                      0.152     2.298 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_2/O
                         net (fo=1, routed)           0.316     2.614    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_2_n_0
    SLICE_X115Y224       LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.037     2.651 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.072     2.723    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X115Y224       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.156     2.338    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X115Y224       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.716ns  (logic 1.346ns (49.558%)  route 1.370ns (50.442%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        2.338ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.338ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.156ns (routing 0.598ns, distribution 1.558ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[13])
                                                      1.059     1.059 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[13]
                         net (fo=1, routed)           0.655     1.714    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_31_0[13]
    SLICE_X112Y251       LUT5 (Prop_F6LUT_SLICEM_I4_O)
                                                      0.051     1.765 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_33/O
                         net (fo=1, routed)           0.042     1.807    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_33_n_0
    SLICE_X112Y251       LUT6 (Prop_H6LUT_SLICEM_I5_O)
                                                      0.039     1.846 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_10/O
                         net (fo=1, routed)           0.222     2.068    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_10_n_0
    SLICE_X113Y245       LUT5 (Prop_E6LUT_SLICEM_I3_O)
                                                      0.052     2.120 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_2/O
                         net (fo=1, routed)           0.379     2.499    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_2_n_0
    SLICE_X113Y225       LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.145     2.644 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.072     2.716    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X113Y225       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.156     2.338    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y225       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.572ns  (logic 1.111ns (43.196%)  route 1.461ns (56.804%))
  Logic Levels:           5  (LUT5=1 LUT6=4)
  Clock Path Skew:        2.331ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.331ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.149ns (routing 0.598ns, distribution 1.551ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[11])
                                                      0.753     0.753 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[11]
                         net (fo=1, routed)           0.639     1.392    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_31_0[11]
    SLICE_X113Y250       LUT6 (Prop_G6LUT_SLICEM_I5_O)
                                                      0.037     1.429 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_48/O
                         net (fo=1, routed)           0.047     1.476    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_48_n_0
    SLICE_X113Y250       LUT6 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.101     1.577 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_39/O
                         net (fo=1, routed)           0.142     1.719    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_39_n_0
    SLICE_X113Y247       LUT5 (Prop_E6LUT_SLICEM_I1_O)
                                                      0.091     1.810 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_23/O
                         net (fo=1, routed)           0.218     2.028    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_23_n_0
    SLICE_X113Y242       LUT6 (Prop_H6LUT_SLICEM_I5_O)
                                                      0.039     2.067 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_6/O
                         net (fo=1, routed)           0.357     2.424    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_6_n_0
    SLICE_X113Y223       LUT6 (Prop_H6LUT_SLICEM_I5_O)
                                                      0.090     2.514 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.058     2.572    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X113Y223       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.149     2.331    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y223       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.562ns  (logic 1.089ns (42.506%)  route 1.473ns (57.494%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        2.333ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.333ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.151ns (routing 0.598ns, distribution 1.553ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[10])
                                                      0.753     0.753 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[10]
                         net (fo=1, routed)           0.651     1.404    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_31_0[10]
    SLICE_X113Y251       LUT5 (Prop_D6LUT_SLICEM_I4_O)
                                                      0.099     1.503 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_26/O
                         net (fo=1, routed)           0.173     1.676    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_26_n_0
    SLICE_X113Y248       LUT6 (Prop_F6LUT_SLICEM_I2_O)
                                                      0.088     1.764 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_17/O
                         net (fo=1, routed)           0.194     1.958    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_17_n_0
    SLICE_X114Y243       LUT6 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.050     2.008 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_5/O
                         net (fo=1, routed)           0.406     2.414    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_5_n_0
    SLICE_X114Y222       LUT5 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.099     2.513 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.049     2.562    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X114Y222       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.151     2.333    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X114Y222       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.522ns  (logic 1.204ns (47.740%)  route 1.318ns (52.260%))
  Logic Levels:           5  (LUT5=1 LUT6=4)
  Clock Path Skew:        2.329ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.329ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.147ns (routing 0.598ns, distribution 1.549ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[8])
                                                      0.731     0.731 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[8]
                         net (fo=1, routed)           0.642     1.373    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_31_0[8]
    SLICE_X112Y246       LUT6 (Prop_F6LUT_SLICEM_I5_O)
                                                      0.148     1.521 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_30/O
                         net (fo=1, routed)           0.041     1.562    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_30_n_0
    SLICE_X112Y246       LUT6 (Prop_G6LUT_SLICEM_I5_O)
                                                      0.052     1.614 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_21/O
                         net (fo=1, routed)           0.048     1.662    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_21_n_0
    SLICE_X112Y246       LUT5 (Prop_E6LUT_SLICEM_I0_O)
                                                      0.100     1.762 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_8/O
                         net (fo=1, routed)           0.267     2.029    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_8_n_0
    SLICE_X113Y243       LUT6 (Prop_F6LUT_SLICEM_I2_O)
                                                      0.051     2.080 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_2/O
                         net (fo=1, routed)           0.248     2.328    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_2_n_0
    SLICE_X113Y226       LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.122     2.450 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.072     2.522    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    SLICE_X113Y226       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.147     2.329    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y226       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.398ns  (logic 1.012ns (42.202%)  route 1.386ns (57.798%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        2.343ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.343ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.161ns (routing 0.598ns, distribution 1.563ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[12])
                                                      0.759     0.759 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[12]
                         net (fo=1, routed)           0.668     1.427    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_31_0[12]
    SLICE_X112Y251       LUT5 (Prop_G6LUT_SLICEM_I4_O)
                                                      0.037     1.464 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_17/O
                         net (fo=1, routed)           0.140     1.604    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_17_n_0
    SLICE_X112Y247       LUT6 (Prop_H6LUT_SLICEM_I5_O)
                                                      0.039     1.643 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_9/O
                         net (fo=1, routed)           0.222     1.865    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_9_n_0
    SLICE_X113Y245       LUT5 (Prop_B6LUT_SLICEM_I3_O)
                                                      0.089     1.954 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_2/O
                         net (fo=1, routed)           0.290     2.244    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_2_n_0
    SLICE_X113Y227       LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.088     2.332 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.066     2.398    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X113Y227       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.161     2.343    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y227       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.217ns  (logic 1.044ns (47.091%)  route 1.173ns (52.909%))
  Logic Levels:           4  (LUT3=1 LUT6=3)
  Clock Path Skew:        2.338ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.338ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.156ns (routing 0.598ns, distribution 1.558ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[14])
                                                      0.779     0.779 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[14]
                         net (fo=1, routed)           0.685     1.464    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_31_0[14]
    SLICE_X113Y249       LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.088     1.552 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_27/O
                         net (fo=1, routed)           0.039     1.591    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_27_n_0
    SLICE_X113Y249       LUT3 (Prop_E6LUT_SLICEM_I1_O)
                                                      0.037     1.628 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_9/O
                         net (fo=1, routed)           0.157     1.785    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_9_n_0
    SLICE_X113Y247       LUT6 (Prop_G6LUT_SLICEM_I3_O)
                                                      0.052     1.837 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_2/O
                         net (fo=1, routed)           0.226     2.063    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_2_n_0
    SLICE_X113Y237       LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.088     2.151 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.066     2.217    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X113Y237       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.156     2.338    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y237       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.077ns  (logic 0.504ns (46.797%)  route 0.573ns (53.203%))
  Logic Levels:           4  (LUT3=1 LUT6=3)
  Clock Path Skew:        1.628ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.628ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.481ns (routing 0.404ns, distribution 1.077ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[14])
                                                      0.398     0.398 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[14]
                         net (fo=1, routed)           0.330     0.728    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_31_0[14]
    SLICE_X113Y249       LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.035     0.763 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_27/O
                         net (fo=1, routed)           0.022     0.785    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_27_n_0
    SLICE_X113Y249       LUT3 (Prop_E6LUT_SLICEM_I1_O)
                                                      0.014     0.799 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_9/O
                         net (fo=1, routed)           0.079     0.878    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_9_n_0
    SLICE_X113Y247       LUT6 (Prop_G6LUT_SLICEM_I3_O)
                                                      0.022     0.900 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_2/O
                         net (fo=1, routed)           0.118     1.018    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_2_n_0
    SLICE_X113Y237       LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.035     1.053 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.024     1.077    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X113Y237       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.481     1.628    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y237       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.177ns  (logic 0.485ns (41.206%)  route 0.692ns (58.794%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        1.635ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.635ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.488ns (routing 0.404ns, distribution 1.084ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[12])
                                                      0.386     0.386 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[12]
                         net (fo=1, routed)           0.324     0.710    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_31_0[12]
    SLICE_X112Y251       LUT5 (Prop_G6LUT_SLICEM_I4_O)
                                                      0.014     0.724 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_17/O
                         net (fo=1, routed)           0.078     0.802    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_17_n_0
    SLICE_X112Y247       LUT6 (Prop_H6LUT_SLICEM_I5_O)
                                                      0.015     0.817 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_9/O
                         net (fo=1, routed)           0.112     0.929    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_9_n_0
    SLICE_X113Y245       LUT5 (Prop_B6LUT_SLICEM_I3_O)
                                                      0.035     0.964 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_2/O
                         net (fo=1, routed)           0.154     1.118    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_2_n_0
    SLICE_X113Y227       LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.035     1.153 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.024     1.177    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X113Y227       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.488     1.635    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y227       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.231ns  (logic 0.575ns (46.710%)  route 0.656ns (53.290%))
  Logic Levels:           5  (LUT5=1 LUT6=4)
  Clock Path Skew:        1.622ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.622ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.475ns (routing 0.404ns, distribution 1.071ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[8])
                                                      0.382     0.382 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[8]
                         net (fo=1, routed)           0.315     0.697    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_31_0[8]
    SLICE_X112Y246       LUT6 (Prop_F6LUT_SLICEM_I5_O)
                                                      0.059     0.756 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_30/O
                         net (fo=1, routed)           0.023     0.779    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_30_n_0
    SLICE_X112Y246       LUT6 (Prop_G6LUT_SLICEM_I5_O)
                                                      0.022     0.801 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_21/O
                         net (fo=1, routed)           0.026     0.827    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_21_n_0
    SLICE_X112Y246       LUT5 (Prop_E6LUT_SLICEM_I0_O)
                                                      0.040     0.867 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_8/O
                         net (fo=1, routed)           0.134     1.001    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_8_n_0
    SLICE_X113Y243       LUT6 (Prop_F6LUT_SLICEM_I2_O)
                                                      0.022     1.023 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_2/O
                         net (fo=1, routed)           0.132     1.155    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_2_n_0
    SLICE_X113Y226       LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.050     1.205 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.026     1.231    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    SLICE_X113Y226       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.475     1.622    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y226       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.234ns  (logic 0.507ns (41.086%)  route 0.727ns (58.914%))
  Logic Levels:           5  (LUT5=1 LUT6=4)
  Clock Path Skew:        1.623ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.623ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.476ns (routing 0.404ns, distribution 1.072ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[11])
                                                      0.367     0.367 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[11]
                         net (fo=1, routed)           0.305     0.672    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_31_0[11]
    SLICE_X113Y250       LUT6 (Prop_G6LUT_SLICEM_I5_O)
                                                      0.014     0.686 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_48/O
                         net (fo=1, routed)           0.026     0.712    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_48_n_0
    SLICE_X113Y250       LUT6 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.041     0.753 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_39/O
                         net (fo=1, routed)           0.075     0.828    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_39_n_0
    SLICE_X113Y247       LUT5 (Prop_E6LUT_SLICEM_I1_O)
                                                      0.035     0.863 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_23/O
                         net (fo=1, routed)           0.112     0.975    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_23_n_0
    SLICE_X113Y242       LUT6 (Prop_H6LUT_SLICEM_I5_O)
                                                      0.015     0.990 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_6/O
                         net (fo=1, routed)           0.188     1.178    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_6_n_0
    SLICE_X113Y223       LUT6 (Prop_H6LUT_SLICEM_I5_O)
                                                      0.035     1.213 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.021     1.234    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X113Y223       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.476     1.623    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y223       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.237ns  (logic 0.514ns (41.552%)  route 0.723ns (58.448%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        1.625ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.625ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.478ns (routing 0.404ns, distribution 1.074ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[10])
                                                      0.375     0.375 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[10]
                         net (fo=1, routed)           0.312     0.687    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_31_0[10]
    SLICE_X113Y251       LUT5 (Prop_D6LUT_SLICEM_I4_O)
                                                      0.041     0.728 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_26/O
                         net (fo=1, routed)           0.086     0.814    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_26_n_0
    SLICE_X113Y248       LUT6 (Prop_F6LUT_SLICEM_I2_O)
                                                      0.035     0.849 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_17/O
                         net (fo=1, routed)           0.100     0.949    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_17_n_0
    SLICE_X114Y243       LUT6 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.022     0.971 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_5/O
                         net (fo=1, routed)           0.209     1.180    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_5_n_0
    SLICE_X114Y222       LUT5 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.041     1.221 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.016     1.237    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X114Y222       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.478     1.625    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X114Y222       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.297ns  (logic 0.610ns (47.032%)  route 0.687ns (52.968%))
  Logic Levels:           5  (LUT4=1 LUT5=1 LUT6=3)
  Clock Path Skew:        1.630ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.630ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.483ns (routing 0.404ns, distribution 1.079ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[15])
                                                      0.413     0.413 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[15]
                         net (fo=1, routed)           0.306     0.719    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_31_0[15]
    SLICE_X113Y246       LUT4 (Prop_B6LUT_SLICEM_I0_O)
                                                      0.060     0.779 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_65/O
                         net (fo=1, routed)           0.079     0.858    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_65_n_0
    SLICE_X113Y246       LUT5 (Prop_C6LUT_SLICEM_I3_O)
                                                      0.022     0.880 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_31/O
                         net (fo=1, routed)           0.047     0.927    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_31_n_0
    SLICE_X113Y245       LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.040     0.967 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_11/O
                         net (fo=1, routed)           0.064     1.031    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_11_n_0
    SLICE_X115Y245       LUT6 (Prop_H6LUT_SLICEM_I5_O)
                                                      0.061     1.092 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_2/O
                         net (fo=1, routed)           0.165     1.257    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_2_n_0
    SLICE_X115Y224       LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.014     1.271 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.026     1.297    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X115Y224       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.483     1.630    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X115Y224       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.324ns  (logic 0.642ns (48.489%)  route 0.682ns (51.511%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        1.629ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.629ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.482ns (routing 0.404ns, distribution 1.078ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[13])
                                                      0.524     0.524 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[13]
                         net (fo=1, routed)           0.312     0.836    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_31_0[13]
    SLICE_X112Y251       LUT5 (Prop_F6LUT_SLICEM_I4_O)
                                                      0.022     0.858 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_33/O
                         net (fo=1, routed)           0.025     0.883    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_33_n_0
    SLICE_X112Y251       LUT6 (Prop_H6LUT_SLICEM_I5_O)
                                                      0.015     0.898 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_10/O
                         net (fo=1, routed)           0.116     1.014    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_10_n_0
    SLICE_X113Y245       LUT5 (Prop_E6LUT_SLICEM_I3_O)
                                                      0.022     1.036 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_2/O
                         net (fo=1, routed)           0.203     1.239    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_2_n_0
    SLICE_X113Y225       LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.059     1.298 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.026     1.324    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X113Y225       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.482     1.629    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y225       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.365ns  (logic 0.558ns (40.879%)  route 0.807ns (59.121%))
  Logic Levels:           5  (LUT5=1 LUT6=4)
  Clock Path Skew:        1.623ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.623ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.476ns (routing 0.404ns, distribution 1.072ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[9])
                                                      0.338     0.338 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[9]
                         net (fo=1, routed)           0.324     0.662    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_31_0[9]
    SLICE_X113Y249       LUT6 (Prop_C6LUT_SLICEM_I5_O)
                                                      0.059     0.721 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_27/O
                         net (fo=1, routed)           0.047     0.768    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_27_n_0
    SLICE_X113Y249       LUT6 (Prop_H6LUT_SLICEM_I5_O)
                                                      0.041     0.809 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_19/O
                         net (fo=1, routed)           0.137     0.946    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_19_n_0
    SLICE_X112Y246       LUT5 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.035     0.981 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_9/O
                         net (fo=1, routed)           0.142     1.123    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_9_n_0
    SLICE_X112Y239       LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.035     1.158 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_2/O
                         net (fo=1, routed)           0.136     1.294    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_2_n_0
    SLICE_X113Y223       LUT6 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.050     1.344 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.021     1.365    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    SLICE_X113Y223       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.476     1.623    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y223       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.985ns  (logic 0.076ns (7.716%)  route 0.909ns (92.284%))
  Logic Levels:           2  (BUFGCE=1 LUT1=1)
  Clock Path Skew:        -0.330ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.647ns
    Source Clock Delay      (SCD):    1.977ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.628ns (routing 0.748ns, distribution 0.880ns)
  Clock Net Delay (Destination): 1.500ns (routing 0.404ns, distribution 1.096ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       1.628     1.977    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X82Y270        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y270        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     2.015 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.224     2.239    d_1_i/rst_dac0/U0/peripheral_aresetn[0]
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.256 r  d_1_i/rst_dac0/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=29204, routed)       0.678     2.934    d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/src_in
    SLICE_X110Y263       LUT1 (Prop_A5LUT_SLICEM_I0_O)
                                                      0.021     2.955 r  d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/syncstages_ff_reg[0]_xlnx_opt/O
                         net (fo=1, routed)           0.007     2.962    d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/syncstages_ff_reg[0]_xlnx_opt_1
    SLICE_X110Y263       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.500     1.647    d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/dest_clk
    SLICE_X110Y263       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/cdc_dac1_clk_valid_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.986ns  (logic 0.093ns (9.432%)  route 0.893ns (90.568%))
  Logic Levels:           2  (BUFGCE=1 LUT1=1)
  Clock Path Skew:        -0.321ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.656ns
    Source Clock Delay      (SCD):    1.977ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.628ns (routing 0.748ns, distribution 0.880ns)
  Clock Net Delay (Destination): 1.509ns (routing 0.404ns, distribution 1.105ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       1.628     1.977    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X82Y270        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y270        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     2.015 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.224     2.239    d_1_i/rst_dac0/U0/peripheral_aresetn[0]
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.256 r  d_1_i/rst_dac0/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=29204, routed)       0.662     2.918    d_1_i/usp_rf_data_converter_0/inst/cdc_dac1_clk_valid_i/src_in
    SLICE_X116Y255       LUT1 (Prop_A5LUT_SLICEL_I0_O)
                                                      0.038     2.956 r  d_1_i/usp_rf_data_converter_0/inst/cdc_dac1_clk_valid_i/syncstages_ff_reg[0]_xlnx_opt/O
                         net (fo=1, routed)           0.007     2.963    d_1_i/usp_rf_data_converter_0/inst/cdc_dac1_clk_valid_i/syncstages_ff_reg[0]_xlnx_opt_1
    SLICE_X116Y255       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_dac1_clk_valid_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.509     1.656    d_1_i/usp_rf_data_converter_0/inst/cdc_dac1_clk_valid_i/dest_clk
    SLICE_X116Y255       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_dac1_clk_valid_i/syncstages_ff_reg[0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFDAC1_CLK
  To Clock:  clk_pl_0

Max Delay             8 Endpoints
Min Delay             8 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.795ns  (logic 1.604ns (42.266%)  route 2.191ns (57.734%))
  Logic Levels:           5  (LUT4=1 LUT5=1 LUT6=3)
  Clock Path Skew:        2.338ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.338ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.156ns (routing 0.598ns, distribution 1.558ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[13])
                                                      1.059     1.059 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[13]
                         net (fo=1, routed)           1.135     2.194    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_28_0[13]
    SLICE_X115Y249       LUT4 (Prop_B6LUT_SLICEM_I0_O)
                                                      0.125     2.319 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_62/O
                         net (fo=1, routed)           0.090     2.409    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_62_n_0
    SLICE_X114Y249       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.090     2.499 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_31/O
                         net (fo=1, routed)           0.187     2.686    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_31_n_0
    SLICE_X115Y248       LUT6 (Prop_G6LUT_SLICEM_I1_O)
                                                      0.037     2.723 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_9/O
                         net (fo=1, routed)           0.328     3.051    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_9_n_0
    SLICE_X113Y245       LUT5 (Prop_E6LUT_SLICEM_I2_O)
                                                      0.148     3.199 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_2/O
                         net (fo=1, routed)           0.379     3.578    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_2_n_0
    SLICE_X113Y225       LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.145     3.723 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.072     3.795    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X113Y225       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.156     2.338    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y225       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.454ns  (logic 1.147ns (33.208%)  route 2.307ns (66.792%))
  Logic Levels:           5  (LUT6=5)
  Clock Path Skew:        2.331ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.331ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.149ns (routing 0.598ns, distribution 1.551ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[11])
                                                      0.753     0.753 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[11]
                         net (fo=1, routed)           1.442     2.195    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_28_0[11]
    SLICE_X112Y248       LUT6 (Prop_B6LUT_SLICEM_I5_O)
                                                      0.052     2.247 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_46/O
                         net (fo=1, routed)           0.048     2.295    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_46_n_0
    SLICE_X112Y248       LUT6 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.101     2.396 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_35/O
                         net (fo=1, routed)           0.201     2.597    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_35_n_0
    SLICE_X114Y247       LUT6 (Prop_B6LUT_SLICEL_I2_O)
                                                      0.098     2.695 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_22/O
                         net (fo=1, routed)           0.201     2.896    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_22_n_0
    SLICE_X113Y242       LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.053     2.949 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_6/O
                         net (fo=1, routed)           0.357     3.306    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_6_n_0
    SLICE_X113Y223       LUT6 (Prop_H6LUT_SLICEM_I5_O)
                                                      0.090     3.396 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.058     3.454    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X113Y223       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.149     2.331    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y223       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.167ns  (logic 1.175ns (37.101%)  route 1.992ns (62.899%))
  Logic Levels:           5  (LUT4=1 LUT5=1 LUT6=3)
  Clock Path Skew:        2.343ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.343ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.161ns (routing 0.598ns, distribution 1.563ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[12])
                                                      0.759     0.759 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[12]
                         net (fo=1, routed)           1.198     1.957    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_28_0[12]
    SLICE_X116Y249       LUT4 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.150     2.107 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_21/O
                         net (fo=1, routed)           0.087     2.194    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_21_n_0
    SLICE_X115Y249       LUT6 (Prop_H6LUT_SLICEM_I5_O)
                                                      0.039     2.233 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_16/O
                         net (fo=1, routed)           0.091     2.324    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_16_n_0
    SLICE_X115Y248       LUT6 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.039     2.363 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_8/O
                         net (fo=1, routed)           0.260     2.623    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_8_n_0
    SLICE_X113Y245       LUT5 (Prop_B6LUT_SLICEM_I2_O)
                                                      0.100     2.723 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_2/O
                         net (fo=1, routed)           0.290     3.013    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_2_n_0
    SLICE_X113Y227       LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.088     3.101 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.066     3.167    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X113Y227       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.161     2.343    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y227       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.124ns  (logic 1.241ns (39.725%)  route 1.883ns (60.275%))
  Logic Levels:           5  (LUT5=1 LUT6=4)
  Clock Path Skew:        2.338ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.338ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.156ns (routing 0.598ns, distribution 1.558ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[15])
                                                      0.840     0.840 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[15]
                         net (fo=1, routed)           1.093     1.933    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_28_0[15]
    SLICE_X115Y249       LUT5 (Prop_C6LUT_SLICEM_I1_O)
                                                      0.088     2.021 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_59/O
                         net (fo=1, routed)           0.059     2.080    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_59_n_0
    SLICE_X115Y249       LUT6 (Prop_F6LUT_SLICEM_I5_O)
                                                      0.148     2.228 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_28/O
                         net (fo=1, routed)           0.257     2.485    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_28_n_0
    SLICE_X116Y245       LUT6 (Prop_F6LUT_SLICEL_I3_O)
                                                      0.089     2.574 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_10/O
                         net (fo=1, routed)           0.086     2.660    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_10_n_0
    SLICE_X115Y245       LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.039     2.699 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_2/O
                         net (fo=1, routed)           0.316     3.015    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_2_n_0
    SLICE_X115Y224       LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.037     3.052 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.072     3.124    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X115Y224       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.156     2.338    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X115Y224       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.094ns  (logic 1.262ns (40.789%)  route 1.832ns (59.211%))
  Logic Levels:           5  (LUT5=1 LUT6=4)
  Clock Path Skew:        2.338ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.338ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.156ns (routing 0.598ns, distribution 1.558ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[14])
                                                      0.779     0.779 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[14]
                         net (fo=1, routed)           0.989     1.768    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_28_0[14]
    SLICE_X115Y249       LUT5 (Prop_D6LUT_SLICEM_I3_O)
                                                      0.145     1.913 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_50/O
                         net (fo=1, routed)           0.042     1.955    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_50_n_0
    SLICE_X115Y249       LUT6 (Prop_G6LUT_SLICEM_I5_O)
                                                      0.100     2.055 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_24/O
                         net (fo=1, routed)           0.153     2.208    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_24_n_0
    SLICE_X116Y245       LUT6 (Prop_G6LUT_SLICEL_I2_O)
                                                      0.050     2.258 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_8/O
                         net (fo=1, routed)           0.356     2.614    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_8_n_0
    SLICE_X113Y247       LUT6 (Prop_G6LUT_SLICEM_I2_O)
                                                      0.100     2.714 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_2/O
                         net (fo=1, routed)           0.226     2.940    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_2_n_0
    SLICE_X113Y237       LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.088     3.028 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.066     3.094    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X113Y237       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.156     2.338    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y237       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.082ns  (logic 1.127ns (36.567%)  route 1.955ns (63.433%))
  Logic Levels:           4  (LUT4=1 LUT6=3)
  Clock Path Skew:        2.329ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.329ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.147ns (routing 0.598ns, distribution 1.549ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[8])
                                                      0.731     0.731 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[8]
                         net (fo=1, routed)           1.186     1.917    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_28_0[8]
    SLICE_X116Y249       LUT4 (Prop_E6LUT_SLICEL_I0_O)
                                                      0.147     2.064 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_22/O
                         net (fo=1, routed)           0.189     2.253    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_22_n_0
    SLICE_X115Y247       LUT6 (Prop_G6LUT_SLICEM_I2_O)
                                                      0.090     2.343 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_10/O
                         net (fo=1, routed)           0.260     2.603    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_10_n_0
    SLICE_X113Y243       LUT6 (Prop_F6LUT_SLICEM_I4_O)
                                                      0.037     2.640 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_2/O
                         net (fo=1, routed)           0.248     2.888    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_2_n_0
    SLICE_X113Y226       LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.122     3.010 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.072     3.082    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    SLICE_X113Y226       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.147     2.329    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y226       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.962ns  (logic 1.023ns (34.537%)  route 1.939ns (65.463%))
  Logic Levels:           5  (LUT6=5)
  Clock Path Skew:        2.331ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.331ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.149ns (routing 0.598ns, distribution 1.551ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[9])
                                                      0.674     0.674 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[9]
                         net (fo=1, routed)           1.175     1.849    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_28_0[9]
    SLICE_X116Y247       LUT6 (Prop_G6LUT_SLICEL_I5_O)
                                                      0.089     1.938 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_28/O
                         net (fo=1, routed)           0.099     2.037    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_28_n_0
    SLICE_X114Y247       LUT6 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.049     2.086 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_20/O
                         net (fo=1, routed)           0.039     2.125    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_20_n_0
    SLICE_X114Y247       LUT6 (Prop_G6LUT_SLICEL_I3_O)
                                                      0.035     2.160 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_10/O
                         net (fo=1, routed)           0.306     2.466    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_10_n_0
    SLICE_X112Y239       LUT6 (Prop_H6LUT_SLICEM_I5_O)
                                                      0.053     2.519 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_2/O
                         net (fo=1, routed)           0.261     2.780    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_2_n_0
    SLICE_X113Y223       LUT6 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.123     2.903 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.059     2.962    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    SLICE_X113Y223       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.149     2.331    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y223       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.653ns  (logic 0.976ns (36.789%)  route 1.677ns (63.211%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        2.333ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.333ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.151ns (routing 0.598ns, distribution 1.553ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[10])
                                                      0.753     0.753 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[10]
                         net (fo=1, routed)           0.972     1.725    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_28_0[10]
    SLICE_X116Y247       LUT5 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.036     1.761 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_28/O
                         net (fo=1, routed)           0.091     1.852    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_28_n_0
    SLICE_X115Y247       LUT6 (Prop_H6LUT_SLICEM_I3_O)
                                                      0.053     1.905 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_18/O
                         net (fo=1, routed)           0.159     2.064    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_18_n_0
    SLICE_X114Y243       LUT6 (Prop_G6LUT_SLICEL_I1_O)
                                                      0.035     2.099 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_5/O
                         net (fo=1, routed)           0.406     2.505    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_5_n_0
    SLICE_X114Y222       LUT5 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.099     2.604 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.049     2.653    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X114Y222       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.151     2.333    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X114Y222       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.302ns  (logic 0.467ns (35.868%)  route 0.835ns (64.132%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        1.625ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.625ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.478ns (routing 0.404ns, distribution 1.074ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[10])
                                                      0.375     0.375 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[10]
                         net (fo=1, routed)           0.480     0.855    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_28_0[10]
    SLICE_X116Y247       LUT5 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.014     0.869 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_28/O
                         net (fo=1, routed)           0.047     0.916    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_28_n_0
    SLICE_X115Y247       LUT6 (Prop_H6LUT_SLICEM_I3_O)
                                                      0.023     0.939 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_18/O
                         net (fo=1, routed)           0.083     1.022    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_18_n_0
    SLICE_X114Y243       LUT6 (Prop_G6LUT_SLICEL_I1_O)
                                                      0.014     1.036 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_5/O
                         net (fo=1, routed)           0.209     1.245    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_5_n_0
    SLICE_X114Y222       LUT5 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.041     1.286 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.016     1.302    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X114Y222       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.478     1.625    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X114Y222       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.462ns  (logic 0.482ns (32.969%)  route 0.980ns (67.031%))
  Logic Levels:           5  (LUT6=5)
  Clock Path Skew:        1.623ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.623ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.476ns (routing 0.404ns, distribution 1.072ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[9])
                                                      0.338     0.338 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[9]
                         net (fo=1, routed)           0.590     0.928    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_28_0[9]
    SLICE_X116Y247       LUT6 (Prop_G6LUT_SLICEL_I5_O)
                                                      0.035     0.963 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_28/O
                         net (fo=1, routed)           0.052     1.015    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_28_n_0
    SLICE_X114Y247       LUT6 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.022     1.037 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_20/O
                         net (fo=1, routed)           0.021     1.058    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_20_n_0
    SLICE_X114Y247       LUT6 (Prop_G6LUT_SLICEL_I3_O)
                                                      0.014     1.072 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_10/O
                         net (fo=1, routed)           0.160     1.232    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_10_n_0
    SLICE_X112Y239       LUT6 (Prop_H6LUT_SLICEM_I5_O)
                                                      0.023     1.255 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_2/O
                         net (fo=1, routed)           0.136     1.391    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_2_n_0
    SLICE_X113Y223       LUT6 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.050     1.441 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.021     1.462    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    SLICE_X113Y223       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.476     1.623    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y223       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.510ns  (logic 0.594ns (39.338%)  route 0.916ns (60.662%))
  Logic Levels:           5  (LUT5=1 LUT6=4)
  Clock Path Skew:        1.628ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.628ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.481ns (routing 0.404ns, distribution 1.077ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[14])
                                                      0.398     0.398 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[14]
                         net (fo=1, routed)           0.488     0.886    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_28_0[14]
    SLICE_X115Y249       LUT5 (Prop_D6LUT_SLICEM_I3_O)
                                                      0.059     0.945 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_50/O
                         net (fo=1, routed)           0.023     0.968    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_50_n_0
    SLICE_X115Y249       LUT6 (Prop_G6LUT_SLICEM_I5_O)
                                                      0.040     1.008 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_24/O
                         net (fo=1, routed)           0.080     1.088    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_24_n_0
    SLICE_X116Y245       LUT6 (Prop_G6LUT_SLICEL_I2_O)
                                                      0.022     1.110 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_8/O
                         net (fo=1, routed)           0.183     1.293    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_8_n_0
    SLICE_X113Y247       LUT6 (Prop_G6LUT_SLICEM_I2_O)
                                                      0.040     1.333 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_2/O
                         net (fo=1, routed)           0.118     1.451    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_2_n_0
    SLICE_X113Y237       LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.035     1.486 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.024     1.510    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X113Y237       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.481     1.628    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y237       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.514ns  (logic 0.571ns (37.715%)  route 0.943ns (62.285%))
  Logic Levels:           5  (LUT5=1 LUT6=4)
  Clock Path Skew:        1.630ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.630ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.483ns (routing 0.404ns, distribution 1.079ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[15])
                                                      0.413     0.413 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[15]
                         net (fo=1, routed)           0.543     0.956    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_28_0[15]
    SLICE_X115Y249       LUT5 (Prop_C6LUT_SLICEM_I1_O)
                                                      0.035     0.991 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_59/O
                         net (fo=1, routed)           0.031     1.022    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_59_n_0
    SLICE_X115Y249       LUT6 (Prop_F6LUT_SLICEM_I5_O)
                                                      0.059     1.081 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_28/O
                         net (fo=1, routed)           0.132     1.213    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_28_n_0
    SLICE_X116Y245       LUT6 (Prop_F6LUT_SLICEL_I3_O)
                                                      0.035     1.248 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_10/O
                         net (fo=1, routed)           0.046     1.294    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_10_n_0
    SLICE_X115Y245       LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.015     1.309 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_2/O
                         net (fo=1, routed)           0.165     1.474    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_2_n_0
    SLICE_X115Y224       LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.014     1.488 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.026     1.514    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X115Y224       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.483     1.630    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X115Y224       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.514ns  (logic 0.540ns (35.667%)  route 0.974ns (64.333%))
  Logic Levels:           4  (LUT4=1 LUT6=3)
  Clock Path Skew:        1.622ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.622ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.475ns (routing 0.404ns, distribution 1.071ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[8])
                                                      0.382     0.382 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[8]
                         net (fo=1, routed)           0.588     0.970    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_28_0[8]
    SLICE_X116Y249       LUT4 (Prop_E6LUT_SLICEL_I0_O)
                                                      0.059     1.029 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_22/O
                         net (fo=1, routed)           0.096     1.125    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_22_n_0
    SLICE_X115Y247       LUT6 (Prop_G6LUT_SLICEM_I2_O)
                                                      0.035     1.160 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_10/O
                         net (fo=1, routed)           0.132     1.292    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_10_n_0
    SLICE_X113Y243       LUT6 (Prop_F6LUT_SLICEM_I4_O)
                                                      0.014     1.306 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_2/O
                         net (fo=1, routed)           0.132     1.438    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_2_n_0
    SLICE_X113Y226       LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.050     1.488 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.026     1.514    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    SLICE_X113Y226       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.475     1.622    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y226       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.547ns  (logic 0.552ns (35.682%)  route 0.995ns (64.318%))
  Logic Levels:           5  (LUT4=1 LUT5=1 LUT6=3)
  Clock Path Skew:        1.635ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.635ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.488ns (routing 0.404ns, distribution 1.084ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[12])
                                                      0.386     0.386 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[12]
                         net (fo=1, routed)           0.588     0.974    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_28_0[12]
    SLICE_X116Y249       LUT4 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.060     1.034 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_21/O
                         net (fo=1, routed)           0.046     1.080    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_21_n_0
    SLICE_X115Y249       LUT6 (Prop_H6LUT_SLICEM_I5_O)
                                                      0.015     1.095 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_16/O
                         net (fo=1, routed)           0.050     1.145    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_16_n_0
    SLICE_X115Y248       LUT6 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.015     1.160 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_8/O
                         net (fo=1, routed)           0.133     1.293    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_8_n_0
    SLICE_X113Y245       LUT5 (Prop_B6LUT_SLICEM_I2_O)
                                                      0.041     1.334 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_2/O
                         net (fo=1, routed)           0.154     1.488    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_2_n_0
    SLICE_X113Y227       LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.035     1.523 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.024     1.547    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X113Y227       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.488     1.635    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y227       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.685ns  (logic 0.529ns (31.395%)  route 1.156ns (68.605%))
  Logic Levels:           5  (LUT6=5)
  Clock Path Skew:        1.623ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.623ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.476ns (routing 0.404ns, distribution 1.072ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[11])
                                                      0.367     0.367 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[11]
                         net (fo=1, routed)           0.715     1.082    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_28_0[11]
    SLICE_X112Y248       LUT6 (Prop_B6LUT_SLICEM_I5_O)
                                                      0.022     1.104 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_46/O
                         net (fo=1, routed)           0.027     1.131    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_46_n_0
    SLICE_X112Y248       LUT6 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.041     1.172 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_35/O
                         net (fo=1, routed)           0.103     1.275    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_35_n_0
    SLICE_X114Y247       LUT6 (Prop_B6LUT_SLICEL_I2_O)
                                                      0.041     1.316 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_22/O
                         net (fo=1, routed)           0.102     1.418    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_22_n_0
    SLICE_X113Y242       LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.023     1.441 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_6/O
                         net (fo=1, routed)           0.188     1.629    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_6_n_0
    SLICE_X113Y223       LUT6 (Prop_H6LUT_SLICEM_I5_O)
                                                      0.035     1.664 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.021     1.685    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X113Y223       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.476     1.623    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y223       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.835ns  (logic 0.741ns (40.381%)  route 1.094ns (59.619%))
  Logic Levels:           5  (LUT4=1 LUT5=1 LUT6=3)
  Clock Path Skew:        1.629ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.629ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.482ns (routing 0.404ns, distribution 1.078ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[13])
                                                      0.524     0.524 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[13]
                         net (fo=1, routed)           0.556     1.080    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_28_0[13]
    SLICE_X115Y249       LUT4 (Prop_B6LUT_SLICEM_I0_O)
                                                      0.050     1.130 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_62/O
                         net (fo=1, routed)           0.048     1.178    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_62_n_0
    SLICE_X114Y249       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.035     1.213 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_31/O
                         net (fo=1, routed)           0.095     1.308    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_31_n_0
    SLICE_X115Y248       LUT6 (Prop_G6LUT_SLICEM_I1_O)
                                                      0.014     1.322 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_9/O
                         net (fo=1, routed)           0.166     1.488    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_9_n_0
    SLICE_X113Y245       LUT5 (Prop_E6LUT_SLICEM_I2_O)
                                                      0.059     1.547 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_2/O
                         net (fo=1, routed)           0.203     1.750    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_2_n_0
    SLICE_X113Y225       LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.059     1.809 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.026     1.835    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X113Y225       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.482     1.629    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y225       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_out1_d_1_clk_adc0_x2_0
  To Clock:  clk_pl_0

Max Delay           269 Endpoints
Min Delay           269 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/FABRIC_CLK
                            (rising edge-triggered cell HSADC clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.528ns  (logic 0.723ns (20.493%)  route 2.805ns (79.507%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        -3.441ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.338ns
    Source Clock Delay      (SCD):    5.779ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.511ns (routing 0.858ns, distribution 1.653ns)
  Clock Net Delay (Destination): 2.156ns (routing 0.598ns, distribution 1.558ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.595     3.122    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.995 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.240    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.268 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       2.511     5.779    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/m0_axis_aclk
    HSADC_X0Y0           HSADC                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/FABRIC_CLK
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_FABRIC_CLK_STATUS_COMMON[5])
                                                      0.450     6.229 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[5]
                         net (fo=1, routed)           2.383     8.612    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[5]
    SLICE_X114Y213       LUT6 (Prop_C6LUT_SLICEL_I3_O)
                                                      0.146     8.758 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_12/O
                         net (fo=1, routed)           0.041     8.799    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_12_n_0
    SLICE_X114Y213       LUT6 (Prop_B6LUT_SLICEL_I1_O)
                                                      0.090     8.889 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_4/O
                         net (fo=1, routed)           0.315     9.204    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_4_n_0
    SLICE_X115Y224       LUT6 (Prop_C6LUT_SLICEM_I2_O)
                                                      0.037     9.241 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_1/O
                         net (fo=1, routed)           0.066     9.307    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_79
    SLICE_X115Y224       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.156     2.338    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X115Y224       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[5]/C

Slack:                    inf
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/cdc_adc2_clk_valid_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.878ns  (logic 0.079ns (4.206%)  route 1.799ns (95.794%))
  Logic Levels:           0  
  Clock Path Skew:        -3.019ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.334ns
    Source Clock Delay      (SCD):    5.353ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.085ns (routing 0.858ns, distribution 1.227ns)
  Clock Net Delay (Destination): 2.152ns (routing 0.598ns, distribution 1.554ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.595     3.122    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.995 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.240    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.268 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       2.085     5.353    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
    SLICE_X59Y182        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X59Y182        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     5.432 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=2, routed)           1.799     7.232    d_1_i/usp_rf_data_converter_0/inst/cdc_adc2_clk_valid_i/src_in
    SLICE_X112Y186       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_adc2_clk_valid_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.152     2.334    d_1_i/usp_rf_data_converter_0/inst/cdc_adc2_clk_valid_i/dest_clk
    SLICE_X112Y186       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_adc2_clk_valid_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/cdc_adc0_clk_valid_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.777ns  (logic 0.079ns (4.445%)  route 1.698ns (95.555%))
  Logic Levels:           0  
  Clock Path Skew:        -3.023ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.330ns
    Source Clock Delay      (SCD):    5.353ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.085ns (routing 0.858ns, distribution 1.227ns)
  Clock Net Delay (Destination): 2.148ns (routing 0.598ns, distribution 1.550ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.595     3.122    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.995 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.240    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.268 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       2.085     5.353    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
    SLICE_X59Y182        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X59Y182        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     5.432 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=2, routed)           1.698     7.131    d_1_i/usp_rf_data_converter_0/inst/cdc_adc0_clk_valid_i/src_in
    SLICE_X114Y182       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_adc0_clk_valid_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.148     2.330    d_1_i/usp_rf_data_converter_0/inst/cdc_adc0_clk_valid_i/dest_clk
    SLICE_X114Y182       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_adc0_clk_valid_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.391ns  (logic 0.078ns (19.965%)  route 0.313ns (80.035%))
  Logic Levels:           0  
  Clock Path Skew:        -3.417ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.057ns
    Source Clock Delay      (SCD):    5.474ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.206ns (routing 0.858ns, distribution 1.348ns)
  Clock Net Delay (Destination): 1.875ns (routing 0.598ns, distribution 1.277ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.595     3.122    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.995 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.240    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.268 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       2.206     5.474    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X30Y185        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X30Y185        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.078     5.552 r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/Q
                         net (fo=2, routed)           0.313     5.865    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/src_in
    SLICE_X30Y183        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.875     2.057    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/dest_clk
    SLICE_X30Y183        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.414ns  (logic 0.081ns (19.564%)  route 0.333ns (80.436%))
  Logic Levels:           0  
  Clock Path Skew:        -3.298ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.002ns
    Source Clock Delay      (SCD):    5.300ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.032ns (routing 0.858ns, distribution 1.174ns)
  Clock Net Delay (Destination): 1.820ns (routing 0.598ns, distribution 1.222ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.595     3.122    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.995 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.240    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.268 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       2.032     5.300    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X58Y135        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X58Y135        FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.081     5.381 r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/Q
                         net (fo=2, routed)           0.333     5.714    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/src_in
    SLICE_X55Y140        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.820     2.002    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/dest_clk
    SLICE_X55Y140        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_14_27/RAMB_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[17]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.605ns  (logic 0.307ns (19.128%)  route 1.298ns (80.872%))
  Logic Levels:           0  
  Clock Path Skew:        -3.362ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.105ns
    Source Clock Delay      (SCD):    5.467ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.199ns (routing 0.858ns, distribution 1.341ns)
  Clock Net Delay (Destination): 1.923ns (routing 0.598ns, distribution 1.325ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.595     3.122    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.995 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.240    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.268 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       2.199     5.467    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_14_27/WCLK
    SLICE_X67Y229        RAMD32                                       r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_14_27/RAMB_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X67Y229        RAMD32 (Prop_B6LUT_SLICEM_CLK_O)
                                                      0.307     5.774 r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_14_27/RAMB_D1/O
                         net (fo=1, routed)           1.298     7.072    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob0__0[17]
    SLICE_X62Y317        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[17]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.923     2.105    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/m_axis_aclk
    SLICE_X62Y317        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[17]/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_56_63/RAMB/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[58]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.566ns  (logic 0.292ns (18.646%)  route 1.274ns (81.354%))
  Logic Levels:           0  
  Clock Path Skew:        -3.381ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.094ns
    Source Clock Delay      (SCD):    5.475ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.207ns (routing 0.858ns, distribution 1.349ns)
  Clock Net Delay (Destination): 1.912ns (routing 0.598ns, distribution 1.314ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.595     3.122    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.995 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.240    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.268 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       2.207     5.475    d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_56_63/WCLK
    SLICE_X31Y214        RAMD32                                       r  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_56_63/RAMB/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X31Y214        RAMD32 (Prop_B5LUT_SLICEM_CLK_O)
                                                      0.292     5.767 r  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_56_63/RAMB/O
                         net (fo=1, routed)           1.274     7.041    d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob0__0[58]
    SLICE_X23Y272        FDRE                                         r  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[58]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.912     2.094    d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/m_axis_aclk
    SLICE_X23Y272        FDRE                                         r  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[58]/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/wptr_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.584ns  (logic 0.179ns (11.299%)  route 1.405ns (88.701%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        -3.348ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.093ns
    Source Clock Delay      (SCD):    5.441ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.173ns (routing 0.858ns, distribution 1.315ns)
  Clock Net Delay (Destination): 1.911ns (routing 0.598ns, distribution 1.313ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.595     3.122    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.995 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.240    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.268 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       2.173     5.441    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/s_axis_aclk
    SLICE_X65Y233        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/wptr_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y233        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.080     5.521 r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/wptr_reg[1]/Q
                         net (fo=83, routed)          0.571     6.092    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/wptr_g_i/Q[1]
    SLICE_X65Y223        LUT2 (Prop_H6LUT_SLICEL_I1_O)
                                                      0.099     6.191 r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/wptr_g_i/wptr[1]_i_1__1/O
                         net (fo=2, routed)           0.834     7.025    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/wptr_g_i/D[0]
    SLICE_X64Y280        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.911     2.093    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/wptr_g_i/m_axis_aclk
    SLICE_X64Y280        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][0]/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_14_27/RAMC_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[19]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.550ns  (logic 0.307ns (19.806%)  route 1.243ns (80.194%))
  Logic Levels:           0  
  Clock Path Skew:        -3.347ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.120ns
    Source Clock Delay      (SCD):    5.467ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.199ns (routing 0.858ns, distribution 1.341ns)
  Clock Net Delay (Destination): 1.938ns (routing 0.598ns, distribution 1.340ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.595     3.122    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.995 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.240    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.268 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       2.199     5.467    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_14_27/WCLK
    SLICE_X67Y229        RAMD32                                       r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_14_27/RAMC_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X67Y229        RAMD32 (Prop_C6LUT_SLICEM_CLK_O)
                                                      0.307     5.774 r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_14_27/RAMC_D1/O
                         net (fo=1, routed)           1.243     7.017    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob0__0[19]
    SLICE_X63Y316        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[19]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.938     2.120    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/m_axis_aclk
    SLICE_X63Y316        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[19]/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/wptr_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][1]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.560ns  (logic 0.080ns (5.129%)  route 1.480ns (94.871%))
  Logic Levels:           0  
  Clock Path Skew:        -3.348ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.093ns
    Source Clock Delay      (SCD):    5.441ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.173ns (routing 0.858ns, distribution 1.315ns)
  Clock Net Delay (Destination): 1.911ns (routing 0.598ns, distribution 1.313ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.595     3.122    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.995 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.240    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.268 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       2.173     5.441    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/s_axis_aclk
    SLICE_X65Y233        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/wptr_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y233        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.080     5.521 r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/wptr_reg[1]/Q
                         net (fo=83, routed)          1.480     7.001    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/wptr_g_i/Q[1]
    SLICE_X64Y280        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.911     2.093    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/wptr_g_i/m_axis_aclk
    SLICE_X64Y280        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][1]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.189ns  (logic 0.040ns (21.200%)  route 0.149ns (78.800%))
  Logic Levels:           0  
  Clock Path Skew:        -1.779ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.409ns
    Source Clock Delay      (SCD):    3.188ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.117ns (routing 0.470ns, distribution 0.647ns)
  Clock Net Delay (Destination): 1.262ns (routing 0.404ns, distribution 0.858ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.415     1.678    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.908 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.054    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.071 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.117     3.188    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X58Y135        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X58Y135        FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.040     3.228 r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/Q
                         net (fo=2, routed)           0.149     3.376    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/src_in
    SLICE_X55Y140        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.262     1.409    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/dest_clk
    SLICE_X55Y140        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.175ns  (logic 0.039ns (22.317%)  route 0.136ns (77.683%))
  Logic Levels:           0  
  Clock Path Skew:        -1.840ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.444ns
    Source Clock Delay      (SCD):    3.284ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.213ns (routing 0.470ns, distribution 0.743ns)
  Clock Net Delay (Destination): 1.297ns (routing 0.404ns, distribution 0.893ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.415     1.678    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.908 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.054    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.071 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.213     3.284    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X30Y185        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X30Y185        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.039     3.323 r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/Q
                         net (fo=2, routed)           0.136     3.458    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/src_in
    SLICE_X30Y183        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.297     1.444    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/dest_clk
    SLICE_X30Y183        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/cdc_adc0_clk_valid_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.861ns  (logic 0.039ns (4.532%)  route 0.822ns (95.468%))
  Logic Levels:           0  
  Clock Path Skew:        -1.597ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.619ns
    Source Clock Delay      (SCD):    3.216ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.145ns (routing 0.470ns, distribution 0.675ns)
  Clock Net Delay (Destination): 1.472ns (routing 0.404ns, distribution 1.068ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.415     1.678    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.908 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.054    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.071 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.145     3.216    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
    SLICE_X59Y182        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X59Y182        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     3.255 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=2, routed)           0.822     4.076    d_1_i/usp_rf_data_converter_0/inst/cdc_adc0_clk_valid_i/src_in
    SLICE_X114Y182       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_adc0_clk_valid_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.472     1.619    d_1_i/usp_rf_data_converter_0/inst/cdc_adc0_clk_valid_i/dest_clk
    SLICE_X114Y182       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_adc0_clk_valid_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/cdc_adc2_clk_valid_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.925ns  (logic 0.039ns (4.218%)  route 0.886ns (95.782%))
  Logic Levels:           0  
  Clock Path Skew:        -1.591ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.625ns
    Source Clock Delay      (SCD):    3.216ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.145ns (routing 0.470ns, distribution 0.675ns)
  Clock Net Delay (Destination): 1.478ns (routing 0.404ns, distribution 1.074ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.415     1.678    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.908 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.054    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.071 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.145     3.216    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
    SLICE_X59Y182        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X59Y182        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     3.255 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=2, routed)           0.886     4.140    d_1_i/usp_rf_data_converter_0/inst/cdc_adc2_clk_valid_i/src_in
    SLICE_X112Y186       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_adc2_clk_valid_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.478     1.625    d_1_i/usp_rf_data_converter_0/inst/cdc_adc2_clk_valid_i/dest_clk
    SLICE_X112Y186       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_adc2_clk_valid_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/FABRIC_CLK
                            (rising edge-triggered cell HSADC clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.572ns  (logic 0.442ns (28.117%)  route 1.130ns (71.883%))
  Logic Levels:           5  (LUT5=2 LUT6=3)
  Clock Path Skew:        -1.779ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.630ns
    Source Clock Delay      (SCD):    3.409ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.338ns (routing 0.470ns, distribution 0.868ns)
  Clock Net Delay (Destination): 1.483ns (routing 0.404ns, distribution 1.079ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.415     1.678    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.908 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.054    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.071 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.338     3.409    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/m2_axis_aclk
    HSADC_X0Y2           HSADC                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/FABRIC_CLK
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_FABRIC_CLK_STATUS_COMMON[5])
                                                      0.228     3.637 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[5]
                         net (fo=1, routed)           0.586     4.223    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_22_1[5]
    SLICE_X106Y216       LUT5 (Prop_A6LUT_SLICEL_I3_O)
                                                      0.060     4.283 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_28/O
                         net (fo=1, routed)           0.024     4.307    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_28_n_0
    SLICE_X106Y216       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.014     4.321 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_25/O
                         net (fo=1, routed)           0.264     4.585    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_25_n_0
    SLICE_X110Y217       LUT6 (Prop_G6LUT_SLICEM_I5_O)
                                                      0.050     4.635 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_16/O
                         net (fo=1, routed)           0.160     4.795    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_16_n_0
    SLICE_X115Y220       LUT5 (Prop_F6LUT_SLICEM_I0_O)
                                                      0.050     4.845 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_6/O
                         net (fo=1, routed)           0.072     4.917    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_6_n_0
    SLICE_X115Y224       LUT6 (Prop_C6LUT_SLICEM_I4_O)
                                                      0.040     4.957 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_1/O
                         net (fo=1, routed)           0.024     4.981    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_79
    SLICE_X115Y224       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.483     1.630    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X115Y224       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[5]/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_0_13/RAMF_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.170ns  (logic 0.111ns (65.294%)  route 0.059ns (34.706%))
  Logic Levels:           0  
  Clock Path Skew:        -1.816ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.488ns
    Source Clock Delay      (SCD):    3.304ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.233ns (routing 0.470ns, distribution 0.763ns)
  Clock Net Delay (Destination): 1.341ns (routing 0.404ns, distribution 0.937ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.415     1.678    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.908 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.054    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.071 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.233     3.304    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_0_13/WCLK
    SLICE_X66Y322        RAMD32                                       r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_0_13/RAMF_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y322        RAMD32 (Prop_F6LUT_SLICEM_CLK_O)
                                                      0.111     3.415 r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_0_13/RAMF_D1/O
                         net (fo=1, routed)           0.059     3.474    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob0__0[11]
    SLICE_X65Y322        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.341     1.488    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/m_axis_aclk
    SLICE_X65Y322        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_0_13/RAMA_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.177ns  (logic 0.111ns (62.712%)  route 0.066ns (37.288%))
  Logic Levels:           0  
  Clock Path Skew:        -1.808ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.496ns
    Source Clock Delay      (SCD):    3.304ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.233ns (routing 0.470ns, distribution 0.763ns)
  Clock Net Delay (Destination): 1.349ns (routing 0.404ns, distribution 0.945ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.415     1.678    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.908 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.054    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.071 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.233     3.304    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_0_13/WCLK
    SLICE_X66Y322        RAMD32                                       r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_0_13/RAMA_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y322        RAMD32 (Prop_A6LUT_SLICEM_CLK_O)
                                                      0.111     3.415 r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_0_13/RAMA_D1/O
                         net (fo=1, routed)           0.066     3.481    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob0__0[1]
    SLICE_X66Y323        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.349     1.496    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/m_axis_aclk
    SLICE_X66Y323        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_0_13/RAME/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.190ns  (logic 0.108ns (56.842%)  route 0.082ns (43.158%))
  Logic Levels:           0  
  Clock Path Skew:        -1.808ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.496ns
    Source Clock Delay      (SCD):    3.304ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.233ns (routing 0.470ns, distribution 0.763ns)
  Clock Net Delay (Destination): 1.349ns (routing 0.404ns, distribution 0.945ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.415     1.678    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.908 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.054    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.071 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.233     3.304    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_0_13/WCLK
    SLICE_X66Y322        RAMD32                                       r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_0_13/RAME/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y322        RAMD32 (Prop_E5LUT_SLICEM_CLK_O)
                                                      0.108     3.412 r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_0_13/RAME/O
                         net (fo=1, routed)           0.082     3.494    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob0__0[8]
    SLICE_X66Y323        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.349     1.496    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/m_axis_aclk
    SLICE_X66Y323        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_0_13/RAMB/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.192ns  (logic 0.110ns (57.292%)  route 0.082ns (42.708%))
  Logic Levels:           0  
  Clock Path Skew:        -1.816ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.488ns
    Source Clock Delay      (SCD):    3.304ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.233ns (routing 0.470ns, distribution 0.763ns)
  Clock Net Delay (Destination): 1.341ns (routing 0.404ns, distribution 0.937ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.415     1.678    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.908 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.054    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.071 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.233     3.304    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_0_13/WCLK
    SLICE_X66Y322        RAMD32                                       r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_0_13/RAMB/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y322        RAMD32 (Prop_B5LUT_SLICEM_CLK_O)
                                                      0.110     3.414 r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_0_13/RAMB/O
                         net (fo=1, routed)           0.082     3.496    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob0__0[2]
    SLICE_X65Y322        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.341     1.488    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/m_axis_aclk
    SLICE_X65Y322        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_0_13/RAMC_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.192ns  (logic 0.110ns (57.292%)  route 0.082ns (42.708%))
  Logic Levels:           0  
  Clock Path Skew:        -1.816ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.488ns
    Source Clock Delay      (SCD):    3.304ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.233ns (routing 0.470ns, distribution 0.763ns)
  Clock Net Delay (Destination): 1.341ns (routing 0.404ns, distribution 0.937ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.415     1.678    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.908 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.054    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.071 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.233     3.304    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_0_13/WCLK
    SLICE_X66Y322        RAMD32                                       r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_0_13/RAMC_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y322        RAMD32 (Prop_C6LUT_SLICEM_CLK_O)
                                                      0.110     3.414 r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_0_13/RAMC_D1/O
                         net (fo=1, routed)           0.082     3.496    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob0__0[5]
    SLICE_X65Y322        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.341     1.488    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/m_axis_aclk
    SLICE_X65Y322        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[5]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_out1_d_1_clk_core_0
  To Clock:  clk_pl_0

Max Delay           124 Endpoints
Min Delay           124 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.929ns  (logic 0.215ns (11.145%)  route 1.714ns (88.855%))
  Logic Levels:           1  (LUT1=1)
  Clock Path Skew:        -3.433ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.248ns
    Source Clock Delay      (SCD):    5.681ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.244ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.335ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      2.043ns (routing 0.920ns, distribution 1.123ns)
  Clock Net Delay (Destination): 2.066ns (routing 0.598ns, distribution 1.468ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.819     3.492    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.365 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.610    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.638 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        2.043     5.681    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X53Y322        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X53Y322        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     5.758 f  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=4, routed)           1.394     7.152    d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/m_axis_aresetn
    SLICE_X10Y309        LUT1 (Prop_A5LUT_SLICEL_I0_O)
                                                      0.138     7.290 r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst_i_1/O
                         net (fo=1, routed)           0.320     7.610    d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/src_rst
    SLICE_X10Y309        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.066     2.248    d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/dest_clk
    SLICE_X10Y309        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.749ns  (logic 0.201ns (11.492%)  route 1.548ns (88.508%))
  Logic Levels:           1  (LUT1=1)
  Clock Path Skew:        -3.433ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.248ns
    Source Clock Delay      (SCD):    5.681ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.244ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.335ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      2.043ns (routing 0.920ns, distribution 1.123ns)
  Clock Net Delay (Destination): 2.066ns (routing 0.598ns, distribution 1.468ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.819     3.492    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.365 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.610    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.638 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        2.043     5.681    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X53Y322        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X53Y322        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     5.758 f  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=4, routed)           1.394     7.152    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/m_axis_aresetn
    SLICE_X10Y309        LUT1 (Prop_A6LUT_SLICEL_I0_O)
                                                      0.124     7.276 r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst_i_1/O
                         net (fo=1, routed)           0.154     7.430    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/src_rst
    SLICE_X10Y309        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.066     2.248    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/dest_clk
    SLICE_X10Y309        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.927ns  (logic 0.079ns (8.523%)  route 0.848ns (91.477%))
  Logic Levels:           0  
  Clock Path Skew:        -3.438ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.256ns
    Source Clock Delay      (SCD):    5.694ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.244ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.335ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      2.056ns (routing 0.920ns, distribution 1.136ns)
  Clock Net Delay (Destination): 2.074ns (routing 0.598ns, distribution 1.476ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.819     3.492    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.365 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.610    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.638 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        2.056     5.694    d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/rd_clk
    SLICE_X10Y312        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X10Y312        FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.079     5.773 r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/Q
                         net (fo=85, routed)          0.848     6.621    d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/src_rst
    SLICE_X9Y302         FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.074     2.256    d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/dest_clk
    SLICE_X9Y302         FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.894ns  (logic 0.128ns (14.315%)  route 0.766ns (85.685%))
  Logic Levels:           1  (LUT1=1)
  Clock Path Skew:        -3.581ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.100ns
    Source Clock Delay      (SCD):    5.681ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.244ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.335ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      2.043ns (routing 0.920ns, distribution 1.123ns)
  Clock Net Delay (Destination): 1.918ns (routing 0.598ns, distribution 1.320ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.819     3.492    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.365 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.610    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.638 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        2.043     5.681    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X53Y322        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X53Y322        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     5.758 f  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=4, routed)           0.290     6.048    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/m_axis_aresetn
    SLICE_X58Y326        LUT1 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.051     6.099 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst_i_1/O
                         net (fo=1, routed)           0.476     6.575    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/src_rst
    SLICE_X63Y332        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.918     2.100    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/dest_clk
    SLICE_X63Y332        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.477ns  (logic 0.127ns (26.601%)  route 0.350ns (73.399%))
  Logic Levels:           1  (LUT1=1)
  Clock Path Skew:        -3.639ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.042ns
    Source Clock Delay      (SCD):    5.681ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.244ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.335ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      2.043ns (routing 0.920ns, distribution 1.123ns)
  Clock Net Delay (Destination): 1.860ns (routing 0.598ns, distribution 1.262ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.819     3.492    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.365 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.610    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.638 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        2.043     5.681    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X53Y322        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X53Y322        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     5.758 f  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=4, routed)           0.196     5.954    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/m_axis_aresetn
    SLICE_X58Y322        LUT1 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.050     6.004 r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst_i_1/O
                         net (fo=1, routed)           0.154     6.158    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/src_rst
    SLICE_X58Y322        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.860     2.042    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/dest_clk
    SLICE_X58Y322        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.424ns  (logic 0.079ns (18.630%)  route 0.345ns (81.370%))
  Logic Levels:           0  
  Clock Path Skew:        -3.625ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.053ns
    Source Clock Delay      (SCD):    5.678ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.244ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.335ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      2.040ns (routing 0.920ns, distribution 1.120ns)
  Clock Net Delay (Destination): 1.871ns (routing 0.598ns, distribution 1.273ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.819     3.492    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.365 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.610    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.638 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        2.040     5.678    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/rd_clk
    SLICE_X59Y321        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X59Y321        FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.079     5.757 r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/Q
                         net (fo=85, routed)          0.345     6.102    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/src_rst
    SLICE_X58Y321        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.871     2.053    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/dest_clk
    SLICE_X58Y321        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.317ns  (logic 0.078ns (24.640%)  route 0.239ns (75.360%))
  Logic Levels:           0  
  Clock Path Skew:        -3.633ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.095ns
    Source Clock Delay      (SCD):    5.728ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.244ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.335ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      2.090ns (routing 0.920ns, distribution 1.170ns)
  Clock Net Delay (Destination): 1.913ns (routing 0.598ns, distribution 1.315ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.819     3.492    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.365 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.610    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.638 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        2.090     5.728    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/rd_clk
    SLICE_X63Y333        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X63Y333        FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.078     5.806 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/Q
                         net (fo=85, routed)          0.239     6.045    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/src_rst
    SLICE_X63Y333        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.913     2.095    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/dest_clk
    SLICE_X63Y333        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.298ns  (logic 0.079ns (26.524%)  route 0.219ns (73.476%))
  Logic Levels:           0  
  Clock Path Skew:        -3.446ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.248ns
    Source Clock Delay      (SCD):    5.694ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.244ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.335ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      2.056ns (routing 0.920ns, distribution 1.136ns)
  Clock Net Delay (Destination): 2.066ns (routing 0.598ns, distribution 1.468ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.819     3.492    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.365 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.610    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.638 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        2.056     5.694    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/rd_clk
    SLICE_X10Y313        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X10Y313        FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.079     5.773 r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/Q
                         net (fo=85, routed)          0.219     5.992    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/src_rst
    SLICE_X10Y310        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.066     2.248    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/dest_clk
    SLICE_X10Y310        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.c_time_abs_r_reg[8]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/QPROC_xREG/axi_rdata_reg[26]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.879ns  (logic 0.687ns (23.860%)  route 2.192ns (76.140%))
  Logic Levels:           6  (CARRY8=3 LUT2=1 LUT5=1 LUT6=1)
  Clock Path Skew:        -3.479ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.202ns
    Source Clock Delay      (SCD):    5.681ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.244ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.335ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      2.043ns (routing 0.920ns, distribution 1.123ns)
  Clock Net Delay (Destination): 2.020ns (routing 0.598ns, distribution 1.422ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.819     3.492    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.365 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.610    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.638 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        2.043     5.681    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/c_clk_i
    SLICE_X38Y374        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.c_time_abs_r_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X38Y374        FDRE (Prop_BFF2_SLICEL_C_Q)
                                                      0.080     5.761 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.c_time_abs_r_reg[8]/Q
                         net (fo=2, routed)           0.752     6.513    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.c_time_abs_r_reg_n_0_[8]
    SLICE_X33Y375        LUT2 (Prop_A6LUT_SLICEL_I0_O)
                                                      0.149     6.662 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/axi_rdata[15]_i_14/O
                         net (fo=1, routed)           0.009     6.671    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/axi_rdata[15]_i_14_n_0
    SLICE_X33Y375        CARRY8 (Prop_CARRY8_SLICEL_S[0]_CO[7])
                                                      0.190     6.861 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/axi_rdata_reg[15]_i_5/CO[7]
                         net (fo=1, routed)           0.026     6.887    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/axi_rdata_reg[15]_i_5_n_0
    SLICE_X33Y376        CARRY8 (Prop_CARRY8_SLICEL_CI_CO[7])
                                                      0.015     6.902 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/axi_rdata_reg[23]_i_5/CO[7]
                         net (fo=1, routed)           0.026     6.928    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/axi_rdata_reg[23]_i_5_n_0
    SLICE_X33Y377        CARRY8 (Prop_CARRY8_SLICEL_CI_O[2])
                                                      0.067     6.995 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/axi_rdata_reg[31]_i_6/O[2]
                         net (fo=5, routed)           0.661     7.655    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/QPROC_xREG/c_time_usr[26]
    SLICE_X29Y358        LUT6 (Prop_H6LUT_SLICEL_I2_O)
                                                      0.150     7.805 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/QPROC_xREG/axi_rdata[26]_i_2/O
                         net (fo=1, routed)           0.670     8.475    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/QPROC_xREG/axi_rdata[26]_i_2_n_0
    SLICE_X16Y349        LUT5 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.036     8.511 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/QPROC_xREG/axi_rdata[26]_i_1/O
                         net (fo=1, routed)           0.049     8.560    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/QPROC_xREG/reg_data_out[26]
    SLICE_X16Y349        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/QPROC_xREG/axi_rdata_reg[26]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.020     2.202    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/QPROC_xREG/ps_clk_i
    SLICE_X16Y349        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/QPROC_xREG/axi_rdata_reg[26]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.c_time_abs_r_reg[8]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/QPROC_xREG/axi_rdata_reg[20]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.864ns  (logic 0.729ns (25.453%)  route 2.135ns (74.547%))
  Logic Levels:           5  (CARRY8=2 LUT2=1 LUT5=1 LUT6=1)
  Clock Path Skew:        -3.489ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.192ns
    Source Clock Delay      (SCD):    5.681ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.244ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.335ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      2.043ns (routing 0.920ns, distribution 1.123ns)
  Clock Net Delay (Destination): 2.010ns (routing 0.598ns, distribution 1.412ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.819     3.492    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.365 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.610    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.638 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        2.043     5.681    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/c_clk_i
    SLICE_X38Y374        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.c_time_abs_r_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X38Y374        FDRE (Prop_BFF2_SLICEL_C_Q)
                                                      0.080     5.761 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.c_time_abs_r_reg[8]/Q
                         net (fo=2, routed)           0.752     6.513    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.c_time_abs_r_reg_n_0_[8]
    SLICE_X33Y375        LUT2 (Prop_A6LUT_SLICEL_I0_O)
                                                      0.149     6.662 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/axi_rdata[15]_i_14/O
                         net (fo=1, routed)           0.009     6.671    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/axi_rdata[15]_i_14_n_0
    SLICE_X33Y375        CARRY8 (Prop_CARRY8_SLICEL_S[0]_CO[7])
                                                      0.190     6.861 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/axi_rdata_reg[15]_i_5/CO[7]
                         net (fo=1, routed)           0.026     6.887    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/axi_rdata_reg[15]_i_5_n_0
    SLICE_X33Y376        CARRY8 (Prop_CARRY8_SLICEL_CI_O[4])
                                                      0.086     6.973 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/axi_rdata_reg[23]_i_5/O[4]
                         net (fo=5, routed)           0.625     7.598    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/QPROC_xREG/c_time_usr[20]
    SLICE_X34Y364        LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                      0.125     7.723 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/QPROC_xREG/axi_rdata[20]_i_2/O
                         net (fo=1, routed)           0.651     8.374    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/QPROC_xREG/axi_rdata[20]_i_2_n_0
    SLICE_X18Y350        LUT5 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.099     8.473 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/QPROC_xREG/axi_rdata[20]_i_1/O
                         net (fo=1, routed)           0.072     8.545    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/QPROC_xREG/reg_data_out[20]
    SLICE_X18Y350        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/QPROC_xREG/axi_rdata_reg[20]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.010     2.192    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/QPROC_xREG/ps_clk_i
    SLICE_X18Y350        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/QPROC_xREG/axi_rdata_reg[20]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.123ns  (logic 0.039ns (31.707%)  route 0.084ns (68.293%))
  Logic Levels:           0  
  Clock Path Skew:        -1.846ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.559ns
    Source Clock Delay      (SCD):    3.406ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.244ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.335ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      1.125ns (routing 0.503ns, distribution 0.622ns)
  Clock Net Delay (Destination): 1.412ns (routing 0.404ns, distribution 1.008ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       1.539     1.888    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     2.118 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.264    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.281 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.125     3.406    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X12Y310        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X12Y310        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.039     3.445 r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/Q
                         net (fo=1, routed)           0.084     3.529    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[1]
    SLICE_X14Y309        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.412     1.559    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X14Y309        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.129ns  (logic 0.039ns (30.233%)  route 0.090ns (69.767%))
  Logic Levels:           0  
  Clock Path Skew:        -1.848ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.555ns
    Source Clock Delay      (SCD):    3.403ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.244ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.335ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      1.122ns (routing 0.503ns, distribution 0.619ns)
  Clock Net Delay (Destination): 1.408ns (routing 0.404ns, distribution 1.004ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       1.539     1.888    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     2.118 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.264    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.281 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.122     3.403    d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X12Y302        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X12Y302        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.039     3.442 r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/Q
                         net (fo=1, routed)           0.090     3.532    d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[1]
    SLICE_X12Y302        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.408     1.555    d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X12Y302        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.129ns  (logic 0.039ns (30.265%)  route 0.090ns (69.735%))
  Logic Levels:           0  
  Clock Path Skew:        -1.838ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.573ns
    Source Clock Delay      (SCD):    3.411ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.244ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.335ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      1.130ns (routing 0.503ns, distribution 0.627ns)
  Clock Net Delay (Destination): 1.426ns (routing 0.404ns, distribution 1.022ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       1.539     1.888    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     2.118 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.264    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.281 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.130     3.411    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/rd_clk
    SLICE_X10Y313        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X10Y313        FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.039     3.450 r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/Q
                         net (fo=85, routed)          0.090     3.540    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/src_rst
    SLICE_X10Y310        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.426     1.573    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/dest_clk
    SLICE_X10Y310        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.140ns  (logic 0.039ns (27.857%)  route 0.101ns (72.143%))
  Logic Levels:           0  
  Clock Path Skew:        -1.847ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.558ns
    Source Clock Delay      (SCD):    3.406ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.244ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.335ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      1.125ns (routing 0.503ns, distribution 0.622ns)
  Clock Net Delay (Destination): 1.411ns (routing 0.404ns, distribution 1.007ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       1.539     1.888    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     2.118 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.264    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.281 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.125     3.406    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X12Y310        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X12Y310        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     3.445 r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/Q
                         net (fo=1, routed)           0.101     3.546    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[0]
    SLICE_X12Y309        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.411     1.558    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X12Y309        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.150ns  (logic 0.039ns (26.000%)  route 0.111ns (74.000%))
  Logic Levels:           0  
  Clock Path Skew:        -1.841ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.559ns
    Source Clock Delay      (SCD):    3.400ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.244ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.335ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      1.119ns (routing 0.503ns, distribution 0.616ns)
  Clock Net Delay (Destination): 1.412ns (routing 0.404ns, distribution 1.008ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       1.539     1.888    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     2.118 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.264    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.281 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.119     3.400    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X14Y309        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X14Y309        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     3.439 r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[4]/Q
                         net (fo=1, routed)           0.111     3.550    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[4]
    SLICE_X14Y309        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.412     1.559    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X14Y309        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.129ns  (logic 0.039ns (30.233%)  route 0.090ns (69.767%))
  Logic Levels:           0  
  Clock Path Skew:        -1.964ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.471ns
    Source Clock Delay      (SCD):    3.435ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.244ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.335ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      1.154ns (routing 0.503ns, distribution 0.651ns)
  Clock Net Delay (Destination): 1.324ns (routing 0.404ns, distribution 0.920ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       1.539     1.888    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     2.118 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.264    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.281 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.154     3.435    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X62Y325        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X62Y325        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.039     3.474 r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/Q
                         net (fo=1, routed)           0.090     3.564    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[3]
    SLICE_X62Y325        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.324     1.471    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X62Y325        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.133ns  (logic 0.038ns (28.620%)  route 0.095ns (71.380%))
  Logic Levels:           0  
  Clock Path Skew:        -1.959ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.475ns
    Source Clock Delay      (SCD):    3.434ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.244ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.335ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      1.153ns (routing 0.503ns, distribution 0.650ns)
  Clock Net Delay (Destination): 1.328ns (routing 0.404ns, distribution 0.924ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       1.539     1.888    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     2.118 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.264    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.281 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.153     3.434    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/rd_clk
    SLICE_X63Y333        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X63Y333        FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.038     3.472 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/Q
                         net (fo=85, routed)          0.095     3.567    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/src_rst
    SLICE_X63Y333        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.328     1.475    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/dest_clk
    SLICE_X63Y333        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.142ns  (logic 0.039ns (27.465%)  route 0.103ns (72.535%))
  Logic Levels:           0  
  Clock Path Skew:        -1.964ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.471ns
    Source Clock Delay      (SCD):    3.435ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.244ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.335ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      1.154ns (routing 0.503ns, distribution 0.651ns)
  Clock Net Delay (Destination): 1.324ns (routing 0.404ns, distribution 0.920ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       1.539     1.888    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     2.118 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.264    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.281 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.154     3.435    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X62Y325        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X62Y325        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     3.474 r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/Q
                         net (fo=1, routed)           0.103     3.577    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[2]
    SLICE_X62Y325        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.324     1.471    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X62Y325        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.173ns  (logic 0.040ns (23.121%)  route 0.133ns (76.879%))
  Logic Levels:           0  
  Clock Path Skew:        -1.839ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.566ns
    Source Clock Delay      (SCD):    3.406ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.244ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.335ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      1.125ns (routing 0.503ns, distribution 0.622ns)
  Clock Net Delay (Destination): 1.419ns (routing 0.404ns, distribution 1.015ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       1.539     1.888    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     2.118 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.264    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.281 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.125     3.406    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X12Y310        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X12Y310        FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.040     3.446 r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/Q
                         net (fo=1, routed)           0.133     3.579    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[3]
    SLICE_X13Y309        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.419     1.566    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X13Y309        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.135ns  (logic 0.041ns (30.370%)  route 0.094ns (69.630%))
  Logic Levels:           0  
  Clock Path Skew:        -1.961ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.484ns
    Source Clock Delay      (SCD):    3.445ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.244ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.335ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Source):      1.164ns (routing 0.503ns, distribution 0.661ns)
  Clock Net Delay (Destination): 1.337ns (routing 0.404ns, distribution 0.933ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       1.539     1.888    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     2.118 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.264    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.281 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.164     3.445    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X66Y334        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y334        FDRE (Prop_DFF2_SLICEM_C_Q)
                                                      0.041     3.486 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/Q
                         net (fo=1, routed)           0.094     3.580    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[1]
    SLICE_X66Y334        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.337     1.484    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X66Y334        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_pl_0
  To Clock:  clk_pl_0

Max Delay           175 Endpoints
Min Delay           175 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc10_over_range/syncstages_ff_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_intc_0/U0/INTC_CORE_I/INTR_DETECT_GEN[6].ASYNC_GEN.intr_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.293ns  (logic 0.608ns (14.162%)  route 3.685ns (85.838%))
  Logic Levels:           5  (LUT4=2 LUT5=1 LUT6=2)
  Clock Path Skew:        -0.343ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.309ns
    Source Clock Delay      (SCD):    2.652ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.426ns (routing 0.662ns, distribution 1.764ns)
  Clock Net Delay (Destination): 2.127ns (routing 0.598ns, distribution 1.529ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.426     2.652    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc10_over_range/dest_clk
    SLICE_X118Y171       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc10_over_range/syncstages_ff_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X118Y171       FDRE (Prop_DFF2_SLICEM_C_Q)
                                                      0.080     2.732 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc10_over_range/syncstages_ff_reg[4]/Q
                         net (fo=2, routed)           1.299     4.031    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/adc10_stat_sync[1]
    SLICE_X111Y221       LUT4 (Prop_D5LUT_SLICEL_I2_O)
                                                      0.157     4.188 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/irq_INST_0_i_43/O
                         net (fo=1, routed)           0.246     4.434    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/irq_INST_0_i_43_n_0
    SLICE_X111Y221       LUT6 (Prop_F6LUT_SLICEL_I1_O)
                                                      0.035     4.469 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/irq_INST_0_i_22/O
                         net (fo=2, routed)           0.093     4.562    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/adc10_irq_en_reg
    SLICE_X111Y222       LUT4 (Prop_E6LUT_SLICEL_I1_O)
                                                      0.123     4.685 f  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/irq_INST_0_i_7/O
                         net (fo=2, routed)           0.446     5.131    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/adc13_irq_en_reg
    SLICE_X111Y239       LUT6 (Prop_F6LUT_SLICEL_I4_O)
                                                      0.123     5.254 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/irq_INST_0_i_1/O
                         net (fo=1, routed)           0.133     5.387    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/irq_INST_0_i_1_n_0
    SLICE_X111Y238       LUT5 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.090     5.477 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/irq_INST_0/O
                         net (fo=1, routed)           1.468     6.945    d_1_i/axi_intc_0/U0/INTC_CORE_I/intr[6]
    SLICE_X99Y111        FDRE                                         r  d_1_i/axi_intc_0/U0/INTC_CORE_I/INTR_DETECT_GEN[6].ASYNC_GEN.intr_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.127     2.309    d_1_i/axi_intc_0/U0/INTC_CORE_I/s_axi_aclk
    SLICE_X99Y111        FDRE                                         r  d_1_i/axi_intc_0/U0/INTC_CORE_I/INTR_DETECT_GEN[6].ASYNC_GEN.intr_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/s01_entry_pipeline/s01_mmu/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        4.134ns  (logic 0.079ns (1.911%)  route 4.055ns (98.089%))
  Logic Levels:           0  
  Clock Path Skew:        -0.172ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.128ns
    Source Clock Delay      (SCD):    2.300ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.074ns (routing 0.662ns, distribution 1.412ns)
  Clock Net Delay (Destination): 1.946ns (routing 0.598ns, distribution 1.348ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.074     2.300    d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X49Y147        FDRE                                         r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y147        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.379 r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=120, routed)         4.055     6.434    d_1_i/axi_smc/inst/s01_entry_pipeline/s01_mmu/inst/xpm_cdc_async_rst_inst/src_arst
    SLICE_X73Y79         FDCE                                         f  d_1_i/axi_smc/inst/s01_entry_pipeline/s01_mmu/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.946     2.128    d_1_i/axi_smc/inst/s01_entry_pipeline/s01_mmu/inst/xpm_cdc_async_rst_inst/dest_clk
    SLICE_X73Y79         FDCE                                         r  d_1_i/axi_smc/inst/s01_entry_pipeline/s01_mmu/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/s01_entry_pipeline/s01_mmu/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        4.134ns  (logic 0.079ns (1.911%)  route 4.055ns (98.089%))
  Logic Levels:           0  
  Clock Path Skew:        -0.172ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.128ns
    Source Clock Delay      (SCD):    2.300ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.074ns (routing 0.662ns, distribution 1.412ns)
  Clock Net Delay (Destination): 1.946ns (routing 0.598ns, distribution 1.348ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.074     2.300    d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X49Y147        FDRE                                         r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y147        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.379 r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=120, routed)         4.055     6.434    d_1_i/axi_smc/inst/s01_entry_pipeline/s01_mmu/inst/xpm_cdc_async_rst_inst/src_arst
    SLICE_X73Y79         FDCE                                         f  d_1_i/axi_smc/inst/s01_entry_pipeline/s01_mmu/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.946     2.128    d_1_i/axi_smc/inst/s01_entry_pipeline/s01_mmu/inst/xpm_cdc_async_rst_inst/dest_clk
    SLICE_X73Y79         FDCE                                         r  d_1_i/axi_smc/inst/s01_entry_pipeline/s01_mmu/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/s01_entry_pipeline/s01_mmu/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        4.134ns  (logic 0.079ns (1.911%)  route 4.055ns (98.089%))
  Logic Levels:           0  
  Clock Path Skew:        -0.172ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.128ns
    Source Clock Delay      (SCD):    2.300ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.074ns (routing 0.662ns, distribution 1.412ns)
  Clock Net Delay (Destination): 1.946ns (routing 0.598ns, distribution 1.348ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.074     2.300    d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X49Y147        FDRE                                         r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y147        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.379 r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=120, routed)         4.055     6.434    d_1_i/axi_smc/inst/s01_entry_pipeline/s01_mmu/inst/xpm_cdc_async_rst_inst/src_arst
    SLICE_X73Y79         FDCE                                         f  d_1_i/axi_smc/inst/s01_entry_pipeline/s01_mmu/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.946     2.128    d_1_i/axi_smc/inst/s01_entry_pipeline/s01_mmu/inst/xpm_cdc_async_rst_inst/dest_clk
    SLICE_X73Y79         FDCE                                         r  d_1_i/axi_smc/inst/s01_entry_pipeline/s01_mmu/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/s05_entry_pipeline/s05_transaction_regulator/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        4.082ns  (logic 0.079ns (1.935%)  route 4.003ns (98.065%))
  Logic Levels:           0  
  Clock Path Skew:        -0.170ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.130ns
    Source Clock Delay      (SCD):    2.300ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.074ns (routing 0.662ns, distribution 1.412ns)
  Clock Net Delay (Destination): 1.948ns (routing 0.598ns, distribution 1.350ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.074     2.300    d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X49Y147        FDRE                                         r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y147        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.379 r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=120, routed)         4.003     6.382    d_1_i/axi_smc/inst/s05_entry_pipeline/s05_transaction_regulator/inst/xpm_cdc_async_rst_inst/src_arst
    SLICE_X71Y74         FDCE                                         f  d_1_i/axi_smc/inst/s05_entry_pipeline/s05_transaction_regulator/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.948     2.130    d_1_i/axi_smc/inst/s05_entry_pipeline/s05_transaction_regulator/inst/xpm_cdc_async_rst_inst/dest_clk
    SLICE_X71Y74         FDCE                                         r  d_1_i/axi_smc/inst/s05_entry_pipeline/s05_transaction_regulator/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/s05_entry_pipeline/s05_transaction_regulator/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        4.082ns  (logic 0.079ns (1.935%)  route 4.003ns (98.065%))
  Logic Levels:           0  
  Clock Path Skew:        -0.170ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.130ns
    Source Clock Delay      (SCD):    2.300ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.074ns (routing 0.662ns, distribution 1.412ns)
  Clock Net Delay (Destination): 1.948ns (routing 0.598ns, distribution 1.350ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.074     2.300    d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X49Y147        FDRE                                         r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y147        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.379 r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=120, routed)         4.003     6.382    d_1_i/axi_smc/inst/s05_entry_pipeline/s05_transaction_regulator/inst/xpm_cdc_async_rst_inst/src_arst
    SLICE_X71Y74         FDCE                                         f  d_1_i/axi_smc/inst/s05_entry_pipeline/s05_transaction_regulator/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.948     2.130    d_1_i/axi_smc/inst/s05_entry_pipeline/s05_transaction_regulator/inst/xpm_cdc_async_rst_inst/dest_clk
    SLICE_X71Y74         FDCE                                         r  d_1_i/axi_smc/inst/s05_entry_pipeline/s05_transaction_regulator/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/s05_entry_pipeline/s05_transaction_regulator/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        4.082ns  (logic 0.079ns (1.935%)  route 4.003ns (98.065%))
  Logic Levels:           0  
  Clock Path Skew:        -0.170ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.130ns
    Source Clock Delay      (SCD):    2.300ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.074ns (routing 0.662ns, distribution 1.412ns)
  Clock Net Delay (Destination): 1.948ns (routing 0.598ns, distribution 1.350ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.074     2.300    d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X49Y147        FDRE                                         r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y147        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.379 r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=120, routed)         4.003     6.382    d_1_i/axi_smc/inst/s05_entry_pipeline/s05_transaction_regulator/inst/xpm_cdc_async_rst_inst/src_arst
    SLICE_X71Y74         FDCE                                         f  d_1_i/axi_smc/inst/s05_entry_pipeline/s05_transaction_regulator/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.948     2.130    d_1_i/axi_smc/inst/s05_entry_pipeline/s05_transaction_regulator/inst/xpm_cdc_async_rst_inst/dest_clk
    SLICE_X71Y74         FDCE                                         r  d_1_i/axi_smc/inst/s05_entry_pipeline/s05_transaction_regulator/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_dma_mr/U0/I_RST_MODULE/REG_HRD_RST_OUT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.844ns  (logic 0.079ns (2.055%)  route 3.765ns (97.945%))
  Logic Levels:           0  
  Clock Path Skew:        -0.335ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.059ns
    Source Clock Delay      (SCD):    2.394ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.168ns (routing 0.662ns, distribution 1.506ns)
  Clock Net Delay (Destination): 1.877ns (routing 0.598ns, distribution 1.279ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.168     2.394    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X71Y113        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X71Y113        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     2.473 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/Q
                         net (fo=155, routed)         3.765     6.238    d_1_i/axi_dma_mr/U0/I_RST_MODULE/REG_HRD_RST_OUT/peripheral_aresetn[0]_bufg_place_replica
    SLICE_X54Y9          FDRE                                         r  d_1_i/axi_dma_mr/U0/I_RST_MODULE/REG_HRD_RST_OUT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.877     2.059    d_1_i/axi_dma_mr/U0/I_RST_MODULE/REG_HRD_RST_OUT/s_axi_lite_aclk
    SLICE_X54Y9          FDRE                                         r  d_1_i/axi_dma_mr/U0/I_RST_MODULE/REG_HRD_RST_OUT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C

Slack:                    inf
  Source:                 d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        3.859ns  (logic 0.079ns (2.047%)  route 3.780ns (97.953%))
  Logic Levels:           0  
  Clock Path Skew:        -0.202ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.098ns
    Source Clock Delay      (SCD):    2.300ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.074ns (routing 0.662ns, distribution 1.412ns)
  Clock Net Delay (Destination): 1.916ns (routing 0.598ns, distribution 1.318ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.074     2.300    d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X49Y147        FDRE                                         r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y147        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.379 r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=120, routed)         3.780     6.159    d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X66Y101        FDCE                                         f  d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.916     2.098    d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X66Y101        FDCE                                         r  d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        3.859ns  (logic 0.079ns (2.047%)  route 3.780ns (97.953%))
  Logic Levels:           0  
  Clock Path Skew:        -0.202ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.098ns
    Source Clock Delay      (SCD):    2.300ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.074ns (routing 0.662ns, distribution 1.412ns)
  Clock Net Delay (Destination): 1.916ns (routing 0.598ns, distribution 1.318ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.074     2.300    d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X49Y147        FDRE                                         r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y147        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.379 r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=120, routed)         3.780     6.159    d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X66Y101        FDCE                                         f  d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.916     2.098    d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X66Y101        FDCE                                         r  d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/axis_switch_gen/inst/gen_static_router.inst_static_router/inst_start_router_config/ctrl_soft_reset_r_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_rst_synch/inst_xpm_cdc_single/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.130ns  (logic 0.038ns (29.231%)  route 0.092ns (70.769%))
  Logic Levels:           0  
  Clock Path Skew:        0.173ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.440ns
    Source Clock Delay      (SCD):    1.268ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.148ns (routing 0.358ns, distribution 0.790ns)
  Clock Net Delay (Destination): 1.293ns (routing 0.404ns, distribution 0.889ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.148     1.268    d_1_i/axis_switch_gen/inst/gen_static_router.inst_static_router/inst_start_router_config/s_axi_ctrl_aclk
    SLICE_X39Y303        FDRE                                         r  d_1_i/axis_switch_gen/inst/gen_static_router.inst_static_router/inst_start_router_config/ctrl_soft_reset_r_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X39Y303        FDRE (Prop_CFF_SLICEM_C_Q)
                                                      0.038     1.306 r  d_1_i/axis_switch_gen/inst/gen_static_router.inst_static_router/inst_start_router_config/ctrl_soft_reset_r_reg/Q
                         net (fo=1, routed)           0.092     1.398    d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_rst_synch/inst_xpm_cdc_single/src_in
    SLICE_X39Y303        FDRE                                         r  d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_rst_synch/inst_xpm_cdc_single/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.293     1.440    d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_rst_synch/inst_xpm_cdc_single/dest_clk
    SLICE_X39Y303        FDRE                                         r  d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_rst_synch/inst_xpm_cdc_single/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_avg/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_avg/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.096ns  (logic 0.039ns (40.689%)  route 0.057ns (59.311%))
  Logic Levels:           0  
  Clock Path Skew:        0.180ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.491ns
    Source Clock Delay      (SCD):    1.312ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.192ns (routing 0.358ns, distribution 0.834ns)
  Clock Net Delay (Destination): 1.344ns (routing 0.404ns, distribution 0.940ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.192     1.312    d_1_i/axis_switch_avg/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X19Y226        FDRE                                         r  d_1_i/axis_switch_avg/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X19Y226        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.039     1.351 r  d_1_i/axis_switch_avg/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/Q
                         net (fo=2, routed)           0.057     1.407    d_1_i/axis_switch_avg/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/src_in
    SLICE_X19Y226        FDRE                                         r  d_1_i/axis_switch_avg/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.344     1.491    d_1_i/axis_switch_avg/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/dest_clk
    SLICE_X19Y226        FDRE                                         r  d_1_i/axis_switch_avg/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.106ns  (logic 0.039ns (36.792%)  route 0.067ns (63.208%))
  Logic Levels:           0  
  Clock Path Skew:        0.179ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.493ns
    Source Clock Delay      (SCD):    1.315ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.195ns (routing 0.358ns, distribution 0.837ns)
  Clock Net Delay (Destination): 1.346ns (routing 0.404ns, distribution 0.942ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.195     1.315    d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X20Y238        FDRE                                         r  d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X20Y238        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.039     1.354 r  d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/Q
                         net (fo=2, routed)           0.067     1.421    d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/src_in
    SLICE_X20Y237        FDRE                                         r  d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.346     1.493    d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/dest_clk
    SLICE_X20Y237        FDRE                                         r  d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_avg/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_avg/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.124ns  (logic 0.039ns (31.532%)  route 0.085ns (68.468%))
  Logic Levels:           0  
  Clock Path Skew:        0.173ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.487ns
    Source Clock Delay      (SCD):    1.315ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.195ns (routing 0.358ns, distribution 0.837ns)
  Clock Net Delay (Destination): 1.340ns (routing 0.404ns, distribution 0.936ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.195     1.315    d_1_i/axis_switch_avg/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X19Y227        FDRE                                         r  d_1_i/axis_switch_avg/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X19Y227        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     1.354 r  d_1_i/axis_switch_avg/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/Q
                         net (fo=2, routed)           0.085     1.438    d_1_i/axis_switch_avg/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/src_in
    SLICE_X19Y226        FDRE                                         r  d_1_i/axis_switch_avg/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.340     1.487    d_1_i/axis_switch_avg/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/dest_clk
    SLICE_X19Y226        FDRE                                         r  d_1_i/axis_switch_avg/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.133ns  (logic 0.038ns (28.551%)  route 0.095ns (71.448%))
  Logic Levels:           0  
  Clock Path Skew:        0.177ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.491ns
    Source Clock Delay      (SCD):    1.315ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.195ns (routing 0.358ns, distribution 0.837ns)
  Clock Net Delay (Destination): 1.344ns (routing 0.404ns, distribution 0.940ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.195     1.315    d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X20Y237        FDRE                                         r  d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X20Y237        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     1.353 r  d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/Q
                         net (fo=2, routed)           0.095     1.448    d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/src_in
    SLICE_X20Y239        FDRE                                         r  d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.344     1.491    d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/dest_clk
    SLICE_X20Y239        FDRE                                         r  d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.133ns  (logic 0.038ns (28.551%)  route 0.095ns (71.448%))
  Logic Levels:           0  
  Clock Path Skew:        0.181ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.498ns
    Source Clock Delay      (SCD):    1.317ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.197ns (routing 0.358ns, distribution 0.839ns)
  Clock Net Delay (Destination): 1.351ns (routing 0.404ns, distribution 0.947ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.197     1.317    d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X31Y301        FDRE                                         r  d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X31Y301        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     1.355 r  d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/Q
                         net (fo=2, routed)           0.095     1.450    d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/src_in
    SLICE_X31Y301        FDRE                                         r  d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.351     1.498    d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/dest_clk
    SLICE_X31Y301        FDRE                                         r  d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.174ns  (logic 0.038ns (21.883%)  route 0.136ns (78.117%))
  Logic Levels:           0  
  Clock Path Skew:        0.198ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.497ns
    Source Clock Delay      (SCD):    1.299ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.179ns (routing 0.358ns, distribution 0.821ns)
  Clock Net Delay (Destination): 1.350ns (routing 0.404ns, distribution 0.946ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.179     1.299    d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X28Y297        FDRE                                         r  d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X28Y297        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     1.337 r  d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/Q
                         net (fo=2, routed)           0.136     1.472    d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/src_in
    SLICE_X31Y301        FDRE                                         r  d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.350     1.497    d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/dest_clk
    SLICE_X31Y301        FDRE                                         r  d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/s02_entry_pipeline/s02_mmu/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.515ns  (logic 0.039ns (7.571%)  route 0.476ns (92.429%))
  Logic Levels:           0  
  Clock Path Skew:        0.203ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.452ns
    Source Clock Delay      (SCD):    1.249ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.129ns (routing 0.358ns, distribution 0.771ns)
  Clock Net Delay (Destination): 1.305ns (routing 0.404ns, distribution 0.901ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.129     1.249    d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X49Y147        FDRE                                         r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y147        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     1.288 r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=120, routed)         0.476     1.764    d_1_i/axi_smc/inst/s02_entry_pipeline/s02_mmu/inst/xpm_cdc_async_rst_inst/src_arst
    SLICE_X23Y147        FDCE                                         f  d_1_i/axi_smc/inst/s02_entry_pipeline/s02_mmu/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.305     1.452    d_1_i/axi_smc/inst/s02_entry_pipeline/s02_mmu/inst/xpm_cdc_async_rst_inst/dest_clk
    SLICE_X23Y147        FDCE                                         r  d_1_i/axi_smc/inst/s02_entry_pipeline/s02_mmu/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/s02_entry_pipeline/s02_mmu/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.515ns  (logic 0.039ns (7.571%)  route 0.476ns (92.429%))
  Logic Levels:           0  
  Clock Path Skew:        0.203ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.452ns
    Source Clock Delay      (SCD):    1.249ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.129ns (routing 0.358ns, distribution 0.771ns)
  Clock Net Delay (Destination): 1.305ns (routing 0.404ns, distribution 0.901ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.129     1.249    d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X49Y147        FDRE                                         r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y147        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     1.288 r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=120, routed)         0.476     1.764    d_1_i/axi_smc/inst/s02_entry_pipeline/s02_mmu/inst/xpm_cdc_async_rst_inst/src_arst
    SLICE_X23Y147        FDCE                                         f  d_1_i/axi_smc/inst/s02_entry_pipeline/s02_mmu/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.305     1.452    d_1_i/axi_smc/inst/s02_entry_pipeline/s02_mmu/inst/xpm_cdc_async_rst_inst/dest_clk
    SLICE_X23Y147        FDCE                                         r  d_1_i/axi_smc/inst/s02_entry_pipeline/s02_mmu/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/s02_entry_pipeline/s02_mmu/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.515ns  (logic 0.039ns (7.571%)  route 0.476ns (92.429%))
  Logic Levels:           0  
  Clock Path Skew:        0.203ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.452ns
    Source Clock Delay      (SCD):    1.249ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.129ns (routing 0.358ns, distribution 0.771ns)
  Clock Net Delay (Destination): 1.305ns (routing 0.404ns, distribution 0.901ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.129     1.249    d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X49Y147        FDRE                                         r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y147        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     1.288 r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=120, routed)         0.476     1.764    d_1_i/axi_smc/inst/s02_entry_pipeline/s02_mmu/inst/xpm_cdc_async_rst_inst/src_arst
    SLICE_X23Y147        FDCE                                         f  d_1_i/axi_smc/inst/s02_entry_pipeline/s02_mmu/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.305     1.452    d_1_i/axi_smc/inst/s02_entry_pipeline/s02_mmu/inst/xpm_cdc_async_rst_inst/dest_clk
    SLICE_X23Y147        FDCE                                         r  d_1_i/axi_smc/inst/s02_entry_pipeline/s02_mmu/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[2]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  mmcm_clkout5
  To Clock:  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK

Max Delay            94 Endpoints
Min Delay           102 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[0]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.480ns  (logic 0.078ns (5.270%)  route 1.402ns (94.730%))
  Logic Levels:           0  
  Clock Path Skew:        1.202ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.449ns
    Source Clock Delay      (SCD):    4.247ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.494ns (routing 0.539ns, distribution 0.955ns)
  Clock Net Delay (Destination): 2.607ns (routing 1.525ns, distribution 1.082ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.725    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.753 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.494     4.247    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X110Y338       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X110Y338       FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     4.325 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         1.402     5.727    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/SR[0]
    SLICE_X113Y338       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[0]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.353     2.818    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.842 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.607     5.449    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/m_bscan_tck[0]
    SLICE_X113Y338       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[0]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[10]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.480ns  (logic 0.078ns (5.270%)  route 1.402ns (94.730%))
  Logic Levels:           0  
  Clock Path Skew:        1.202ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.449ns
    Source Clock Delay      (SCD):    4.247ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.494ns (routing 0.539ns, distribution 0.955ns)
  Clock Net Delay (Destination): 2.607ns (routing 1.525ns, distribution 1.082ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.725    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.753 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.494     4.247    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X110Y338       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X110Y338       FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     4.325 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         1.402     5.727    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/SR[0]
    SLICE_X113Y338       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[10]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.353     2.818    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.842 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.607     5.449    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/m_bscan_tck[0]
    SLICE_X113Y338       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[10]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[11]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.480ns  (logic 0.078ns (5.270%)  route 1.402ns (94.730%))
  Logic Levels:           0  
  Clock Path Skew:        1.202ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.449ns
    Source Clock Delay      (SCD):    4.247ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.494ns (routing 0.539ns, distribution 0.955ns)
  Clock Net Delay (Destination): 2.607ns (routing 1.525ns, distribution 1.082ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.725    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.753 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.494     4.247    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X110Y338       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X110Y338       FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     4.325 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         1.402     5.727    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/SR[0]
    SLICE_X113Y338       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[11]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.353     2.818    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.842 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.607     5.449    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/m_bscan_tck[0]
    SLICE_X113Y338       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[11]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[1]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.480ns  (logic 0.078ns (5.270%)  route 1.402ns (94.730%))
  Logic Levels:           0  
  Clock Path Skew:        1.202ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.449ns
    Source Clock Delay      (SCD):    4.247ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.494ns (routing 0.539ns, distribution 0.955ns)
  Clock Net Delay (Destination): 2.607ns (routing 1.525ns, distribution 1.082ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.725    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.753 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.494     4.247    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X110Y338       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X110Y338       FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     4.325 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         1.402     5.727    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/SR[0]
    SLICE_X113Y338       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[1]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.353     2.818    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.842 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.607     5.449    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/m_bscan_tck[0]
    SLICE_X113Y338       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[1]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[6]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.480ns  (logic 0.078ns (5.270%)  route 1.402ns (94.730%))
  Logic Levels:           0  
  Clock Path Skew:        1.202ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.449ns
    Source Clock Delay      (SCD):    4.247ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.494ns (routing 0.539ns, distribution 0.955ns)
  Clock Net Delay (Destination): 2.607ns (routing 1.525ns, distribution 1.082ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.725    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.753 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.494     4.247    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X110Y338       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X110Y338       FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     4.325 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         1.402     5.727    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/SR[0]
    SLICE_X113Y338       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[6]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.353     2.818    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.842 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.607     5.449    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/m_bscan_tck[0]
    SLICE_X113Y338       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[6]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[7]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.480ns  (logic 0.078ns (5.270%)  route 1.402ns (94.730%))
  Logic Levels:           0  
  Clock Path Skew:        1.202ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.449ns
    Source Clock Delay      (SCD):    4.247ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.494ns (routing 0.539ns, distribution 0.955ns)
  Clock Net Delay (Destination): 2.607ns (routing 1.525ns, distribution 1.082ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.725    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.753 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.494     4.247    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X110Y338       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X110Y338       FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     4.325 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         1.402     5.727    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/SR[0]
    SLICE_X113Y338       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[7]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.353     2.818    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.842 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.607     5.449    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/m_bscan_tck[0]
    SLICE_X113Y338       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[7]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[8]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.480ns  (logic 0.078ns (5.270%)  route 1.402ns (94.730%))
  Logic Levels:           0  
  Clock Path Skew:        1.202ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.449ns
    Source Clock Delay      (SCD):    4.247ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.494ns (routing 0.539ns, distribution 0.955ns)
  Clock Net Delay (Destination): 2.607ns (routing 1.525ns, distribution 1.082ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.725    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.753 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.494     4.247    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X110Y338       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X110Y338       FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     4.325 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         1.402     5.727    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/SR[0]
    SLICE_X113Y338       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[8]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.353     2.818    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.842 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.607     5.449    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/m_bscan_tck[0]
    SLICE_X113Y338       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[8]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[9]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.480ns  (logic 0.078ns (5.270%)  route 1.402ns (94.730%))
  Logic Levels:           0  
  Clock Path Skew:        1.202ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.449ns
    Source Clock Delay      (SCD):    4.247ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.494ns (routing 0.539ns, distribution 0.955ns)
  Clock Net Delay (Destination): 2.607ns (routing 1.525ns, distribution 1.082ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.725    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.753 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.494     4.247    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X110Y338       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X110Y338       FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     4.325 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         1.402     5.727    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/SR[0]
    SLICE_X113Y338       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[9]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.353     2.818    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.842 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.607     5.449    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/m_bscan_tck[0]
    SLICE_X113Y338       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[9]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[2]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.477ns  (logic 0.078ns (5.281%)  route 1.399ns (94.719%))
  Logic Levels:           0  
  Clock Path Skew:        1.201ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.448ns
    Source Clock Delay      (SCD):    4.247ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.494ns (routing 0.539ns, distribution 0.955ns)
  Clock Net Delay (Destination): 2.606ns (routing 1.525ns, distribution 1.081ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.725    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.753 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.494     4.247    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X110Y338       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X110Y338       FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     4.325 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         1.399     5.724    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/SR[0]
    SLICE_X113Y338       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[2]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.353     2.818    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.842 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.606     5.448    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/m_bscan_tck[0]
    SLICE_X113Y338       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[2]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[3]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.477ns  (logic 0.078ns (5.281%)  route 1.399ns (94.719%))
  Logic Levels:           0  
  Clock Path Skew:        1.201ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.448ns
    Source Clock Delay      (SCD):    4.247ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.494ns (routing 0.539ns, distribution 0.955ns)
  Clock Net Delay (Destination): 2.606ns (routing 1.525ns, distribution 1.081ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.725    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.753 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.494     4.247    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X110Y338       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X110Y338       FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     4.325 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         1.399     5.724    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/SR[0]
    SLICE_X113Y338       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[3]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.353     2.818    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.842 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.606     5.448    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/m_bscan_tck[0]
    SLICE_X113Y338       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[3]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_1_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.120ns  (logic 0.040ns (33.333%)  route 0.080ns (66.667%))
  Logic Levels:           0  
  Clock Path Skew:        5.892ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.558ns
    Source Clock Delay      (SCD):    2.666ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.819ns (routing 0.299ns, distribution 0.520ns)
  Clock Net Delay (Destination): 1.789ns (routing 1.028ns, distribution 0.761ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.830    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.847 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.819     2.666    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/clk
    SLICE_X111Y331       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X111Y331       FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.040     2.706 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_reg[3]/Q
                         net (fo=1, routed)           0.080     2.786    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg[3]
    SLICE_X111Y332       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_1_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.450     6.750    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.769 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.789     8.558    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/m_bscan_tck[0]
    SLICE_X111Y332       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_1_reg[3]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_1_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.119ns  (logic 0.040ns (33.613%)  route 0.079ns (66.387%))
  Logic Levels:           0  
  Clock Path Skew:        5.896ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.563ns
    Source Clock Delay      (SCD):    2.667ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.820ns (routing 0.299ns, distribution 0.521ns)
  Clock Net Delay (Destination): 1.794ns (routing 1.028ns, distribution 0.766ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.830    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.847 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.820     2.667    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/clk
    SLICE_X111Y333       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X111Y333       FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.040     2.707 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_reg[1]/Q
                         net (fo=1, routed)           0.079     2.786    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg[1]
    SLICE_X111Y334       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_1_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.450     6.750    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.769 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.794     8.563    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/m_bscan_tck[0]
    SLICE_X111Y334       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_1_reg[1]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_1_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.119ns  (logic 0.040ns (33.613%)  route 0.079ns (66.387%))
  Logic Levels:           0  
  Clock Path Skew:        5.889ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.557ns
    Source Clock Delay      (SCD):    2.668ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.821ns (routing 0.299ns, distribution 0.522ns)
  Clock Net Delay (Destination): 1.788ns (routing 1.028ns, distribution 0.760ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.830    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.847 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.821     2.668    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/clk
    SLICE_X114Y332       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X114Y332       FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.040     2.708 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_reg[0]/Q
                         net (fo=1, routed)           0.079     2.787    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg[0]
    SLICE_X114Y333       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_1_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.450     6.750    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.769 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.788     8.557    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/m_bscan_tck[0]
    SLICE_X114Y333       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_1_reg[0]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_1_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.125ns  (logic 0.039ns (31.200%)  route 0.086ns (68.800%))
  Logic Levels:           0  
  Clock Path Skew:        5.898ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.561ns
    Source Clock Delay      (SCD):    2.663ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.816ns (routing 0.299ns, distribution 0.517ns)
  Clock Net Delay (Destination): 1.792ns (routing 1.028ns, distribution 0.764ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.830    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.847 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.816     2.663    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/clk
    SLICE_X113Y331       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X113Y331       FDRE (Prop_AFF2_SLICEM_C_Q)
                                                      0.039     2.702 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_reg[1]/Q
                         net (fo=1, routed)           0.086     2.788    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg[1]
    SLICE_X113Y332       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_1_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.450     6.750    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.769 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.792     8.561    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/m_bscan_tck[0]
    SLICE_X113Y332       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_1_reg[1]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_1_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.124ns  (logic 0.039ns (31.452%)  route 0.085ns (68.548%))
  Logic Levels:           0  
  Clock Path Skew:        5.897ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.562ns
    Source Clock Delay      (SCD):    2.665ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.818ns (routing 0.299ns, distribution 0.519ns)
  Clock Net Delay (Destination): 1.793ns (routing 1.028ns, distribution 0.765ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.830    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.847 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.818     2.665    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/clk
    SLICE_X112Y334       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X112Y334       FDRE (Prop_AFF2_SLICEM_C_Q)
                                                      0.039     2.704 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_reg[2]/Q
                         net (fo=1, routed)           0.085     2.789    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg[2]
    SLICE_X112Y335       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_1_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.450     6.750    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.769 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.793     8.562    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/m_bscan_tck[0]
    SLICE_X112Y335       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_1_reg[2]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_1_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.124ns  (logic 0.039ns (31.452%)  route 0.085ns (68.548%))
  Logic Levels:           0  
  Clock Path Skew:        5.898ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.563ns
    Source Clock Delay      (SCD):    2.665ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.818ns (routing 0.299ns, distribution 0.519ns)
  Clock Net Delay (Destination): 1.794ns (routing 1.028ns, distribution 0.766ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.830    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.847 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.818     2.665    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/clk
    SLICE_X115Y332       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X115Y332       FDRE (Prop_AFF2_SLICEM_C_Q)
                                                      0.039     2.704 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_reg[2]/Q
                         net (fo=1, routed)           0.085     2.789    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg[2]
    SLICE_X115Y333       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_1_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.450     6.750    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.769 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.794     8.563    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/m_bscan_tck[0]
    SLICE_X115Y333       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_1_reg[2]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_1_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.124ns  (logic 0.039ns (31.452%)  route 0.085ns (68.548%))
  Logic Levels:           0  
  Clock Path Skew:        5.894ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.560ns
    Source Clock Delay      (SCD):    2.666ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.819ns (routing 0.299ns, distribution 0.520ns)
  Clock Net Delay (Destination): 1.791ns (routing 1.028ns, distribution 0.763ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.830    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.847 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.819     2.666    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/clk
    SLICE_X109Y333       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X109Y333       FDRE (Prop_AFF2_SLICEM_C_Q)
                                                      0.039     2.705 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_reg[2]/Q
                         net (fo=1, routed)           0.085     2.790    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg[2]
    SLICE_X109Y334       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_1_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.450     6.750    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.769 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.791     8.560    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/m_bscan_tck[0]
    SLICE_X109Y334       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_1_reg[2]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_1_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.124ns  (logic 0.039ns (31.452%)  route 0.085ns (68.548%))
  Logic Levels:           0  
  Clock Path Skew:        5.893ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.561ns
    Source Clock Delay      (SCD):    2.668ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.821ns (routing 0.299ns, distribution 0.522ns)
  Clock Net Delay (Destination): 1.792ns (routing 1.028ns, distribution 0.764ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.830    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.847 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.821     2.668    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/clk
    SLICE_X112Y332       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X112Y332       FDRE (Prop_AFF2_SLICEM_C_Q)
                                                      0.039     2.707 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_reg[0]/Q
                         net (fo=1, routed)           0.085     2.792    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg[0]
    SLICE_X112Y333       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_1_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.450     6.750    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.769 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.792     8.561    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/m_bscan_tck[0]
    SLICE_X112Y333       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_1_reg[0]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[2]/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.127ns  (logic 0.038ns (29.921%)  route 0.089ns (70.079%))
  Logic Levels:           0  
  Clock Path Skew:        5.904ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.569ns
    Source Clock Delay      (SCD):    2.665ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.818ns (routing 0.299ns, distribution 0.519ns)
  Clock Net Delay (Destination): 1.800ns (routing 1.028ns, distribution 0.772ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.830    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.847 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.818     2.665    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_clk
    SLICE_X109Y339       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X109Y339       FDCE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     2.703 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[2]/Q
                         net (fo=1, routed)           0.089     2.792    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q[2]
    SLICE_X109Y341       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.450     6.750    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.769 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.800     8.569    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/wr_clk
    SLICE_X109Y341       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[2]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_1_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.124ns  (logic 0.039ns (31.452%)  route 0.085ns (68.548%))
  Logic Levels:           0  
  Clock Path Skew:        5.894ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.563ns
    Source Clock Delay      (SCD):    2.669ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.822ns (routing 0.299ns, distribution 0.523ns)
  Clock Net Delay (Destination): 1.794ns (routing 1.028ns, distribution 0.766ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.830    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.847 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.822     2.669    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/clk
    SLICE_X110Y331       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X110Y331       FDRE (Prop_AFF2_SLICEM_C_Q)
                                                      0.039     2.708 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_reg[1]/Q
                         net (fo=1, routed)           0.085     2.793    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg[1]
    SLICE_X110Y332       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_1_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.450     6.750    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.769 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.794     8.563    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/m_bscan_tck[0]
    SLICE_X110Y332       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_1_reg[1]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFDAC0_CLK
  To Clock:  mmcm_clkout0

Max Delay             1 Endpoint
Min Delay             1 Endpoint
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[9]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/trigger_resync_i/data_int_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.851ns  (logic 0.079ns (4.268%)  route 1.772ns (95.732%))
  Logic Levels:           0  
  Clock Path Skew:        1.676ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.329ns
    Source Clock Delay      (SCD):    3.653ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.980ns (routing 1.381ns, distribution 1.599ns)
  Clock Net Delay (Destination): 2.176ns (routing 0.716ns, distribution 1.460ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       2.980     3.653    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X19Y400        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[9]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X19Y400        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     3.732 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[9]/Q
                         net (fo=2, routed)           1.772     5.504    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/trigger_resync_i/trigger
    SLICE_X17Y216        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/trigger_resync_i/data_int_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.129    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.176     5.329    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/trigger_resync_i/aclk
    SLICE_X17Y216        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/trigger_resync_i/data_int_reg_reg[0]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[9]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/trigger_resync_i/data_int_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.933ns  (logic 0.039ns (4.181%)  route 0.894ns (95.819%))
  Logic Levels:           0  
  Clock Path Skew:        1.140ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.121ns
    Source Clock Delay      (SCD):    1.981ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.632ns (routing 0.748ns, distribution 0.884ns)
  Clock Net Delay (Destination): 1.502ns (routing 0.485ns, distribution 1.017ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=91136, routed)       1.632     1.981    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X19Y400        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[9]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X19Y400        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     2.020 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[9]/Q
                         net (fo=2, routed)           0.894     2.914    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/trigger_resync_i/trigger
    SLICE_X17Y216        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/trigger_resync_i/data_int_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.502     3.121    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/trigger_resync_i/aclk
    SLICE_X17Y216        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/trigger_resync_i/data_int_reg_reg[0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_out1_d_1_clk_adc0_x2_0
  To Clock:  mmcm_clkout0

Max Delay           518 Endpoints
Min Delay           518 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_238_251/RAMF/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[248]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.208ns  (logic 0.295ns (24.421%)  route 0.913ns (75.579%))
  Logic Levels:           0  
  Clock Path Skew:        -0.298ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.172ns
    Source Clock Delay      (SCD):    5.470ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      2.202ns (routing 0.858ns, distribution 1.344ns)
  Clock Net Delay (Destination): 2.019ns (routing 0.716ns, distribution 1.303ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.595     3.122    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.995 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.240    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.268 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       2.202     5.470    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_238_251/WCLK
    SLICE_X37Y233        RAMD32                                       r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_238_251/RAMF/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X37Y233        RAMD32 (Prop_F5LUT_SLICEM_CLK_O)
                                                      0.295     5.765 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_238_251/RAMF/O
                         net (fo=1, routed)           0.913     6.678    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[248]
    SLICE_X43Y238        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[248]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.129    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.019     5.172    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X43Y238        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[248]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_238_251/RAMC_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[243]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.121ns  (logic 0.307ns (27.386%)  route 0.814ns (72.614%))
  Logic Levels:           0  
  Clock Path Skew:        -0.298ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.172ns
    Source Clock Delay      (SCD):    5.470ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      2.202ns (routing 0.858ns, distribution 1.344ns)
  Clock Net Delay (Destination): 2.019ns (routing 0.716ns, distribution 1.303ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.595     3.122    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.995 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.240    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.268 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       2.202     5.470    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_238_251/WCLK
    SLICE_X37Y233        RAMD32                                       r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_238_251/RAMC_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X37Y233        RAMD32 (Prop_C6LUT_SLICEM_CLK_O)
                                                      0.307     5.777 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_238_251/RAMC_D1/O
                         net (fo=1, routed)           0.814     6.591    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[243]
    SLICE_X43Y235        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[243]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.129    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.019     5.172    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X43Y235        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[243]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_238_251/RAMC/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[242]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.121ns  (logic 0.288ns (25.691%)  route 0.833ns (74.309%))
  Logic Levels:           0  
  Clock Path Skew:        -0.294ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.176ns
    Source Clock Delay      (SCD):    5.470ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      2.202ns (routing 0.858ns, distribution 1.344ns)
  Clock Net Delay (Destination): 2.023ns (routing 0.716ns, distribution 1.307ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.595     3.122    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.995 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.240    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.268 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       2.202     5.470    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_238_251/WCLK
    SLICE_X37Y233        RAMD32                                       r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_238_251/RAMC/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X37Y233        RAMD32 (Prop_C5LUT_SLICEM_CLK_O)
                                                      0.288     5.758 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_238_251/RAMC/O
                         net (fo=1, routed)           0.833     6.591    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[242]
    SLICE_X41Y238        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[242]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.129    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.023     5.176    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X41Y238        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[242]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAME/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[36]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.129ns  (logic 0.288ns (25.509%)  route 0.841ns (74.491%))
  Logic Levels:           0  
  Clock Path Skew:        -0.291ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.168ns
    Source Clock Delay      (SCD):    5.459ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      2.191ns (routing 0.858ns, distribution 1.333ns)
  Clock Net Delay (Destination): 2.015ns (routing 0.716ns, distribution 1.299ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.595     3.122    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.995 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.240    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.268 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       2.191     5.459    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/WCLK
    SLICE_X35Y216        RAMD32                                       r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAME/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X35Y216        RAMD32 (Prop_E5LUT_SLICEM_CLK_O)
                                                      0.288     5.747 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAME/O
                         net (fo=1, routed)           0.841     6.588    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[36]
    SLICE_X39Y218        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[36]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.129    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.015     5.168    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X39Y218        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[36]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27/RAMB_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[17]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.120ns  (logic 0.307ns (27.411%)  route 0.813ns (72.589%))
  Logic Levels:           0  
  Clock Path Skew:        -0.289ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.168ns
    Source Clock Delay      (SCD):    5.457ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      2.189ns (routing 0.858ns, distribution 1.331ns)
  Clock Net Delay (Destination): 2.015ns (routing 0.716ns, distribution 1.299ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.595     3.122    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.995 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.240    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.268 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       2.189     5.457    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27/WCLK
    SLICE_X37Y217        RAMD32                                       r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27/RAMB_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X37Y217        RAMD32 (Prop_B6LUT_SLICEM_CLK_O)
                                                      0.307     5.764 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27/RAMB_D1/O
                         net (fo=1, routed)           0.813     6.577    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[17]
    SLICE_X39Y218        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[17]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.129    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.015     5.168    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X39Y218        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[17]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_266_279/RAME/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[274]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.106ns  (logic 0.288ns (26.040%)  route 0.818ns (73.960%))
  Logic Levels:           0  
  Clock Path Skew:        -0.296ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.172ns
    Source Clock Delay      (SCD):    5.468ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      2.200ns (routing 0.858ns, distribution 1.342ns)
  Clock Net Delay (Destination): 2.019ns (routing 0.716ns, distribution 1.303ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.595     3.122    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.995 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.240    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.268 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       2.200     5.468    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_266_279/WCLK
    SLICE_X37Y228        RAMD32                                       r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_266_279/RAME/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X37Y228        RAMD32 (Prop_E5LUT_SLICEM_CLK_O)
                                                      0.288     5.756 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_266_279/RAME/O
                         net (fo=1, routed)           0.818     6.574    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[274]
    SLICE_X43Y235        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[274]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.129    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.019     5.172    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X43Y235        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[274]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMC_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[33]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.106ns  (logic 0.307ns (27.758%)  route 0.799ns (72.242%))
  Logic Levels:           0  
  Clock Path Skew:        -0.286ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.173ns
    Source Clock Delay      (SCD):    5.459ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      2.191ns (routing 0.858ns, distribution 1.333ns)
  Clock Net Delay (Destination): 2.020ns (routing 0.716ns, distribution 1.304ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.595     3.122    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.995 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.240    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.268 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       2.191     5.459    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/WCLK
    SLICE_X35Y216        RAMD32                                       r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMC_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X35Y216        RAMD32 (Prop_C6LUT_SLICEM_CLK_O)
                                                      0.307     5.766 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMC_D1/O
                         net (fo=1, routed)           0.799     6.565    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[33]
    SLICE_X38Y228        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[33]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.129    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.020     5.173    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X38Y228        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[33]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMF/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[38]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.085ns  (logic 0.295ns (27.189%)  route 0.790ns (72.811%))
  Logic Levels:           0  
  Clock Path Skew:        -0.291ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.168ns
    Source Clock Delay      (SCD):    5.459ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      2.191ns (routing 0.858ns, distribution 1.333ns)
  Clock Net Delay (Destination): 2.015ns (routing 0.716ns, distribution 1.299ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.595     3.122    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.995 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.240    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.268 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       2.191     5.459    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/WCLK
    SLICE_X35Y216        RAMD32                                       r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMF/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X35Y216        RAMD32 (Prop_F5LUT_SLICEM_CLK_O)
                                                      0.295     5.754 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMF/O
                         net (fo=1, routed)           0.790     6.544    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[38]
    SLICE_X39Y218        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[38]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.129    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.015     5.168    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X39Y218        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[38]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/RAMB_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[45]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.067ns  (logic 0.307ns (28.772%)  route 0.760ns (71.228%))
  Logic Levels:           0  
  Clock Path Skew:        -0.305ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.172ns
    Source Clock Delay      (SCD):    5.477ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      2.209ns (routing 0.858ns, distribution 1.351ns)
  Clock Net Delay (Destination): 2.019ns (routing 0.716ns, distribution 1.303ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.595     3.122    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.995 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.240    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.268 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       2.209     5.477    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/WCLK
    SLICE_X34Y229        RAMD32                                       r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/RAMB_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X34Y229        RAMD32 (Prop_B6LUT_SLICEM_CLK_O)
                                                      0.307     5.784 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/RAMB_D1/O
                         net (fo=1, routed)           0.760     6.544    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[45]
    SLICE_X38Y227        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[45]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.129    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.019     5.172    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X38Y227        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[45]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27/RAMD_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[21]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.084ns  (logic 0.301ns (27.768%)  route 0.783ns (72.232%))
  Logic Levels:           0  
  Clock Path Skew:        -0.289ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.168ns
    Source Clock Delay      (SCD):    5.457ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      2.189ns (routing 0.858ns, distribution 1.331ns)
  Clock Net Delay (Destination): 2.015ns (routing 0.716ns, distribution 1.299ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.595     3.122    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.995 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.240    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.268 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       2.189     5.457    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27/WCLK
    SLICE_X37Y217        RAMD32                                       r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27/RAMD_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X37Y217        RAMD32 (Prop_D6LUT_SLICEM_CLK_O)
                                                      0.301     5.758 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_14_27/RAMD_D1/O
                         net (fo=1, routed)           0.783     6.541    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[21]
    SLICE_X39Y218        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[21]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.129    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.015     5.168    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X39Y218        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[21]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.146ns  (logic 0.039ns (26.712%)  route 0.107ns (73.288%))
  Logic Levels:           0  
  Clock Path Skew:        -0.214ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.010ns
    Source Clock Delay      (SCD):    3.224ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      1.153ns (routing 0.470ns, distribution 0.683ns)
  Clock Net Delay (Destination): 1.391ns (routing 0.485ns, distribution 0.906ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.415     1.678    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.908 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.054    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.071 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.153     3.224    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk
    SLICE_X40Y227        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X40Y227        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.039     3.263 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/Q
                         net (fo=1, routed)           0.107     3.370    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[3]
    SLICE_X40Y226        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.391     3.010    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk
    SLICE_X40Y226        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.161ns  (logic 0.039ns (24.224%)  route 0.122ns (75.776%))
  Logic Levels:           0  
  Clock Path Skew:        -0.214ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.010ns
    Source Clock Delay      (SCD):    3.224ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      1.153ns (routing 0.470ns, distribution 0.683ns)
  Clock Net Delay (Destination): 1.391ns (routing 0.485ns, distribution 0.906ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.415     1.678    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.908 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.054    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.071 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.153     3.224    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk
    SLICE_X40Y227        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X40Y227        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     3.263 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]/Q
                         net (fo=1, routed)           0.122     3.385    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[2]
    SLICE_X40Y226        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.391     3.010    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk
    SLICE_X40Y226        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153/RAMG_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[153]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.157ns  (logic 0.105ns (66.879%)  route 0.052ns (33.121%))
  Logic Levels:           0  
  Clock Path Skew:        -0.232ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.003ns
    Source Clock Delay      (SCD):    3.235ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      1.164ns (routing 0.470ns, distribution 0.694ns)
  Clock Net Delay (Destination): 1.384ns (routing 0.485ns, distribution 0.899ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.415     1.678    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.908 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.054    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.071 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.164     3.235    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153/WCLK
    SLICE_X46Y235        RAMD32                                       r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153/RAMG_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X46Y235        RAMD32 (Prop_G6LUT_SLICEM_CLK_O)
                                                      0.105     3.340 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153/RAMG_D1/O
                         net (fo=1, routed)           0.052     3.392    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[153]
    SLICE_X47Y235        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[153]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.384     3.003    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X47Y235        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[153]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153/RAME_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[149]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.172ns  (logic 0.108ns (62.791%)  route 0.064ns (37.209%))
  Logic Levels:           0  
  Clock Path Skew:        -0.232ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.003ns
    Source Clock Delay      (SCD):    3.235ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      1.164ns (routing 0.470ns, distribution 0.694ns)
  Clock Net Delay (Destination): 1.384ns (routing 0.485ns, distribution 0.899ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.415     1.678    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.908 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.054    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.071 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.164     3.235    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153/WCLK
    SLICE_X46Y235        RAMD32                                       r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153/RAME_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X46Y235        RAMD32 (Prop_E6LUT_SLICEM_CLK_O)
                                                      0.108     3.343 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153/RAME_D1/O
                         net (fo=1, routed)           0.064     3.407    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[149]
    SLICE_X47Y235        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[149]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.384     3.003    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X47Y235        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[149]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_224_237/RAMB_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[227]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.163ns  (logic 0.110ns (67.485%)  route 0.053ns (32.515%))
  Logic Levels:           0  
  Clock Path Skew:        -0.216ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.030ns
    Source Clock Delay      (SCD):    3.246ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      1.175ns (routing 0.470ns, distribution 0.705ns)
  Clock Net Delay (Destination): 1.411ns (routing 0.485ns, distribution 0.926ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.415     1.678    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.908 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.054    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.071 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.175     3.246    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_224_237/WCLK
    SLICE_X48Y252        RAMD32                                       r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_224_237/RAMB_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X48Y252        RAMD32 (Prop_B6LUT_SLICEM_CLK_O)
                                                      0.110     3.356 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_224_237/RAMB_D1/O
                         net (fo=1, routed)           0.053     3.409    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[227]
    SLICE_X49Y252        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[227]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.411     3.030    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X49Y252        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[227]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_252_265/RAMG/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[264]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.180ns  (logic 0.105ns (58.333%)  route 0.075ns (41.667%))
  Logic Levels:           0  
  Clock Path Skew:        -0.234ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.998ns
    Source Clock Delay      (SCD):    3.232ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      1.161ns (routing 0.470ns, distribution 0.691ns)
  Clock Net Delay (Destination): 1.379ns (routing 0.485ns, distribution 0.894ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.415     1.678    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.908 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.054    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.071 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.161     3.232    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_252_265/WCLK
    SLICE_X48Y230        RAMD32                                       r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_252_265/RAMG/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X48Y230        RAMD32 (Prop_G5LUT_SLICEM_CLK_O)
                                                      0.105     3.337 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_252_265/RAMG/O
                         net (fo=1, routed)           0.075     3.412    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[264]
    SLICE_X50Y230        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[264]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.379     2.998    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X50Y230        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[264]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_294_307/RAME/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[302]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.189ns  (logic 0.108ns (57.143%)  route 0.081ns (42.857%))
  Logic Levels:           0  
  Clock Path Skew:        -0.226ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.005ns
    Source Clock Delay      (SCD):    3.231ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      1.160ns (routing 0.470ns, distribution 0.690ns)
  Clock Net Delay (Destination): 1.386ns (routing 0.485ns, distribution 0.901ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.415     1.678    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.908 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.054    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.071 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.160     3.231    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_294_307/WCLK
    SLICE_X46Y222        RAMD32                                       r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_294_307/RAME/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X46Y222        RAMD32 (Prop_E5LUT_SLICEM_CLK_O)
                                                      0.108     3.339 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_294_307/RAME/O
                         net (fo=1, routed)           0.081     3.420    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[302]
    SLICE_X46Y221        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[302]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.386     3.005    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X46Y221        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[302]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_378_391/RAMF_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[389]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.204ns  (logic 0.111ns (54.412%)  route 0.093ns (45.588%))
  Logic Levels:           0  
  Clock Path Skew:        -0.233ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.985ns
    Source Clock Delay      (SCD):    3.218ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      1.147ns (routing 0.470ns, distribution 0.677ns)
  Clock Net Delay (Destination): 1.366ns (routing 0.485ns, distribution 0.881ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.415     1.678    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.908 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.054    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.071 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.147     3.218    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_378_391/WCLK
    SLICE_X53Y210        RAMD32                                       r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_378_391/RAMF_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X53Y210        RAMD32 (Prop_F6LUT_SLICEM_CLK_O)
                                                      0.111     3.329 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_378_391/RAMF_D1/O
                         net (fo=1, routed)           0.093     3.422    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[389]
    SLICE_X52Y214        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[389]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.366     2.985    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X52Y214        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[389]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_224_237/RAMA_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[225]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.179ns  (logic 0.111ns (62.011%)  route 0.068ns (37.989%))
  Logic Levels:           0  
  Clock Path Skew:        -0.214ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.032ns
    Source Clock Delay      (SCD):    3.246ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      1.175ns (routing 0.470ns, distribution 0.705ns)
  Clock Net Delay (Destination): 1.413ns (routing 0.485ns, distribution 0.928ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.415     1.678    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.908 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.054    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.071 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.175     3.246    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_224_237/WCLK
    SLICE_X48Y252        RAMD32                                       r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_224_237/RAMA_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X48Y252        RAMD32 (Prop_A6LUT_SLICEM_CLK_O)
                                                      0.111     3.357 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_224_237/RAMA_D1/O
                         net (fo=1, routed)           0.068     3.425    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[225]
    SLICE_X47Y252        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[225]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.413     3.032    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X47Y252        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[225]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_462_475/RAMF_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[473]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.191ns  (logic 0.111ns (58.115%)  route 0.080ns (41.885%))
  Logic Levels:           0  
  Clock Path Skew:        -0.229ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.005ns
    Source Clock Delay      (SCD):    3.234ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      1.163ns (routing 0.470ns, distribution 0.693ns)
  Clock Net Delay (Destination): 1.386ns (routing 0.485ns, distribution 0.901ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.415     1.678    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.908 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.054    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.071 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.163     3.234    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_462_475/WCLK
    SLICE_X48Y188        RAMD32                                       r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_462_475/RAMF_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X48Y188        RAMD32 (Prop_F6LUT_SLICEM_CLK_O)
                                                      0.111     3.345 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_462_475/RAMF_D1/O
                         net (fo=1, routed)           0.080     3.425    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[473]
    SLICE_X47Y189        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[473]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.386     3.005    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X47Y189        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[473]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_pl_0
  To Clock:  mmcm_clkout0

Max Delay           106 Endpoints
Min Delay           106 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[23]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[23]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.239ns  (logic 0.080ns (6.457%)  route 1.159ns (93.543%))
  Logic Levels:           0  
  Clock Path Skew:        2.809ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.262ns
    Source Clock Delay      (SCD):    2.452ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.226ns (routing 0.662ns, distribution 1.564ns)
  Clock Net Delay (Destination): 2.109ns (routing 0.716ns, distribution 1.393ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.226     2.452    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X13Y196        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[23]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X13Y196        FDRE (Prop_DFF2_SLICEM_C_Q)
                                                      0.080     2.532 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[23]/Q
                         net (fo=2, routed)           1.159     3.691    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/WADDR_REG[23]
    SLICE_X30Y184        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[23]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.129    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.109     5.262    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X30Y184        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[23]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[19]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[19]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.221ns  (logic 0.080ns (6.552%)  route 1.141ns (93.448%))
  Logic Levels:           0  
  Clock Path Skew:        2.736ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.188ns
    Source Clock Delay      (SCD):    2.452ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.226ns (routing 0.662ns, distribution 1.564ns)
  Clock Net Delay (Destination): 2.035ns (routing 0.716ns, distribution 1.319ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.226     2.452    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X13Y196        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[19]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X13Y196        FDRE (Prop_BFF2_SLICEM_C_Q)
                                                      0.080     2.532 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[19]/Q
                         net (fo=2, routed)           1.141     3.673    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/WADDR_REG[19]
    SLICE_X40Y178        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[19]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.129    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.035     5.188    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X40Y178        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[19]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[30]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[30]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.158ns  (logic 0.079ns (6.820%)  route 1.079ns (93.180%))
  Logic Levels:           0  
  Clock Path Skew:        2.769ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.254ns
    Source Clock Delay      (SCD):    2.485ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.259ns (routing 0.662ns, distribution 1.597ns)
  Clock Net Delay (Destination): 2.101ns (routing 0.716ns, distribution 1.385ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.259     2.485    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X9Y190         FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[30]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X9Y190         FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     2.564 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[30]/Q
                         net (fo=2, routed)           1.079     3.644    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/WADDR_REG[30]
    SLICE_X31Y183        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[30]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.129    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.101     5.254    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X31Y183        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[30]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[26]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[26]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.149ns  (logic 0.079ns (6.878%)  route 1.070ns (93.122%))
  Logic Levels:           0  
  Clock Path Skew:        2.769ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.254ns
    Source Clock Delay      (SCD):    2.485ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.259ns (routing 0.662ns, distribution 1.597ns)
  Clock Net Delay (Destination): 2.101ns (routing 0.716ns, distribution 1.385ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.259     2.485    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X9Y190         FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[26]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X9Y190         FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.079     2.564 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[26]/Q
                         net (fo=2, routed)           1.070     3.634    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/WADDR_REG[26]
    SLICE_X31Y183        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[26]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.129    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.101     5.254    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X31Y183        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[26]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[25]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[25]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.133ns  (logic 0.081ns (7.149%)  route 1.052ns (92.851%))
  Logic Levels:           0  
  Clock Path Skew:        2.769ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.254ns
    Source Clock Delay      (SCD):    2.485ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.259ns (routing 0.662ns, distribution 1.597ns)
  Clock Net Delay (Destination): 2.101ns (routing 0.716ns, distribution 1.385ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.259     2.485    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X9Y190         FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[25]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X9Y190         FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.081     2.566 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[25]/Q
                         net (fo=2, routed)           1.052     3.618    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/WADDR_REG[25]
    SLICE_X31Y183        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[25]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.129    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.101     5.254    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X31Y183        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[25]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[24]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[24]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.110ns  (logic 0.079ns (7.117%)  route 1.031ns (92.883%))
  Logic Levels:           0  
  Clock Path Skew:        2.769ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.254ns
    Source Clock Delay      (SCD):    2.485ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.259ns (routing 0.662ns, distribution 1.597ns)
  Clock Net Delay (Destination): 2.101ns (routing 0.716ns, distribution 1.385ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.259     2.485    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X9Y190         FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[24]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X9Y190         FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     2.564 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[24]/Q
                         net (fo=2, routed)           1.031     3.595    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/WADDR_REG[24]
    SLICE_X31Y183        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[24]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.129    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.101     5.254    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X31Y183        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[24]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[31]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[31]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.077ns  (logic 0.081ns (7.518%)  route 0.996ns (92.482%))
  Logic Levels:           0  
  Clock Path Skew:        2.756ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.241ns
    Source Clock Delay      (SCD):    2.485ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.259ns (routing 0.662ns, distribution 1.597ns)
  Clock Net Delay (Destination): 2.088ns (routing 0.716ns, distribution 1.372ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.259     2.485    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X9Y190         FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[31]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X9Y190         FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     2.566 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[31]/Q
                         net (fo=2, routed)           0.996     3.563    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/WADDR_REG[31]
    SLICE_X33Y185        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[31]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.129    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.088     5.241    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X33Y185        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[31]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[28]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[28]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.017ns  (logic 0.079ns (7.768%)  route 0.938ns (92.232%))
  Logic Levels:           0  
  Clock Path Skew:        2.769ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.254ns
    Source Clock Delay      (SCD):    2.485ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.259ns (routing 0.662ns, distribution 1.597ns)
  Clock Net Delay (Destination): 2.101ns (routing 0.716ns, distribution 1.385ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.259     2.485    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X9Y190         FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[28]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X9Y190         FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.079     2.564 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[28]/Q
                         net (fo=2, routed)           0.938     3.502    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/WADDR_REG[28]
    SLICE_X31Y183        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[28]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.129    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.101     5.254    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X31Y183        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[28]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[21]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[21]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.041ns  (logic 0.077ns (7.398%)  route 0.964ns (92.602%))
  Logic Levels:           0  
  Clock Path Skew:        2.796ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.248ns
    Source Clock Delay      (SCD):    2.452ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.226ns (routing 0.662ns, distribution 1.564ns)
  Clock Net Delay (Destination): 2.095ns (routing 0.716ns, distribution 1.379ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.226     2.452    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X13Y196        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[21]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X13Y196        FDRE (Prop_CFF2_SLICEM_C_Q)
                                                      0.077     2.529 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[21]/Q
                         net (fo=2, routed)           0.964     3.493    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/WADDR_REG[21]
    SLICE_X33Y177        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[21]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.129    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.095     5.248    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X33Y177        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[21]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[29]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[29]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.969ns  (logic 0.080ns (8.256%)  route 0.889ns (91.744%))
  Logic Levels:           0  
  Clock Path Skew:        2.756ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.241ns
    Source Clock Delay      (SCD):    2.485ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.259ns (routing 0.662ns, distribution 1.597ns)
  Clock Net Delay (Destination): 2.088ns (routing 0.716ns, distribution 1.372ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.259     2.485    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X9Y190         FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[29]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X9Y190         FDRE (Prop_CFF2_SLICEL_C_Q)
                                                      0.080     2.565 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[29]/Q
                         net (fo=2, routed)           0.889     3.454    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/WADDR_REG[29]
    SLICE_X33Y185        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[29]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.129    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.088     5.241    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X33Y185        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[29]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg2_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/len_reg_r_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.122ns  (logic 0.040ns (32.702%)  route 0.082ns (67.297%))
  Logic Levels:           0  
  Clock Path Skew:        1.810ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.078ns
    Source Clock Delay      (SCD):    1.268ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.148ns (routing 0.358ns, distribution 0.790ns)
  Clock Net Delay (Destination): 1.459ns (routing 0.485ns, distribution 0.974ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.148     1.268    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X29Y182        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg2_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X29Y182        FDRE (Prop_CFF2_SLICEL_C_Q)
                                                      0.040     1.308 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg2_reg[5]/Q
                         net (fo=2, routed)           0.082     1.390    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/RLENGTH_REG[5]
    SLICE_X29Y182        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/len_reg_r_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.459     3.078    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/aclk
    SLICE_X29Y182        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/len_reg_r_reg[5]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg2_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/len_reg_r_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.128ns  (logic 0.039ns (30.540%)  route 0.089ns (69.460%))
  Logic Levels:           0  
  Clock Path Skew:        1.810ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.078ns
    Source Clock Delay      (SCD):    1.268ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.148ns (routing 0.358ns, distribution 0.790ns)
  Clock Net Delay (Destination): 1.459ns (routing 0.485ns, distribution 0.974ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.148     1.268    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X29Y182        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg2_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X29Y182        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.039     1.307 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg2_reg[0]/Q
                         net (fo=2, routed)           0.089     1.396    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/RLENGTH_REG[0]
    SLICE_X29Y182        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/len_reg_r_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.459     3.078    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/aclk
    SLICE_X29Y182        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/len_reg_r_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.121ns  (logic 0.038ns (31.290%)  route 0.083ns (68.710%))
  Logic Levels:           0  
  Clock Path Skew:        1.806ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.082ns
    Source Clock Delay      (SCD):    1.276ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.156ns (routing 0.358ns, distribution 0.798ns)
  Clock Net Delay (Destination): 1.463ns (routing 0.485ns, distribution 0.978ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.156     1.276    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X31Y173        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X31Y173        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     1.314 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[0]/Q
                         net (fo=2, routed)           0.083     1.397    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/WADDR_REG[0]
    SLICE_X31Y173        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.463     3.082    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X31Y173        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg2_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/len_reg_r_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.134ns  (logic 0.039ns (29.173%)  route 0.095ns (70.826%))
  Logic Levels:           0  
  Clock Path Skew:        1.810ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.078ns
    Source Clock Delay      (SCD):    1.268ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.148ns (routing 0.358ns, distribution 0.790ns)
  Clock Net Delay (Destination): 1.459ns (routing 0.485ns, distribution 0.974ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.148     1.268    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X29Y182        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg2_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X29Y182        FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.039     1.307 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg2_reg[4]/Q
                         net (fo=2, routed)           0.095     1.402    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/RLENGTH_REG[4]
    SLICE_X29Y182        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/len_reg_r_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.459     3.078    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/aclk
    SLICE_X29Y182        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/len_reg_r_reg[4]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg5_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/nburst_reg_r_reg[6]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.132ns  (logic 0.039ns (29.617%)  route 0.093ns (70.383%))
  Logic Levels:           0  
  Clock Path Skew:        1.798ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.075ns
    Source Clock Delay      (SCD):    1.277ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.157ns (routing 0.358ns, distribution 0.799ns)
  Clock Net Delay (Destination): 1.456ns (routing 0.485ns, distribution 0.971ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.157     1.277    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X24Y194        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg5_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X24Y194        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     1.316 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg5_reg[6]/Q
                         net (fo=2, routed)           0.093     1.409    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/WNBURST_REG[6]
    SLICE_X24Y194        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/nburst_reg_r_reg[6]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.456     3.075    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X24Y194        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/nburst_reg_r_reg[6]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg5_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/nburst_reg_r_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.137ns  (logic 0.038ns (27.802%)  route 0.099ns (72.198%))
  Logic Levels:           0  
  Clock Path Skew:        1.798ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.075ns
    Source Clock Delay      (SCD):    1.277ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.157ns (routing 0.358ns, distribution 0.799ns)
  Clock Net Delay (Destination): 1.456ns (routing 0.485ns, distribution 0.971ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.157     1.277    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X24Y194        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg5_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X24Y194        FDRE (Prop_CFF_SLICEM_C_Q)
                                                      0.038     1.315 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg5_reg[4]/Q
                         net (fo=2, routed)           0.099     1.414    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/WNBURST_REG[4]
    SLICE_X24Y194        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/nburst_reg_r_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.456     3.075    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X24Y194        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/nburst_reg_r_reg[4]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg2_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/len_reg_r_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.148ns  (logic 0.040ns (27.011%)  route 0.108ns (72.989%))
  Logic Levels:           0  
  Clock Path Skew:        1.810ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.078ns
    Source Clock Delay      (SCD):    1.268ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.148ns (routing 0.358ns, distribution 0.790ns)
  Clock Net Delay (Destination): 1.459ns (routing 0.485ns, distribution 0.974ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.148     1.268    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X29Y182        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg2_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X29Y182        FDRE (Prop_BFF2_SLICEL_C_Q)
                                                      0.040     1.308 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg2_reg[3]/Q
                         net (fo=2, routed)           0.108     1.416    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/RLENGTH_REG[3]
    SLICE_X29Y182        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/len_reg_r_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.459     3.078    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/aclk
    SLICE_X29Y182        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/len_reg_r_reg[3]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.141ns  (logic 0.039ns (27.722%)  route 0.102ns (72.278%))
  Logic Levels:           0  
  Clock Path Skew:        1.806ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.082ns
    Source Clock Delay      (SCD):    1.276ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.156ns (routing 0.358ns, distribution 0.798ns)
  Clock Net Delay (Destination): 1.463ns (routing 0.485ns, distribution 0.978ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.156     1.276    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X31Y173        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X31Y173        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.039     1.315 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[7]/Q
                         net (fo=2, routed)           0.102     1.417    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/WADDR_REG[7]
    SLICE_X31Y173        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.463     3.082    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X31Y173        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[7]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg1_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/addr_reg_r_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.154ns  (logic 0.039ns (25.377%)  route 0.115ns (74.623%))
  Logic Levels:           0  
  Clock Path Skew:        1.809ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.073ns
    Source Clock Delay      (SCD):    1.264ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.144ns (routing 0.358ns, distribution 0.786ns)
  Clock Net Delay (Destination): 1.454ns (routing 0.485ns, distribution 0.969ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.144     1.264    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X29Y198        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg1_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X29Y198        FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.039     1.303 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg1_reg[4]/Q
                         net (fo=2, routed)           0.115     1.418    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/RADDR_REG[4]
    SLICE_X29Y198        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/addr_reg_r_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.454     3.073    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/aclk
    SLICE_X29Y198        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/addr_reg_r_reg[4]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg5_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/nburst_reg_r_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.142ns  (logic 0.039ns (27.526%)  route 0.103ns (72.474%))
  Logic Levels:           0  
  Clock Path Skew:        1.798ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.075ns
    Source Clock Delay      (SCD):    1.277ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.157ns (routing 0.358ns, distribution 0.799ns)
  Clock Net Delay (Destination): 1.456ns (routing 0.485ns, distribution 0.971ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.157     1.277    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X24Y194        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg5_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X24Y194        FDRE (Prop_AFF2_SLICEM_C_Q)
                                                      0.039     1.316 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg5_reg[1]/Q
                         net (fo=2, routed)           0.103     1.419    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/WNBURST_REG[1]
    SLICE_X24Y194        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/nburst_reg_r_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.456     3.075    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X24Y194        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/nburst_reg_r_reg[1]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  mmcm_clkout0
  To Clock:  mmcm_clkout0

Max Delay            68 Endpoints
Min Delay            68 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_w_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR
                            (recovery check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        4.029ns  (logic 0.078ns (1.936%)  route 3.951ns (98.064%))
  Logic Levels:           0  
  Clock Path Skew:        -0.106ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.942ns
    Source Clock Delay      (SCD):    5.048ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.286ns (routing 0.788ns, distribution 1.498ns)
  Clock Net Delay (Destination): 1.789ns (routing 0.716ns, distribution 1.073ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.286     5.048    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X41Y173        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X41Y173        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     5.126 r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          3.951     9.077    d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_w_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X81Y172        FDCE                                         f  d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_w_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.129    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.789     4.942    d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_w_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X81Y172        FDCE                                         r  d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_w_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_w_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR
                            (recovery check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        4.029ns  (logic 0.078ns (1.936%)  route 3.951ns (98.064%))
  Logic Levels:           0  
  Clock Path Skew:        -0.106ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.942ns
    Source Clock Delay      (SCD):    5.048ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.286ns (routing 0.788ns, distribution 1.498ns)
  Clock Net Delay (Destination): 1.789ns (routing 0.716ns, distribution 1.073ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.286     5.048    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X41Y173        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X41Y173        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     5.126 r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          3.951     9.077    d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_w_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X81Y172        FDCE                                         f  d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_w_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.129    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.789     4.942    d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_w_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X81Y172        FDCE                                         r  d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_w_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_w_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR
                            (recovery check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        4.029ns  (logic 0.078ns (1.936%)  route 3.951ns (98.064%))
  Logic Levels:           0  
  Clock Path Skew:        -0.106ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.942ns
    Source Clock Delay      (SCD):    5.048ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.286ns (routing 0.788ns, distribution 1.498ns)
  Clock Net Delay (Destination): 1.789ns (routing 0.716ns, distribution 1.073ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.286     5.048    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X41Y173        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X41Y173        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     5.126 r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          3.951     9.077    d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_w_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X81Y172        FDCE                                         f  d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_w_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.129    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.789     4.942    d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_w_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X81Y172        FDCE                                         r  d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_w_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR
                            (recovery check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        3.614ns  (logic 0.078ns (2.158%)  route 3.536ns (97.842%))
  Logic Levels:           0  
  Clock Path Skew:        0.004ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.052ns
    Source Clock Delay      (SCD):    5.048ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.286ns (routing 0.788ns, distribution 1.498ns)
  Clock Net Delay (Destination): 1.899ns (routing 0.716ns, distribution 1.183ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.286     5.048    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X41Y173        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X41Y173        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     5.126 r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          3.536     8.662    d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X80Y171        FDCE                                         f  d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.129    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.899     5.052    d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X80Y171        FDCE                                         r  d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR
                            (recovery check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        3.614ns  (logic 0.078ns (2.158%)  route 3.536ns (97.842%))
  Logic Levels:           0  
  Clock Path Skew:        0.004ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.052ns
    Source Clock Delay      (SCD):    5.048ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.286ns (routing 0.788ns, distribution 1.498ns)
  Clock Net Delay (Destination): 1.899ns (routing 0.716ns, distribution 1.183ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.286     5.048    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X41Y173        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X41Y173        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     5.126 r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          3.536     8.662    d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X80Y171        FDCE                                         f  d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.129    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.899     5.052    d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X80Y171        FDCE                                         r  d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR
                            (recovery check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        3.614ns  (logic 0.078ns (2.158%)  route 3.536ns (97.842%))
  Logic Levels:           0  
  Clock Path Skew:        0.004ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.052ns
    Source Clock Delay      (SCD):    5.048ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.286ns (routing 0.788ns, distribution 1.498ns)
  Clock Net Delay (Destination): 1.899ns (routing 0.716ns, distribution 1.183ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.286     5.048    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X41Y173        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X41Y173        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     5.126 r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          3.536     8.662    d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X80Y171        FDCE                                         f  d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.129    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.899     5.052    d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X80Y171        FDCE                                         r  d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_w_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR
                            (recovery check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        3.599ns  (logic 0.078ns (2.167%)  route 3.521ns (97.833%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.054ns
    Source Clock Delay      (SCD):    5.048ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.286ns (routing 0.788ns, distribution 1.498ns)
  Clock Net Delay (Destination): 1.901ns (routing 0.716ns, distribution 1.185ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.286     5.048    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X41Y173        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X41Y173        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     5.126 r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          3.521     8.647    d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_w_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X79Y172        FDCE                                         f  d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_w_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.129    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.901     5.054    d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_w_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X79Y172        FDCE                                         r  d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_w_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_w_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR
                            (recovery check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        3.599ns  (logic 0.078ns (2.167%)  route 3.521ns (97.833%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.054ns
    Source Clock Delay      (SCD):    5.048ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.286ns (routing 0.788ns, distribution 1.498ns)
  Clock Net Delay (Destination): 1.901ns (routing 0.716ns, distribution 1.185ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.286     5.048    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X41Y173        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X41Y173        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     5.126 r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          3.521     8.647    d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_w_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X79Y172        FDCE                                         f  d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_w_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.129    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.901     5.054    d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_w_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X79Y172        FDCE                                         r  d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_w_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_w_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR
                            (recovery check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        3.599ns  (logic 0.078ns (2.167%)  route 3.521ns (97.833%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.054ns
    Source Clock Delay      (SCD):    5.048ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.286ns (routing 0.788ns, distribution 1.498ns)
  Clock Net Delay (Destination): 1.901ns (routing 0.716ns, distribution 1.185ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.286     5.048    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X41Y173        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X41Y173        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     5.126 r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          3.521     8.647    d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_w_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X79Y172        FDCE                                         f  d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_w_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.129    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.901     5.054    d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_w_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X79Y172        FDCE                                         r  d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_w_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR
                            (recovery check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        3.152ns  (logic 0.078ns (2.474%)  route 3.074ns (97.526%))
  Logic Levels:           0  
  Clock Path Skew:        -0.111ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.937ns
    Source Clock Delay      (SCD):    5.048ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.286ns (routing 0.788ns, distribution 1.498ns)
  Clock Net Delay (Destination): 1.784ns (routing 0.716ns, distribution 1.068ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.286     5.048    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X41Y173        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X41Y173        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     5.126 r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          3.074     8.200    d_1_i/ddr4/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/xpm_cdc_async_rst_inst/src_arst
    SLICE_X81Y171        FDCE                                         f  d_1_i/ddr4/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.129    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.784     4.937    d_1_i/ddr4/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/xpm_cdc_async_rst_inst/dest_clk
    SLICE_X81Y171        FDCE                                         r  d_1_i/ddr4/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[0]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_transaction_regulator/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR
                            (removal check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.347ns  (logic 0.039ns (11.245%)  route 0.308ns (88.755%))
  Logic Levels:           0  
  Clock Path Skew:        -0.036ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.075ns
    Source Clock Delay      (SCD):    3.111ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.258ns (routing 0.435ns, distribution 0.823ns)
  Clock Net Delay (Destination): 1.456ns (routing 0.485ns, distribution 0.971ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.836    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.853 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.258     3.111    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X41Y173        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X41Y173        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     3.150 r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          0.308     3.457    d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_transaction_regulator/inst/xpm_cdc_async_rst_inst/src_arst
    SLICE_X35Y173        FDCE                                         f  d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_transaction_regulator/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.456     3.075    d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_transaction_regulator/inst/xpm_cdc_async_rst_inst/dest_clk
    SLICE_X35Y173        FDCE                                         r  d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_transaction_regulator/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_transaction_regulator/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR
                            (removal check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.347ns  (logic 0.039ns (11.245%)  route 0.308ns (88.755%))
  Logic Levels:           0  
  Clock Path Skew:        -0.036ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.075ns
    Source Clock Delay      (SCD):    3.111ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.258ns (routing 0.435ns, distribution 0.823ns)
  Clock Net Delay (Destination): 1.456ns (routing 0.485ns, distribution 0.971ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.836    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.853 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.258     3.111    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X41Y173        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X41Y173        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     3.150 r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          0.308     3.457    d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_transaction_regulator/inst/xpm_cdc_async_rst_inst/src_arst
    SLICE_X35Y173        FDCE                                         f  d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_transaction_regulator/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.456     3.075    d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_transaction_regulator/inst/xpm_cdc_async_rst_inst/dest_clk
    SLICE_X35Y173        FDCE                                         r  d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_transaction_regulator/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_transaction_regulator/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR
                            (removal check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.347ns  (logic 0.039ns (11.245%)  route 0.308ns (88.755%))
  Logic Levels:           0  
  Clock Path Skew:        -0.036ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.075ns
    Source Clock Delay      (SCD):    3.111ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.258ns (routing 0.435ns, distribution 0.823ns)
  Clock Net Delay (Destination): 1.456ns (routing 0.485ns, distribution 0.971ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.836    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.853 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.258     3.111    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X41Y173        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X41Y173        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     3.150 r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          0.308     3.457    d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_transaction_regulator/inst/xpm_cdc_async_rst_inst/src_arst
    SLICE_X35Y173        FDCE                                         f  d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_transaction_regulator/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.456     3.075    d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_transaction_regulator/inst/xpm_cdc_async_rst_inst/dest_clk
    SLICE_X35Y173        FDCE                                         r  d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_transaction_regulator/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR
                            (removal check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.386ns  (logic 0.039ns (10.101%)  route 0.347ns (89.899%))
  Logic Levels:           0  
  Clock Path Skew:        -0.024ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.086ns
    Source Clock Delay      (SCD):    3.111ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.258ns (routing 0.435ns, distribution 0.823ns)
  Clock Net Delay (Destination): 1.468ns (routing 0.485ns, distribution 0.983ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.836    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.853 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.258     3.111    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X41Y173        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X41Y173        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     3.150 r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          0.347     3.497    d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/xpm_cdc_async_rst_inst/src_arst
    SLICE_X29Y180        FDCE                                         f  d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.468     3.086    d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/xpm_cdc_async_rst_inst/dest_clk
    SLICE_X29Y180        FDCE                                         r  d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR
                            (removal check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.386ns  (logic 0.039ns (10.101%)  route 0.347ns (89.899%))
  Logic Levels:           0  
  Clock Path Skew:        -0.024ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.086ns
    Source Clock Delay      (SCD):    3.111ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.258ns (routing 0.435ns, distribution 0.823ns)
  Clock Net Delay (Destination): 1.468ns (routing 0.485ns, distribution 0.983ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.836    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.853 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.258     3.111    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X41Y173        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X41Y173        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     3.150 r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          0.347     3.497    d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/xpm_cdc_async_rst_inst/src_arst
    SLICE_X29Y180        FDCE                                         f  d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.468     3.086    d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/xpm_cdc_async_rst_inst/dest_clk
    SLICE_X29Y180        FDCE                                         r  d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR
                            (removal check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.386ns  (logic 0.039ns (10.101%)  route 0.347ns (89.899%))
  Logic Levels:           0  
  Clock Path Skew:        -0.024ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.086ns
    Source Clock Delay      (SCD):    3.111ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.258ns (routing 0.435ns, distribution 0.823ns)
  Clock Net Delay (Destination): 1.468ns (routing 0.485ns, distribution 0.983ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.836    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.853 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.258     3.111    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X41Y173        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X41Y173        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     3.150 r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          0.347     3.497    d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/xpm_cdc_async_rst_inst/src_arst
    SLICE_X29Y180        FDCE                                         f  d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.468     3.086    d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/xpm_cdc_async_rst_inst/dest_clk
    SLICE_X29Y180        FDCE                                         r  d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/div_clk_rst_r1_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/rst_ddr4/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.596ns  (logic 0.039ns (6.544%)  route 0.557ns (93.456%))
  Logic Levels:           0  
  Clock Path Skew:        -0.012ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.933ns
    Source Clock Delay      (SCD):    2.945ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.092ns (routing 0.435ns, distribution 0.657ns)
  Clock Net Delay (Destination): 1.314ns (routing 0.485ns, distribution 0.829ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.836    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.853 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.092     2.945    d_1_i/ddr4/ddr4_0/inst/c0_ddr4_ui_clk
    SLICE_X95Y187        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/div_clk_rst_r1_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y187        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.039     2.984 r  d_1_i/ddr4/ddr4_0/inst/div_clk_rst_r1_reg/Q
                         net (fo=1, routed)           0.557     3.541    d_1_i/ddr4/rst_ddr4/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/ext_reset_in
    SLICE_X108Y128       FDRE                                         r  d_1_i/ddr4/rst_ddr4/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.314     2.933    d_1_i/ddr4/rst_ddr4/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/slowest_sync_clk
    SLICE_X108Y128       FDRE                                         r  d_1_i/ddr4/rst_ddr4/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR
                            (removal check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.456ns  (logic 0.039ns (8.557%)  route 0.417ns (91.443%))
  Logic Levels:           0  
  Clock Path Skew:        -0.041ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.070ns
    Source Clock Delay      (SCD):    3.111ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.258ns (routing 0.435ns, distribution 0.823ns)
  Clock Net Delay (Destination): 1.451ns (routing 0.485ns, distribution 0.966ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.836    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.853 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.258     3.111    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X41Y173        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X41Y173        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     3.150 r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          0.417     3.566    d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/xpm_cdc_async_rst_inst/src_arst
    SLICE_X35Y164        FDCE                                         f  d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.451     3.070    d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/xpm_cdc_async_rst_inst/dest_clk
    SLICE_X35Y164        FDCE                                         r  d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR
                            (removal check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.456ns  (logic 0.039ns (8.557%)  route 0.417ns (91.443%))
  Logic Levels:           0  
  Clock Path Skew:        -0.041ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.070ns
    Source Clock Delay      (SCD):    3.111ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.258ns (routing 0.435ns, distribution 0.823ns)
  Clock Net Delay (Destination): 1.451ns (routing 0.485ns, distribution 0.966ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.836    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.853 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.258     3.111    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X41Y173        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X41Y173        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     3.150 r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          0.417     3.566    d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/xpm_cdc_async_rst_inst/src_arst
    SLICE_X35Y164        FDCE                                         f  d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.451     3.070    d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/xpm_cdc_async_rst_inst/dest_clk
    SLICE_X35Y164        FDCE                                         r  d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR
                            (removal check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.456ns  (logic 0.039ns (8.557%)  route 0.417ns (91.443%))
  Logic Levels:           0  
  Clock Path Skew:        -0.041ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.070ns
    Source Clock Delay      (SCD):    3.111ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.258ns (routing 0.435ns, distribution 0.823ns)
  Clock Net Delay (Destination): 1.451ns (routing 0.485ns, distribution 0.966ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.836    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.853 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.258     3.111    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X41Y173        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X41Y173        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     3.150 r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          0.417     3.566    d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/xpm_cdc_async_rst_inst/src_arst
    SLICE_X35Y164        FDCE                                         f  d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.451     3.070    d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/xpm_cdc_async_rst_inst/dest_clk
    SLICE_X35Y164        FDCE                                         r  d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[2]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  mmcm_clkout5
  To Clock:  mmcm_clkout0

Max Delay             0 Endpoints
Min Delay            28 Endpoints
--------------------------------------------------------------------------------------


Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[1].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.098ns  (logic 0.037ns (37.755%)  route 0.061ns (62.245%))
  Logic Levels:           0  
  Clock Path Skew:        0.278ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.879ns
    Source Clock Delay      (SCD):    2.601ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.754ns (routing 0.299ns, distribution 0.455ns)
  Clock Net Delay (Destination): 1.260ns (routing 0.485ns, distribution 0.775ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.830    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.847 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.754     2.601    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/CLK
    SLICE_X93Y321        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y321        FDRE (Prop_FFF_SLICEM_C_Q)
                                                      0.037     2.638 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[1]/Q
                         net (fo=1, routed)           0.061     2.699    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/out[1]
    SLICE_X92Y321        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[1].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.260     2.879    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[15].sync_reg_reg[1]_0
    SLICE_X92Y321        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[1].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[6].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.128ns  (logic 0.039ns (30.469%)  route 0.089ns (69.531%))
  Logic Levels:           0  
  Clock Path Skew:        0.283ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.875ns
    Source Clock Delay      (SCD):    2.592ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.745ns (routing 0.299ns, distribution 0.446ns)
  Clock Net Delay (Destination): 1.256ns (routing 0.485ns, distribution 0.771ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.830    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.847 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.745     2.592    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/CLK
    SLICE_X92Y328        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y328        FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.039     2.631 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[6]/Q
                         net (fo=1, routed)           0.089     2.720    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/out[6]
    SLICE_X93Y328        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[6].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.256     2.875    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[15].sync_reg_reg[1]_0
    SLICE_X93Y328        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[6].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[8]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[8].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.121ns  (logic 0.038ns (31.405%)  route 0.083ns (68.595%))
  Logic Levels:           0  
  Clock Path Skew:        0.278ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.879ns
    Source Clock Delay      (SCD):    2.601ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.754ns (routing 0.299ns, distribution 0.455ns)
  Clock Net Delay (Destination): 1.260ns (routing 0.485ns, distribution 0.775ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.830    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.847 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.754     2.601    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/CLK
    SLICE_X93Y323        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y323        FDRE (Prop_CFF_SLICEM_C_Q)
                                                      0.038     2.639 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[8]/Q
                         net (fo=1, routed)           0.083     2.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/out[8]
    SLICE_X92Y321        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[8].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.260     2.879    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[7].sync_reg_reg[1]_0
    SLICE_X92Y321        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[8].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[0].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.125ns  (logic 0.038ns (30.400%)  route 0.087ns (69.600%))
  Logic Levels:           0  
  Clock Path Skew:        0.277ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.878ns
    Source Clock Delay      (SCD):    2.601ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.754ns (routing 0.299ns, distribution 0.455ns)
  Clock Net Delay (Destination): 1.259ns (routing 0.485ns, distribution 0.774ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.830    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.847 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.754     2.601    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/CLK
    SLICE_X93Y323        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y323        FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.038     2.639 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[0]/Q
                         net (fo=1, routed)           0.087     2.726    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/out[0]
    SLICE_X93Y324        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[0].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.259     2.878    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[7].sync_reg_reg[1]_0
    SLICE_X93Y324        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[0].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_we_r_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_we_sync/SYNC[0].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.130ns  (logic 0.039ns (30.000%)  route 0.091ns (70.000%))
  Logic Levels:           0  
  Clock Path Skew:        0.274ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.875ns
    Source Clock Delay      (SCD):    2.601ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.754ns (routing 0.299ns, distribution 0.455ns)
  Clock Net Delay (Destination): 1.256ns (routing 0.485ns, distribution 0.771ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.830    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.847 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.754     2.601    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/CLK
    SLICE_X95Y328        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_we_r_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y328        FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.039     2.640 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_we_r_reg/Q
                         net (fo=1, routed)           0.091     2.731    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_we_sync/D[0]
    SLICE_X93Y328        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_we_sync/SYNC[0].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.256     2.875    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_we_sync/SYNC[0].sync_reg_reg[1]_0
    SLICE_X93Y328        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_we_sync/SYNC[0].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[14]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[14].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.130ns  (logic 0.039ns (30.000%)  route 0.091ns (70.000%))
  Logic Levels:           0  
  Clock Path Skew:        0.285ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.886ns
    Source Clock Delay      (SCD):    2.602ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.755ns (routing 0.299ns, distribution 0.456ns)
  Clock Net Delay (Destination): 1.268ns (routing 0.485ns, distribution 0.783ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.830    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.847 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.755     2.602    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/CLK
    SLICE_X96Y337        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[14]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y337        FDRE (Prop_GFF2_SLICEM_C_Q)
                                                      0.039     2.641 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[14]/Q
                         net (fo=1, routed)           0.091     2.732    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/out[14]
    SLICE_X94Y338        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[14].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.268     2.886    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[15].sync_reg_reg[1]_0
    SLICE_X94Y338        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[14].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_rdy_cptd_sclk_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_cptd_sync/SYNC[0].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.157ns  (logic 0.039ns (24.841%)  route 0.118ns (75.159%))
  Logic Levels:           0  
  Clock Path Skew:        0.278ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.876ns
    Source Clock Delay      (SCD):    2.598ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.751ns (routing 0.299ns, distribution 0.452ns)
  Clock Net Delay (Destination): 1.257ns (routing 0.485ns, distribution 0.772ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.830    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.847 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.751     2.598    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/CLK
    SLICE_X95Y328        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_rdy_cptd_sclk_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y328        FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.039     2.637 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_rdy_cptd_sclk_reg/Q
                         net (fo=1, routed)           0.118     2.755    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_cptd_sync/SYNC[0].sync_reg_reg[0]_0[0]
    SLICE_X93Y327        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_cptd_sync/SYNC[0].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.257     2.876    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_cptd_sync/SYNC[0].sync_reg_reg[1]_0
    SLICE_X93Y327        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_cptd_sync/SYNC[0].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[3].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.158ns  (logic 0.038ns (24.051%)  route 0.120ns (75.949%))
  Logic Levels:           0  
  Clock Path Skew:        0.270ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.872ns
    Source Clock Delay      (SCD):    2.602ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.755ns (routing 0.299ns, distribution 0.456ns)
  Clock Net Delay (Destination): 1.253ns (routing 0.485ns, distribution 0.768ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.830    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.847 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.755     2.602    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/CLK
    SLICE_X94Y327        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y327        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     2.640 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[3]/Q
                         net (fo=1, routed)           0.120     2.760    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/out[3]
    SLICE_X92Y325        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[3].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.253     2.872    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[7].sync_reg_reg[1]_0
    SLICE_X92Y325        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[3].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[4].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.161ns  (logic 0.037ns (22.981%)  route 0.124ns (77.019%))
  Logic Levels:           0  
  Clock Path Skew:        0.282ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.883ns
    Source Clock Delay      (SCD):    2.601ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.754ns (routing 0.299ns, distribution 0.455ns)
  Clock Net Delay (Destination): 1.264ns (routing 0.485ns, distribution 0.779ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.830    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.847 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.754     2.601    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/CLK
    SLICE_X93Y322        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y322        FDRE (Prop_FFF_SLICEM_C_Q)
                                                      0.037     2.638 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[4]/Q
                         net (fo=1, routed)           0.124     2.762    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/out[4]
    SLICE_X93Y316        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[4].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.264     2.883    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[7].sync_reg_reg[1]_0
    SLICE_X93Y316        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[4].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[7].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.160ns  (logic 0.039ns (24.375%)  route 0.121ns (75.625%))
  Logic Levels:           0  
  Clock Path Skew:        0.280ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.883ns
    Source Clock Delay      (SCD):    2.603ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.756ns (routing 0.299ns, distribution 0.457ns)
  Clock Net Delay (Destination): 1.264ns (routing 0.485ns, distribution 0.779ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.830    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.847 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.756     2.603    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/CLK
    SLICE_X96Y317        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y317        FDRE (Prop_EFF2_SLICEM_C_Q)
                                                      0.039     2.642 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[7]/Q
                         net (fo=1, routed)           0.121     2.763    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/out[7]
    SLICE_X93Y316        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[7].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.264     2.883    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[7].sync_reg_reg[1]_0
    SLICE_X93Y316        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[7].sync_reg_reg[0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  mmcm_clkout6
  To Clock:  mmcm_clkout0

Max Delay             0 Endpoints
Min Delay           129 Endpoints
--------------------------------------------------------------------------------------


Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/riu2clb_valid_r1_riuclk_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[6].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.098ns  (logic 0.038ns (38.775%)  route 0.060ns (61.224%))
  Logic Levels:           0  
  Clock Path Skew:        -0.111ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.859ns
    Source Clock Delay      (SCD):    2.970ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.107ns (routing 0.439ns, distribution 0.668ns)
  Clock Net Delay (Destination): 1.240ns (routing 0.485ns, distribution 0.755ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     1.846    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.863 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.107     2.970    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X90Y276        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/riu2clb_valid_r1_riuclk_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X90Y276        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     3.008 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/riu2clb_valid_r1_riuclk_reg[6]/Q
                         net (fo=1, routed)           0.060     3.068    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[19].sync_reg_reg[0]_0[6]
    SLICE_X90Y276        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[6].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.240     2.859    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[19].sync_reg_reg[1]_0
    SLICE_X90Y276        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[6].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/phy2clb_fixdly_rdy_upp_riuclk_int_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_fixdly_rdy_upp/SYNC[1].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.116ns  (logic 0.039ns (33.665%)  route 0.077ns (66.335%))
  Logic Levels:           0  
  Clock Path Skew:        -0.118ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.842ns
    Source Clock Delay      (SCD):    2.960ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.097ns (routing 0.439ns, distribution 0.658ns)
  Clock Net Delay (Destination): 1.223ns (routing 0.485ns, distribution 0.738ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     1.846    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.863 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.097     2.960    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X81Y215        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/phy2clb_fixdly_rdy_upp_riuclk_int_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y215        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     2.999 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/phy2clb_fixdly_rdy_upp_riuclk_int_reg[1]/Q
                         net (fo=2, routed)           0.077     3.076    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_fixdly_rdy_upp/phy2clb_fixdly_rdy_upp_riuclk[1]
    SLICE_X81Y215        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_fixdly_rdy_upp/SYNC[1].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.223     2.842    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_fixdly_rdy_upp/SYNC[19].sync_reg_reg[1]_0
    SLICE_X81Y215        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_fixdly_rdy_upp/SYNC[1].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/phy2clb_phy_rdy_low_riuclk_int_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_phy_rdy_low/SYNC[2].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.118ns  (logic 0.039ns (33.051%)  route 0.079ns (66.949%))
  Logic Levels:           0  
  Clock Path Skew:        -0.117ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.849ns
    Source Clock Delay      (SCD):    2.966ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.103ns (routing 0.439ns, distribution 0.664ns)
  Clock Net Delay (Destination): 1.230ns (routing 0.485ns, distribution 0.745ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     1.846    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.863 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.103     2.966    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X81Y226        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/phy2clb_phy_rdy_low_riuclk_int_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y226        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     3.005 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/phy2clb_phy_rdy_low_riuclk_int_reg[2]/Q
                         net (fo=2, routed)           0.079     3.084    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_phy_rdy_low/phy2clb_phy_rdy_low_riuclk[2]
    SLICE_X81Y226        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_phy_rdy_low/SYNC[2].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.230     2.849    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_phy_rdy_low/SYNC[19].sync_reg_reg[1]_0
    SLICE_X81Y226        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_phy_rdy_low/SYNC[2].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/riu2clb_valid_r1_riuclk_reg[15]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[15].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.114ns  (logic 0.039ns (34.211%)  route 0.075ns (65.790%))
  Logic Levels:           0  
  Clock Path Skew:        -0.110ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.863ns
    Source Clock Delay      (SCD):    2.973ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.110ns (routing 0.439ns, distribution 0.671ns)
  Clock Net Delay (Destination): 1.244ns (routing 0.485ns, distribution 0.759ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     1.846    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.863 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.110     2.973    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X91Y280        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/riu2clb_valid_r1_riuclk_reg[15]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y280        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     3.012 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/riu2clb_valid_r1_riuclk_reg[15]/Q
                         net (fo=1, routed)           0.075     3.087    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[19].sync_reg_reg[0]_0[15]
    SLICE_X91Y280        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[15].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.244     2.863    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[19].sync_reg_reg[1]_0
    SLICE_X91Y280        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[15].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[29]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[29].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.116ns  (logic 0.040ns (34.483%)  route 0.076ns (65.517%))
  Logic Levels:           0  
  Clock Path Skew:        -0.111ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.866ns
    Source Clock Delay      (SCD):    2.977ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.114ns (routing 0.439ns, distribution 0.675ns)
  Clock Net Delay (Destination): 1.247ns (routing 0.485ns, distribution 0.762ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     1.846    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.863 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.114     2.977    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X92Y335        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[29]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y335        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.040     3.017 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[29]/Q
                         net (fo=1, routed)           0.076     3.093    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[31].sync_reg_reg[0]_0[29]
    SLICE_X92Y335        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[29].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.247     2.866    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[30].sync_reg_reg[1]_0
    SLICE_X92Y335        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[29].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/riu2clb_valid_r1_riuclk_reg[12]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[12].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.124ns  (logic 0.038ns (30.645%)  route 0.086ns (69.355%))
  Logic Levels:           0  
  Clock Path Skew:        -0.104ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.866ns
    Source Clock Delay      (SCD):    2.970ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.107ns (routing 0.439ns, distribution 0.668ns)
  Clock Net Delay (Destination): 1.247ns (routing 0.485ns, distribution 0.762ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     1.846    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.863 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.107     2.970    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X90Y277        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/riu2clb_valid_r1_riuclk_reg[12]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X90Y277        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     3.008 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/riu2clb_valid_r1_riuclk_reg[12]/Q
                         net (fo=1, routed)           0.086     3.094    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[19].sync_reg_reg[0]_0[12]
    SLICE_X90Y277        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[12].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.247     2.866    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[19].sync_reg_reg[1]_0
    SLICE_X90Y277        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[12].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/phy2clb_phy_rdy_low_riuclk_int_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_phy_rdy_low/SYNC[3].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.130ns  (logic 0.040ns (30.769%)  route 0.090ns (69.231%))
  Logic Levels:           0  
  Clock Path Skew:        -0.117ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.849ns
    Source Clock Delay      (SCD):    2.966ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.103ns (routing 0.439ns, distribution 0.664ns)
  Clock Net Delay (Destination): 1.230ns (routing 0.485ns, distribution 0.745ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     1.846    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.863 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.103     2.966    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X81Y226        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/phy2clb_phy_rdy_low_riuclk_int_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y226        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.040     3.006 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/phy2clb_phy_rdy_low_riuclk_int_reg[3]/Q
                         net (fo=2, routed)           0.090     3.096    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_phy_rdy_low/phy2clb_phy_rdy_low_riuclk[3]
    SLICE_X81Y226        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_phy_rdy_low/SYNC[3].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.230     2.849    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_phy_rdy_low/SYNC[19].sync_reg_reg[1]_0
    SLICE_X81Y226        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_phy_rdy_low/SYNC[3].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/riu2clb_valid_r1_riuclk_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[1].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.118ns  (logic 0.039ns (33.051%)  route 0.079ns (66.949%))
  Logic Levels:           0  
  Clock Path Skew:        -0.110ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.869ns
    Source Clock Delay      (SCD):    2.979ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.116ns (routing 0.439ns, distribution 0.677ns)
  Clock Net Delay (Destination): 1.250ns (routing 0.485ns, distribution 0.765ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     1.846    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.863 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.116     2.979    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X88Y285        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/riu2clb_valid_r1_riuclk_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y285        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     3.018 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/riu2clb_valid_r1_riuclk_reg[1]/Q
                         net (fo=1, routed)           0.079     3.097    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[19].sync_reg_reg[0]_0[1]
    SLICE_X88Y285        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[1].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.250     2.869    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[19].sync_reg_reg[1]_0
    SLICE_X88Y285        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[1].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/riu2clb_valid_r1_riuclk_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[7].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.114ns  (logic 0.039ns (34.211%)  route 0.075ns (65.790%))
  Logic Levels:           0  
  Clock Path Skew:        -0.122ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.864ns
    Source Clock Delay      (SCD):    2.986ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.123ns (routing 0.439ns, distribution 0.684ns)
  Clock Net Delay (Destination): 1.245ns (routing 0.485ns, distribution 0.760ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     1.846    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.863 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.123     2.986    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X88Y298        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/riu2clb_valid_r1_riuclk_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y298        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     3.025 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/riu2clb_valid_r1_riuclk_reg[7]/Q
                         net (fo=1, routed)           0.075     3.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[19].sync_reg_reg[0]_0[7]
    SLICE_X88Y298        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[7].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.245     2.864    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[19].sync_reg_reg[1]_0
    SLICE_X88Y298        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[7].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[22]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[22].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.104ns  (logic 0.038ns (36.538%)  route 0.066ns (63.461%))
  Logic Levels:           0  
  Clock Path Skew:        -0.101ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.895ns
    Source Clock Delay      (SCD):    2.996ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.133ns (routing 0.439ns, distribution 0.694ns)
  Clock Net Delay (Destination): 1.276ns (routing 0.485ns, distribution 0.791ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     1.846    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.863 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.133     2.996    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X86Y353        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[22]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X86Y353        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     3.034 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[22]/Q
                         net (fo=1, routed)           0.066     3.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[31].sync_reg_reg[0]_0[22]
    SLICE_X85Y353        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[22].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.276     2.895    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[30].sync_reg_reg[1]_0
    SLICE_X85Y353        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[22].sync_reg_reg[0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  sys_clk_ddr4_clk_p
  To Clock:  mmcm_clkout0

Max Delay             1 Endpoint
Min Delay             1 Endpoint
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_div_sync_r_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.286ns  (logic 0.081ns (28.318%)  route 0.205ns (71.682%))
  Logic Levels:           0  
  Clock Path Skew:        2.157ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.977ns
    Source Clock Delay      (SCD):    2.820ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.734ns (routing 0.702ns, distribution 1.032ns)
  Clock Net Delay (Destination): 1.824ns (routing 0.716ns, distribution 1.108ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.734     2.820    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X84Y309        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X84Y309        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.081     2.901 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/Q
                         net (fo=2, routed)           0.205     3.106    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div
    SLICE_X84Y310        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_div_sync_r_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.129    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.824     4.977    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk_0
    SLICE_X84Y310        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_div_sync_r_reg[0]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_div_sync_r_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.123ns  (logic 0.040ns (32.604%)  route 0.083ns (67.396%))
  Logic Levels:           0  
  Clock Path Skew:        1.316ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.892ns
    Source Clock Delay      (SCD):    1.576ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.959ns (routing 0.389ns, distribution 0.570ns)
  Clock Net Delay (Destination): 1.273ns (routing 0.485ns, distribution 0.788ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          0.959     1.576    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X84Y309        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X84Y309        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.040     1.616 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/Q
                         net (fo=2, routed)           0.083     1.699    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div
    SLICE_X84Y310        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_div_sync_r_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.619 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.273     2.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk_0
    SLICE_X84Y310        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_div_sync_r_reg[0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  To Clock:  mmcm_clkout5

Max Delay            78 Endpoints
Min Delay            86 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMG/CLK
                            (rising edge-triggered cell RAMD32 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.002ns  (logic 0.281ns (28.044%)  route 0.721ns (71.956%))
  Logic Levels:           0  
  Clock Path Skew:        -6.388ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.439ns
    Source Clock Delay      (SCD):    10.827ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.933ns (routing 1.680ns, distribution 1.253ns)
  Clock Net Delay (Destination): 1.294ns (routing 0.490ns, distribution 0.804ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.566     7.866    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.894 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.933    10.827    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/WCLK
    SLICE_X109Y335       RAMD32                                       r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMG/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X109Y335       RAMD32 (Prop_G5LUT_SLICEM_CLK_O)
                                                      0.281    11.108 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMG/O
                         net (fo=1, routed)           0.721    11.829    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/dout_i0[12]
    SLICE_X108Y334       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207     3.121    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.145 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.294     4.439    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/rd_clk
    SLICE_X108Y334       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[12]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB/CLK
                            (rising edge-triggered cell RAMD32 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.968ns  (logic 0.292ns (30.165%)  route 0.676ns (69.835%))
  Logic Levels:           0  
  Clock Path Skew:        -6.388ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.439ns
    Source Clock Delay      (SCD):    10.827ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.933ns (routing 1.680ns, distribution 1.253ns)
  Clock Net Delay (Destination): 1.294ns (routing 0.490ns, distribution 0.804ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.566     7.866    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.894 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.933    10.827    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/WCLK
    SLICE_X109Y335       RAMD32                                       r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X109Y335       RAMD32 (Prop_B5LUT_SLICEM_CLK_O)
                                                      0.292    11.119 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB/O
                         net (fo=1, routed)           0.676    11.795    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/dout_i0[2]
    SLICE_X108Y334       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207     3.121    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.145 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.294     4.439    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/rd_clk
    SLICE_X108Y334       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[2]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/wrdata_rst_reg/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_rd_reg1_reg/PRE
                            (recovery check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        0.908ns  (logic 0.079ns (8.699%)  route 0.829ns (91.301%))
  Logic Levels:           0  
  Clock Path Skew:        -6.384ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.411ns
    Source Clock Delay      (SCD):    10.795ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.901ns (routing 1.680ns, distribution 1.221ns)
  Clock Net Delay (Destination): 1.266ns (routing 0.490ns, distribution 0.776ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.566     7.866    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.894 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.901    10.795    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/m_bscan_tck[0]
    SLICE_X110Y338       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/wrdata_rst_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X110Y338       FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.079    10.874 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/wrdata_rst_reg/Q
                         net (fo=20, routed)          0.829    11.703    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rst
    SLICE_X106Y337       FDPE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_rd_reg1_reg/PRE
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207     3.121    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.145 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.266     4.411    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
    SLICE_X106Y337       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_rd_reg1_reg/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/wrdata_rst_reg/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_rd_reg2_reg/PRE
                            (recovery check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        0.908ns  (logic 0.079ns (8.699%)  route 0.829ns (91.301%))
  Logic Levels:           0  
  Clock Path Skew:        -6.384ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.411ns
    Source Clock Delay      (SCD):    10.795ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.901ns (routing 1.680ns, distribution 1.221ns)
  Clock Net Delay (Destination): 1.266ns (routing 0.490ns, distribution 0.776ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.566     7.866    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.894 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.901    10.795    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/m_bscan_tck[0]
    SLICE_X110Y338       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/wrdata_rst_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X110Y338       FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.079    10.874 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/wrdata_rst_reg/Q
                         net (fo=20, routed)          0.829    11.703    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rst
    SLICE_X106Y337       FDPE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_rd_reg2_reg/PRE
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207     3.121    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.145 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.266     4.411    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
    SLICE_X106Y337       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_rd_reg2_reg/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[10]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.781ns  (logic 0.081ns (10.371%)  route 0.700ns (89.629%))
  Logic Levels:           0  
  Clock Path Skew:        -6.391ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.418ns
    Source Clock Delay      (SCD):    10.809ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.915ns (routing 1.680ns, distribution 1.235ns)
  Clock Net Delay (Destination): 1.273ns (routing 0.490ns, distribution 0.783ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.566     7.866    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.894 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.915    10.809    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X108Y345       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[10]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X108Y345       FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.081    10.890 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[10]/Q
                         net (fo=2, routed)           0.700    11.590    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in[10]
    SLICE_X106Y343       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207     3.121    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.145 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.273     4.418    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/clk
    SLICE_X106Y343       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[10]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[19]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[19]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.734ns  (logic 0.078ns (10.633%)  route 0.656ns (89.367%))
  Logic Levels:           0  
  Clock Path Skew:        -6.361ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.447ns
    Source Clock Delay      (SCD):    10.808ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.914ns (routing 1.680ns, distribution 1.234ns)
  Clock Net Delay (Destination): 1.302ns (routing 0.490ns, distribution 0.812ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.566     7.866    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.894 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.914    10.808    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/m_bscan_tck[0]
    SLICE_X113Y337       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[19]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X113Y337       FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.078    10.886 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[19]/Q
                         net (fo=2, routed)           0.656    11.542    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in[19]
    SLICE_X114Y337       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[19]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207     3.121    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.145 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.302     4.447    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/clk
    SLICE_X114Y337       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[19]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[8]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.676ns  (logic 0.079ns (11.692%)  route 0.597ns (88.308%))
  Logic Levels:           0  
  Clock Path Skew:        -6.396ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.418ns
    Source Clock Delay      (SCD):    10.814ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.920ns (routing 1.680ns, distribution 1.240ns)
  Clock Net Delay (Destination): 1.273ns (routing 0.490ns, distribution 0.783ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.566     7.866    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.894 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.920    10.814    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X108Y345       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X108Y345       FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.079    10.893 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[8]/Q
                         net (fo=2, routed)           0.597    11.490    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in[8]
    SLICE_X106Y344       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207     3.121    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.145 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.273     4.418    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/clk
    SLICE_X106Y344       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[8]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.657ns  (logic 0.079ns (12.028%)  route 0.578ns (87.972%))
  Logic Levels:           0  
  Clock Path Skew:        -6.391ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.418ns
    Source Clock Delay      (SCD):    10.809ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.915ns (routing 1.680ns, distribution 1.235ns)
  Clock Net Delay (Destination): 1.273ns (routing 0.490ns, distribution 0.783ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.566     7.866    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.894 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.915    10.809    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X108Y345       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X108Y345       FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079    10.888 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[5]/Q
                         net (fo=2, routed)           0.578    11.466    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in[5]
    SLICE_X106Y344       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207     3.121    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.145 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.273     4.418    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/clk
    SLICE_X106Y344       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[5]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[16]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[16]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.632ns  (logic 0.081ns (12.816%)  route 0.551ns (87.184%))
  Logic Levels:           0  
  Clock Path Skew:        -6.396ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.418ns
    Source Clock Delay      (SCD):    10.814ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.920ns (routing 1.680ns, distribution 1.240ns)
  Clock Net Delay (Destination): 1.273ns (routing 0.490ns, distribution 0.783ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.566     7.866    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.894 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.920    10.814    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X108Y345       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[16]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X108Y345       FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.081    10.895 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[16]/Q
                         net (fo=2, routed)           0.551    11.446    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in[16]
    SLICE_X106Y343       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[16]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207     3.121    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.145 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.273     4.418    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/clk
    SLICE_X106Y343       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[16]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/icn_cmd_en_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/icn_cmd_en_5_temp_reg/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.640ns  (logic 0.079ns (12.351%)  route 0.561ns (87.649%))
  Logic Levels:           0  
  Clock Path Skew:        -6.347ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.458ns
    Source Clock Delay      (SCD):    10.805ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.911ns (routing 1.680ns, distribution 1.231ns)
  Clock Net Delay (Destination): 1.313ns (routing 0.490ns, distribution 0.823ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           3.566     7.866    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     7.894 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.911    10.805    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/m_bscan_tck[0]
    SLICE_X112Y327       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/icn_cmd_en_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X112Y327       FDRE (Prop_EFF2_SLICEM_C_Q)
                                                      0.079    10.884 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/icn_cmd_en_reg[5]/Q
                         net (fo=6, routed)           0.561    11.445    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/p_1_in1_in
    SLICE_X111Y348       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/icn_cmd_en_5_temp_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207     3.121    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.145 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.313     4.458    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/clk
    SLICE_X111Y348       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/icn_cmd_en_5_temp_reg/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.100ns  (logic 0.039ns (39.000%)  route 0.061ns (61.000%))
  Logic Levels:           0  
  Clock Path Skew:        -1.392ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.543ns
    Source Clock Delay      (SCD):    3.935ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.592ns (routing 0.916ns, distribution 0.676ns)
  Clock Net Delay (Destination): 0.931ns (routing 0.333ns, distribution 0.598ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.861     2.326    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.343 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.592     3.935    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_clk
    SLICE_X109Y339       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X109Y339       FDCE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     3.974 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[0]/Q
                         net (fo=1, routed)           0.061     4.035    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q[0]
    SLICE_X109Y338       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.593    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.612 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.931     2.543    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/rd_clk
    SLICE_X109Y338       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[22]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[22]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.096ns  (logic 0.038ns (39.507%)  route 0.058ns (60.493%))
  Logic Levels:           0  
  Clock Path Skew:        -1.397ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.543ns
    Source Clock Delay      (SCD):    3.940ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.597ns (routing 0.916ns, distribution 0.681ns)
  Clock Net Delay (Destination): 0.931ns (routing 0.333ns, distribution 0.598ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.861     2.326    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.343 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.597     3.940    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/m_bscan_tck[0]
    SLICE_X113Y337       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[22]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X113Y337       FDRE (Prop_CFF_SLICEM_C_Q)
                                                      0.038     3.978 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[22]/Q
                         net (fo=2, routed)           0.058     4.036    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in[22]
    SLICE_X114Y337       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[22]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.593    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.612 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.931     2.543    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/clk
    SLICE_X114Y337       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[22]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/shift_reg_in_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/ctl_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.107ns  (logic 0.040ns (37.383%)  route 0.067ns (62.617%))
  Logic Levels:           0  
  Clock Path Skew:        -1.382ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.547ns
    Source Clock Delay      (SCD):    3.929ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.586ns (routing 0.916ns, distribution 0.670ns)
  Clock Net Delay (Destination): 0.935ns (routing 0.333ns, distribution 0.602ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.861     2.326    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.343 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.586     3.929    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/m_bscan_tck[0]
    SLICE_X114Y331       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/shift_reg_in_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X114Y331       FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.040     3.969 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/shift_reg_in_reg[0]/Q
                         net (fo=2, routed)           0.067     4.036    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/shift_reg_in[0]
    SLICE_X114Y332       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/ctl_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.593    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.612 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.935     2.547    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/clk
    SLICE_X114Y332       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/ctl_reg_reg[0]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[20]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[20]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.097ns  (logic 0.038ns (39.049%)  route 0.059ns (60.952%))
  Logic Levels:           0  
  Clock Path Skew:        -1.397ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.543ns
    Source Clock Delay      (SCD):    3.940ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.597ns (routing 0.916ns, distribution 0.681ns)
  Clock Net Delay (Destination): 0.931ns (routing 0.333ns, distribution 0.598ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.861     2.326    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.343 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.597     3.940    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/m_bscan_tck[0]
    SLICE_X113Y337       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[20]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X113Y337       FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     3.978 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[20]/Q
                         net (fo=2, routed)           0.059     4.037    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in[20]
    SLICE_X114Y337       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[20]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.593    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.612 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.931     2.543    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/clk
    SLICE_X114Y337       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[20]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[12]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.102ns  (logic 0.039ns (38.354%)  route 0.063ns (61.645%))
  Logic Levels:           0  
  Clock Path Skew:        -1.393ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.547ns
    Source Clock Delay      (SCD):    3.940ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.597ns (routing 0.916ns, distribution 0.681ns)
  Clock Net Delay (Destination): 0.935ns (routing 0.333ns, distribution 0.602ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.861     2.326    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.343 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.597     3.940    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/m_bscan_tck[0]
    SLICE_X113Y337       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[12]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X113Y337       FDRE (Prop_AFF2_SLICEM_C_Q)
                                                      0.039     3.979 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[12]/Q
                         net (fo=2, routed)           0.063     4.041    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in[12]
    SLICE_X114Y337       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.593    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.612 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.935     2.547    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/clk
    SLICE_X114Y337       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[12]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/icn_cmd_en_temp_reg/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/ctl_reg_en_1_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.109ns  (logic 0.038ns (34.964%)  route 0.071ns (65.036%))
  Logic Levels:           0  
  Clock Path Skew:        -1.392ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.541ns
    Source Clock Delay      (SCD):    3.933ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.590ns (routing 0.916ns, distribution 0.674ns)
  Clock Net Delay (Destination): 0.929ns (routing 0.333ns, distribution 0.596ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.861     2.326    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.343 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.590     3.933    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/m_bscan_tck[0]
    SLICE_X113Y332       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/icn_cmd_en_temp_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X113Y332       FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     3.971 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/icn_cmd_en_temp_reg/Q
                         net (fo=4, routed)           0.071     4.042    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/icn_cmd_en_temp
    SLICE_X113Y333       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/ctl_reg_en_1_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.593    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.612 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.929     2.541    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/clk
    SLICE_X113Y333       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/ctl_reg_en_1_reg[0]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[13]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.106ns  (logic 0.040ns (37.650%)  route 0.066ns (62.350%))
  Logic Levels:           0  
  Clock Path Skew:        -1.393ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.547ns
    Source Clock Delay      (SCD):    3.940ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.597ns (routing 0.916ns, distribution 0.681ns)
  Clock Net Delay (Destination): 0.935ns (routing 0.333ns, distribution 0.602ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.861     2.326    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.343 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.597     3.940    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/m_bscan_tck[0]
    SLICE_X113Y337       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[13]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X113Y337       FDRE (Prop_BFF2_SLICEM_C_Q)
                                                      0.040     3.980 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[13]/Q
                         net (fo=2, routed)           0.066     4.046    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in[13]
    SLICE_X114Y337       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.593    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.612 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.935     2.547    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/clk
    SLICE_X114Y337       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[13]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[21]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[21]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.107ns  (logic 0.038ns (35.620%)  route 0.069ns (64.381%))
  Logic Levels:           0  
  Clock Path Skew:        -1.397ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.543ns
    Source Clock Delay      (SCD):    3.940ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.597ns (routing 0.916ns, distribution 0.681ns)
  Clock Net Delay (Destination): 0.931ns (routing 0.333ns, distribution 0.598ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.861     2.326    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.343 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.597     3.940    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/m_bscan_tck[0]
    SLICE_X113Y337       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[21]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X113Y337       FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.038     3.978 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[21]/Q
                         net (fo=2, routed)           0.069     4.046    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in[21]
    SLICE_X114Y337       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[21]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.593    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.612 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.931     2.543    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/clk
    SLICE_X114Y337       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[21]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/shift_reg_in_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.119ns  (logic 0.040ns (33.613%)  route 0.079ns (66.387%))
  Logic Levels:           0  
  Clock Path Skew:        -1.386ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.543ns
    Source Clock Delay      (SCD):    3.929ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.586ns (routing 0.916ns, distribution 0.670ns)
  Clock Net Delay (Destination): 0.931ns (routing 0.333ns, distribution 0.598ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.861     2.326    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.343 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.586     3.929    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/m_bscan_tck[0]
    SLICE_X114Y331       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/shift_reg_in_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X114Y331       FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.040     3.969 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/shift_reg_in_reg[0]/Q
                         net (fo=2, routed)           0.079     4.048    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_reg[2]_0[0]
    SLICE_X114Y332       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.593    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.612 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.931     2.543    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/clk
    SLICE_X114Y332       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_reg[0]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/shift_reg_in_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/ctl_reg_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.121ns  (logic 0.040ns (33.058%)  route 0.081ns (66.942%))
  Logic Levels:           0  
  Clock Path Skew:        -1.382ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.547ns
    Source Clock Delay      (SCD):    3.929ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.586ns (routing 0.916ns, distribution 0.670ns)
  Clock Net Delay (Destination): 0.935ns (routing 0.333ns, distribution 0.602ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.861     2.326    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.343 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.586     3.929    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/m_bscan_tck[0]
    SLICE_X114Y331       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/shift_reg_in_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X114Y331       FDRE (Prop_BFF2_SLICEL_C_Q)
                                                      0.040     3.969 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/shift_reg_in_reg[1]/Q
                         net (fo=2, routed)           0.081     4.050    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/shift_reg_in[1]
    SLICE_X114Y332       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/ctl_reg_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.593    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.612 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.935     2.547    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/clk
    SLICE_X114Y332       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/ctl_reg_reg[1]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  mmcm_clkout0
  To Clock:  mmcm_clkout5

Max Delay             0 Endpoints
Min Delay            10 Endpoints
--------------------------------------------------------------------------------------


Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[1].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.100ns  (logic 0.039ns (39.000%)  route 0.061ns (61.000%))
  Logic Levels:           0  
  Clock Path Skew:        -0.499ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.470ns
    Source Clock Delay      (SCD):    2.969ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.116ns (routing 0.435ns, distribution 0.681ns)
  Clock Net Delay (Destination): 0.858ns (routing 0.333ns, distribution 0.525ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.836    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.853 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.116     2.969    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/SYNC[0].sync_reg_reg[1]
    SLICE_X92Y321        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y321        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     3.008 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[1]/Q
                         net (fo=1, routed)           0.061     3.069    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[1]
    SLICE_X93Y321        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[1].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.593    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.612 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.858     2.470    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/CLK
    SLICE_X93Y321        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[1].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[2].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.134ns  (logic 0.039ns (29.104%)  route 0.095ns (70.896%))
  Logic Levels:           0  
  Clock Path Skew:        -0.494ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.466ns
    Source Clock Delay      (SCD):    2.960ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.107ns (routing 0.435ns, distribution 0.672ns)
  Clock Net Delay (Destination): 0.854ns (routing 0.333ns, distribution 0.521ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.836    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.853 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.107     2.960    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/SYNC[0].sync_reg_reg[1]
    SLICE_X92Y328        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y328        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.039     2.999 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[2]/Q
                         net (fo=1, routed)           0.095     3.094    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[2]
    SLICE_X95Y328        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[2].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.593    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.612 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.854     2.466    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/CLK
    SLICE_X95Y328        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[2].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[8]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[8].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.132ns  (logic 0.039ns (29.545%)  route 0.093ns (70.455%))
  Logic Levels:           0  
  Clock Path Skew:        -0.493ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.471ns
    Source Clock Delay      (SCD):    2.964ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.111ns (routing 0.435ns, distribution 0.676ns)
  Clock Net Delay (Destination): 0.859ns (routing 0.333ns, distribution 0.526ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.836    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.853 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.111     2.964    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/SYNC[0].sync_reg_reg[1]
    SLICE_X93Y323        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y323        FDRE (Prop_EFF2_SLICEM_C_Q)
                                                      0.039     3.003 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[8]/Q
                         net (fo=1, routed)           0.093     3.096    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[8]
    SLICE_X93Y323        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[8].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.593    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.612 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.859     2.471    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/CLK
    SLICE_X93Y323        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[8].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_rdy_lvl_fclk_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_sync/SYNC[0].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.140ns  (logic 0.039ns (27.920%)  route 0.101ns (72.080%))
  Logic Levels:           0  
  Clock Path Skew:        -0.487ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.479ns
    Source Clock Delay      (SCD):    2.967ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.114ns (routing 0.435ns, distribution 0.679ns)
  Clock Net Delay (Destination): 0.867ns (routing 0.333ns, distribution 0.534ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.836    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.853 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.114     2.967    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/SYNC[0].sync_reg_reg[1]
    SLICE_X93Y324        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_rdy_lvl_fclk_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y324        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.039     3.006 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_rdy_lvl_fclk_reg/Q
                         net (fo=2, routed)           0.101     3.106    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_sync/D[0]
    SLICE_X94Y323        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_sync/SYNC[0].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.593    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.612 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.867     2.479    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_sync/CLK
    SLICE_X94Y323        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_sync/SYNC[0].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[0].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.146ns  (logic 0.039ns (26.712%)  route 0.107ns (73.288%))
  Logic Levels:           0  
  Clock Path Skew:        -0.494ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.470ns
    Source Clock Delay      (SCD):    2.964ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.111ns (routing 0.435ns, distribution 0.676ns)
  Clock Net Delay (Destination): 0.858ns (routing 0.333ns, distribution 0.525ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.836    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.853 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.111     2.964    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/SYNC[0].sync_reg_reg[1]
    SLICE_X93Y323        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y323        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.039     3.003 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[0]/Q
                         net (fo=1, routed)           0.107     3.110    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[0]
    SLICE_X93Y322        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[0].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.593    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.612 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.858     2.470    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/CLK
    SLICE_X93Y322        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[0].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[6].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.154ns  (logic 0.040ns (25.974%)  route 0.114ns (74.026%))
  Logic Levels:           0  
  Clock Path Skew:        -0.496ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.468ns
    Source Clock Delay      (SCD):    2.964ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.111ns (routing 0.435ns, distribution 0.676ns)
  Clock Net Delay (Destination): 0.856ns (routing 0.333ns, distribution 0.523ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.836    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.853 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.111     2.964    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/SYNC[0].sync_reg_reg[1]
    SLICE_X93Y323        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y323        FDRE (Prop_FFF2_SLICEM_C_Q)
                                                      0.040     3.004 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[6]/Q
                         net (fo=1, routed)           0.114     3.118    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[6]
    SLICE_X95Y325        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[6].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.593    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.612 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.856     2.468    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/CLK
    SLICE_X95Y325        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[6].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[5].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.162ns  (logic 0.039ns (24.074%)  route 0.123ns (75.926%))
  Logic Levels:           0  
  Clock Path Skew:        -0.493ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.471ns
    Source Clock Delay      (SCD):    2.964ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.111ns (routing 0.435ns, distribution 0.676ns)
  Clock Net Delay (Destination): 0.859ns (routing 0.333ns, distribution 0.526ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.836    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.853 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.111     2.964    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/SYNC[0].sync_reg_reg[1]
    SLICE_X93Y323        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y323        FDRE (Prop_GFF2_SLICEM_C_Q)
                                                      0.039     3.003 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[5]/Q
                         net (fo=1, routed)           0.123     3.126    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[5]
    SLICE_X93Y323        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[5].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.593    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.612 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.859     2.471    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/CLK
    SLICE_X93Y323        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[5].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[7].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.171ns  (logic 0.040ns (23.392%)  route 0.131ns (76.608%))
  Logic Levels:           0  
  Clock Path Skew:        -0.494ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.466ns
    Source Clock Delay      (SCD):    2.960ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.107ns (routing 0.435ns, distribution 0.672ns)
  Clock Net Delay (Destination): 0.854ns (routing 0.333ns, distribution 0.521ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.836    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.853 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.107     2.960    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/SYNC[0].sync_reg_reg[1]
    SLICE_X92Y328        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y328        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.040     3.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[7]/Q
                         net (fo=1, routed)           0.131     3.131    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[7]
    SLICE_X95Y328        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[7].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.593    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.612 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.854     2.466    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/CLK
    SLICE_X95Y328        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[7].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[4].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.275ns  (logic 0.040ns (14.545%)  route 0.235ns (85.455%))
  Logic Levels:           0  
  Clock Path Skew:        -0.500ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.460ns
    Source Clock Delay      (SCD):    2.960ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.107ns (routing 0.435ns, distribution 0.672ns)
  Clock Net Delay (Destination): 0.848ns (routing 0.333ns, distribution 0.515ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.836    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.853 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.107     2.960    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/SYNC[0].sync_reg_reg[1]
    SLICE_X92Y328        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y328        FDRE (Prop_FFF2_SLICEL_C_Q)
                                                      0.040     3.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[4]/Q
                         net (fo=1, routed)           0.235     3.235    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[4]
    SLICE_X92Y328        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[4].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.593    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.612 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.848     2.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/CLK
    SLICE_X92Y328        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[4].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[3].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.337ns  (logic 0.040ns (11.869%)  route 0.297ns (88.131%))
  Logic Levels:           0  
  Clock Path Skew:        -0.500ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.460ns
    Source Clock Delay      (SCD):    2.960ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.107ns (routing 0.435ns, distribution 0.672ns)
  Clock Net Delay (Destination): 0.848ns (routing 0.333ns, distribution 0.515ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.836    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.853 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.107     2.960    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/SYNC[0].sync_reg_reg[1]
    SLICE_X92Y328        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y328        FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.040     3.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[3]/Q
                         net (fo=1, routed)           0.297     3.297    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[3]
    SLICE_X92Y328        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[3].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.593    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y102        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.612 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.848     2.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/CLK
    SLICE_X92Y328        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[3].sync_reg_reg[0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  mmcm_clkout0
  To Clock:  mmcm_clkout6

Max Delay             0 Endpoints
Min Delay            35 Endpoints
--------------------------------------------------------------------------------------


Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/en_vtc_in_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_en_vtc_sync/SYNC[0].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.094ns  (logic 0.039ns (41.489%)  route 0.055ns (58.511%))
  Logic Levels:           0  
  Clock Path Skew:        -0.067ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.897ns
    Source Clock Delay      (SCD):    2.964ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.111ns (routing 0.435ns, distribution 0.676ns)
  Clock Net Delay (Destination): 1.267ns (routing 0.492ns, distribution 0.775ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.836    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.853 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.111     2.964    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/SYNC[19].sync_reg_reg[1]
    SLICE_X85Y295        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/en_vtc_in_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y295        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.039     3.003 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/en_vtc_in_reg/Q
                         net (fo=1, routed)           0.055     3.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_en_vtc_sync/D[0]
    SLICE_X85Y295        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_en_vtc_sync/SYNC[0].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     1.611    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.630 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.267     2.897    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_en_vtc_sync/CLK
    SLICE_X85Y295        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_en_vtc_sync/SYNC[0].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_ready_lvl_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_ready_lvl_sync/SYNC[0].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.100ns  (logic 0.039ns (38.964%)  route 0.061ns (61.036%))
  Logic Levels:           0  
  Clock Path Skew:        -0.064ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.896ns
    Source Clock Delay      (SCD):    2.960ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.107ns (routing 0.435ns, distribution 0.672ns)
  Clock Net Delay (Destination): 1.266ns (routing 0.492ns, distribution 0.774ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.836    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.853 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.107     2.960    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/odt_shift_reg[0][17]
    SLICE_X88Y298        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_ready_lvl_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y298        FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.039     2.999 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_ready_lvl_reg/Q
                         net (fo=2, routed)           0.061     3.060    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_ready_lvl_sync/D[0]
    SLICE_X88Y298        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_ready_lvl_sync/SYNC[0].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     1.611    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.630 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.266     2.896    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_ready_lvl_sync/CLK
    SLICE_X88Y298        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_ready_lvl_sync/SYNC[0].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[17]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[17].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.098ns  (logic 0.038ns (38.775%)  route 0.060ns (61.224%))
  Logic Levels:           0  
  Clock Path Skew:        -0.072ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.902ns
    Source Clock Delay      (SCD):    2.974ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.121ns (routing 0.435ns, distribution 0.686ns)
  Clock Net Delay (Destination): 1.272ns (routing 0.492ns, distribution 0.780ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.836    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.853 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.121     2.974    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/odt_shift_reg[0][17]
    SLICE_X90Y348        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[17]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X90Y348        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     3.012 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[17]/Q
                         net (fo=1, routed)           0.060     3.072    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[17]
    SLICE_X90Y348        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[17].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     1.611    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.630 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.272     2.902    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/CLK
    SLICE_X90Y348        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[17].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[31]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.103ns  (logic 0.039ns (37.864%)  route 0.064ns (62.136%))
  Logic Levels:           0  
  Clock Path Skew:        -0.059ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.912ns
    Source Clock Delay      (SCD):    2.971ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.118ns (routing 0.435ns, distribution 0.683ns)
  Clock Net Delay (Destination): 1.282ns (routing 0.492ns, distribution 0.790ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.836    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.853 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.118     2.971    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/odt_shift_reg[0][17]
    SLICE_X89Y348        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[31]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y348        FDRE (Prop_GFF2_SLICEM_C_Q)
                                                      0.039     3.010 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[31]/Q
                         net (fo=1, routed)           0.064     3.074    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[31]
    SLICE_X89Y349        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     1.611    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.630 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.282     2.912    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/CLK
    SLICE_X89Y349        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[12]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[12].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.107ns  (logic 0.039ns (36.449%)  route 0.068ns (63.551%))
  Logic Levels:           0  
  Clock Path Skew:        -0.060ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.915ns
    Source Clock Delay      (SCD):    2.975ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.122ns (routing 0.435ns, distribution 0.687ns)
  Clock Net Delay (Destination): 1.285ns (routing 0.492ns, distribution 0.793ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.836    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.853 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.122     2.975    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/odt_shift_reg[0][17]
    SLICE_X89Y305        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[12]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y305        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.039     3.014 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[12]/Q
                         net (fo=1, routed)           0.068     3.082    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[12]
    SLICE_X89Y306        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[12].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     1.611    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.630 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.285     2.915    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/CLK
    SLICE_X89Y306        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[12].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/rst_r1_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_fab_rst_sync/SYNC[0].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.120ns  (logic 0.039ns (32.500%)  route 0.081ns (67.500%))
  Logic Levels:           0  
  Clock Path Skew:        -0.062ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.905ns
    Source Clock Delay      (SCD):    2.967ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.114ns (routing 0.435ns, distribution 0.679ns)
  Clock Net Delay (Destination): 1.275ns (routing 0.492ns, distribution 0.783ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.836    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.853 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.114     2.967    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/SYNC[19].sync_reg_reg[1]
    SLICE_X85Y333        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/rst_r1_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y333        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     3.006 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/rst_r1_reg/Q
                         net (fo=1, routed)           0.081     3.087    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_fab_rst_sync/D[0]
    SLICE_X85Y333        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_fab_rst_sync/SYNC[0].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     1.611    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.630 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.275     2.905    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_fab_rst_sync/CLK
    SLICE_X85Y333        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_fab_rst_sync/SYNC[0].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[7].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.122ns  (logic 0.039ns (31.967%)  route 0.083ns (68.033%))
  Logic Levels:           0  
  Clock Path Skew:        -0.075ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.890ns
    Source Clock Delay      (SCD):    2.965ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.112ns (routing 0.435ns, distribution 0.677ns)
  Clock Net Delay (Destination): 1.260ns (routing 0.492ns, distribution 0.768ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.836    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.853 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.112     2.965    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/odt_shift_reg[0][17]
    SLICE_X92Y322        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y322        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.039     3.004 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[7]/Q
                         net (fo=1, routed)           0.083     3.087    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[7]
    SLICE_X92Y322        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[7].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     1.611    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.630 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.260     2.890    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/CLK
    SLICE_X92Y322        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[7].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[6].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.115ns  (logic 0.039ns (33.913%)  route 0.076ns (66.087%))
  Logic Levels:           0  
  Clock Path Skew:        -0.071ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.904ns
    Source Clock Delay      (SCD):    2.975ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.122ns (routing 0.435ns, distribution 0.687ns)
  Clock Net Delay (Destination): 1.274ns (routing 0.492ns, distribution 0.782ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.836    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.853 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.122     2.975    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/odt_shift_reg[0][17]
    SLICE_X91Y316        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y316        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.039     3.014 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[6]/Q
                         net (fo=1, routed)           0.076     3.090    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[6]
    SLICE_X91Y316        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[6].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     1.611    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.630 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.274     2.904    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/CLK
    SLICE_X91Y316        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[6].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[14]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[14].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.114ns  (logic 0.039ns (34.211%)  route 0.075ns (65.790%))
  Logic Levels:           0  
  Clock Path Skew:        -0.070ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.907ns
    Source Clock Delay      (SCD):    2.977ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.124ns (routing 0.435ns, distribution 0.689ns)
  Clock Net Delay (Destination): 1.277ns (routing 0.492ns, distribution 0.785ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.836    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.853 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.124     2.977    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/odt_shift_reg[0][17]
    SLICE_X88Y345        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[14]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y345        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     3.016 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[14]/Q
                         net (fo=1, routed)           0.075     3.091    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[14]
    SLICE_X88Y345        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[14].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     1.611    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.630 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.277     2.907    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/CLK
    SLICE_X88Y345        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[14].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[29]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[29].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.129ns  (logic 0.039ns (30.233%)  route 0.090ns (69.767%))
  Logic Levels:           0  
  Clock Path Skew:        -0.071ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.892ns
    Source Clock Delay      (SCD):    2.963ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.110ns (routing 0.435ns, distribution 0.675ns)
  Clock Net Delay (Destination): 1.262ns (routing 0.492ns, distribution 0.770ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.836    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.853 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.110     2.963    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/odt_shift_reg[0][17]
    SLICE_X88Y297        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[29]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y297        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.039     3.002 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[29]/Q
                         net (fo=1, routed)           0.090     3.092    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[29]
    SLICE_X88Y297        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[29].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     1.611    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.630 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.262     2.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/CLK
    SLICE_X88Y297        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[29].sync_reg_reg[0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  mmcm_clkout6
  To Clock:  mmcm_clkout6

Max Delay             2 Endpoints
Min Delay           486 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/FDRE_inst/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Reset_DFF/Synchronize.use_sync_reset.sync_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.668ns  (logic 0.079ns (11.826%)  route 0.589ns (88.174%))
  Logic Levels:           0  
  Clock Path Skew:        0.174ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.995ns
    Source Clock Delay      (SCD):    4.821ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.042ns (routing 0.799ns, distribution 1.243ns)
  Clock Net Delay (Destination): 1.830ns (routing 0.726ns, distribution 1.104ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     2.751    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.779 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        2.042     4.821    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/slowest_sync_clk
    SLICE_X85Y333        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/FDRE_inst/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y333        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     4.900 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/FDRE_inst/Q
                         net (fo=1, routed)           0.589     5.489    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Reset_DFF/Reset
    SLICE_X86Y338        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Reset_DFF/Synchronize.use_sync_reset.sync_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.227     3.141    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.165 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.830     4.995    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Reset_DFF/Clk
    SLICE_X86Y338        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Reset_DFF/Synchronize.use_sync_reset.sync_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_mb_logic_r1_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.570ns  (logic 0.076ns (13.341%)  route 0.494ns (86.659%))
  Logic Levels:           0  
  Clock Path Skew:        0.167ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.020ns
    Source Clock Delay      (SCD):    4.853ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.074ns (routing 0.799ns, distribution 1.275ns)
  Clock Net Delay (Destination): 1.855ns (routing 0.726ns, distribution 1.129ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     2.751    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.779 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        2.074     4.853    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/c0_riu_clk
    SLICE_X82Y323        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_mb_logic_r1_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y323        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     4.929 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_mb_logic_r1_reg/Q
                         net (fo=5, routed)           0.494     5.423    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/ext_reset_in
    SLICE_X82Y313        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.227     3.141    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.165 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.855     5.020    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/slowest_sync_clk
    SLICE_X82Y313        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_mb_logic_r1_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.262ns  (logic 0.038ns (14.497%)  route 0.224ns (85.503%))
  Logic Levels:           0  
  Clock Path Skew:        -0.078ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.925ns
    Source Clock Delay      (SCD):    3.003ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.140ns (routing 0.439ns, distribution 0.701ns)
  Clock Net Delay (Destination): 1.295ns (routing 0.492ns, distribution 0.803ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     1.846    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.863 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.140     3.003    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/c0_riu_clk
    SLICE_X82Y323        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_mb_logic_r1_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y323        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     3.041 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_mb_logic_r1_reg/Q
                         net (fo=5, routed)           0.224     3.265    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/ext_reset_in
    SLICE_X82Y313        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     1.611    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.630 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.295     2.925    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/slowest_sync_clk
    SLICE_X82Y313        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/FDRE_inst/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Reset_DFF/Synchronize.use_sync_reset.sync_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.293ns  (logic 0.039ns (13.311%)  route 0.254ns (86.689%))
  Logic Levels:           0  
  Clock Path Skew:        -0.079ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.911ns
    Source Clock Delay      (SCD):    2.990ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.127ns (routing 0.439ns, distribution 0.688ns)
  Clock Net Delay (Destination): 1.281ns (routing 0.492ns, distribution 0.789ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     1.846    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.863 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.127     2.990    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/slowest_sync_clk
    SLICE_X85Y333        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/FDRE_inst/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y333        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     3.029 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/FDRE_inst/Q
                         net (fo=1, routed)           0.254     3.283    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Reset_DFF/Reset
    SLICE_X86Y338        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Reset_DFF/Synchronize.use_sync_reset.sync_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     1.611    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.630 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.281     2.911    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Reset_DFF/Clk
    SLICE_X86Y338        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Reset_DFF/Synchronize.use_sync_reset.sync_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[4]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.347ns  (logic 0.038ns (10.942%)  route 0.309ns (89.058%))
  Logic Levels:           0  
  Clock Path Skew:        -0.019ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.985ns
    Source Clock Delay      (SCD):    3.004ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.141ns (routing 0.439ns, distribution 0.702ns)
  Clock Net Delay (Destination): 1.355ns (routing 0.492ns, distribution 0.863ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     1.846    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.863 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.141     3.004    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X82Y323        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y323        FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.038     3.042 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[4]/Q
                         net (fo=22, routed)          0.309     3.351    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control_1[4]
    BITSLICE_CONTROL_X0Y42
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[4]
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     1.611    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.630 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.355     2.985    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/riu_clk
    BITSLICE_CONTROL_X0Y42
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[4]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.348ns  (logic 0.038ns (10.910%)  route 0.310ns (89.090%))
  Logic Levels:           0  
  Clock Path Skew:        -0.023ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.981ns
    Source Clock Delay      (SCD):    3.004ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.141ns (routing 0.439ns, distribution 0.702ns)
  Clock Net Delay (Destination): 1.351ns (routing 0.492ns, distribution 0.859ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     1.846    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.863 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.141     3.004    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X82Y323        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y323        FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.038     3.042 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[4]/Q
                         net (fo=22, routed)          0.310     3.352    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control_3[4]
    BITSLICE_CONTROL_X0Y43
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[4]
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     1.611    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.630 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.351     2.981    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/riu_clk
    BITSLICE_CONTROL_X0Y43
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[10]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[10]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.374ns  (logic 0.038ns (10.149%)  route 0.336ns (89.851%))
  Logic Levels:           0  
  Clock Path Skew:        -0.017ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.977ns
    Source Clock Delay      (SCD):    2.994ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.131ns (routing 0.439ns, distribution 0.692ns)
  Clock Net Delay (Destination): 1.347ns (routing 0.492ns, distribution 0.855ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     1.846    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.863 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.131     2.994    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X82Y332        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[10]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y332        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     3.032 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[10]/Q
                         net (fo=22, routed)          0.336     3.368    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control_1[10]
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[10]
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     1.611    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.630 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.347     2.977    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/riu_clk
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[10]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[10]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.374ns  (logic 0.038ns (10.149%)  route 0.336ns (89.851%))
  Logic Levels:           0  
  Clock Path Skew:        -0.009ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.985ns
    Source Clock Delay      (SCD):    2.994ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.131ns (routing 0.439ns, distribution 0.692ns)
  Clock Net Delay (Destination): 1.355ns (routing 0.492ns, distribution 0.863ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     1.846    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.863 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.131     2.994    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X82Y332        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[10]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y332        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     3.032 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[10]/Q
                         net (fo=22, routed)          0.336     3.368    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control_3[10]
    BITSLICE_CONTROL_X0Y45
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[10]
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     1.611    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.630 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.355     2.985    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/riu_clk
    BITSLICE_CONTROL_X0Y45
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_addr_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_ADDR[0]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.378ns  (logic 0.039ns (10.326%)  route 0.339ns (89.674%))
  Logic Levels:           0  
  Clock Path Skew:        -0.043ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.967ns
    Source Clock Delay      (SCD):    3.010ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.147ns (routing 0.439ns, distribution 0.708ns)
  Clock Net Delay (Destination): 1.337ns (routing 0.492ns, distribution 0.845ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     1.846    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.863 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.147     3.010    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X84Y306        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_addr_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X84Y306        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.039     3.049 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_addr_reg[0]/Q
                         net (fo=22, routed)          0.339     3.387    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control_11[0]
    BITSLICE_CONTROL_X0Y38
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_ADDR[0]
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     1.611    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.630 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.337     2.967    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/riu_clk
    BITSLICE_CONTROL_X0Y38
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_addr_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_ADDR[0]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.378ns  (logic 0.039ns (10.326%)  route 0.339ns (89.674%))
  Logic Levels:           0  
  Clock Path Skew:        -0.039ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.971ns
    Source Clock Delay      (SCD):    3.010ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.147ns (routing 0.439ns, distribution 0.708ns)
  Clock Net Delay (Destination): 1.341ns (routing 0.492ns, distribution 0.849ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     1.846    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.863 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.147     3.010    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X84Y306        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_addr_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X84Y306        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.039     3.049 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_addr_reg[0]/Q
                         net (fo=22, routed)          0.339     3.387    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control_13[0]
    BITSLICE_CONTROL_X0Y39
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_ADDR[0]
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     1.611    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.630 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.341     2.971    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/riu_clk
    BITSLICE_CONTROL_X0Y39
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[3]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.392ns  (logic 0.038ns (9.697%)  route 0.354ns (90.303%))
  Logic Levels:           0  
  Clock Path Skew:        -0.019ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.985ns
    Source Clock Delay      (SCD):    3.004ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.141ns (routing 0.439ns, distribution 0.702ns)
  Clock Net Delay (Destination): 1.355ns (routing 0.492ns, distribution 0.863ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     1.846    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.863 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.141     3.004    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X82Y323        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y323        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     3.042 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[3]/Q
                         net (fo=22, routed)          0.354     3.395    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control_1[3]
    BITSLICE_CONTROL_X0Y42
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[3]
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     1.611    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.630 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.355     2.985    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/riu_clk
    BITSLICE_CONTROL_X0Y42
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[3]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.393ns  (logic 0.038ns (9.672%)  route 0.355ns (90.328%))
  Logic Levels:           0  
  Clock Path Skew:        -0.023ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.981ns
    Source Clock Delay      (SCD):    3.004ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.141ns (routing 0.439ns, distribution 0.702ns)
  Clock Net Delay (Destination): 1.351ns (routing 0.492ns, distribution 0.859ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     1.846    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.863 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.141     3.004    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X82Y323        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y323        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     3.042 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[3]/Q
                         net (fo=22, routed)          0.355     3.396    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control_3[3]
    BITSLICE_CONTROL_X0Y43
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[3]
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     1.611    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.630 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.351     2.981    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/riu_clk
    BITSLICE_CONTROL_X0Y43
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  sys_clk_ddr4_clk_p
  To Clock:  mmcm_clkout6

Max Delay             2 Endpoints
Min Delay             2 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_riu_sync_r_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.322ns  (logic 0.081ns (25.152%)  route 0.241ns (74.848%))
  Logic Levels:           0  
  Clock Path Skew:        2.198ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.018ns
    Source Clock Delay      (SCD):    2.820ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.167ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.734ns (routing 0.702ns, distribution 1.032ns)
  Clock Net Delay (Destination): 1.853ns (routing 0.726ns, distribution 1.127ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.734     2.820    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X84Y309        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X84Y309        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.081     2.901 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/Q
                         net (fo=2, routed)           0.241     3.142    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div
    SLICE_X84Y306        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_riu_sync_r_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.227     3.141    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.165 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.853     5.018    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/c0_riu_clk
    SLICE_X84Y306        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_riu_sync_r_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_mb_sync_r_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.282ns  (logic 0.081ns (28.723%)  route 0.201ns (71.277%))
  Logic Levels:           0  
  Clock Path Skew:        2.195ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.016ns
    Source Clock Delay      (SCD):    2.821ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.167ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.735ns (routing 0.702ns, distribution 1.033ns)
  Clock Net Delay (Destination): 1.851ns (routing 0.726ns, distribution 1.125ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.735     2.821    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X84Y305        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X84Y305        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.081     2.902 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/Q
                         net (fo=1, routed)           0.201     3.103    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb
    SLICE_X84Y306        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_mb_sync_r_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.369     2.284    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     2.914 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.227     3.141    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.165 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.851     5.016    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/c0_riu_clk
    SLICE_X84Y306        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_mb_sync_r_reg[0]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_mb_sync_r_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.119ns  (logic 0.040ns (33.613%)  route 0.079ns (66.387%))
  Logic Levels:           0  
  Clock Path Skew:        1.344ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.921ns
    Source Clock Delay      (SCD):    1.577ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.167ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.960ns (routing 0.389ns, distribution 0.571ns)
  Clock Net Delay (Destination): 1.291ns (routing 0.492ns, distribution 0.799ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          0.960     1.577    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X84Y305        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X84Y305        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.040     1.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/Q
                         net (fo=1, routed)           0.079     1.696    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb
    SLICE_X84Y306        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_mb_sync_r_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     1.611    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.630 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.291     2.921    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/c0_riu_clk
    SLICE_X84Y306        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_mb_sync_r_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_riu_sync_r_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.148ns  (logic 0.040ns (27.085%)  route 0.108ns (72.915%))
  Logic Levels:           0  
  Clock Path Skew:        1.349ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.925ns
    Source Clock Delay      (SCD):    1.576ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.167ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.959ns (routing 0.389ns, distribution 0.570ns)
  Clock Net Delay (Destination): 1.295ns (routing 0.492ns, distribution 0.803ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          0.959     1.576    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X84Y309        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X84Y309        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.040     1.616 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/Q
                         net (fo=2, routed)           0.108     1.724    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div
    SLICE_X84Y306        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_riu_sync_r_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.942     1.729    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     1.611    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.630 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.295     2.925    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/c0_riu_clk
    SLICE_X84Y306        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_riu_sync_r_reg[0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_pl_0
  To Clock:  sys_clk_ddr4_clk_p

Max Delay             2 Endpoints
Min Delay             2 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/rst_100/U0/BSR_OUT_DFF[0].FDRE_BSR/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[0]/PRE
                            (recovery check against rising-edge clock sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        0.875ns  (logic 0.079ns (9.029%)  route 0.796ns (90.971%))
  Logic Levels:           0  
  Clock Path Skew:        -0.098ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.442ns
    Source Clock Delay      (SCD):    2.540ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.314ns (routing 0.662ns, distribution 1.652ns)
  Clock Net Delay (Destination): 1.527ns (routing 0.637ns, distribution 0.890ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.314     2.540    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X92Y110        FDRE                                         r  d_1_i/rst_100/U0/BSR_OUT_DFF[0].FDRE_BSR/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y110        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.619 f  d_1_i/rst_100/U0/BSR_OUT_DFF[0].FDRE_BSR/Q
                         net (fo=2, routed)           0.796     3.415    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_rst
    SLICE_X92Y180        FDPE                                         f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[0]/PRE
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.527     2.442    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X92Y180        FDPE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/rst_100/U0/BSR_OUT_DFF[0].FDRE_BSR/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[1]/PRE
                            (recovery check against rising-edge clock sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        0.875ns  (logic 0.079ns (9.029%)  route 0.796ns (90.971%))
  Logic Levels:           0  
  Clock Path Skew:        -0.098ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.442ns
    Source Clock Delay      (SCD):    2.540ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.314ns (routing 0.662ns, distribution 1.652ns)
  Clock Net Delay (Destination): 1.527ns (routing 0.637ns, distribution 0.890ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.314     2.540    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X92Y110        FDRE                                         r  d_1_i/rst_100/U0/BSR_OUT_DFF[0].FDRE_BSR/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y110        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.619 f  d_1_i/rst_100/U0/BSR_OUT_DFF[0].FDRE_BSR/Q
                         net (fo=2, routed)           0.796     3.415    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_rst
    SLICE_X92Y180        FDPE                                         f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[1]/PRE
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.527     2.442    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X92Y180        FDPE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[1]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/rst_100/U0/BSR_OUT_DFF[0].FDRE_BSR/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[0]/PRE
                            (removal check against rising-edge clock sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.436ns  (logic 0.039ns (8.945%)  route 0.397ns (91.055%))
  Logic Levels:           0  
  Clock Path Skew:        0.482ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.873ns
    Source Clock Delay      (SCD):    1.391ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.271ns (routing 0.358ns, distribution 0.913ns)
  Clock Net Delay (Destination): 1.086ns (routing 0.434ns, distribution 0.652ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.271     1.391    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X92Y110        FDRE                                         r  d_1_i/rst_100/U0/BSR_OUT_DFF[0].FDRE_BSR/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y110        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     1.430 f  d_1_i/rst_100/U0/BSR_OUT_DFF[0].FDRE_BSR/Q
                         net (fo=2, routed)           0.397     1.827    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_rst
    SLICE_X92Y180        FDPE                                         f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[0]/PRE
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.086     1.873    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X92Y180        FDPE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/rst_100/U0/BSR_OUT_DFF[0].FDRE_BSR/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[1]/PRE
                            (removal check against rising-edge clock sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.436ns  (logic 0.039ns (8.945%)  route 0.397ns (91.055%))
  Logic Levels:           0  
  Clock Path Skew:        0.482ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.873ns
    Source Clock Delay      (SCD):    1.391ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.271ns (routing 0.358ns, distribution 0.913ns)
  Clock Net Delay (Destination): 1.086ns (routing 0.434ns, distribution 0.652ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.271     1.391    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X92Y110        FDRE                                         r  d_1_i/rst_100/U0/BSR_OUT_DFF[0].FDRE_BSR/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y110        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     1.430 f  d_1_i/rst_100/U0/BSR_OUT_DFF[0].FDRE_BSR/Q
                         net (fo=2, routed)           0.397     1.827    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_rst
    SLICE_X92Y180        FDPE                                         f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[1]/PRE
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.086     1.873    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X92Y180        FDPE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[1]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_pl_0
  To Clock:  

Max Delay             6 Endpoints
Min Delay             6 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        2.744ns  (logic 0.028ns (1.020%)  route 2.716ns (98.980%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 fall edge)
                                                      5.000     5.000 f  
    PS8_X0Y0             PS8                          0.000     5.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     5.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     5.226 f  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55323, routed)       2.518     7.744    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    HSDAC_X0Y1           HSDAC                                        f  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/PLL_MONCLK
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        2.736ns  (logic 0.028ns (1.023%)  route 2.708ns (98.977%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 fall edge)
                                                      5.000     5.000 f  
    PS8_X0Y0             PS8                          0.000     5.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     5.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     5.226 f  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55323, routed)       2.510     7.736    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    HSDAC_X0Y0           HSDAC                                        f  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/PLL_MONCLK
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        2.721ns  (logic 0.028ns (1.029%)  route 2.693ns (98.971%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 fall edge)
                                                      5.000     5.000 f  
    PS8_X0Y0             PS8                          0.000     5.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     5.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     5.226 f  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55323, routed)       2.495     7.721    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    HSADC_X0Y0           HSADC                                        f  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/PLL_MONCLK
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        2.699ns  (logic 0.028ns (1.038%)  route 2.671ns (98.962%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 fall edge)
                                                      5.000     5.000 f  
    PS8_X0Y0             PS8                          0.000     5.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     5.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     5.226 f  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55323, routed)       2.473     7.699    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    HSADC_X0Y3           HSADC                                        f  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/PLL_MONCLK
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        2.698ns  (logic 0.028ns (1.038%)  route 2.670ns (98.962%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 fall edge)
                                                      5.000     5.000 f  
    PS8_X0Y0             PS8                          0.000     5.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     5.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     5.226 f  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55323, routed)       2.472     7.698    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    HSADC_X0Y1           HSADC                                        f  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/PLL_MONCLK
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        2.678ns  (logic 0.028ns (1.046%)  route 2.650ns (98.954%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 fall edge)
                                                      5.000     5.000 f  
    PS8_X0Y0             PS8                          0.000     5.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     5.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     5.226 f  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55323, routed)       2.452     7.678    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    HSADC_X0Y2           HSADC                                        f  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/PLL_MONCLK
  -------------------------------------------------------------------    -------------------





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.446ns  (logic 0.017ns (1.176%)  route 1.429ns (98.824%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55323, routed)       1.326     1.446    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    HSADC_X0Y3           HSADC                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/PLL_MONCLK
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.449ns  (logic 0.017ns (1.173%)  route 1.432ns (98.827%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55323, routed)       1.329     1.449    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    HSADC_X0Y2           HSADC                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/PLL_MONCLK
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.461ns  (logic 0.017ns (1.164%)  route 1.444ns (98.836%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55323, routed)       1.341     1.461    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    HSADC_X0Y1           HSADC                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/PLL_MONCLK
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.468ns  (logic 0.017ns (1.158%)  route 1.451ns (98.842%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55323, routed)       1.348     1.468    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    HSDAC_X0Y0           HSDAC                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/PLL_MONCLK
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.476ns  (logic 0.017ns (1.152%)  route 1.459ns (98.848%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55323, routed)       1.356     1.476    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    HSDAC_X0Y1           HSDAC                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/PLL_MONCLK
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.478ns  (logic 0.017ns (1.150%)  route 1.461ns (98.850%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=55323, routed)       1.358     1.478    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    HSADC_X0Y0           HSADC                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/PLL_MONCLK
  -------------------------------------------------------------------    -------------------





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  mmcm_clkout0
  To Clock:  

Max Delay             1 Endpoint
Min Delay             1 Endpoint
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/cal_RESET_n_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            ddr4_pl_reset_n
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        2.452ns  (logic 0.926ns (37.753%)  route 1.526ns (62.247%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.156ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.021ns (routing 0.788ns, distribution 1.233ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.530     2.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.489 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       2.021     4.783    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X91Y318        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/cal_RESET_n_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y318        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     4.862 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/cal_RESET_n_reg[0]/Q
                         net (fo=1, routed)           1.526     6.388    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/cal_RESET_n[0]
    A17                  OBUF (Prop_OUTBUF_HPIOB_M_I_O)
                                                      0.847     7.234 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/OBUF_reset_n/O
                         net (fo=0)                   0.000     7.234    ddr4_pl_reset_n
    A17                                                               r  ddr4_pl_reset_n (OUT)
  -------------------------------------------------------------------    -------------------





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/cal_RESET_n_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            ddr4_pl_reset_n
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.159ns  (logic 0.459ns (39.611%)  route 0.700ns (60.389%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.156ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.118ns (routing 0.435ns, distribution 0.683ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.843     1.460    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.690 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.836    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y112        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.853 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41415, routed)       1.118     2.971    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X91Y318        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/cal_RESET_n_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y318        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     3.010 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/cal_RESET_n_reg[0]/Q
                         net (fo=1, routed)           0.700     3.710    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/cal_RESET_n[0]
    A17                  OBUF (Prop_OUTBUF_HPIOB_M_I_O)
                                                      0.420     4.130 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/OBUF_reset_n/O
                         net (fo=0)                   0.000     4.130    ddr4_pl_reset_n
    A17                                                               r  ddr4_pl_reset_n (OUT)
  -------------------------------------------------------------------    -------------------





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  
  To Clock:  clk_out1_d_1_clk_adc0_x2_0

Max Delay            81 Endpoints
Min Delay            81 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/LOCKED
                            (internal pin)
  Destination:            d_1_i/rst_adc0_x2/U0/EXT_LPF/lpf_int_reg/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.515ns  (logic 0.099ns (6.535%)  route 1.416ns (93.465%))
  Logic Levels:           1  (LUT4=1)
  Clock Uncertainty:      0.122ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Destination): 1.803ns (routing 0.782ns, distribution 1.021ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    MMCM_X0Y1            MMCME4_ADV                   0.000     0.000 f  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/LOCKED
                         net (fo=1, routed)           1.367     1.367    d_1_i/rst_adc0_x2/U0/EXT_LPF/dcm_locked
    SLICE_X57Y154        LUT4 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.099     1.466 r  d_1_i/rst_adc0_x2/U0/EXT_LPF/lpf_int0/O
                         net (fo=1, routed)           0.049     1.515    d_1_i/rst_adc0_x2/U0/EXT_LPF/lpf_int0__0
    SLICE_X57Y154        FDRE                                         r  d_1_i/rst_adc0_x2/U0/EXT_LPF/lpf_int_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.341     2.727    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.357 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.572    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.596 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.803     5.399    d_1_i/rst_adc0_x2/U0/EXT_LPF/slowest_sync_clk
    SLICE_X57Y154        FDRE                                         r  d_1_i/rst_adc0_x2/U0/EXT_LPF/lpf_int_reg/C

Slack:                    inf
  Source:                 d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_real[1]/DSP_C_DATA_INST/C_DATA[22]
                            (internal pin)
  Destination:            d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_dds[1].dout_mux_r[1][6]_i_1_psdsp/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.301ns  (logic 0.694ns (53.344%)  route 0.607ns (46.656%))
  Logic Levels:           2  (DSP_ALU=1 DSP_OUTPUT=1)
  Clock Uncertainty:      0.122ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Destination): 2.072ns (routing 0.782ns, distribution 1.290ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    DSP48E2_X17Y24       DSP_C_DATA                   0.000     0.000 r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_real[1]/DSP_C_DATA_INST/C_DATA[22]
                         net (fo=2, routed)           0.000     0.000    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_real[1]/DSP_C_DATA.C_DATA<22>
    DSP48E2_X17Y24       DSP_ALU (Prop_DSP_ALU_DSP48E2_C_DATA[22]_ALU_OUT[22])
                                                      0.585     0.585 f  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_real[1]/DSP_ALU_INST/ALU_OUT[22]
                         net (fo=1, routed)           0.000     0.585    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_real[1]/DSP_ALU.ALU_OUT<22>
    DSP48E2_X17Y24       DSP_OUTPUT (Prop_DSP_OUTPUT_DSP48E2_ALU_OUT[22]_P[22])
                                                      0.109     0.694 r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_real[1]/DSP_OUTPUT_INST/P[22]
                         net (fo=1, routed)           0.607     1.301    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_dds[1].dout_mux_r[1][6]_i_1_psdsp_n
    SLICE_X89Y63         FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_dds[1].dout_mux_r[1][6]_i_1_psdsp/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.341     2.727    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.357 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.572    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.596 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       2.072     5.668    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/aclk
    SLICE_X89Y63         FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_dds[1].dout_mux_r[1][6]_i_1_psdsp/C

Slack:                    inf
  Source:                 d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_real[1]/DSP_C_DATA_INST/C_DATA[21]
                            (internal pin)
  Destination:            d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_dds[1].dout_mux_r[1][5]_i_1_psdsp/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.240ns  (logic 0.694ns (55.968%)  route 0.546ns (44.032%))
  Logic Levels:           2  (DSP_ALU=1 DSP_OUTPUT=1)
  Clock Uncertainty:      0.122ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Destination): 2.072ns (routing 0.782ns, distribution 1.290ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    DSP48E2_X17Y24       DSP_C_DATA                   0.000     0.000 r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_real[1]/DSP_C_DATA_INST/C_DATA[21]
                         net (fo=2, routed)           0.000     0.000    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_real[1]/DSP_C_DATA.C_DATA<21>
    DSP48E2_X17Y24       DSP_ALU (Prop_DSP_ALU_DSP48E2_C_DATA[21]_ALU_OUT[21])
                                                      0.585     0.585 f  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_real[1]/DSP_ALU_INST/ALU_OUT[21]
                         net (fo=1, routed)           0.000     0.585    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_real[1]/DSP_ALU.ALU_OUT<21>
    DSP48E2_X17Y24       DSP_OUTPUT (Prop_DSP_OUTPUT_DSP48E2_ALU_OUT[21]_P[21])
                                                      0.109     0.694 r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_real[1]/DSP_OUTPUT_INST/P[21]
                         net (fo=1, routed)           0.546     1.240    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_dds[1].dout_mux_r[1][5]_i_1_psdsp_n
    SLICE_X89Y63         FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_dds[1].dout_mux_r[1][5]_i_1_psdsp/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.341     2.727    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.357 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.572    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.596 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       2.072     5.668    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/aclk
    SLICE_X89Y63         FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_dds[1].dout_mux_r[1][5]_i_1_psdsp/C

Slack:                    inf
  Source:                 d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_real[0]/DSP_C_DATA_INST/C_DATA[29]
                            (internal pin)
  Destination:            d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_dds[0].dout_mux_r[0][13]_i_1_psdsp/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.210ns  (logic 0.694ns (57.355%)  route 0.516ns (42.645%))
  Logic Levels:           2  (DSP_ALU=1 DSP_OUTPUT=1)
  Clock Uncertainty:      0.122ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Destination): 2.114ns (routing 0.782ns, distribution 1.332ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    DSP48E2_X20Y38       DSP_C_DATA                   0.000     0.000 r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_real[0]/DSP_C_DATA_INST/C_DATA[29]
                         net (fo=2, routed)           0.000     0.000    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_real[0]/DSP_C_DATA.C_DATA<29>
    DSP48E2_X20Y38       DSP_ALU (Prop_DSP_ALU_DSP48E2_C_DATA[29]_ALU_OUT[29])
                                                      0.585     0.585 f  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_real[0]/DSP_ALU_INST/ALU_OUT[29]
                         net (fo=1, routed)           0.000     0.585    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_real[0]/DSP_ALU.ALU_OUT<29>
    DSP48E2_X20Y38       DSP_OUTPUT (Prop_DSP_OUTPUT_DSP48E2_ALU_OUT[29]_P[29])
                                                      0.109     0.694 r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_real[0]/DSP_OUTPUT_INST/P[29]
                         net (fo=1, routed)           0.516     1.210    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_dds[0].dout_mux_r[0][13]_i_1_psdsp_n
    SLICE_X98Y110        FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_dds[0].dout_mux_r[0][13]_i_1_psdsp/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.341     2.727    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.357 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.572    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.596 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       2.114     5.710    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/aclk
    SLICE_X98Y110        FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_dds[0].dout_mux_r[0][13]_i_1_psdsp/C

Slack:                    inf
  Source:                 d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_real[0]/DSP_C_DATA_INST/C_DATA[30]
                            (internal pin)
  Destination:            d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_dds[0].dout_mux_r[0][14]_i_1_psdsp/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.199ns  (logic 0.694ns (57.882%)  route 0.505ns (42.118%))
  Logic Levels:           2  (DSP_ALU=1 DSP_OUTPUT=1)
  Clock Uncertainty:      0.122ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Destination): 2.114ns (routing 0.782ns, distribution 1.332ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    DSP48E2_X20Y38       DSP_C_DATA                   0.000     0.000 r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_real[0]/DSP_C_DATA_INST/C_DATA[30]
                         net (fo=2, routed)           0.000     0.000    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_real[0]/DSP_C_DATA.C_DATA<30>
    DSP48E2_X20Y38       DSP_ALU (Prop_DSP_ALU_DSP48E2_C_DATA[30]_ALU_OUT[30])
                                                      0.585     0.585 f  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_real[0]/DSP_ALU_INST/ALU_OUT[30]
                         net (fo=1, routed)           0.000     0.585    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_real[0]/DSP_ALU.ALU_OUT<30>
    DSP48E2_X20Y38       DSP_OUTPUT (Prop_DSP_OUTPUT_DSP48E2_ALU_OUT[30]_P[30])
                                                      0.109     0.694 r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_real[0]/DSP_OUTPUT_INST/P[30]
                         net (fo=1, routed)           0.505     1.199    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_dds[0].dout_mux_r[0][14]_i_1_psdsp_n
    SLICE_X98Y110        FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_dds[0].dout_mux_r[0][14]_i_1_psdsp/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.341     2.727    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.357 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.572    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.596 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       2.114     5.710    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/aclk
    SLICE_X98Y110        FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_dds[0].dout_mux_r[0][14]_i_1_psdsp/C

Slack:                    inf
  Source:                 d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_imag[1]/DSP_C_DATA_INST/C_DATA[31]
                            (internal pin)
  Destination:            d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_dds[1].dout_mux_r[1][31]_i_1_psdsp/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.194ns  (logic 0.694ns (58.124%)  route 0.500ns (41.876%))
  Logic Levels:           2  (DSP_ALU=1 DSP_OUTPUT=1)
  Clock Uncertainty:      0.122ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Destination): 2.063ns (routing 0.782ns, distribution 1.281ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    DSP48E2_X17Y25       DSP_C_DATA                   0.000     0.000 r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_imag[1]/DSP_C_DATA_INST/C_DATA[31]
                         net (fo=2, routed)           0.000     0.000    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_imag[1]/DSP_C_DATA.C_DATA<31>
    DSP48E2_X17Y25       DSP_ALU (Prop_DSP_ALU_DSP48E2_C_DATA[31]_ALU_OUT[31])
                                                      0.585     0.585 f  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_imag[1]/DSP_ALU_INST/ALU_OUT[31]
                         net (fo=1, routed)           0.000     0.585    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_imag[1]/DSP_ALU.ALU_OUT<31>
    DSP48E2_X17Y25       DSP_OUTPUT (Prop_DSP_OUTPUT_DSP48E2_ALU_OUT[31]_P[31])
                                                      0.109     0.694 r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_imag[1]/DSP_OUTPUT_INST/P[31]
                         net (fo=1, routed)           0.500     1.194    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_dds[1].dout_mux_r[1][31]_i_1_psdsp_n
    SLICE_X89Y64         FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_dds[1].dout_mux_r[1][31]_i_1_psdsp/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.341     2.727    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.357 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.572    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.596 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       2.063     5.659    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/aclk
    SLICE_X89Y64         FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_dds[1].dout_mux_r[1][31]_i_1_psdsp/C

Slack:                    inf
  Source:                 d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_real[0]/DSP_C_DATA_INST/C_DATA[23]
                            (internal pin)
  Destination:            d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_dds[0].dout_mux_r[0][7]_i_1_psdsp/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.179ns  (logic 0.694ns (58.863%)  route 0.485ns (41.137%))
  Logic Levels:           2  (DSP_ALU=1 DSP_OUTPUT=1)
  Clock Uncertainty:      0.122ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Destination): 2.110ns (routing 0.782ns, distribution 1.328ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    DSP48E2_X20Y38       DSP_C_DATA                   0.000     0.000 r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_real[0]/DSP_C_DATA_INST/C_DATA[23]
                         net (fo=2, routed)           0.000     0.000    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_real[0]/DSP_C_DATA.C_DATA<23>
    DSP48E2_X20Y38       DSP_ALU (Prop_DSP_ALU_DSP48E2_C_DATA[23]_ALU_OUT[23])
                                                      0.585     0.585 f  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_real[0]/DSP_ALU_INST/ALU_OUT[23]
                         net (fo=1, routed)           0.000     0.585    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_real[0]/DSP_ALU.ALU_OUT<23>
    DSP48E2_X20Y38       DSP_OUTPUT (Prop_DSP_OUTPUT_DSP48E2_ALU_OUT[23]_P[23])
                                                      0.109     0.694 r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_real[0]/DSP_OUTPUT_INST/P[23]
                         net (fo=1, routed)           0.485     1.179    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_dds[0].dout_mux_r[0][7]_i_1_psdsp_n
    SLICE_X100Y104       FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_dds[0].dout_mux_r[0][7]_i_1_psdsp/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.341     2.727    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.357 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.572    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.596 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       2.110     5.706    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/aclk
    SLICE_X100Y104       FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_dds[0].dout_mux_r[0][7]_i_1_psdsp/C

Slack:                    inf
  Source:                 d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_real[0]/DSP_C_DATA_INST/C_DATA[22]
                            (internal pin)
  Destination:            d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_dds[0].dout_mux_r[0][6]_i_1_psdsp/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.106ns  (logic 0.694ns (62.749%)  route 0.412ns (37.251%))
  Logic Levels:           2  (DSP_ALU=1 DSP_OUTPUT=1)
  Clock Uncertainty:      0.122ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Destination): 2.110ns (routing 0.782ns, distribution 1.328ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    DSP48E2_X20Y38       DSP_C_DATA                   0.000     0.000 r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_real[0]/DSP_C_DATA_INST/C_DATA[22]
                         net (fo=2, routed)           0.000     0.000    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_real[0]/DSP_C_DATA.C_DATA<22>
    DSP48E2_X20Y38       DSP_ALU (Prop_DSP_ALU_DSP48E2_C_DATA[22]_ALU_OUT[22])
                                                      0.585     0.585 f  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_real[0]/DSP_ALU_INST/ALU_OUT[22]
                         net (fo=1, routed)           0.000     0.585    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_real[0]/DSP_ALU.ALU_OUT<22>
    DSP48E2_X20Y38       DSP_OUTPUT (Prop_DSP_OUTPUT_DSP48E2_ALU_OUT[22]_P[22])
                                                      0.109     0.694 r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_real[0]/DSP_OUTPUT_INST/P[22]
                         net (fo=1, routed)           0.412     1.106    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_dds[0].dout_mux_r[0][6]_i_1_psdsp_n
    SLICE_X100Y103       FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_dds[0].dout_mux_r[0][6]_i_1_psdsp/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.341     2.727    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.357 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.572    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.596 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       2.110     5.706    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/aclk
    SLICE_X100Y103       FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_dds[0].dout_mux_r[0][6]_i_1_psdsp/C

Slack:                    inf
  Source:                 d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_real[0]/DSP_C_DATA_INST/C_DATA[25]
                            (internal pin)
  Destination:            d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_dds[0].dout_mux_r[0][9]_i_1_psdsp/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.100ns  (logic 0.694ns (63.091%)  route 0.406ns (36.909%))
  Logic Levels:           2  (DSP_ALU=1 DSP_OUTPUT=1)
  Clock Uncertainty:      0.122ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Destination): 2.110ns (routing 0.782ns, distribution 1.328ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    DSP48E2_X20Y38       DSP_C_DATA                   0.000     0.000 r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_real[0]/DSP_C_DATA_INST/C_DATA[25]
                         net (fo=2, routed)           0.000     0.000    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_real[0]/DSP_C_DATA.C_DATA<25>
    DSP48E2_X20Y38       DSP_ALU (Prop_DSP_ALU_DSP48E2_C_DATA[25]_ALU_OUT[25])
                                                      0.585     0.585 f  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_real[0]/DSP_ALU_INST/ALU_OUT[25]
                         net (fo=1, routed)           0.000     0.585    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_real[0]/DSP_ALU.ALU_OUT<25>
    DSP48E2_X20Y38       DSP_OUTPUT (Prop_DSP_OUTPUT_DSP48E2_ALU_OUT[25]_P[25])
                                                      0.109     0.694 r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_real[0]/DSP_OUTPUT_INST/P[25]
                         net (fo=1, routed)           0.406     1.100    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_dds[0].dout_mux_r[0][9]_i_1_psdsp_n
    SLICE_X100Y104       FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_dds[0].dout_mux_r[0][9]_i_1_psdsp/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.341     2.727    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.357 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.572    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.596 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       2.110     5.706    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/aclk
    SLICE_X100Y104       FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_dds[0].dout_mux_r[0][9]_i_1_psdsp/C

Slack:                    inf
  Source:                 d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_imag[3]/DSP_C_DATA_INST/C_DATA[19]
                            (internal pin)
  Destination:            d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_dds[3].dout_mux_r[3][19]_i_1_psdsp/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.099ns  (logic 0.694ns (63.148%)  route 0.405ns (36.852%))
  Logic Levels:           2  (DSP_ALU=1 DSP_OUTPUT=1)
  Clock Uncertainty:      0.122ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Destination): 2.123ns (routing 0.782ns, distribution 1.341ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    DSP48E2_X20Y40       DSP_C_DATA                   0.000     0.000 r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_imag[3]/DSP_C_DATA_INST/C_DATA[19]
                         net (fo=2, routed)           0.000     0.000    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_imag[3]/DSP_C_DATA.C_DATA<19>
    DSP48E2_X20Y40       DSP_ALU (Prop_DSP_ALU_DSP48E2_C_DATA[19]_ALU_OUT[19])
                                                      0.585     0.585 f  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_imag[3]/DSP_ALU_INST/ALU_OUT[19]
                         net (fo=1, routed)           0.000     0.585    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_imag[3]/DSP_ALU.ALU_OUT<19>
    DSP48E2_X20Y40       DSP_OUTPUT (Prop_DSP_OUTPUT_DSP48E2_ALU_OUT[19]_P[19])
                                                      0.109     0.694 r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_imag[3]/DSP_OUTPUT_INST/P[19]
                         net (fo=1, routed)           0.405     1.099    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_dds[3].dout_mux_r[3][19]_i_1_psdsp_n
    SLICE_X103Y102       FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_dds[3].dout_mux_r[3][19]_i_1_psdsp/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.341     2.727    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.357 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.572    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.596 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       2.123     5.719    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/aclk
    SLICE_X103Y102       FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_dds[3].dout_mux_r[3][19]_i_1_psdsp/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_imag[1]/DSP_C_DATA_INST/C_DATA[23]
                            (internal pin)
  Destination:            d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_dds[1].dout_mux_r[1][23]_i_1_psdsp/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.202ns  (logic 0.132ns (65.347%)  route 0.070ns (34.653%))
  Logic Levels:           2  (DSP_ALU=1 DSP_OUTPUT=1)
  Clock Uncertainty:      0.122ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Destination): 1.429ns (routing 0.521ns, distribution 0.908ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    DSP48E2_X17Y25       DSP_C_DATA                   0.000     0.000 r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_imag[1]/DSP_C_DATA_INST/C_DATA[23]
                         net (fo=2, routed)           0.000     0.000    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_imag[1]/DSP_C_DATA.C_DATA<23>
    DSP48E2_X17Y25       DSP_ALU (Prop_DSP_ALU_DSP48E2_C_DATA[23]_ALU_OUT[23])
                                                      0.102     0.102 f  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_imag[1]/DSP_ALU_INST/ALU_OUT[23]
                         net (fo=1, routed)           0.000     0.102    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_imag[1]/DSP_ALU.ALU_OUT<23>
    DSP48E2_X17Y25       DSP_OUTPUT (Prop_DSP_OUTPUT_DSP48E2_ALU_OUT[23]_P[23])
                                                      0.030     0.132 r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_imag[1]/DSP_OUTPUT_INST/P[23]
                         net (fo=1, routed)           0.070     0.202    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_dds[1].dout_mux_r[1][23]_i_1_psdsp_n
    SLICE_X89Y62         FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_dds[1].dout_mux_r[1][23]_i_1_psdsp/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.583     1.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.640 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.806    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.825 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.429     3.254    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/aclk
    SLICE_X89Y62         FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_dds[1].dout_mux_r[1][23]_i_1_psdsp/C

Slack:                    inf
  Source:                 d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_real[1]/DSP_C_DATA_INST/C_DATA[19]
                            (internal pin)
  Destination:            d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_dds[1].dout_mux_r[1][3]_i_1_psdsp/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.204ns  (logic 0.132ns (64.706%)  route 0.072ns (35.294%))
  Logic Levels:           2  (DSP_ALU=1 DSP_OUTPUT=1)
  Clock Uncertainty:      0.122ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Destination): 1.425ns (routing 0.521ns, distribution 0.904ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    DSP48E2_X17Y24       DSP_C_DATA                   0.000     0.000 r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_real[1]/DSP_C_DATA_INST/C_DATA[19]
                         net (fo=2, routed)           0.000     0.000    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_real[1]/DSP_C_DATA.C_DATA<19>
    DSP48E2_X17Y24       DSP_ALU (Prop_DSP_ALU_DSP48E2_C_DATA[19]_ALU_OUT[19])
                                                      0.102     0.102 f  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_real[1]/DSP_ALU_INST/ALU_OUT[19]
                         net (fo=1, routed)           0.000     0.102    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_real[1]/DSP_ALU.ALU_OUT<19>
    DSP48E2_X17Y24       DSP_OUTPUT (Prop_DSP_OUTPUT_DSP48E2_ALU_OUT[19]_P[19])
                                                      0.030     0.132 r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_real[1]/DSP_OUTPUT_INST/P[19]
                         net (fo=1, routed)           0.072     0.204    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_dds[1].dout_mux_r[1][3]_i_1_psdsp_n
    SLICE_X88Y62         FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_dds[1].dout_mux_r[1][3]_i_1_psdsp/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.583     1.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.640 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.806    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.825 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.425     3.250    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/aclk
    SLICE_X88Y62         FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_dds[1].dout_mux_r[1][3]_i_1_psdsp/C

Slack:                    inf
  Source:                 d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_real[1]/DSP_C_DATA_INST/C_DATA[17]
                            (internal pin)
  Destination:            d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_dds[1].dout_mux_r[1][1]_i_1_psdsp/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.205ns  (logic 0.132ns (64.390%)  route 0.073ns (35.610%))
  Logic Levels:           2  (DSP_ALU=1 DSP_OUTPUT=1)
  Clock Uncertainty:      0.122ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Destination): 1.431ns (routing 0.521ns, distribution 0.910ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    DSP48E2_X17Y24       DSP_C_DATA                   0.000     0.000 r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_real[1]/DSP_C_DATA_INST/C_DATA[17]
                         net (fo=2, routed)           0.000     0.000    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_real[1]/DSP_C_DATA.C_DATA<17>
    DSP48E2_X17Y24       DSP_ALU (Prop_DSP_ALU_DSP48E2_C_DATA[17]_ALU_OUT[17])
                                                      0.102     0.102 f  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_real[1]/DSP_ALU_INST/ALU_OUT[17]
                         net (fo=1, routed)           0.000     0.102    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_real[1]/DSP_ALU.ALU_OUT<17>
    DSP48E2_X17Y24       DSP_OUTPUT (Prop_DSP_OUTPUT_DSP48E2_ALU_OUT[17]_P[17])
                                                      0.030     0.132 r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_real[1]/DSP_OUTPUT_INST/P[17]
                         net (fo=1, routed)           0.073     0.205    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_dds[1].dout_mux_r[1][1]_i_1_psdsp_n
    SLICE_X89Y62         FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_dds[1].dout_mux_r[1][1]_i_1_psdsp/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.583     1.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.640 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.806    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.825 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.431     3.256    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/aclk
    SLICE_X89Y62         FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_dds[1].dout_mux_r[1][1]_i_1_psdsp/C

Slack:                    inf
  Source:                 d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_real[1]/DSP_C_DATA_INST/C_DATA[20]
                            (internal pin)
  Destination:            d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_dds[1].dout_mux_r[1][4]_i_1_psdsp/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.205ns  (logic 0.132ns (64.390%)  route 0.073ns (35.610%))
  Logic Levels:           2  (DSP_ALU=1 DSP_OUTPUT=1)
  Clock Uncertainty:      0.122ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Destination): 1.431ns (routing 0.521ns, distribution 0.910ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    DSP48E2_X17Y24       DSP_C_DATA                   0.000     0.000 r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_real[1]/DSP_C_DATA_INST/C_DATA[20]
                         net (fo=2, routed)           0.000     0.000    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_real[1]/DSP_C_DATA.C_DATA<20>
    DSP48E2_X17Y24       DSP_ALU (Prop_DSP_ALU_DSP48E2_C_DATA[20]_ALU_OUT[20])
                                                      0.102     0.102 f  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_real[1]/DSP_ALU_INST/ALU_OUT[20]
                         net (fo=1, routed)           0.000     0.102    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_real[1]/DSP_ALU.ALU_OUT<20>
    DSP48E2_X17Y24       DSP_OUTPUT (Prop_DSP_OUTPUT_DSP48E2_ALU_OUT[20]_P[20])
                                                      0.030     0.132 r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_real[1]/DSP_OUTPUT_INST/P[20]
                         net (fo=1, routed)           0.073     0.205    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_dds[1].dout_mux_r[1][4]_i_1_psdsp_n
    SLICE_X89Y62         FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_dds[1].dout_mux_r[1][4]_i_1_psdsp/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.583     1.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.640 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.806    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.825 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.431     3.256    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/aclk
    SLICE_X89Y62         FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_dds[1].dout_mux_r[1][4]_i_1_psdsp/C

Slack:                    inf
  Source:                 d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_imag[1]/DSP_C_DATA_INST/C_DATA[22]
                            (internal pin)
  Destination:            d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_dds[1].dout_mux_r[1][22]_i_1_psdsp/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.206ns  (logic 0.132ns (64.078%)  route 0.074ns (35.922%))
  Logic Levels:           2  (DSP_ALU=1 DSP_OUTPUT=1)
  Clock Uncertainty:      0.122ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Destination): 1.429ns (routing 0.521ns, distribution 0.908ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    DSP48E2_X17Y25       DSP_C_DATA                   0.000     0.000 r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_imag[1]/DSP_C_DATA_INST/C_DATA[22]
                         net (fo=2, routed)           0.000     0.000    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_imag[1]/DSP_C_DATA.C_DATA<22>
    DSP48E2_X17Y25       DSP_ALU (Prop_DSP_ALU_DSP48E2_C_DATA[22]_ALU_OUT[22])
                                                      0.102     0.102 f  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_imag[1]/DSP_ALU_INST/ALU_OUT[22]
                         net (fo=1, routed)           0.000     0.102    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_imag[1]/DSP_ALU.ALU_OUT<22>
    DSP48E2_X17Y25       DSP_OUTPUT (Prop_DSP_OUTPUT_DSP48E2_ALU_OUT[22]_P[22])
                                                      0.030     0.132 r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_imag[1]/DSP_OUTPUT_INST/P[22]
                         net (fo=1, routed)           0.074     0.206    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_dds[1].dout_mux_r[1][22]_i_1_psdsp_n
    SLICE_X89Y62         FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_dds[1].dout_mux_r[1][22]_i_1_psdsp/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.583     1.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.640 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.806    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.825 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.429     3.254    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/aclk
    SLICE_X89Y62         FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_dds[1].dout_mux_r[1][22]_i_1_psdsp/C

Slack:                    inf
  Source:                 d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_imag[3]/DSP_C_DATA_INST/C_DATA[28]
                            (internal pin)
  Destination:            d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_dds[3].dout_mux_r[3][28]_i_1_psdsp/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.206ns  (logic 0.132ns (64.078%)  route 0.074ns (35.922%))
  Logic Levels:           2  (DSP_ALU=1 DSP_OUTPUT=1)
  Clock Uncertainty:      0.122ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Destination): 1.467ns (routing 0.521ns, distribution 0.946ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    DSP48E2_X20Y40       DSP_C_DATA                   0.000     0.000 r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_imag[3]/DSP_C_DATA_INST/C_DATA[28]
                         net (fo=2, routed)           0.000     0.000    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_imag[3]/DSP_C_DATA.C_DATA<28>
    DSP48E2_X20Y40       DSP_ALU (Prop_DSP_ALU_DSP48E2_C_DATA[28]_ALU_OUT[28])
                                                      0.102     0.102 f  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_imag[3]/DSP_ALU_INST/ALU_OUT[28]
                         net (fo=1, routed)           0.000     0.102    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_imag[3]/DSP_ALU.ALU_OUT<28>
    DSP48E2_X20Y40       DSP_OUTPUT (Prop_DSP_OUTPUT_DSP48E2_ALU_OUT[28]_P[28])
                                                      0.030     0.132 r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_imag[3]/DSP_OUTPUT_INST/P[28]
                         net (fo=1, routed)           0.074     0.206    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_dds[3].dout_mux_r[3][28]_i_1_psdsp_n
    SLICE_X102Y103       FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_dds[3].dout_mux_r[3][28]_i_1_psdsp/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.583     1.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.640 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.806    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.825 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.467     3.292    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/aclk
    SLICE_X102Y103       FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_dds[3].dout_mux_r[3][28]_i_1_psdsp/C

Slack:                    inf
  Source:                 d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_real[1]/DSP_C_DATA_INST/C_DATA[16]
                            (internal pin)
  Destination:            d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_dds[1].dout_mux_r[1][0]_i_1_psdsp/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.207ns  (logic 0.132ns (63.768%)  route 0.075ns (36.232%))
  Logic Levels:           2  (DSP_ALU=1 DSP_OUTPUT=1)
  Clock Uncertainty:      0.122ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Destination): 1.425ns (routing 0.521ns, distribution 0.904ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    DSP48E2_X17Y24       DSP_C_DATA                   0.000     0.000 r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_real[1]/DSP_C_DATA_INST/C_DATA[16]
                         net (fo=2, routed)           0.000     0.000    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_real[1]/DSP_C_DATA.C_DATA<16>
    DSP48E2_X17Y24       DSP_ALU (Prop_DSP_ALU_DSP48E2_C_DATA[16]_ALU_OUT[16])
                                                      0.102     0.102 f  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_real[1]/DSP_ALU_INST/ALU_OUT[16]
                         net (fo=1, routed)           0.000     0.102    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_real[1]/DSP_ALU.ALU_OUT<16>
    DSP48E2_X17Y24       DSP_OUTPUT (Prop_DSP_OUTPUT_DSP48E2_ALU_OUT[16]_P[16])
                                                      0.030     0.132 r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_real[1]/DSP_OUTPUT_INST/P[16]
                         net (fo=1, routed)           0.075     0.207    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_dds[1].dout_mux_r[1][0]_i_1_psdsp_n
    SLICE_X88Y62         FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_dds[1].dout_mux_r[1][0]_i_1_psdsp/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.583     1.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.640 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.806    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.825 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.425     3.250    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/aclk
    SLICE_X88Y62         FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_dds[1].dout_mux_r[1][0]_i_1_psdsp/C

Slack:                    inf
  Source:                 d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_imag[0]/DSP_C_DATA_INST/C_DATA[17]
                            (internal pin)
  Destination:            d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_dds[0].dout_mux_r[0][17]_i_1_psdsp/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.207ns  (logic 0.132ns (63.768%)  route 0.075ns (36.232%))
  Logic Levels:           2  (DSP_ALU=1 DSP_OUTPUT=1)
  Clock Uncertainty:      0.122ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Destination): 1.424ns (routing 0.521ns, distribution 0.903ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    DSP48E2_X18Y34       DSP_C_DATA                   0.000     0.000 r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_imag[0]/DSP_C_DATA_INST/C_DATA[17]
                         net (fo=2, routed)           0.000     0.000    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_imag[0]/DSP_C_DATA.C_DATA<17>
    DSP48E2_X18Y34       DSP_ALU (Prop_DSP_ALU_DSP48E2_C_DATA[17]_ALU_OUT[17])
                                                      0.102     0.102 f  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_imag[0]/DSP_ALU_INST/ALU_OUT[17]
                         net (fo=1, routed)           0.000     0.102    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_imag[0]/DSP_ALU.ALU_OUT<17>
    DSP48E2_X18Y34       DSP_OUTPUT (Prop_DSP_OUTPUT_DSP48E2_ALU_OUT[17]_P[17])
                                                      0.030     0.132 r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_imag[0]/DSP_OUTPUT_INST/P[17]
                         net (fo=1, routed)           0.075     0.207    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_dds[0].dout_mux_r[0][17]_i_1_psdsp_n
    SLICE_X95Y87         FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_dds[0].dout_mux_r[0][17]_i_1_psdsp/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.583     1.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.640 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.806    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.825 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.424     3.249    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/aclk
    SLICE_X95Y87         FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_dds[0].dout_mux_r[0][17]_i_1_psdsp/C

Slack:                    inf
  Source:                 d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_imag[3]/DSP_C_DATA_INST/C_DATA[18]
                            (internal pin)
  Destination:            d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_dds[3].dout_mux_r[3][18]_i_1_psdsp/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.207ns  (logic 0.132ns (63.768%)  route 0.075ns (36.232%))
  Logic Levels:           2  (DSP_ALU=1 DSP_OUTPUT=1)
  Clock Uncertainty:      0.122ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Destination): 1.470ns (routing 0.521ns, distribution 0.949ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    DSP48E2_X20Y40       DSP_C_DATA                   0.000     0.000 r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_imag[3]/DSP_C_DATA_INST/C_DATA[18]
                         net (fo=2, routed)           0.000     0.000    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_imag[3]/DSP_C_DATA.C_DATA<18>
    DSP48E2_X20Y40       DSP_ALU (Prop_DSP_ALU_DSP48E2_C_DATA[18]_ALU_OUT[18])
                                                      0.102     0.102 f  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_imag[3]/DSP_ALU_INST/ALU_OUT[18]
                         net (fo=1, routed)           0.000     0.102    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_imag[3]/DSP_ALU.ALU_OUT<18>
    DSP48E2_X20Y40       DSP_OUTPUT (Prop_DSP_OUTPUT_DSP48E2_ALU_OUT[18]_P[18])
                                                      0.030     0.132 r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_imag[3]/DSP_OUTPUT_INST/P[18]
                         net (fo=1, routed)           0.075     0.207    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_dds[3].dout_mux_r[3][18]_i_1_psdsp_n
    SLICE_X103Y102       FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_dds[3].dout_mux_r[3][18]_i_1_psdsp/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.583     1.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.640 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.806    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.825 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.470     3.295    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/aclk
    SLICE_X103Y102       FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_dds[3].dout_mux_r[3][18]_i_1_psdsp/C

Slack:                    inf
  Source:                 d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_real[1]/DSP_C_DATA_INST/C_DATA[26]
                            (internal pin)
  Destination:            d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_dds[1].dout_mux_r[1][10]_i_1_psdsp/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.207ns  (logic 0.132ns (63.768%)  route 0.075ns (36.232%))
  Logic Levels:           2  (DSP_ALU=1 DSP_OUTPUT=1)
  Clock Uncertainty:      0.122ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Destination): 1.435ns (routing 0.521ns, distribution 0.914ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    DSP48E2_X17Y24       DSP_C_DATA                   0.000     0.000 r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_real[1]/DSP_C_DATA_INST/C_DATA[26]
                         net (fo=2, routed)           0.000     0.000    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_real[1]/DSP_C_DATA.C_DATA<26>
    DSP48E2_X17Y24       DSP_ALU (Prop_DSP_ALU_DSP48E2_C_DATA[26]_ALU_OUT[26])
                                                      0.102     0.102 f  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_real[1]/DSP_ALU_INST/ALU_OUT[26]
                         net (fo=1, routed)           0.000     0.102    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_real[1]/DSP_ALU.ALU_OUT<26>
    DSP48E2_X17Y24       DSP_OUTPUT (Prop_DSP_OUTPUT_DSP48E2_ALU_OUT[26]_P[26])
                                                      0.030     0.132 r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/py_round_real[1]/DSP_OUTPUT_INST/P[26]
                         net (fo=1, routed)           0.075     0.207    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_dds[1].dout_mux_r[1][10]_i_1_psdsp_n
    SLICE_X89Y63         FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_dds[1].dout_mux_r[1][10]_i_1_psdsp/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y3         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.583     1.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.640 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.806    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.825 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X2Y2 (CLOCK_ROOT)    net (fo=85832, routed)       1.435     3.260    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/aclk
    SLICE_X89Y63         FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/GEN_dds[1].dout_mux_r[1][10]_i_1_psdsp/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  
  To Clock:  clk_out1_d_1_clk_core_0

Max Delay             2 Endpoints
Min Delay             2 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 PMOD1_0_LS
                            (input port)
  Destination:            d_1_i/qick_processor_0/inst/proc_start_cdc_reg/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.741ns  (logic 0.643ns (17.181%)  route 3.098ns (82.819%))
  Logic Levels:           2  (IBUFCTRL=1 INBUF=1)
  Clock Path Skew:        5.758ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.758ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.123ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.085ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Destination): 1.819ns (routing 0.838ns, distribution 0.981ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    L14                                               0.000     0.000 r  PMOD1_0_LS (IN)
                         net (fo=0)                   0.000     0.000    PMOD1_0_LS_IBUF_inst/I
    L14                  INBUF (Prop_INBUF_HPIOB_S_PAD_O)
                                                      0.643     0.643 r  PMOD1_0_LS_IBUF_inst/INBUF_INST/O
                         net (fo=1, routed)           0.000     0.643    PMOD1_0_LS_IBUF_inst/OUT
    L14                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_S_I_O)
                                                      0.000     0.643 r  PMOD1_0_LS_IBUF_inst/IBUFCTRL_INST/O
                         net (fo=1, routed)           3.098     3.741    d_1_i/qick_processor_0/inst/proc_start_i
    SLICE_X12Y352        FDRE                                         r  d_1_i/qick_processor_0/inst/proc_start_cdc_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.549     3.070    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.700 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.915    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.939 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.819     5.758    d_1_i/qick_processor_0/inst/c_clk_i
    SLICE_X12Y352        FDRE                                         r  d_1_i/qick_processor_0/inst/proc_start_cdc_reg/C

Slack:                    inf
  Source:                 d_1_i/clk_core/inst/mmcme4_adv_inst/LOCKED
                            (internal pin)
  Destination:            d_1_i/rst_core/U0/EXT_LPF/lpf_int_reg/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.443ns  (logic 0.124ns (8.593%)  route 1.319ns (91.407%))
  Logic Levels:           1  (LUT4=1)
  Clock Uncertainty:      0.123ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.085ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Destination): 1.839ns (routing 0.838ns, distribution 1.001ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    MMCM_X0Y5            MMCME4_ADV                   0.000     0.000 f  d_1_i/clk_core/inst/mmcme4_adv_inst/LOCKED
                         net (fo=1, routed)           1.268     1.268    d_1_i/rst_core/U0/EXT_LPF/dcm_locked
    SLICE_X57Y310        LUT4 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.124     1.392 r  d_1_i/rst_core/U0/EXT_LPF/lpf_int0/O
                         net (fo=1, routed)           0.051     1.443    d_1_i/rst_core/U0/EXT_LPF/lpf_int0__0
    SLICE_X57Y310        FDRE                                         r  d_1_i/rst_core/U0/EXT_LPF/lpf_int_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       2.549     3.070    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.700 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.915    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.939 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.839     5.778    d_1_i/rst_core/U0/EXT_LPF/slowest_sync_clk
    SLICE_X57Y310        FDRE                                         r  d_1_i/rst_core/U0/EXT_LPF/lpf_int_reg/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/clk_core/inst/mmcme4_adv_inst/LOCKED
                            (internal pin)
  Destination:            d_1_i/rst_core/U0/EXT_LPF/lpf_int_reg/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.710ns  (logic 0.050ns (7.042%)  route 0.660ns (92.958%))
  Logic Levels:           1  (LUT4=1)
  Clock Uncertainty:      0.123ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.085ns
    Phase Error              (PE):    0.073ns
  Clock Net Delay (Destination): 1.268ns (routing 0.553ns, distribution 0.715ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    MMCM_X0Y5            MMCME4_ADV                   0.000     0.000 f  d_1_i/clk_core/inst/mmcme4_adv_inst/LOCKED
                         net (fo=1, routed)           0.643     0.643    d_1_i/rst_core/U0/EXT_LPF/dcm_locked
    SLICE_X57Y310        LUT4 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.050     0.693 r  d_1_i/rst_core/U0/EXT_LPF/lpf_int0/O
                         net (fo=1, routed)           0.017     0.710    d_1_i/rst_core/U0/EXT_LPF/lpf_int0__0
    SLICE_X57Y310        FDRE                                         r  d_1_i/rst_core/U0/EXT_LPF/lpf_int_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       1.708     2.156    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.861 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     2.027    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     2.046 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.268     3.314    d_1_i/rst_core/U0/EXT_LPF/slowest_sync_clk
    SLICE_X57Y310        FDRE                                         r  d_1_i/rst_core/U0/EXT_LPF/lpf_int_reg/C

Slack:                    inf
  Source:                 PMOD1_0_LS
                            (input port)
  Destination:            d_1_i/qick_processor_0/inst/proc_start_cdc_reg/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.604ns period=5.208ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.611ns  (logic 0.194ns (12.064%)  route 1.417ns (87.936%))
  Logic Levels:           2  (IBUFCTRL=1 INBUF=1)
  Clock Path Skew:        3.302ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.302ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Net Delay (Destination): 1.256ns (routing 0.553ns, distribution 0.703ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    L14                                               0.000     0.000 r  PMOD1_0_LS (IN)
                         net (fo=0)                   0.000     0.000    PMOD1_0_LS_IBUF_inst/I
    L14                  INBUF (Prop_INBUF_HPIOB_S_PAD_O)
                                                      0.194     0.194 r  PMOD1_0_LS_IBUF_inst/INBUF_INST/O
                         net (fo=1, routed)           0.000     0.194    PMOD1_0_LS_IBUF_inst/OUT
    L14                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_S_I_O)
                                                      0.000     0.194 r  PMOD1_0_LS_IBUF_inst/IBUFCTRL_INST/O
                         net (fo=1, routed)           1.417     1.611    d_1_i/qick_processor_0/inst/proc_start_i
    SLICE_X12Y352        FDRE                                         r  d_1_i/qick_processor_0/inst/proc_start_cdc_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y108       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
                         net (fo=91136, routed)       1.708     2.156    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.861 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     2.027    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y139        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     2.046 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y5 (CLOCK_ROOT)    net (fo=4503, routed)        1.256     3.302    d_1_i/qick_processor_0/inst/c_clk_i
    SLICE_X12Y352        FDRE                                         r  d_1_i/qick_processor_0/inst/proc_start_cdc_reg/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  
  To Clock:  clk_pl_0

Max Delay             7 Endpoints
Min Delay             7 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[3]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.667ns  (logic 0.504ns (13.743%)  route 3.163ns (86.257%))
  Logic Levels:           5  (LUT6=5)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.145ns (routing 0.598ns, distribution 1.547ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[3]
                         net (fo=2, routed)           2.400     2.400    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[3]
    SLICE_X114Y215       LUT6 (Prop_G6LUT_SLICEL_I3_O)
                                                      0.123     2.523 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_70/O
                         net (fo=1, routed)           0.043     2.566    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_70_n_0
    SLICE_X114Y215       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.099     2.665 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_46/O
                         net (fo=1, routed)           0.206     2.871    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_46_n_0
    SLICE_X112Y215       LUT6 (Prop_C6LUT_SLICEM_I4_O)
                                                      0.098     2.969 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_18/O
                         net (fo=1, routed)           0.096     3.065    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_18_n_0
    SLICE_X112Y216       LUT6 (Prop_H6LUT_SLICEM_I3_O)
                                                      0.039     3.104 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_5/O
                         net (fo=1, routed)           0.352     3.456    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_5_n_0
    SLICE_X112Y227       LUT6 (Prop_C6LUT_SLICEM_I4_O)
                                                      0.145     3.601 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_1/O
                         net (fo=1, routed)           0.066     3.667    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_81
    SLICE_X112Y227       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.145     2.327    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X112Y227       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[3]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[1]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.555ns  (logic 0.445ns (12.516%)  route 3.110ns (87.484%))
  Logic Levels:           4  (LUT6=4)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.157ns (routing 0.598ns, distribution 1.559ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[1]
                         net (fo=2, routed)           2.268     2.268    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[1]
    SLICE_X114Y214       LUT6 (Prop_F6LUT_SLICEL_I1_O)
                                                      0.097     2.365 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_26/O
                         net (fo=1, routed)           0.203     2.568    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_26_n_0
    SLICE_X114Y212       LUT6 (Prop_B6LUT_SLICEL_I5_O)
                                                      0.051     2.619 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_8/O
                         net (fo=1, routed)           0.195     2.814    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_8_n_0
    SLICE_X113Y216       LUT6 (Prop_D6LUT_SLICEM_I1_O)
                                                      0.145     2.959 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_3/O
                         net (fo=1, routed)           0.386     3.345    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_3_n_0
    SLICE_X113Y228       LUT6 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.152     3.497 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_1/O
                         net (fo=1, routed)           0.058     3.555    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_83
    SLICE_X113Y228       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.157     2.339    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y228       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[0]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.296ns  (logic 0.627ns (19.022%)  route 2.669ns (80.978%))
  Logic Levels:           5  (LUT5=1 LUT6=4)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.161ns (routing 0.598ns, distribution 1.563ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[0]
                         net (fo=2, routed)           1.388     1.388    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_22_1[0]
    SLICE_X107Y214       LUT5 (Prop_D6LUT_SLICEM_I3_O)
                                                      0.145     1.533 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_68/O
                         net (fo=1, routed)           0.098     1.631    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_68_n_0
    SLICE_X107Y216       LUT6 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.090     1.721 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_40/O
                         net (fo=1, routed)           0.515     2.236    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_40_n_0
    SLICE_X109Y215       LUT6 (Prop_D6LUT_SLICEM_I2_O)
                                                      0.145     2.381 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_14/O
                         net (fo=1, routed)           0.437     2.818    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_14_n_0
    SLICE_X113Y222       LUT6 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.125     2.943 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_4/O
                         net (fo=1, routed)           0.159     3.102    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_4_n_0
    SLICE_X113Y227       LUT6 (Prop_D6LUT_SLICEM_I2_O)
                                                      0.122     3.224 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_1/O
                         net (fo=1, routed)           0.072     3.296    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_84
    SLICE_X113Y227       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.161     2.343    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y227       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[2]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.079ns  (logic 0.411ns (13.350%)  route 2.668ns (86.650%))
  Logic Levels:           4  (LUT6=4)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.156ns (routing 0.598ns, distribution 1.558ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[2]
                         net (fo=2, routed)           2.017     2.017    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[2]
    SLICE_X113Y214       LUT6 (Prop_B6LUT_SLICEM_I3_O)
                                                      0.100     2.117 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_47/O
                         net (fo=1, routed)           0.088     2.205    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_47_n_0
    SLICE_X113Y215       LUT6 (Prop_G6LUT_SLICEM_I3_O)
                                                      0.100     2.305 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_17/O
                         net (fo=1, routed)           0.102     2.407    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_17_n_0
    SLICE_X113Y213       LUT6 (Prop_G6LUT_SLICEM_I4_O)
                                                      0.123     2.530 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_4/O
                         net (fo=1, routed)           0.395     2.925    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_4_n_0
    SLICE_X113Y225       LUT6 (Prop_C6LUT_SLICEM_I3_O)
                                                      0.088     3.013 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_1/O
                         net (fo=1, routed)           0.066     3.079    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_82
    SLICE_X113Y225       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.156     2.338    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y225       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[4]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.055ns  (logic 0.559ns (18.298%)  route 2.496ns (81.702%))
  Logic Levels:           5  (LUT4=1 LUT5=1 LUT6=3)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.151ns (routing 0.598ns, distribution 1.553ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[4]
                         net (fo=1, routed)           1.165     1.165    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_22_1[4]
    SLICE_X107Y217       LUT5 (Prop_F6LUT_SLICEM_I3_O)
                                                      0.148     1.313 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_53/O
                         net (fo=1, routed)           0.099     1.412    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_53_n_0
    SLICE_X107Y217       LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.122     1.534 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_38/O
                         net (fo=1, routed)           0.558     2.092    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_38_n_0
    SLICE_X110Y217       LUT6 (Prop_H6LUT_SLICEM_I5_O)
                                                      0.152     2.244 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_22/O
                         net (fo=1, routed)           0.309     2.553    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_22_n_0
    SLICE_X113Y222       LUT4 (Prop_A6LUT_SLICEM_I0_O)
                                                      0.100     2.653 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_5/O
                         net (fo=1, routed)           0.293     2.946    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_5_n_0
    SLICE_X113Y239       LUT6 (Prop_D6LUT_SLICEM_I3_O)
                                                      0.037     2.983 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_1/O
                         net (fo=1, routed)           0.072     3.055    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_80
    SLICE_X113Y239       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.151     2.333    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y239       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[4]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[7]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.961ns  (logic 0.631ns (21.310%)  route 2.330ns (78.690%))
  Logic Levels:           5  (LUT5=1 LUT6=4)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.153ns (routing 0.598ns, distribution 1.555ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[7]
                         net (fo=1, routed)           1.166     1.166    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_22_1[7]
    SLICE_X107Y217       LUT5 (Prop_B6LUT_SLICEM_I3_O)
                                                      0.149     1.315 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_36/O
                         net (fo=1, routed)           0.222     1.537    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_36_n_0
    SLICE_X107Y217       LUT6 (Prop_C6LUT_SLICEM_I5_O)
                                                      0.088     1.625 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_30/O
                         net (fo=1, routed)           0.458     2.083    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_30_n_0
    SLICE_X110Y218       LUT6 (Prop_F6LUT_SLICEM_I4_O)
                                                      0.148     2.231 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_17/O
                         net (fo=1, routed)           0.282     2.513    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_17_n_0
    SLICE_X114Y224       LUT6 (Prop_F6LUT_SLICEL_I1_O)
                                                      0.097     2.610 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_6/O
                         net (fo=1, routed)           0.154     2.764    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_6_n_0
    SLICE_X114Y228       LUT6 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.149     2.913 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_1/O
                         net (fo=1, routed)           0.048     2.961    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_77
    SLICE_X114Y228       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.153     2.335    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X114Y228       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[7]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[5]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.423ns  (logic 0.364ns (15.023%)  route 2.059ns (84.977%))
  Logic Levels:           5  (LUT6=5)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.156ns (routing 0.598ns, distribution 1.558ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[5]
                         net (fo=1, routed)           1.058     1.058    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_28_0[5]
    SLICE_X116Y247       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.090     1.148 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_27/O
                         net (fo=1, routed)           0.096     1.244    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_27_n_0
    SLICE_X114Y247       LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.051     1.295 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_20/O
                         net (fo=1, routed)           0.293     1.588    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_20_n_0
    SLICE_X112Y244       LUT6 (Prop_H6LUT_SLICEM_I3_O)
                                                      0.039     1.627 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_10/O
                         net (fo=1, routed)           0.091     1.718    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_10_n_0
    SLICE_X112Y243       LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.039     1.757 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_2/O
                         net (fo=1, routed)           0.455     2.212    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_2_n_0
    SLICE_X115Y224       LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.145     2.357 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_1/O
                         net (fo=1, routed)           0.066     2.423    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_79
    SLICE_X115Y224       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       2.156     2.338    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X115Y224       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[5]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[1]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.568ns  (logic 0.145ns (25.550%)  route 0.423ns (74.450%))
  Logic Levels:           3  (LUT6=3)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.482ns (routing 0.404ns, distribution 1.078ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[1]
                         net (fo=2, routed)           0.302     0.302    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_55_0[1]
    SLICE_X114Y230       LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.050     0.352 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_17/O
                         net (fo=1, routed)           0.056     0.408    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_17_n_0
    SLICE_X114Y228       LUT6 (Prop_B6LUT_SLICEL_I3_O)
                                                      0.060     0.468 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_5/O
                         net (fo=1, routed)           0.044     0.512    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_5_n_0
    SLICE_X113Y228       LUT6 (Prop_H6LUT_SLICEM_I3_O)
                                                      0.035     0.547 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_1/O
                         net (fo=1, routed)           0.021     0.568    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_83
    SLICE_X113Y228       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.482     1.629    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y228       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[0]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.572ns  (logic 0.079ns (13.811%)  route 0.493ns (86.189%))
  Logic Levels:           4  (LUT6=4)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.488ns (routing 0.404ns, distribution 1.084ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[0]
                         net (fo=1, routed)           0.303     0.303    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_55_0[0]
    SLICE_X114Y229       LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.015     0.318 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_49/O
                         net (fo=1, routed)           0.073     0.391    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_49_n_0
    SLICE_X114Y228       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.035     0.426 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_19/O
                         net (fo=1, routed)           0.021     0.447    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_19_n_0
    SLICE_X114Y227       LUT6 (Prop_H6LUT_SLICEL_I2_O)
                                                      0.015     0.462 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_5/O
                         net (fo=1, routed)           0.070     0.532    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_5_n_0
    SLICE_X113Y227       LUT6 (Prop_D6LUT_SLICEM_I3_O)
                                                      0.014     0.546 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_1/O
                         net (fo=1, routed)           0.026     0.572    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_84
    SLICE_X113Y227       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.488     1.635    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y227       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[7]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.645ns  (logic 0.149ns (23.101%)  route 0.496ns (76.899%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.479ns (routing 0.404ns, distribution 1.075ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[7]
                         net (fo=1, routed)           0.256     0.256    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_55_0[7]
    SLICE_X116Y224       LUT5 (Prop_C6LUT_SLICEL_I4_O)
                                                      0.040     0.296 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_32/O
                         net (fo=1, routed)           0.044     0.340    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_32_n_0
    SLICE_X115Y224       LUT5 (Prop_B6LUT_SLICEM_I0_O)
                                                      0.035     0.375 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_18/O
                         net (fo=1, routed)           0.100     0.475    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_18_n_0
    SLICE_X114Y224       LUT6 (Prop_F6LUT_SLICEL_I4_O)
                                                      0.014     0.489 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_6/O
                         net (fo=1, routed)           0.080     0.569    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_6_n_0
    SLICE_X114Y228       LUT6 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.060     0.629 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_1/O
                         net (fo=1, routed)           0.016     0.645    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_77
    SLICE_X114Y228       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.479     1.626    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X114Y228       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[7]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[4]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.713ns  (logic 0.132ns (18.513%)  route 0.581ns (81.487%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.477ns (routing 0.404ns, distribution 1.073ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[4]
                         net (fo=1, routed)           0.294     0.294    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_31_0[4]
    SLICE_X112Y251       LUT5 (Prop_D6LUT_SLICEM_I4_O)
                                                      0.041     0.335 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_28/O
                         net (fo=1, routed)           0.118     0.453    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_28_n_0
    SLICE_X112Y246       LUT6 (Prop_D6LUT_SLICEM_I3_O)
                                                      0.041     0.494 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_6/O
                         net (fo=1, routed)           0.143     0.637    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_6_n_0
    SLICE_X113Y239       LUT6 (Prop_D6LUT_SLICEM_I4_O)
                                                      0.050     0.687 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_1/O
                         net (fo=1, routed)           0.026     0.713    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_80
    SLICE_X113Y239       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.477     1.624    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y239       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[4]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[3]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.746ns  (logic 0.130ns (17.426%)  route 0.616ns (82.574%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.474ns (routing 0.404ns, distribution 1.070ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[3]
                         net (fo=1, routed)           0.347     0.347    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_55_0[3]
    SLICE_X116Y230       LUT5 (Prop_E6LUT_SLICEL_I4_O)
                                                      0.022     0.369 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_36/O
                         net (fo=1, routed)           0.044     0.413    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_36_n_0
    SLICE_X115Y230       LUT5 (Prop_C6LUT_SLICEM_I1_O)
                                                      0.014     0.427 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_13/O
                         net (fo=1, routed)           0.100     0.527    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_13_n_0
    SLICE_X114Y227       LUT6 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.059     0.586 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_3/O
                         net (fo=1, routed)           0.101     0.687    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_3_n_0
    SLICE_X112Y227       LUT6 (Prop_C6LUT_SLICEM_I1_O)
                                                      0.035     0.722 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_1/O
                         net (fo=1, routed)           0.024     0.746    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_81
    SLICE_X112Y227       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.474     1.621    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X112Y227       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[3]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[2]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.802ns  (logic 0.148ns (18.454%)  route 0.654ns (81.546%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.482ns (routing 0.404ns, distribution 1.078ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[2]
                         net (fo=1, routed)           0.289     0.289    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_55_0[2]
    SLICE_X116Y224       LUT5 (Prop_F6LUT_SLICEL_I4_O)
                                                      0.059     0.348 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_32/O
                         net (fo=1, routed)           0.160     0.508    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_32_n_0
    SLICE_X115Y230       LUT5 (Prop_D6LUT_SLICEM_I1_O)
                                                      0.014     0.522 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_12/O
                         net (fo=1, routed)           0.126     0.648    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_12_n_0
    SLICE_X112Y224       LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                      0.035     0.683 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_3/O
                         net (fo=1, routed)           0.055     0.738    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_3_n_0
    SLICE_X113Y225       LUT6 (Prop_C6LUT_SLICEM_I1_O)
                                                      0.040     0.778 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_1/O
                         net (fo=1, routed)           0.024     0.802    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_82
    SLICE_X113Y225       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.482     1.629    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y225       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[5]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.914ns  (logic 0.176ns (19.256%)  route 0.738ns (80.744%))
  Logic Levels:           4  (LUT4=1 LUT6=3)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.483ns (routing 0.404ns, distribution 1.079ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[5]
                         net (fo=1, routed)           0.295     0.295    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_31_0[5]
    SLICE_X111Y251       LUT4 (Prop_A6LUT_SLICEL_I0_O)
                                                      0.035     0.330 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_22/O
                         net (fo=1, routed)           0.102     0.432    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_22_n_0
    SLICE_X111Y247       LUT6 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.041     0.473 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_11/O
                         net (fo=1, routed)           0.085     0.558    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_11_n_0
    SLICE_X112Y243       LUT6 (Prop_H6LUT_SLICEM_I5_O)
                                                      0.041     0.599 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_2/O
                         net (fo=1, routed)           0.232     0.831    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_2_n_0
    SLICE_X115Y224       LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.059     0.890 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_1/O
                         net (fo=1, routed)           0.024     0.914    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_79
    SLICE_X115Y224       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y50        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=55323, routed)       1.483     1.630    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X115Y224       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[5]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  
  To Clock:  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK

Max Delay             4 Endpoints
Min Delay             4 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
                            (internal pin)
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/iTDI_reg_reg/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        6.609ns  (logic 4.300ns (65.065%)  route 2.309ns (34.935%))
  Logic Levels:           1  (BSCANE2=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.603ns (routing 1.525ns, distribution 1.078ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TDI_TDI)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TDI
                         net (fo=4, routed)           2.309     6.609    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/out
    SLICE_X112Y321       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/iTDI_reg_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.353     2.818    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.842 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.603     5.445    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/m_bscan_tck[0]
    SLICE_X112Y321       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/iTDI_reg_reg/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
                            (internal pin)
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscanid_reg[31]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        5.164ns  (logic 4.448ns (86.139%)  route 0.716ns (13.861%))
  Logic Levels:           2  (BSCANE2=1 LUT4=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.610ns (routing 1.525ns, distribution 1.085ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TDI_TDI)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TDI
                         net (fo=4, routed)           0.665     4.965    dbg_hub/inst/BSCANID.u_xsdbm_id/TDI
    SLICE_X105Y115       LUT4 (Prop_F6LUT_SLICEL_I3_O)
                                                      0.148     5.113 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscanid[31]_i_1/O
                         net (fo=1, routed)           0.051     5.164    dbg_hub/inst/BSCANID.u_xsdbm_id/p_2_in[31]
    SLICE_X105Y115       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscanid_reg[31]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.353     2.818    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.842 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.610     5.452    dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i
    SLICE_X105Y115       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscanid_reg[31]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
                            (internal pin)
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[31]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.961ns  (logic 4.390ns (88.495%)  route 0.571ns (11.505%))
  Logic Levels:           2  (BSCANE2=1 LUT5=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.602ns (routing 1.525ns, distribution 1.077ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TDI_TDI)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TDI
                         net (fo=4, routed)           0.513     4.813    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tdi
    SLICE_X107Y118       LUT5 (Prop_H6LUT_SLICEM_I2_O)
                                                      0.090     4.903 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg[31]_i_2/O
                         net (fo=1, routed)           0.058     4.961    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg[31]_i_2_n_0
    SLICE_X107Y118       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[31]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.353     2.818    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.842 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.602     5.444    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X107Y118       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[31]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
                            (internal pin)
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid_reg[31]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.780ns  (logic 4.397ns (91.984%)  route 0.383ns (8.016%))
  Logic Levels:           2  (BSCANE2=1 LUT2=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.600ns (routing 1.525ns, distribution 1.075ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TDI_TDI)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TDI
                         net (fo=4, routed)           0.335     4.635    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tdi
    SLICE_X106Y108       LUT2 (Prop_G6LUT_SLICEL_I1_O)
                                                      0.097     4.732 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid[31]_i_2/O
                         net (fo=1, routed)           0.048     4.780    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid[31]_i_2_n_0
    SLICE_X106Y108       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid_reg[31]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.353     2.818    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.842 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         2.600     5.442    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X106Y108       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid_reg[31]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
                            (internal pin)
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid_reg[31]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.698ns  (logic 0.505ns (72.325%)  route 0.193ns (27.675%))
  Logic Levels:           2  (BSCANE2=1 LUT2=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.803ns (routing 1.028ns, distribution 0.775ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TDI_TDI)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TDI
                         net (fo=4, routed)           0.177     0.642    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tdi
    SLICE_X106Y108       LUT2 (Prop_G6LUT_SLICEL_I1_O)
                                                      0.040     0.682 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid[31]_i_2/O
                         net (fo=1, routed)           0.016     0.698    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid[31]_i_2_n_0
    SLICE_X106Y108       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid_reg[31]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.450     6.750    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.769 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.803     8.572    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X106Y108       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid_reg[31]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
                            (internal pin)
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[31]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.779ns  (logic 0.500ns (64.193%)  route 0.279ns (35.807%))
  Logic Levels:           2  (BSCANE2=1 LUT5=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.803ns (routing 1.028ns, distribution 0.775ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TDI_TDI)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TDI
                         net (fo=4, routed)           0.258     0.723    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tdi
    SLICE_X107Y118       LUT5 (Prop_H6LUT_SLICEM_I2_O)
                                                      0.035     0.758 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg[31]_i_2/O
                         net (fo=1, routed)           0.021     0.779    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg[31]_i_2_n_0
    SLICE_X107Y118       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[31]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.450     6.750    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.769 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.803     8.572    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X107Y118       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[31]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
                            (internal pin)
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscanid_reg[31]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.874ns  (logic 0.524ns (59.961%)  route 0.350ns (40.039%))
  Logic Levels:           2  (BSCANE2=1 LUT4=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.811ns (routing 1.028ns, distribution 0.783ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TDI_TDI)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TDI
                         net (fo=4, routed)           0.332     0.797    dbg_hub/inst/BSCANID.u_xsdbm_id/TDI
    SLICE_X105Y115       LUT4 (Prop_F6LUT_SLICEL_I3_O)
                                                      0.059     0.856 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscanid[31]_i_1/O
                         net (fo=1, routed)           0.018     0.874    dbg_hub/inst/BSCANID.u_xsdbm_id/p_2_in[31]
    SLICE_X105Y115       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscanid_reg[31]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.450     6.750    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.769 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.811     8.580    dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i
    SLICE_X105Y115       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscanid_reg[31]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
                            (internal pin)
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/iTDI_reg_reg/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.640ns  (logic 0.465ns (28.357%)  route 1.175ns (71.643%))
  Logic Levels:           1  (BSCANE2=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.796ns (routing 1.028ns, distribution 0.768ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TDI_TDI)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TDI
                         net (fo=4, routed)           1.175     1.640    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/out
    SLICE_X112Y321       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/iTDI_reg_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           2.450     6.750    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y181        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     6.769 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.796     8.565    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/m_bscan_tck[0]
    SLICE_X112Y321       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/iTDI_reg_reg/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  
  To Clock:  sys_clk_ddr4_clk_p

Max Delay             2 Endpoints
Min Delay             2 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/LOCKED
                            (internal pin)
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.673ns  (logic 0.246ns (14.704%)  route 1.427ns (85.296%))
  Logic Levels:           2  (LUT3=2)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.541ns (routing 0.637ns, distribution 0.904ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    PLL_X0Y7             PLLE4_ADV                    0.000     0.000 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/LOCKED
                         net (fo=1, routed)           0.986     0.986    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/pll_lock_i[0]
    SLICE_X81Y302        LUT3 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.097     1.083 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/pll_lock__0/O
                         net (fo=1, routed)           0.170     1.253    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/pll_lock
    SLICE_X84Y302        LUT3 (Prop_A6LUT_SLICEL_I2_O)
                                                      0.149     1.402 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_i_1/O
                         net (fo=1, routed)           0.271     1.673    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg0
    SLICE_X84Y309        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.541     2.456    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X84Y309        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/LOCKED
                            (internal pin)
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.771ns  (logic 0.160ns (20.756%)  route 0.611ns (79.244%))
  Logic Levels:           1  (LUT2=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.542ns (routing 0.637ns, distribution 0.905ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    MMCM_X0Y4            MMCME4_ADV                   0.000     0.000 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/LOCKED
                         net (fo=3, routed)           0.370     0.370    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_lock
    SLICE_X84Y300        LUT2 (Prop_G5LUT_SLICEL_I1_O)
                                                      0.160     0.530 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_i_1/O
                         net (fo=1, routed)           0.241     0.771    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg0
    SLICE_X84Y305        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.542     2.457    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X84Y305        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/LOCKED
                            (internal pin)
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.332ns  (logic 0.014ns (4.219%)  route 0.318ns (95.781%))
  Logic Levels:           1  (LUT3=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.085ns (routing 0.434ns, distribution 0.651ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    MMCM_X0Y4            MMCME4_ADV                   0.000     0.000 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/LOCKED
                         net (fo=3, routed)           0.201     0.201    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_lock
    SLICE_X84Y302        LUT3 (Prop_A6LUT_SLICEL_I0_O)
                                                      0.014     0.215 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_i_1/O
                         net (fo=1, routed)           0.117     0.332    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg0
    SLICE_X84Y309        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.085     1.872    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X84Y309        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/LOCKED
                            (internal pin)
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.346ns  (logic 0.058ns (16.784%)  route 0.288ns (83.216%))
  Logic Levels:           1  (LUT2=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.085ns (routing 0.434ns, distribution 0.651ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    MMCM_X0Y4            MMCME4_ADV                   0.000     0.000 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/LOCKED
                         net (fo=3, routed)           0.183     0.183    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_lock
    SLICE_X84Y300        LUT2 (Prop_G5LUT_SLICEL_I1_O)
                                                      0.058     0.241 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_i_1/O
                         net (fo=1, routed)           0.105     0.346    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg0
    SLICE_X84Y305        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y124        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.085     1.872    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X84Y305        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/C





